A WDT simulation verification method, device, equipment and medium

Abstract

The application discloses a WDT simulation verification method and device, equipment and medium, and relates to the technical field of computers, which comprises the following steps: after starting the simulation verification operation, triggering a random test event to control a test component to select a random test sequence and send a corresponding transaction message to a driver, so that the driver sends the transaction message to the WDT; after detecting that the WDT starts to work through the control module, starting a timing operation, and monitoring the output signal of the WDT after reaching the preset timeout, judging whether the output signal meets the first preset condition; if yes, recording the current test coverage, judging whether the current test coverage meets the second preset condition; if not, sending a transaction completion flag to the test component to re-trigger the random test event to send the next transaction message until the current test coverage meets the second preset condition to complete the simulation verification operation. The simulation process can be controlled, the coverage can be quickly converged, and the verification efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a WDT simulation verification method, apparatus, equipment, and medium. Background Technology

[0002] The purpose of a watchdog timer (WDT) is to prevent a program from entering an infinite loop. The watchdog is essentially a counter; it's typically fed a number, and starts counting after the program begins running. If the program runs normally, the CPU will issue an instruction to reset the watchdog to zero after a period of time, restarting the count. If the watchdog counter reaches a set value, it's considered that the program is not functioning correctly, and a system reset will be forced. Depending on the register configuration, the watchdog will generate an interrupt signal or a reset signal in case of a timeout or pre-timeout. The polarity and pulse width of the reset signal will also vary depending on the configuration. Furthermore, the timing of interrupt and reset signal generation will also change due to changes in the watchdog count. Therefore, the challenge in verifying the WDT lies in ensuring functional coverage under various configuration conditions while accurately determining the correctness of the output signals in each functional mode.

[0003] In summary, how to validate WDT to achieve rapid convergence of coverage and improve validation efficiency is a problem that needs to be solved. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a WDT simulation verification method, apparatus, device, and medium, which can verify WDT to achieve rapid coverage convergence and improve verification efficiency. The specific solution is as follows:

[0005] Firstly, this application discloses a WDT simulation verification method, including:

[0006] After the simulation verification operation is started, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send the corresponding transaction message to the driver, so that the transaction message can be sent to WDT through the driver.

[0007] After the control module detects that the WDT has started working, it starts a timing operation, and after the preset timeout time specified by the timing operation is reached, it monitors the output signal of the WDT and determines whether the output signal meets the first preset condition.

[0008] If the first preset condition is met, the current test coverage is recorded, and it is determined whether the current test coverage meets the second preset condition.

[0009] If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering a random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then the simulation verification operation is completed.

[0010] Optionally, after initiating the random test sequence and sending the corresponding transaction message to the driver, the method further includes:

[0011] After the transaction message is detected to be sent, a pause event is triggered to control the test component to select a pause test sequence to stop sending transaction messages.

[0012] Optionally, the WDT simulation verification method further includes:

[0013] The configuration functions corresponding to different bus protocols are predetermined, and the test sequences corresponding to each configuration function are saved to the test sequence library in the test component.

[0014] Optionally, after recording the current test coverage, the method further includes:

[0015] Store the current coverage test rate and the corresponding transaction configuration data in the configuration database;

[0016] Accordingly, the step of sending a transaction completion flag to the test component through the control module to re-jump to the step of triggering a random test event to control the test component to select a random test sequence, and sending the next transaction message until the current test coverage meets the second preset condition, further includes:

[0017] If the current test coverage is found to remain unchanged within a preset unit time, the control module will traverse the configuration database to determine the uncovered target configuration functions.

[0018] Based on the target configuration function, the test component is controlled to select a targeted test sequence and initiate the targeted test sequence to send the next transaction message.

[0019] Optionally, the step of sending a transaction completion flag to the test component via the control module to re-jump to the step of triggering the random test event to control the test component to select a random test sequence, and sending the next transaction message until the current test coverage meets the second preset condition, further includes:

[0020] If it is detected that all test sequences in the test sequence library have been sent and the current test coverage does not meet the second preset condition, then a new target-oriented test sequence is added to the test sequence library based on the current coverage test rate and the transaction configuration data stored in the configuration database.

[0021] The test component is controlled to select the target-oriented test sequence and initiate the target-oriented test sequence to send the next transaction message.

[0022] Optionally, the process of sending the transaction message to the WDT through the driver further includes:

[0023] The control module acquires the configuration data in the register and determines the current test configuration function, as well as the input value, output signal polarity, and duration of the WDT corresponding to the configuration function, based on the configuration data.

[0024] The first preset condition is constructed based on the input value of the WDT, the polarity of the output signal, and the duration.

[0025] Optionally, after determining whether the output signal meets the first preset condition, the method further includes:

[0026] If the first preset condition is not met, the simulation verification operation will be terminated by calling the preset termination function through the control module.

[0027] Secondly, this application discloses a WDT simulation verification device, comprising:

[0028] The random test module is used to trigger a random test event after the simulation verification operation is started, so as to control the test component to select a random test sequence and start the random test sequence to send the corresponding transaction message to the driver, so that the driver can send the transaction message to WDT;

[0029] The output signal monitoring module is used to start a timing operation after the control module detects that the WDT has started working, and to monitor the output signal of the WDT after the preset timeout time specified by the timing operation is reached, and to determine whether the output signal meets the first preset condition.

[0030] The coverage determination module is used to record the current test coverage if the first preset condition is met, and to determine whether the current test coverage meets the second preset condition.

[0031] The repeat test module is used to send a transaction completion flag to the test component through the control module if the second preset condition is not met, so as to jump back to the step of triggering the random test event to control the test component to select a random test sequence, and send the next transaction message until the current test coverage meets the second preset condition, and then complete the simulation verification operation.

[0032] Thirdly, this application discloses an electronic device, including:

[0033] Memory, used to store computer programs;

[0034] A processor is used to execute the computer program to implement the steps of the aforementioned disclosed WDT simulation verification method.

[0035] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed WDT simulation verification method.

[0036] As can be seen, after initiating the simulation verification operation, this application triggers a random test event to control the test component to select a random test sequence and initiates the random test sequence to send corresponding transaction messages to the driver program, so that the driver program can send the transaction messages to the WDT. After detecting that the WDT has started working, the control module initiates a timing operation and monitors the output signal of the WDT after the preset timeout period specified by the timing operation, and determines whether the output signal meets a first preset condition. If the first preset condition is met, the current test coverage is recorded, and it is determined whether the current test coverage meets a second preset condition. If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering the random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then completes the simulation verification operation. Therefore, the control module in this application includes a timing function; when the preset timeout period specified by the timing operation is reached, the output signal of the WDT can be obtained, and it is necessary to determine whether the output signal meets the first preset condition. The control module will only control the test component to send the next transaction message if the output signal meets the first preset condition and the current coverage test rate does not meet the second preset condition. This allows for dynamic control of the simulation process, saving simulation time and improving efficiency. Furthermore, using the current coverage test rate meeting the second preset condition as the condition for ending the simulation enables rapid convergence of the coverage rate, thereby improving verification efficiency. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1 This is a flowchart of a WDT simulation verification method disclosed in this application;

[0039] Figure 2 This is a schematic diagram of a specific verification platform disclosed in this application;

[0040] Figure 3 This is a flowchart of a specific WDT simulation verification method disclosed in this application;

[0041] Figure 4 This is a schematic diagram of a specific WDT simulation verification process disclosed in this application;

[0042] Figure 5 This is a schematic diagram of the structure of a WDT simulation verification device disclosed in this application;

[0043] Figure 6 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0045] Currently, depending on the register configuration, the watchdog timer will generate an interrupt signal or a reset signal in the event of a timeout or pre-timeout. The polarity and pulse width of the reset signal will also vary depending on the configuration. Furthermore, the timing of the interrupt and reset signal generation will also change due to variations in the watchdog count. Therefore, the challenge of WDT verification lies in ensuring functional coverage under various configuration conditions while accurately determining the correctness of the output signals in each functional mode. This application discloses a WDT simulation verification method, apparatus, device, and medium, which can verify the WDT to achieve rapid convergence of coverage and improve verification efficiency.

[0046] See Figure 1 As shown in the embodiment of this application, a WDT simulation verification method is disclosed, which includes:

[0047] Step S11: After starting the simulation verification operation, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send the corresponding transaction message to the driver program so that the transaction message can be sent to the WDT through the driver program.

[0048] In this embodiment, after the simulation verification operation begins, a random test event is triggered to control the test component Test to select a random test sequence and start the random test sequence to send a complete transaction message to the driver so that the driver can send the transaction message to the WDT.

[0049] It should be noted that the verification platform used in this embodiment can be specifically as follows: Figure 2 As shown, the verification platform adds a config module to the traditional UVM components. By selecting different bus configuration information, it enables the selection of driver timing and interface signals in the agent, improving the efficiency of building verification environment components. The verification platform also adds a control module with timing functionality, which can automatically determine the timing of interrupt and reset signals based on monitored functional information, enabling output signal comparison. The register control ports of the Agent and WDT are connected using an I / O interface, which includes all ports of the AMBA (Advanced Microcontroller Bus Architecture) bus protocol, avoiding frequent interface modifications. The AMBA bus protocol is an on-chip interconnect standard designed for high-performance embedded microcontrollers. To match data types of different bus protocols, multiple sets of components are declared in the agent, corresponding to different bus protocols. The instantiation of all components is controlled by the config module. Taking the WDT register port controlled via the APB (Advanced Peripheral Bus) bus as an example, the config module sets the is_active variable of the APB driver and APB monitor in the agent to active mode using the config_db method, while setting other bus protocol-related components to passive mode. This approach simplifies the verification environment and avoids unnecessary components that could slow down the simulation.

[0050] Step S12: After the control module detects that the WDT has started working, it starts a timing operation, and after the preset timeout time specified by the timing operation is reached, it monitors the output signal of the WDT and determines whether the output signal meets the first preset condition.

[0051] In this embodiment, the control module starts a timing operation after detecting that the WDT has started working, and monitors the output signal of the WDT after the preset timeout time specified by the timing operation is reached, so as to determine whether the output signal meets the first preset condition. Specifically, it determines whether the interrupt signal and the reset signal are generated, whether the polarity is correct, and whether the pulse width meets the setting.

[0052] Step S13: If the first preset condition is met, record the current test coverage and determine whether the current test coverage meets the second preset condition.

[0053] In one specific implementation, if the output signal meets the first preset condition, that is, the WDT output result is correct, the control module records the current test coverage and determines whether the current test coverage meets the second preset condition. The second preset condition is that the current test coverage must meet 100%, that is, determine whether the current test coverage has reached 100%.

[0054] In another specific implementation, after determining whether the output signal meets the first preset condition, the method further includes: if the first preset condition is not met, the control module calls a preset termination function to end the simulation verification operation. That is, if the output signal does not meet the first preset condition, meaning the control module determines that the WDT output result is incorrect, the control module calls the finish function to end the simulation and prints the current configuration function to facilitate subsequent debugging.

[0055] Step S14: If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering a random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then completes the simulation verification operation.

[0056] In this embodiment, if the current test coverage does not meet the second preset condition, i.e., it does not reach 100%, the control module sends a transaction completion flag to the test component to redirect back to the step of triggering random test events to control the test component to select a random test sequence. That is, if the current test coverage does not reach 100%, a transaction completion flag is sent to the test component. After receiving the transaction completion flag, the test component continues to trigger random test events, controlling the random test sequence to send the next transaction message until the current test coverage meets the second preset condition after multiple loops, and then the simulation verification operation is completed. In other words, the control module sends a simulation end flag to the test component, and the test component stops sending transaction messages, ending the simulation.

[0057] As can be seen, after initiating the simulation verification operation, this application triggers a random test event to control the test component to select a random test sequence and initiates the random test sequence to send corresponding transaction messages to the driver program, so that the driver program can send the transaction messages to the WDT. After detecting that the WDT has started working, the control module initiates a timing operation and monitors the output signal of the WDT after the preset timeout period specified by the timing operation, and determines whether the output signal meets a first preset condition. If the first preset condition is met, the current test coverage is recorded, and it is determined whether the current test coverage meets a second preset condition. If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering the random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then completes the simulation verification operation. Therefore, the control module in this application includes a timing function; when the preset timeout period specified by the timing operation is reached, the output signal of the WDT can be obtained, and it is necessary to determine whether the output signal meets the first preset condition. The control module will only control the test component to send the next transaction message if the output signal meets the first preset condition and the current coverage test rate does not meet the second preset condition. This allows for dynamic control of the simulation process, saving simulation time and improving efficiency. Furthermore, using the current coverage test rate meeting the second preset condition as the condition for ending the simulation enables rapid convergence of the coverage rate, thereby improving verification efficiency.

[0058] See Figure 3 and Figure 4 As shown, this application discloses a specific WDT simulation verification method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0059] Step S21: After starting the simulation verification operation, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send the corresponding transaction message to the driver program so that the transaction message can be sent to the WDT through the driver program.

[0060] In this embodiment, in a specific implementation, it is necessary to pre-determine the configuration functions corresponding to different bus protocols, and save the test sequences corresponding to each configuration function to the test sequence library in the test component. That is, the test sequence library of the test component pre-stores the test sequences corresponding to different configuration functions.

[0061] Furthermore, the process of sending the transaction message to the WDT via the driver also includes: obtaining configuration data from the registers through the control module, determining the current test configuration function and the input value, output signal polarity, and duration of the WDT corresponding to the configuration function based on the configuration data; and constructing the first preset condition based on the WDT input value, the output signal polarity, and the duration. It can be understood that during the process of the transaction message being sent from the driver to the WDT, the Monitor in the config module monitors the register configuration data and transmits it to the control module. The control module determines the configuration function implemented by the current transaction message based on the collected configuration data, i.e., the WDT input value (also known as the watchdog timer), the output signal polarity, the output signal duration, etc., so as to construct the first preset condition based on the WDT input value, the output signal polarity, and the duration.

[0062] Step S22: After detecting that the transaction message has been sent, a pause event is triggered to control the test component to select a pause test sequence to stop sending transaction messages.

[0063] In this embodiment, it should be noted that the test component includes all test sequences. Besides the random test sequence and the directed test sequence, it also includes a pause test sequence. This sequence does not send any transaction messages; it simply loops infinitely, advancing the simulation time and thus pausing the sending of transaction messages. Therefore, upon detecting that a transaction message has been sent, a pause event is triggered, and the test component selects the pause test sequence to pause the sending of transaction messages.

[0064] Step S23: After the control module detects that the WDT has started working, it starts a timing operation, and after the preset timeout time specified by the timing operation is reached, it monitors the output signal of the WDT and determines whether the output signal meets the first preset condition.

[0065] Step S24: If the first preset condition is met, record the current test coverage rate, store the current coverage test rate and the corresponding transaction configuration data in the configuration database, and determine whether the current test coverage rate meets the second preset condition.

[0066] In this embodiment, if the WDT output is correct, the control module will record the current coverage test rate and store the current coverage test rate and the corresponding transaction configuration data in the internal configuration database.

[0067] Step S25: If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering a random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then completes the simulation verification operation.

[0068] In this embodiment, the process of sending a transaction completion flag to the test component via the control module to redirect back to the triggering of a random test event to control the test component to select a random test sequence, and sending the next transaction message until the current test coverage meets the second preset condition, further includes: if it is detected that the current test coverage has not changed within a preset unit time, the control module traverses the configuration database to determine the uncovered target configuration function; based on the target configuration function, the control module controls the test component to select a targeted test sequence and starts the targeted test sequence to send the next transaction message. It is understood that after sending several transaction messages, the control module may detect that the current test coverage has not increased within the preset unit time, i.e., has not changed. At this time, the control module will traverse the internal configuration database to automatically calculate the uncovered target configuration function. When transmitting the transaction completion flag to the test component, it will also trigger the targeted test sequence event corresponding to the uncovered target configuration function in the test component, and then the test component controls the targeted test sequence to send the next transaction message.

[0069] Furthermore, the above process may also include: if it is detected that all test sequences in the test sequence library have been sent, and the current test coverage does not meet the second preset condition, then a new target-oriented test sequence is added to the test sequence library based on the current coverage test rate stored in the configuration database and the transaction configuration data; the test component is controlled to select the target-oriented test sequence and start the target-oriented test sequence to send the next transaction message. It is understood that if it is detected that all test sequences in the test sequence library have been sent, but the current test coverage has not yet reached 100% and is no longer increasing, the control module will return the coverage and configuration database information, and then, based on the information returned by the control module, add a new target-oriented test sequence to the test sequence library. After updating the test sequence library, the target-oriented test sequence is selected to continue simulation verification until the coverage reaches 100%.

[0070] For more detailed processing procedures regarding steps S23, S24, and S25, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0071] As can be seen, in this embodiment, if the current test coverage is less than 100%, a transaction completion flag is sent to the test component to re-trigger the random test event, controlling the test component to select a random test sequence, and then sending the next transaction message. Furthermore, during this process, if the current test coverage is not detected to have changed within a preset unit time, the control module will traverse the internal configuration database to automatically calculate the uncovered target configuration functions, and then control the test component to select a targeted test sequence based on the target configuration functions. Additionally, if all test sequences in the test sequence library have been sent, but the current test coverage is still less than 100%, a new target-oriented test sequence is added to the test sequence library based on the information returned by the control module, and then the next transaction message is sent. This achieves rapid coverage convergence and full coverage of all configuration function tests, improving verification efficiency.

[0072] See Figure 5 As shown in the figure, this application discloses a WDT simulation verification device, which includes:

[0073] The random test module 11 is used to trigger a random test event after the simulation verification operation is started, so as to control the test component to select a random test sequence and start the random test sequence to send the corresponding transaction message to the driver, so that the transaction message can be sent to WDT through the driver.

[0074] The output signal monitoring module 12 is used to start a timing operation after the control module detects that the WDT has started working, and to monitor the output signal of the WDT after the preset timeout time specified by the timing operation is reached, and to determine whether the output signal meets the first preset condition.

[0075] The coverage determination module 13 is used to record the current test coverage if the first preset condition is met, and to determine whether the current test coverage meets the second preset condition.

[0076] The repeat test module 14 is used to send a transaction completion flag to the test component through the control module if the second preset condition is not met, so as to jump back to the step of triggering the random test event to control the test component to select a random test sequence, and send the next transaction message until the current test coverage meets the second preset condition, and then complete the simulation verification operation.

[0077] As can be seen, after initiating the simulation verification operation, this application triggers a random test event to control the test component to select a random test sequence and initiates the random test sequence to send corresponding transaction messages to the driver program, so that the driver program can send the transaction messages to the WDT. After detecting that the WDT has started working, the control module initiates a timing operation and monitors the output signal of the WDT after the preset timeout period specified by the timing operation, and determines whether the output signal meets a first preset condition. If the first preset condition is met, the current test coverage is recorded, and it is determined whether the current test coverage meets a second preset condition. If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering the random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then completes the simulation verification operation. Therefore, the control module in this application includes a timing function; when the preset timeout period specified by the timing operation is reached, the output signal of the WDT can be obtained, and it is necessary to determine whether the output signal meets the first preset condition. The control module will only control the test component to send the next transaction message if the output signal meets the first preset condition and the current coverage test rate does not meet the second preset condition. This allows for dynamic control of the simulation process, saving simulation time and improving efficiency. Furthermore, using the current coverage test rate meeting the second preset condition as the condition for ending the simulation enables rapid convergence of the coverage rate, thereby improving verification efficiency.

[0078] In some specific embodiments, after the random testing module 11, the system may further include:

[0079] The pause test sequence sending unit is used to trigger a pause event after detecting that the transaction message has been sent, so as to control the test component to select a pause test sequence to stop sending transaction messages.

[0080] In some specific embodiments, the WDT simulation verification device may further include:

[0081] The test sequence storage unit is used to predetermine the configuration functions corresponding to different bus protocols and save the test sequences corresponding to each configuration function to the test sequence library in the test component.

[0082] In some specific embodiments, the coverage determination module 13 may further include:

[0083] A coverage storage unit is used to store the current coverage test rate and the corresponding transaction configuration data in a configuration database.

[0084] Accordingly, the process of the repeat test module 14 may also include:

[0085] The traversal unit is used to determine the uncovered target configuration function by traversing the configuration database through the control module if the current test coverage is detected to have not changed within a preset unit time.

[0086] The directional testing unit is used to control the testing component to select a directional testing sequence based on the target configuration function, and to start the directional testing sequence to send the next transaction message.

[0087] In some specific embodiments, the process of the repeat test module 14 may further include:

[0088] A test sequence addition unit is used to add a new target-oriented test sequence to the test sequence library if it is detected that all test sequences in the test sequence library have been sent and the current test coverage does not meet the second preset condition, based on the current coverage test rate stored in the configuration database and the transaction configuration data.

[0089] The target-oriented test unit is used to control the test component to select the target-oriented test sequence and start the target-oriented test sequence to send the next transaction message.

[0090] In some specific embodiments, the output signal monitoring module 12 may further include:

[0091] The configuration data acquisition unit is used to acquire configuration data in the register through the control module, and determine the current test configuration function and the input value, output signal polarity and duration of the WDT corresponding to the configuration function based on the configuration data.

[0092] The first preset condition construction unit is used to construct the first preset condition based on the input value of the WDT, the polarity of the output signal, and the duration.

[0093] In some specific embodiments, after the output signal monitoring module 12, the system may further include:

[0094] The simulation termination unit is used to terminate the simulation verification operation by calling a preset termination function through the control module if the first preset condition is not met.

[0095] Figure 6This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the WDT simulation verification method performed by the electronic device disclosed in any of the foregoing embodiments.

[0096] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0097] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0098] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0099] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the electronic device 20 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the WDT simulation verification method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0100] Furthermore, embodiments of this application also disclose a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the method steps performed during the WDT simulation verification process disclosed in any of the foregoing embodiments.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0102] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0104] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0105] The foregoing has provided a detailed description of the WDT simulation verification method, apparatus, device, and storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A WDT simulation verification method, characterized in that, include: After the simulation verification operation is started, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send the corresponding transaction message to the driver, so that the transaction message can be sent to WDT through the driver. After the control module detects that the WDT has started working, it initiates a timing operation, and after the preset timeout period specified by the timing operation is reached, it monitors the output signal of the WDT and determines whether the output signal meets a first preset condition; wherein, the first preset condition is constructed based on the input value of the WDT, the polarity of the output signal, and the duration. If the first preset condition is not met, the simulation verification operation is terminated by calling the preset termination function through the control module. If the first preset condition is met, the current test coverage is recorded, and it is determined whether the current test coverage meets the second preset condition. If the second preset condition is not met, the control module sends a transaction completion flag to the test component to jump back to the step of triggering a random test event to control the test component to select a random test sequence, and sends the next transaction message until the current test coverage meets the second preset condition, and then the simulation verification operation is completed.

2. The WDT simulation verification method according to claim 1, characterized in that, After initiating the random test sequence and sending the corresponding transaction message to the driver, the process further includes: After the transaction message is detected to be sent, a pause event is triggered to control the test component to select a pause test sequence to stop sending transaction messages.

3. The WDT simulation verification method according to claim 1, characterized in that, Also includes: The configuration functions corresponding to different bus protocols are predetermined, and the test sequences corresponding to each configuration function are saved to the test sequence library in the test component.

4. The WDT simulation verification method according to claim 3, characterized in that, After recording the current test coverage, it also includes: Store the current test coverage and corresponding transaction configuration data in the configuration database; Accordingly, the step of sending a transaction completion flag to the test component through the control module to re-jump to the step of triggering a random test event to control the test component to select a random test sequence, and sending the next transaction message until the current test coverage meets the second preset condition, further includes: If the current test coverage is found to remain unchanged within a preset unit time, the control module will traverse the configuration database to determine the uncovered target configuration functions. Based on the target configuration function, the test component is controlled to select a targeted test sequence and initiate the targeted test sequence to send the next transaction message.

5. The WDT simulation verification method according to claim 4, characterized in that, The step of sending a transaction completion flag to the test component via the control module to re-jump to the step of triggering a random test event to control the test component to select a random test sequence, and sending the next transaction message, until the current test coverage meets the second preset condition, further includes: If it is detected that all test sequences in the test sequence library have been sent and the current test coverage does not meet the second preset condition, then a new target-oriented test sequence is added to the test sequence library based on the current test coverage stored in the configuration database and the transaction configuration data. The test component is controlled to select the target-oriented test sequence and initiate the target-oriented test sequence to send the next transaction message.

6. The WDT simulation verification method according to claim 3, characterized in that, The process of sending the transaction message to the WDT through the driver also includes: The control module acquires the configuration data in the register and determines the current test configuration function, as well as the input value, output signal polarity, and duration of the WDT corresponding to the configuration function, based on the configuration data. The first preset condition is constructed based on the input value of the WDT, the polarity of the output signal, and the duration.

7. A WDT simulation verification device, characterized in that, include: The random test module is used to trigger a random test event after the simulation verification operation is started, so as to control the test component to select a random test sequence and start the random test sequence to send the corresponding transaction message to the driver, so that the driver can send the transaction message to WDT; An output signal monitoring module is used to initiate a timing operation after the control module detects that the WDT has started working, and to monitor the output signal of the WDT after a preset timeout period is reached, and to determine whether the output signal meets a first preset condition; wherein, the first preset condition is constructed based on the input value of the WDT, the polarity of the output signal, and the duration. The simulation termination unit is used to terminate the simulation verification operation by calling a preset termination function through the control module if the first preset condition is not met. The coverage determination module is used to record the current test coverage if the first preset condition is met, and to determine whether the current test coverage meets the second preset condition. The repeat test module is used to send a transaction completion flag to the test component through the control module if the second preset condition is not met, so as to jump back to the step of triggering the random test event to control the test component to select a random test sequence, and send the next transaction message until the current test coverage meets the second preset condition, and then complete the simulation verification operation.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the WDT simulation verification method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the WDT simulation verification method as described in any one of claims 1 to 6.

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