Germanium-silicon heterojunction bipolar transistor structure and method of forming same, crystal growth method

Abstract

A germanium-silicon heterojunction bipolar transistor structure and its formation method and crystal growth method are disclosed. The method includes: providing a substrate, the substrate including a base and a collector region located on the base; forming a mask layer structure on the substrate, the mask layer structure including a mask layer having a first opening, the mask layer including a host region and a surface region located on the host region, the chemical bonds of the host region material having a first bond energy, the surface region having doped ions, the chemical bonds formed by the doped ions and the ions of the surface region material having a second bond energy, the second bond energy being greater than the first bond energy; using the mask layer as a mask, employing a selective epitaxial process to form a main base region on the surface of the collector region under the first opening, thereby improving the growth selectivity of the main base region material and thus improving the process window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a germanium-silicon heterojunction bipolar transistor structure and its formation method and crystal growth method. Background Technology

[0002] With societal development and the increasing demand for high-performance and low-cost RF components in modern communications, traditional silicon devices can no longer meet these new performance requirements. Because germanium-silicon heterojunction bipolar transistors (HBTs) offer significantly superior high-frequency performance compared to silicon bipolar transistors, and their compatibility with silicon processes allows them to leverage silicon's lower cost, germanium-silicon technology has made substantial progress. Germanium-silicon HBT technology has become one of the mainstream technologies in the RF integrated circuit market and has profoundly impacted the development of modern communication technology.

[0003] The base region of the germanium-silicon heterojunction bipolar transistor structure is made of germanium-silicon and is obtained using a selective epitaxial growth process. However, the process window of this selective epitaxial growth process is relatively small during the formation of the base region, which limits the development of the germanium-silicon heterojunction bipolar transistor structure technology.

[0004] Therefore, the fabrication process of existing germanium-silicon heterojunction bipolar transistor structures needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a germanium-silicon heterojunction bipolar transistor structure and its formation method and crystal growth method, so as to improve the process window for forming germanium-silicon heterojunction bipolar transistor structures.

[0006] To address the aforementioned technical problems, the present invention provides a germanium-silicon heterojunction bipolar transistor structure, comprising: a substrate, the substrate including a base and a collector region located on the base; a mask layer structure located on the substrate, the mask layer structure including a mask layer, the mask layer structure having a second opening, the second opening exposing the top surface of the collector region, the mask layer including a main region and a surface region located on the main region, the chemical bonds of the main region material having a first bond energy, the surface region having doped ions, the chemical bonds formed by the doped ions and the ions of the surface region material having a second bond energy, the second bond energy being greater than the first bond energy; and a main base region located on the surface of the collector region exposed by the second opening.

[0007] Optionally, the doping ions include fluorine ions; the chemical bonds of the host region material include silicon-nitrogen bonds, and the chemical bonds of the surface region material include silicon-fluorine bonds.

[0008] Optionally, the mask layer structure further includes a dielectric layer, two mutually independent outer base regions located on the surface of the dielectric layer, the second opening located within the dielectric layer and exposing the current collector region and a portion of the surface of the outer base regions, the mask layer located on the top surface and sidewalls of the outer base regions, the mask layer having a first opening and the first opening communicating with the second opening, the second opening exposing the current collector region and a portion of the outer base regions; the mask layer includes a cover layer located on the top surface of the outer base regions and a sidewall located on the sidewalls of the outer base regions.

[0009] Accordingly, the present invention also provides a method for forming a germanium-silicon heterojunction bipolar transistor structure, comprising: providing a substrate, the substrate including a base and a collector region located on the base; forming a mask layer structure on the substrate, the mask layer structure including a mask layer having a first opening, the mask layer including a host region and a surface region located on the host region, the chemical bonds of the host region material having a first bond energy, the surface region having doped ions, the chemical bonds formed by the doped ions and the ions of the surface region material having a second bond energy, the second bond energy being greater than the first bond energy; using the mask layer as a mask, selective epitaxy process is used to form a main base region on the surface of the collector region under the first opening.

[0010] Optionally, the mask layer structure further includes a dielectric layer and two mutually separate outer base regions located on the surface of the dielectric layer. The dielectric layer has a second opening. The mask layer is located on the top surface and sidewall of the outer base regions, and the first opening and the second opening are interconnected. The second opening exposes the current collector region and a portion of the outer base regions. The mask layer includes a cover layer located on the top surface of the outer base regions and a sidewall located on the sidewall of the outer base regions. The main base region is located on the surface of the current collector region and a portion of the outer base regions exposed by the second opening.

[0011] Optionally, the method for forming the mask layer structure includes: forming a dielectric material layer, two mutually discrete outer base regions located on the surface of the dielectric material layer, and an initial capping layer located on the top surface of the outer base regions on the substrate, wherein the outer base regions and the initial capping layer have an initial first opening; forming a sidewall material layer on the sidewall of the initial first opening; performing surface treatment on the initial capping layer and the sidewall material layer to form the capping layer with the initial capping layer, forming the sidewall with the sidewall material layer on the sidewall of the initial first opening, and using the initial first opening between the sidewalls as the first opening; after forming the mask layer, etching the dielectric material layer using the mask layer as a mask to form the dielectric layer and the second opening.

[0012] Optionally, after forming the second opening and before the selective epitaxial process, the method further includes cleaning the surface of the current collector region exposed by the second opening.

[0013] Optionally, the surface treatment process includes a first treatment process, which includes an ion doping process and an annealing process following the ion doping process.

[0014] Optionally, the process parameters of the ion doping process include: the doping ion includes fluorine ions, and the doping ion dose range is 1E14 atom / cm². 2 Up to 1E16 atom / cm 2 .

[0015] Optionally, the process parameters of the annealing process include: annealing temperature range of 900℃ to 1100℃, and annealing time range of 10s to 60s.

[0016] Optionally, the surface treatment process further includes a second treatment process, which includes a thinning process following the ion doping process.

[0017] Optionally, the thinning process includes a wet etching process.

[0018] Optionally, the sidewall material layer is also located on the surface of the initial cover layer; the method further includes: after the first treatment and before the thinning process, etching back the sidewall material layer until the surface of the dielectric material layer is exposed.

[0019] Optionally, the sidewall material layer is also located on the surface of the initial cover layer; the method further includes: after the surface treatment, re-etching the sidewall material layer until the surface of the medium material layer is exposed.

[0020] Optionally, the sidewall material layer is also located on the surface of the initial cover layer; the method further includes: etching the sidewall material layer back before the surface treatment until the surface of the dielectric material layer is exposed.

[0021] Optionally, it further includes: forming an emission region on a portion of the surface of the main base region, wherein the emission region and the outer base region are separate from each other.

[0022] Optionally, the chemical bonds of the host region material include silicon-nitrogen bonds, and the chemical bonds of the surface region material include silicon-fluorine bonds.

[0023] Optionally, the material of the main base region includes germanium-silicon.

[0024] The present invention also provides a crystal growth method using selective epitaxy, comprising: providing a substrate; forming a mask material layer on the substrate, wherein the chemical bonds of the mask material layer have a first bond energy; performing a surface treatment on the mask material layer to form an exposed surface region within the mask material layer, wherein the surface region contains doped ions, and the chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy, wherein the second bond energy is greater than the first bond energy; after the surface treatment, etching the mask material layer to form a mask layer and an opening located within the mask layer, wherein the opening exposes the substrate surface; and using the mask layer as a mask, employing a selective epitaxy growth process to form an epitaxial layer on the substrate exposed by the opening.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0026] In the method for forming a germanium-silicon heterojunction bipolar transistor structure provided by the present invention, a mask layer structure is formed on the substrate. The mask layer structure includes a mask layer with a first opening. The mask layer includes a main region and a surface region located on the main region. The chemical bonds of the material in the main region have a first bond energy. The surface region contains doped ions. The chemical bonds formed by the doped ions and the ions in the surface region material have a second bond energy, which is greater than the first bond energy. During the process of forming a main base region on the surface of the collector region under the first opening using the mask layer as a mask and employing a selective epitaxial process, because the second bond energy is greater than the first bond energy, the chemical bonds in the surface region are more difficult to break than the chemical bonds in the mask layer. This reduces the growth of the main base region material on the surface of the mask layer, improves the growth selectivity of the main base region material, and thus improves the process window. Attached Figure Description

[0027] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a germanium-silicon heterojunction bipolar transistor structure.

[0028] Figures 4 to 9 This is a schematic diagram of the steps in a method for forming a germanium-silicon heterojunction bipolar transistor structure according to an embodiment of the present invention.

[0029] Figures 10 to 12 This is a schematic diagram of the crystal growth method of selective epitaxy process according to another embodiment of the present invention. Detailed Implementation

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] As described in the background section, the existing fabrication process for heterojunction bipolar transistor structures needs further improvement. A method for fabricating a germanium-silicon heterojunction bipolar transistor structure will now be explained and analyzed.

[0032] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a germanium-silicon heterojunction bipolar transistor structure.

[0033] Please refer to Figure 1 A substrate is provided, the substrate including a base 100 and a collector region 101, a lead-out region 102 and an isolation region 103 located on the base 100, the isolation region 103 being located on the sidewalls of the collector region 101 and the lead-out region 102; an oxide layer 104, two outer base region structures located on the surface of the oxide layer 104 and a first opening 107 between the two outer base region structures are formed on the substrate, the outer base region structures including an outer base region 105 and a mask layer 106 located on the surface of the outer base region 105, the first opening 107 exposing a portion of the surface of the oxide layer 104 on the collector region 101; a sidewall 108 is formed on the sidewall of the first opening 107.

[0034] Please refer to Figure 2 Using the sidewall 108 as a mask, the oxide layer 104 exposed by the first opening 107 is etched until the current collector region 101 and part of the outer base region 105 are exposed, and a second opening 109 is formed in the oxide layer 104.

[0035] Please refer to Figure 3 A main base region 110 is formed within the second opening 109.

[0036] The above method is used to form a germanium-silicon HBT device. The material of the main base region 110 is germanium-silicon, the material of the mask layer 106 includes silicon nitride, and the material of the sidewall 108 includes silicon nitride. The main base region 110 is formed using a selective epitaxial growth process. In the selective epitaxial growth process, hydrogen chloride and dichlorosilane are used as reactant gases. To improve the selectivity of crystal growth on the surface of the collector region 101 and reduce the formation of unnecessary polycrystalline silicon material on the surface of the mask layer 106, one possible method is to increase the proportion of hydrogen chloride in the reactant gas. However, increasing the proportion of hydrogen chloride will increase the probability of etching the outer base region 105 exposed by the second opening 109, in region A (e.g., Figure 3 As shown, pitting defects (as shown) occur, affecting device performance.

[0037] To address the aforementioned problems, this invention provides a germanium-silicon heterojunction bipolar transistor structure and its formation method, as well as a crystal growth method. A mask layer structure is formed on the substrate. The mask layer structure includes a mask layer with a first opening. The mask layer includes a host region and a surface region located on the host region. The chemical bonds of the host region material have a first bond energy. The surface region contains doped ions, and the chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy, which is greater than the first bond energy. During the selective epitaxial growth process using the mask layer as a mask to form the host base region on the surface of the collector region under the first opening, because the second bond energy is greater than the first bond energy, the chemical bonds in the surface region are more difficult to break compared to the chemical bonds in the mask layer. This reduces the growth of the host base region material on the mask layer surface, improves the growth selectivity of the host base region material, and thus increases the process window.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 9 This is a schematic diagram of the steps in the method for forming a germanium-silicon heterojunction bipolar transistor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 4 A substrate is provided, the substrate including a base 200 and a collector region 201 located on the base 200.

[0041] In this embodiment, the substrate further includes an isolation layer 202 and a lead-out region 203 located on the substrate 200, wherein the isolation layer 202 is located on the sidewall of the current collector region 201 and the lead-out region 203.

[0042] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0043] In this embodiment, the substrate 200 has a heavily doped buried layer 204. The lead-out region 203 is connected to the heavily doped buried layer 204 and is used to lead out the electrical signal of the collector region 201.

[0044] In this embodiment, the substrate 200 has an N-type conductivity; the highly doped buried layer 204 has an N-type conductivity.

[0045] Subsequently, a mask layer structure is formed on the substrate. The mask layer structure includes a mask layer with a first opening. The mask layer includes a host region and a surface region located on the host region. The chemical bonds of the host region material have a first bond energy. The surface region contains doped ions. The chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy, which is greater than the first bond energy.

[0046] In this embodiment, the mask layer structure further includes a dielectric layer and two mutually separate outer base regions located on the surface of the dielectric layer. The dielectric layer has a second opening. The mask layer is located on the top surface and sidewall of the outer base regions, and the first opening and the second opening are interconnected. The second opening exposes the current collector region and a portion of the outer base regions. The mask layer includes a cover layer located on the top surface of the outer base regions and a sidewall located on the sidewall of the outer base regions. The main base region is located on the surface of the current collector region and a portion of the outer base regions exposed by the second opening.

[0047] In this embodiment, please refer to the method for forming the mask layer structure. Figures 5 to 7 .

[0048] Please refer to Figure 5 A dielectric material layer 205, two mutually independent outer base regions 206 located on the surface of the dielectric material layer 205, and an initial cover layer 207 located on the top surface of the outer base regions 206 are formed on the substrate. The outer base regions 206 and the initial cover layer 207 have an initial first opening 208.

[0049] The outer base region 206 is used to connect to the main base region and reduce the contact resistance when the main base region circuit is led out.

[0050] In this embodiment, the initial cover layer 207 includes a first dielectric layer 207a and a second dielectric layer 207b located on the first dielectric layer 207a.

[0051] In this embodiment, the initial cover layer 207 has a double-layer structure. In other embodiments, the initial cover layer 207 can be a single-layer or multi-layer structure.

[0052] In this embodiment, the material of the first dielectric layer 207a is silicon oxide; the material of the second dielectric layer 207b is silicon nitride.

[0053] In this embodiment, the dielectric material layer 205 is made of silicon oxide. The dielectric material layer 205 occupies space for the subsequent formation of the host base region.

[0054] In this embodiment, the method for forming the initial capping layer 207 and the outer base region 206 includes: forming an outer base region material layer (not shown in the figure) on the surface of the dielectric material layer 205; forming a capping material layer (not shown in the figure) on the surface of the outer base region material layer; patterning the capping material layer to form the initial capping layer 207; and using the initial capping layer 207 as a mask to etch the outer base region material layer to form the outer base region 206.

[0055] Please refer to Figure 6 A sidewall material layer 209 is formed on the sidewall of the initial first opening 208.

[0056] In this embodiment, the sidewall material layer 209 is also located on the surface of the initial cover layer.

[0057] The material of the sidewall material layer 209 is a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0058] In this embodiment, the material of the sidewall material layer 209 is silicon nitride.

[0059] The sidewall material layer 209 and the initial capping layer 207 are used to form a mask layer. In this embodiment, the chemical bonds of both the sidewall material layer 209 and the initial capping layer 207 are silicon-nitrogen bonds.

[0060] Please refer to Figure 7 The initial cover layer 207 and the sidewall material layer 209 are surface treated to form the cover layer 210 with the initial cover layer 207, the sidewall material layer 209 of the sidewall of the initial first opening 208 is used to form the sidewall 211, and the initial first opening 208 between the sidewalls 211 is the first opening 212.

[0061] The mask layer structure includes a mask layer having a first opening 212. The mask layer includes a main region (not shown in the figure) and a surface region (not shown in the figure) located on the main region. The chemical bonds of the material in the main region have a first bond energy. The surface region contains doped ions. The chemical bonds formed by the doped ions and the ions of the material in the surface region have a second bond energy, which is greater than the first bond energy.

[0062] Subsequently, during the formation of the host base region on the surface of the current collector region 201 under the first opening 212, since the second bond energy is greater than the first bond energy, the chemical bonds in the surface region are more difficult to break than the chemical bonds in the mask layer, thereby reducing the growth of the host base region material on the mask layer surface, improving the growth selectivity of the host base region material, and thus improving the process window.

[0063] Specifically, the chemical bonds in the host region material include silicon-nitrogen bonds, and the chemical bonds in the surface region material include silicon-fluorine bonds. The bond energy of the silicon-fluorine bond is greater than that of the silicon-nitrogen bond. Therefore, in the subsequent selective epitaxial process for forming the host region, the silicon-fluorine bonds cannot be broken, thereby reducing the growth of the host region material on the mask layer surface and improving the selectivity of crystal growth.

[0064] In this embodiment, the mask layer includes a cover layer 210 located on the top surface of the outer base region 206 and a sidewall 211 located on the sidewall of the outer base region 206.

[0065] In this embodiment, the material of the mask layer includes silicon nitride.

[0066] In this embodiment, the surface treatment process includes a first treatment process, which includes an ion doping process and an annealing process following the ion doping process.

[0067] In this embodiment, the process parameters of the ion doping process include: the doping ion includes fluorine ions, and the doping ion dose range is 1E14 atom / cm. 2 Up to 1E16 atom / cm 2 .

[0068] In this embodiment, the process parameters of the annealing process include: annealing temperature range of 900℃ to 1100℃, and annealing time range of 10s to 60s.

[0069] In this embodiment, the surface treatment process further includes a second processing step, which includes a thinning process following the ion doping process. Since the region with the highest dopant ion concentration is some distance from the surface during the ion doping process, the thinning process exposes this region while reducing damage to the mask layer surface caused during the ion doping process. In another embodiment, the second processing step may not be included.

[0070] In this embodiment, the thinning process includes a wet etching process.

[0071] In this embodiment, after the first processing and before the thinning process, the sidewall material layer is etched back until the surface of the dielectric material layer is exposed. The purpose of placing the etch-back process before the thinning process is that the thinning process can reduce surface damage caused by the etch-back process.

[0072] In another embodiment, after the surface treatment, the sidewall material layer is etched back until the surface of the medium material layer is exposed.

[0073] In another embodiment, prior to the surface treatment, the sidewall material layer is etched back until the surface of the dielectric material layer is exposed.

[0074] Please refer to Figure 8 After the mask layer is formed, the dielectric material layer 205 is etched using the mask layer as a mask to form the dielectric layer 213 and the second opening 214.

[0075] The etching process of the dielectric material layer 205 includes one or both of dry etching and wet etching processes.

[0076] In this embodiment, the etching process for the dielectric material layer 205 is a wet etching process.

[0077] Please refer to Figure 9 Using the mask layer as a mask, a selective epitaxial process is employed to form a main base region 215 on the surface of the collector region 201 under the first opening 212.

[0078] The selective epitaxial growth process of the main base region 215 improves the crystal growth selectivity and the process window.

[0079] The process parameters of the selective epitaxial process include: the reaction gas includes one or more of dichlorosilane, germane and methylsilane, and the reaction gas also includes hydrogen chloride.

[0080] Specifically, the main base region 215 is formed on the surface of the current collector region 201 and part of the outer base region 206 exposed by the second opening 214.

[0081] In this embodiment, the material of the main base region 215 includes germanium silicon.

[0082] In this embodiment, after the second opening 214 is formed and before the selective epitaxial process, the surface of the collector region 201 exposed by the second opening 214 is cleaned. The cleaning process removes impurities from the surface of the collector region 201 to improve the quality of the formed main base region 215.

[0083] In this embodiment, a emission region (not shown in the figure) is subsequently formed on a portion of the surface of the main base region, and the emission region and the outer base region 206 are separate from each other.

[0084] Accordingly, embodiments of the present invention also provide a germanium-silicon heterojunction bipolar transistor structure formed using the above method. Please refer to [link / reference needed]. Figure 9 The system includes: a substrate, the substrate comprising a base 200 and a current collector region 201 located on the base 200; and a mask layer structure located on the substrate, the mask layer structure comprising a mask layer having a second opening 214 therein (e.g., ...). Figure 8 As shown), the second opening 214 exposes the top surface of the current collector region 201. The mask layer includes a main region (not shown) and a surface region (not shown) located on the main region. The chemical bonds of the main region material have a first bond energy. The surface region contains doped ions. The chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy, which is greater than the first bond energy. The main base region 215 is located on the surface of the current collector region 201 exposed by the second opening 214.

[0085] In this embodiment, the doped ions include fluorine ions; the chemical bonds of the host region material include silicon-nitrogen bonds, and the chemical bonds of the surface region material include silicon-fluorine bonds.

[0086] In this embodiment, the mask layer structure further includes a dielectric layer 213 and two mutually independent outer base regions 206 located on the surface of the dielectric layer 213. The second opening 214 is located within the dielectric layer 213 and exposes the current collector region 201 and part of the surface of the outer base regions 206. The mask layer is located on the top surface and sidewalls of the outer base regions 206. The mask layer has a first opening 212 (e.g., ...). Figure 8 As shown in the figure, the first opening 212 and the second opening 214 are interconnected.

[0087] Specifically, the mask layer includes a cover layer 210 located on the top surface of the outer base region 206 and a sidewall 211 located on the sidewall of the outer base region 206.

[0088] Figures 10 to 12 This is a schematic diagram of the crystal growth method of selective epitaxy process according to another embodiment of the present invention.

[0089] In this embodiment, the selective epitaxial process can be used in the formation process of the main base region of a germanium-silicon heterojunction bipolar transistor structure, and can also be used in other selective epitaxial processes. For the crystal growth method of the selective epitaxial process, please refer to... Figures 10 to 12 .

[0090] Please refer to Figure 10 A substrate 300 is provided; a mask material layer 301 is formed on the substrate 300, wherein the chemical bonds of the mask material layer 301 have a first bond energy.

[0091] In this embodiment, the mask material layer 301 is made of silicon nitride.

[0092] Please refer to Figure 11The mask material layer is surface treated to form an exposed surface region 302 within the mask material layer. The surface region 302 contains doped ions, and the chemical bonds formed between the doped ions and the ions of the surface region material have a second bond energy, which is greater than the first bond energy.

[0093] In this embodiment, the surface treatment process includes a first treatment process, which includes an ion doping process and an annealing process following the ion doping process.

[0094] In this embodiment, the process parameters of the ion doping process include: the doping ion includes fluorine ions, and the doping ion dose range is 1E14 atom / cm. 2 Up to 1E16 atom / cm 2 .

[0095] In this embodiment, the process parameters of the annealing process include: annealing temperature range of 900℃ to 1100℃, and annealing time range of 10s to 60s.

[0096] In this embodiment, the surface treatment process further includes a second treatment process, which includes a thinning process following the ion doping process.

[0097] In this embodiment, the thinning process includes a wet etching process.

[0098] Please refer to Figure 12 After the surface treatment, the mask material layer is etched to form a mask layer 304 and an opening (not shown in the figure) located in the mask layer 304, the opening exposing the surface of the substrate 300; using the mask layer 304 as a mask, a selective epitaxial growth process is used to form an epitaxial layer 305 on the substrate 300 exposed by the opening.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A germanium-silicon heterojunction bipolar transistor structure, characterized in that, include: The substrate includes a base and a current collector region located on the base; A mask layer structure located on the substrate, the mask layer structure including a mask layer having a first opening, the top surface of the current collector region being exposed below the first opening, the mask layer including a body region and a surface region located on the body region, the chemical bonds of the body region material having a first bond energy, the surface region containing doped ions, the chemical bonds formed by the doped ions and the ions of the surface region material having a second bond energy, the second bond energy being greater than the first bond energy; The main base region is located on the exposed surface of the collector region.

2. The germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The doped ions include fluorine ions; the chemical bonds of the host region material include silicon-nitrogen bonds, and the chemical bonds of the surface region material include silicon-fluorine bonds.

3. The germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The mask layer structure further includes a dielectric layer, two mutually independent outer base regions located on the surface of the dielectric layer, a second opening located within the dielectric layer and exposing the current collector region and a portion of the surface of the outer base regions, the mask layer located on the top surface and sidewalls of the outer base regions, the mask layer having a first opening and communicating with the second opening, the second opening exposing the current collector region and a portion of the outer base regions; the mask layer includes a cover layer located on the top surface of the outer base regions and a sidewall located on the sidewalls of the outer base regions.

4. A method for forming a germanium-silicon heterojunction bipolar transistor structure, characterized in that, include: A substrate is provided, the substrate comprising a base and a current collector region located on the base; A mask layer structure is formed on the substrate. The mask layer structure includes a mask layer with a first opening. The mask layer includes a host region and a surface region located on the host region. The chemical bonds of the host region material have a first bond energy. The surface region contains dopant ions. The chemical bonds formed by the dopant ions and the ions of the surface region material have a second bond energy, and the second bond energy is greater than the first bond energy. Using the mask layer as a mask, a primary base region is formed on the surface of the current collector region under the first opening using a selective epitaxial process.

5. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 4, characterized in that, The mask layer structure further includes a dielectric layer and two mutually separate outer base regions located on the surface of the dielectric layer. The dielectric layer has a second opening. The mask layer is located on the top surface and sidewall of the outer base regions, and the first opening and the second opening are interconnected. The second opening exposes the current collector region and a portion of the outer base regions. The mask layer includes a cover layer located on the top surface of the outer base regions and a sidewall located on the sidewall of the outer base regions. The main base region is located on the surface of the current collector region and a portion of the outer base regions exposed by the second opening.

6. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 5, characterized in that, The method for forming the mask layer structure includes: forming a dielectric material layer, two mutually discrete outer base regions located on the surface of the dielectric material layer, and an initial capping layer located on the top surface of the outer base regions on the substrate, wherein the outer base regions and the initial capping layer have an initial first opening; forming a sidewall material layer on the sidewall of the initial first opening; performing surface treatment on the initial capping layer and the sidewall material layer to form the capping layer with the initial capping layer, forming the sidewall with the sidewall material layer on the sidewall of the initial first opening, and using the initial first opening between the sidewalls as the first opening; after forming the mask layer, using the mask layer as a mask, etching the dielectric material layer to form the dielectric layer and the second opening.

7. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 6, characterized in that, After the second opening is formed and before the selective epitaxial process, the method further includes cleaning the surface of the current collector region exposed by the second opening.

8. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 6, characterized in that, The surface treatment process includes a first treatment process, which includes an ion doping process and an annealing process following the ion doping process.

9. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The process parameters for the ion doping process include: the doping ion includes fluorine ions, and the doping ion dose range is 1E14 atom / cm². 2 Up to 1E16atom / cm 2 .

10. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The process parameters of the annealing process include: annealing temperature range of 900℃ to 1100℃, and annealing time range of 10s to 60s.

11. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The surface treatment process further includes a second treatment process, which includes a thinning process following the ion doping process.

12. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 11, characterized in that, The thinning process includes wet etching.

13. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 11, characterized in that, The sidewall material layer is also located on the surface of the initial cover layer; the method further includes: after the first treatment and before the thinning process, etching back the sidewall material layer until the surface of the dielectric material layer is exposed.

14. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The sidewall material layer is also located on the surface of the initial cover layer; the method further includes: after the surface treatment, re-etching the sidewall material layer until the surface of the medium material layer is exposed.

15. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The sidewall material layer is also located on the surface of the initial cover layer; the method further includes: etching the sidewall material layer back before the surface treatment until the surface of the medium material layer is exposed.

16. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 5, characterized in that, Also includes: An emission region is formed on a portion of the surface of the primary base region, and the emission region and the outer base region are separate from each other.

17. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 4, characterized in that, The chemical bonds in the main region material include silicon-nitrogen bonds, and the chemical bonds in the surface region material include silicon-fluorine bonds.

18. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 4, characterized in that, The material of the main base region includes germanium and silicon.

19. A method for crystal growth using selective epitaxy, characterized in that, include: Provide substrate; A mask material layer is formed on the substrate, wherein the chemical bonds of the mask material layer have a first bond energy; The mask material layer is surface treated to form an exposed surface region within the mask material layer. The surface region contains doped ions, and the chemical bonds formed between the doped ions and the ions of the surface region material have a second bond energy, which is greater than the first bond energy. After the surface treatment, the mask material layer is etched to form a mask layer and an opening located within the mask layer, the opening exposing the substrate surface; Using the mask layer as a mask, an epitaxial layer is formed on the substrate exposed by the opening using a selective epitaxial growth process.

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