A perovskite / crystalline silicon tandem solar cell preparation method, cell and application

Abstract

The application provides a perovskite / crystalline silicon laminated solar cell preparation method, a cell and application. The body heterojunction film layer obtained by mixing N-type SAM and P-type SAM is used as a core tunneling layer, the performance of the tunneling layer is precisely optimized, the defects of a traditional technical solution are effectively solved, the photoelectric conversion efficiency and stability of a device are improved, and the perovskite / crystalline silicon laminated solar cell prepared by the method can be well applied to the field of space photovoltaics.

Description

Technical Field

[0001] This invention relates to the field of perovskite tandem solar cell technology, specifically to a method for fabricating perovskite / crystalline silicon tandem solar cells, the cells themselves, and their applications in space photovoltaics. Background Technology

[0002] Solar energy is a promising new clean energy source with advantages such as abundant resources and low cost. Currently, photovoltaic (PV) cells are one of the most efficient ways to convert solar energy into electricity, and monocrystalline silicon and polycrystalline silicon solar cells have relatively mature industrialization technologies. In recent years, perovskite / crystalline silicon tandem technology has become one of the research hotspots in the field of photovoltaic technology, attracting widespread attention. The development of this technology is of great significance for improving the photoelectric conversion efficiency of solar cells and reducing manufacturing costs, thereby promoting the further development and application of solar power generation technology. The theoretical effective photoelectric conversion efficiency of crystalline silicon / perovskite tandem solar cells is as high as 40% or more, far exceeding that of crystalline silicon solar cells. The basic principle of perovskite / crystalline silicon tandem technology is to stack perovskite materials and crystalline silicon materials together to form a heterojunction. By utilizing the wide bandgap, high absorption coefficient, and high carrier mobility of perovskite materials, and the stability and good electron transport performance of crystalline silicon materials, the photoelectric conversion efficiency of solar cells can be improved.

[0003] Currently, crystalline silicon / perovskite tandem solar cells commonly employ fully covered transparent conductive oxide films (such as ITO, FTO, or AZO) in their intermediate tunneling layer design. The thickness of these films is typically controlled within the range of 10-100 nm. However, due to the inherent optical properties of the materials, their light transmittance in the 300-1200 nm wavelength band (covering the main absorption spectral range of perovskite and crystalline silicon) is usually below 90%. This shortcoming in light transmittance directly leads to unnecessary reflection and absorption losses of incident light at the tunneling layer, reducing the number of photons entering the upper and lower active layers of the cell, thus affecting the overall light absorption efficiency of the device. At the same time, these transparent conductive oxide films possess both longitudinal and lateral conductivity, while high-efficiency tandem cells only require the tunneling layer to have excellent longitudinal charge transport characteristics. Its lateral conductivity, on the other hand, can promote lateral migration of electrons and holes at the interface and form ineffective recombination, resulting in non-recombination losses and ultimately leading to a decrease in the photoelectric conversion efficiency of the device. If the tunneling layer is directly eliminated to avoid the above problems, the hole transport layer of the P-type self-assembled small organic molecules (SAM, such as PTAA derivatives or spirocyclic materials) prepared by solution spin coating or blade coating in the perovskite top cell will directly contact the n-type polycrystalline silicon doped layer (usually prepared by phosphorus diffusion or ion implantation) on the surface of the TOPCON crystalline silicon bottom cell. This will cause serious carrier recombination loss and generate a large interfacial contact resistance due to the mismatch of the energy level structure of the two types of materials, the high interface defect state density, and the insufficient surface smoothness of the SAM film. Ultimately, this will still significantly degrade the key performance parameters of the device, such as open-circuit voltage and short-circuit current density.

[0004] This emerging cutting-edge technology will also face many challenges in its future applications. For example, in the application of space photovoltaics, although there will be more abundant light energy and conversion efficiency compared to ground-based scenarios, the space environment is characterized by ultra-high vacuum, extreme temperature cycles (-150℃ to +120℃), and strong ultraviolet / high-energy particle radiation. During use, it will also face the risks of thermal shock and microfluidics, and the possibility of maintenance is also low. Therefore, the reliability and long-term stability of solar cells are particularly important. Summary of the Invention

[0005] To address the problem of unnecessary reflection and absorption losses caused by the low light transmittance of the tunneling layer in traditional perovskite / crystalline silicon solar cells, this invention provides a method for fabricating a perovskite / crystalline silicon tandem solar cell and the cell itself. By using a bulk heterojunction layer of mixed N-type SAM and P-type SAM as the core tunneling layer, the performance of the tunneling layer is precisely optimized, effectively solving the defects of traditional technical solutions and improving the photoelectric conversion efficiency and stability of the device. The perovskite / crystalline silicon tandem solar cell prepared by this method can also be well applied in the field of space photovoltaics.

[0006] To achieve the above objectives, the present invention provides the following specific solution:

[0007] A method for fabricating a perovskite / crystalline silicon tandem solar cell includes the following steps: providing a crystalline silicon base cell, and sequentially fabricating an intrinsic heterojunction tunneling layer, a perovskite absorber layer, an electron transport layer, a transparent electrode layer, a second metal electrode layer, and an antireflection layer thereon, wherein the intrinsic heterojunction tunneling layer contains N-type SAM material and P-type SAM material.

[0008] The intrinsic heterojunction tunneling layer is prepared by a solution method, including the following steps: preparing an intrinsic heterojunction tunneling layer precursor solution; mixing and dissolving N-type SAM material and P-type SAM material in an organic solvent at a mass ratio of 1:5 to 5:1; uniformly coating the intrinsic heterojunction tunneling layer precursor solution onto the surface of the crystalline silicon bottom cell by spin coating at a speed of 1000-6000 rpm for 20-120 s; and then performing annealing treatment at a temperature of 50-150℃ for 5-40 min.

[0009] In one embodiment, the N-type SAM material comprises at least one of the following: naphthalimide (NI) series small molecules, N-(2,5-di-tert-butylphenyl)-N'-(methyl)-1,4,5,8-naphthalenetetracarboxydiimide phosphonic acid (PANDI), 3-[(9,10-dioxo-9,10-dihydroanthracene-2-yl)oxy]propylphosphonic acid (PAAQ), and 3-(7-butyl-1,3,6,8-tetraoxo-3,6,7,8-tetrahydrobenzo[lmn][3,8]phenanthroline-2(1H)-yl)propylphosphonic acid (NDP).

[0010] In one embodiment, the P-type SAM material includes at least one of 2PACz, Meo-2PACz, Meo-4PACz, Me-4PACz, Me-PhACz, etc.

[0011] In one embodiment, the organic solvent may be selected from at least one of IPA (isopropanol), ethanol, and toluene (CB).

[0012] In one embodiment, the crystalline silicon bottom cell includes, from bottom to top, a first metal electrode layer, an anti-reflection passivation layer, a substrate passivation layer, an N-type silicon substrate, a substrate surface passivation layer, and an N-type substrate doped layer, wherein the intrinsic heterojunction tunneling layer is fabricated on the N-type substrate doped layer.

[0013] In some embodiments, the crystalline silicon substrate cell can be prepared by the following steps: providing an N-type silicon substrate, preparing a substrate passivation layer on one side of the N-type silicon substrate, preparing an anti-reflection passivation layer on the surface of the substrate passivation layer, preparing a first metal electrode layer on the surface of the anti-reflection passivation layer; and preparing a substrate surface passivation layer on the other side of the N-type silicon substrate, and preparing an N-type substrate doped layer on the surface of the substrate surface passivation layer.

[0014] In one embodiment, the preparation method further includes preparing a passivation layer between the perovskite absorber layer and the electron transport layer.

[0015] In one embodiment, a buffer layer is further provided between the electron transport layer and the transparent electrode layer.

[0016] In another aspect, the present invention provides a perovskite / crystalline silicon tandem solar cell, which is prepared by the above-described preparation method.

[0017] The perovskite / crystalline silicon tandem solar cells described above can also be used in space photovoltaics.

[0018] This application provides a method for fabricating perovskite / crystalline silicon tandem solar cells, the cells themselves, and their applications. An intrinsic heterojunction tunneling layer, incorporating a mixture of N-type and P-type SAM materials, is introduced into the perovskite / crystalline silicon cell structure. Compared to traditional transparent conductive oxide tunneling layers, this method offers several significant advantages: 1. Benefiting from the low optical loss characteristics and ultra-thin film formation capability (film thickness controllable between 0.1-10 nm) of the organic small molecule materials, the transmittance of light in the 300-1200 nm wavelength band can be increased to over 95%, significantly reducing light absorption loss and providing a more sufficient photon supply to the upper and lower active layers; 2. It can significantly suppress the formation of lateral charge transport channels, reducing lateral conductivity by more than an order of magnitude, thereby effectively reducing ineffective lateral recombination of electrons and holes, lowering non-recombination losses, and improving the device's fill factor and conversion efficiency; 3. The intrinsic heterojunction structure allows N-type and P-type materials to form a three-dimensional interpenetrating contact network within the thin film, increasing the contact area by 2-3 times compared to traditional planar heterojunctions. 4. The N-type organic small molecules and P-type SAM molecules can form hydrogen bonds or van der Waals forces to achieve close integration of the two types of molecules during the film formation process, effectively improving the adhesion of the SAM film (the adhesion level can be improved to level 1 or above by cross-cut test), reducing problems such as film peeling and cracking, significantly improving the stability of the device under long-term light and humid heat environment, and extending the service life; 5. The method of this invention simplifies the preparation steps of the stacked battery, so that the tunneling layer and the hole transport layer of the perovskite top battery can be prepared in the same step. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the perovskite / crystalline silicon tandem solar cell structure described in this invention.

[0020] The labels in the figure are as follows: 110, First metal electrode layer; 111, Anti-reflection passivation layer; 112, Substrate passivation layer; 113, N-type silicon substrate; 114, Substrate surface passivation layer; 115, N-type substrate doped layer; 116, Intrinsic heterojunction tunneling layer;

[0021] 211. Perovskite absorption layer; 212. Passivation layer; 213. Electron transport layer; 214. Buffer layer; 215. Transparent electrode layer; 216. Antireflection layer; 217. Second metal electrode layer. Detailed Implementation

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0023] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the traditional fabrication of crystalline silicon / perovskite solar cells, a fully transparent conductive oxide film is typically used as the tunneling layer. The thickness of this type of film is usually controlled within the range of 10-100 nm. However, due to the inherent optical properties of the material, its light transmittance in the 300-1200 nm wavelength band (covering the main absorption spectral range of perovskite and crystalline silicon) is usually maintained below 90%. This shortcoming in light transmittance directly leads to unnecessary reflection and absorption losses of incident light at the tunneling layer, reducing the number of photons entering the upper and lower active layers of the cell, thus affecting the overall light absorption efficiency of the device. At the same time, this type of transparent conductive oxide film has both longitudinal and lateral conductivity. However, high-efficiency tandem cells only require the tunneling layer to have excellent longitudinal charge transport characteristics. Its lateral conductivity will instead promote the lateral migration of electrons and holes at the interface and form ineffective recombination, resulting in non-recombination losses, ultimately leading to a decrease in the photoelectric conversion efficiency of the device.

[0025] To address the aforementioned problems, this invention provides a method for fabricating a perovskite / crystalline silicon tandem solar cell, comprising the steps of: providing a crystalline silicon base cell, and sequentially fabricating thereon an intrinsic heterojunction tunneling layer 116, a perovskite absorber layer 211, a passivation layer 212, an electron transport layer 213, a buffer layer 214, a transparent electrode layer 215, a second metal electrode layer 217, and an antireflection layer 216, wherein the intrinsic heterojunction tunneling layer 116 contains N-type SAM material and P-type SAM material.

[0026] In this application, a bulk heterojunction film layer of mixed N-type SAM and P-type SAM is used as the core tunneling layer. By forming a three-dimensional interpenetrating contact network inside the film, it simultaneously serves as the carrier transport layer for the perovskite top cell, significantly accelerating the tunneling transport rate of carriers and further optimizing charge transport efficiency. The ultrathin film structure also improves the overall light transmittance of the device, greatly reduces light absorption loss, and provides a more sufficient photon supply for the upper and lower active layers of the cell. Secondly, the intrinsic heterojunction tunneling layer 116 with a three-dimensional interpenetrating structure can also suppress the formation of lateral charge transport channels, effectively reducing the ineffective recombination of electrons and holes during lateral transport, and improving the fill factor and conversion efficiency of the device. Hydrogen bonds or van der Waals forces can be formed between N-type organic small molecules and P-type SAM molecules, enabling the two types of molecules to achieve tight interlocking during film formation, effectively improving the adhesion of the SAM film, reducing problems such as film peeling and cracking, significantly improving the stability of the device under long-term light and humid heat environments, and extending its service life.

[0027] In one embodiment, the intrinsic heterojunction tunneling layer 116 is prepared by a solution method, including the following steps: preparing an intrinsic heterojunction tunneling layer precursor solution, mixing and dissolving N-type SAM material and P-type SAM material in an organic solvent at a mass ratio of 1:5 to 5:1, uniformly coating the intrinsic heterojunction tunneling layer precursor solution onto the surface of the crystalline silicon bottom cell by spin coating at a speed of 1000-6000 rpm for 20-120 s, and then performing annealing treatment at a temperature of 50-150℃ for 5-40 min.

[0028] In one embodiment, the N-type SAM material includes one of the following: naphthalimide (NI) series small molecules, N-(2,5-di-tert-butylphenyl)-N'-(methyl)-1,4,5,8-naphthalenetetracarboxydiimide phosphonic acid (PANDI), 3-[(9,10-dioxo-9,10-dihydroanthracene-2-yl)oxy]propylphosphonic acid (PAAQ), and 3-(7-butyl-1,3,6,8-tetraoxo-3,6,7,8-tetrahydrobenzo[lmn][3,8]phenanthroline-2(1H)-yl)propylphosphonic acid (NDP).

[0029] In one embodiment, the P-type SAM material includes at least one of 2PACz, Meo-2PACz, Meo-4PACz, Me-4PACz, Me-PhACz, etc.

[0030] In one embodiment, the organic solvent may be selected from at least one of IPA (isopropanol), ethanol, and toluene (CB).

[0031] In one embodiment, the crystalline silicon bottom cell includes a first metal electrode layer 110, an anti-reflection passivation layer 111, a substrate passivation layer 112, an N-type silicon substrate 113, a substrate surface passivation layer 114, and an N-type substrate doped layer 115, which are stacked sequentially from bottom to top, and the intrinsic heterojunction tunneling layer 116 is prepared on the N-type substrate doped layer 115.

[0032] In some embodiments, the crystalline silicon substrate cell can be prepared by the following steps: providing an N-type silicon substrate 113, preparing a substrate passivation layer 112 on one side of the N-type silicon substrate 113, preparing an anti-reflection passivation layer 111 on the surface of the substrate passivation layer 112, preparing a first metal electrode layer 110 on the surface of the anti-reflection passivation layer 111; and preparing a substrate surface passivation layer 114 on the other side of the N-type silicon substrate 113, and preparing an N-type substrate doped layer 115 on the surface of the substrate surface passivation layer 114.

[0033] Specifically, the substrate passivation layer 112 is deposited using atomic layer deposition (ALD) to deposit an aluminum oxide (Al2O3) film. Trimethylaluminum (TMA) is used as the aluminum source, and water or ozone is used as the oxygen source. The reaction source is alternately introduced at 150-250°C. The thickness is controlled to 5-20 nm by controlling the number of cycles to ensure that the film is uniform and dense.

[0034] Specifically, the anti-reflection passivation layer 111 can be prepared by plasma-enhanced chemical vapor deposition (PECVD), using silane (SiH4) and ammonia (NH3) as reactant gases. Under the action of a high-frequency electric field, plasma is generated, causing the gases to undergo a chemical reaction and deposit on the surface of the substrate passivation layer to form a silicon nitride (SiNx) film.

[0035] Specifically, the passivation layer 114 on the substrate surface is prepared using a thermal oxidation process, where a thin oxide layer (SiO2) is grown on the surface of the N-type silicon substrate 113; alternatively, a thermal oxidation method can be used, in which the N-type silicon substrate is placed in an oxidation furnace, and oxygen is introduced at a high temperature (typically 900-1000℃), causing the silicon wafer surface to react with oxygen to form an oxide layer (SiO2). The thickness of the oxide layer is generally 1-2 nm, and it is required to have good uniformity and insulation properties to achieve effective tunneling and passivation effects.

[0036] Specifically, the N-type substrate doped layer 115 is prepared using a PECVD process, depositing a doped polycrystalline silicon layer on the passivation layer 114 on the substrate surface. Chemical vapor deposition (CVD) can be used, with silane (SiH4) as the silicon source and phosphine (PH3) as the dopant source. The deposition temperature is typically 550-650℃, and the thickness of the polycrystalline silicon layer is usually 50-200 nm. Doping improves the conductivity of the polycrystalline silicon layer and simultaneously creates good contact with the tunneling layer.

[0037] In one embodiment, the first metal electrode layer 110 is deposited using a vapor deposition method, which includes placing the prepared substrate sample on a mask for vapor deposition, with a vapor deposition vacuum degree of 5 × 10⁻⁶. -5 -2×10 -4 Pa, evaporation temperature is 500-2000℃, evaporation rate is 0.1-5Å / S;

[0038] The perovskite absorber layer 211 is produced using a spin-coating flash evaporation method. A perovskite precursor solution is prepared and uniformly coated onto the surface of the intrinsic heterostructure tunneling layer 116. The spin-coating speed is 1000-6000 rpm, and the spin-coating time is 20-120 s. After spin-coating, a flash evaporation operation is performed for 10-60 s at a temperature of 0-100℃. After flash evaporation, an annealing treatment is performed at a temperature of 50-150℃ for 5-40 min.

[0039] Furthermore, the perovskite precursor solution contains an ABX3 structure, wherein the A-site is an organic cation, including CH3NH3. + (MA + ), NH2CH=NH2 + (FA + CH3CH2NH3 + or Cs + At least one of them;

[0040] The B site is a metal cation, including Pb. 2+ Sn 2+ At least one of them;

[0041] The X-position is a halide anion, including F. - Cl - ,Br - I - At least one of them.

[0042] The passivation layer 212 is deposited using a vapor deposition method, which involves evaporating the passivation layer material onto the surface of the perovskite absorber layer 211, with a vapor deposition vacuum degree of 1-5 × 10⁻⁶. -4The vapor deposition temperature is 50-400℃, and the evaporation rate is 0.05-1 Å / s. After evaporation, annealing is performed at a temperature of 0-150℃ for a time of 0-30 min.

[0043] The passivation layer 212 can also be applied using a spin-coating method. A passivation layer dispersion is prepared and uniformly coated onto the surface of the perovskite absorber layer 211. The spin-coating speed is 1000-7000 rpm, and the spin-coating time is 20-120 s. After spin-coating, an annealing operation is performed at a temperature of 40-160℃ for 5-40 min.

[0044] The passivation layer 212 can also be applied by spraying, by spraying the passivation layer dispersion onto the perovskite absorption layer 211 at a spraying rate of 0-100 cm / s. After spraying, an annealing operation is performed at a temperature of 20-170℃ for a time of 0-30 min.

[0045] The passivation layer dispersion is prepared by dissolving the passivation layer material in organic solvents including but not limited to methanol, ethanol, or isopropanol, followed by ultrasonic dissolution. The concentration is 0.1-6 mg / ml, and the ultrasonic time is 0-30 min.

[0046] The passivation layer material includes propylenediamine iodine, including but not limited to at least one of propylenediamine bromide (PDADBr), butylamine chloride (BACl), butylamine bromide (BABr), butylamine iodide (BAI), N,N-dimethyl-1,3-propanediamine hydrochloride (DMePDADCl), and dodecylamine bromide (DDDADBr); it may also be at least one of magnesium fluoride, lithium fluoride, and sodium fluoride.

[0047] In one embodiment, the electron transport layer 213 is produced by spin coating, in which the electron transport layer dispersion is uniformly spin-coated onto the surface of the passivation layer 212, with a spin coating speed of 500-4000 rpm and a spin coating time of 10-80 s.

[0048] Optionally, the electron transport layer 213 can also be deposited using a vapor deposition method, whereby the electron transport layer material is evaporated onto the surface of the passivation layer 212, with a vapor deposition vacuum degree of 5 × 10⁻⁶. -5 -5×10 -4 Pa, evaporation temperature is 100-400℃, evaporation rate is 0.05-1Å / S;

[0049] The electron transport layer dispersion comprises at least one solvent in which the electron transport layer material is dissolved in methanol, ethanol, or isopropanol.

[0050] The electron transport layer material includes zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), and methyl [6,6]-phenyl C61-butyrate (PC). 61 BM), C60 (C 60 At least one of ), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP).

[0051] In one embodiment, the buffer layer 214 is constructed using atomic layer deposition, which involves depositing the buffer layer material onto the surface of the electron transport layer 213 using an atomic layer deposition apparatus, with a deposition vacuum degree of 0-1×10⁻⁶. 4 Pa, the temperature of the deposition pipe is between 50-150℃, and the temperature of the deposition chamber is between 40-150℃;

[0052] Optionally, the buffer layer 214 can also be deposited using a vapor deposition method, whereby the buffer layer material is evaporated onto the surface of the electron transport layer 213, with a vapor deposition vacuum degree of 6 × 10⁻⁶. -5 -4×10 -4 Pa, evaporation temperature is 100-500℃, evaporation rate is 0.05-1Å / S;

[0053] Specifically, the buffer layer material includes at least one of zinc oxide (ZnO), tin dioxide (SnO2), and titanium dioxide (TiO2).

[0054] In one embodiment, the transparent electrode layer 215 is produced by magnetron sputtering, which involves sputtering transparent electrode material onto the surface of the buffer layer 214, with a controlled power of 30-200W.

[0055] Alternatively, the transparent electrode layer 215 can also be deposited using a vapor deposition method, whereby the transparent electrode material is evaporated onto the surface of the buffer layer 214, with a vapor deposition vacuum degree of 1×10⁻⁶. -5 -5×10 -4 Pa, evaporation temperature is 1000-2000℃, evaporation rate is 0.05-3Å / S.

[0056] The transparent electrode layer 215 is one of indium tin oxide, indium zinc oxide, and zinc aluminum oxide;

[0057] The vapor deposition method used for the second metal electrode layer 217 is similar to that of the first metal electrode layer 110, except that the mask is different.

[0058] The first metal electrode layer 110 and the second metal electrode layer 217 are one of silver, gold, copper, aluminum and carbon.

[0059] Specifically, the antireflection layer 216 can be prepared by magnetron sputtering or vapor deposition.

[0060] The antireflective layer 216 is at least one of magnesium fluoride, lithium fluoride (LiF), sodium fluoride (NaF), and silicon oxide (SiO2).

[0061] In another aspect, the present invention provides a perovskite / crystalline silicon tandem solar cell, which is prepared by the above-described preparation method.

[0062] The perovskite / crystalline silicon tandem solar cells described above can also be used in space photovoltaics.

[0063] The following specific embodiments and comparative examples clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0064] Example 1

[0065] Please see Figure 1 This embodiment provides a perovskite / crystalline silicon tandem solar cell, comprising, from bottom to top, a first metal electrode layer 110, an anti-reflection passivation layer 111, a substrate passivation layer 112, an N-type silicon substrate 113, a substrate surface passivation layer 114, an N-type substrate doped layer 115, an intrinsic heterojunction tunneling layer 116, a perovskite absorber layer 211, a passivation layer 212, an electron transport layer 213, a buffer layer 214, a transparent electrode layer 215, a second metal electrode layer 217, and an anti-reflection layer 216. The fabrication method of the tandem solar cell includes the following steps:

[0066] S(1) Provide an N-type silicon substrate 113, and prepare a substrate passivation layer 112 on the back side of the N-type silicon substrate 113. Deposit an aluminum oxide (Al2O3) thin film using atomic layer deposition (ALD), using trimethylaluminum (TMA) as the aluminum source and water or ozone as the oxygen source. Introduce the reaction source at 150°C, and control the thickness to 20 nm by controlling the number of cycles to ensure that the film is uniform and dense.

[0067] S(2) Deposit an anti-reflection passivation layer 111 on the substrate passivation layer 112. Use plasma-enhanced chemical vapor deposition (PECVD) with silane (SiH4) and ammonia (NH3) as reaction gases. Under the action of a high-frequency electric field, plasma is generated, causing the gases to undergo a chemical reaction and deposit on the surface of the substrate passivation layer 112 to form a SiNx film with a thickness of 90nm.

[0068] S(3) A first metal electrode layer 110 is prepared on the anti-reflection passivation layer 111. Aluminum paste is printed by screen printing, and after printing, it is dried and sintered to form good ohmic contact between the metal paste and the silicon wafer surface. The sintering temperature is 900℃. By controlling the sintering temperature and time, the conductivity and adhesion of the electrode are improved.

[0069] S(4) A passivation layer 114 is prepared on the front side of the N-type silicon substrate 113. The silicon wafer is placed in an oxidation furnace by thermal oxidation. Oxygen is introduced at a high temperature (1000℃). The silicon wafer surface reacts with oxygen to generate a SiO2 layer with a thickness of 1.5nm.

[0070] S(5) Deposit an N-type substrate doped layer 115 on the passivation layer 114 on the substrate surface. Chemical vapor deposition (CVD) is used, with silane (SiH4) as the silicon source and phosphine (PH3) as the dopant source, to prepare an n-type polycrystalline silicon layer as needed. The deposition temperature is generally 650℃ and the thickness is 50nm.

[0071] S(6) An intrinsic heterojunction tunneling layer 116 is prepared on an N-type substrate doped layer 115. The intrinsic heterojunction tunneling layer 116 is prepared by solution method. An intrinsic heterojunction tunneling layer precursor solution is prepared by mixing N-type SAM material NDP and P-type SAM material MeO-4PACz at a mass ratio of 1:1 and dissolving them in the organic solvent IPA, with a concentration of 0.5 mg / mL. The intrinsic heterojunction tunneling layer precursor solution is uniformly coated on the surface of the N-type substrate doped layer 115 by spin coating at a speed of 6000 rpm for 120 s. Then, annealing is performed at a temperature of 100℃ for 5 min to form an ultrathin intrinsic heterojunction tunneling layer 116 with a thickness of 0.5 nm.

[0072] S(7) The perovskite layer 211 is prepared by flash evaporation, including the following steps: Dissolve perovskite powder with ABX3 structure in 1 ml of DMF and DMSO solvent, with a solvent ratio of 8:2. After stirring, a perovskite precursor solution is obtained. The battery substrate is placed on a spin coater, and the spin coating speed is set to 3500 rpm and the spin coating time is 30 s. The perovskite precursor solution volume is 120 μl and coated on the surface of the battery substrate. After spin coating, the substrate is transferred to a flash evaporation stage, and the flash evaporation time is set to 30 s and the flash evaporation temperature is 30 °C. After flash evaporation, annealing is performed, and the annealing temperature is set to 100 °C and the annealing time is 15 min to obtain the perovskite absorber layer 211 with a thickness of about 500 nm.

[0073] S(8) Preparation of passivation layer 212: Using vapor deposition, 3 mg of propylenediamine iodine was weighed and placed in a crucible. The sample obtained in the above steps was placed on a mask and put into the vapor deposition chamber. The vapor deposition vacuum was set to 2 × 10⁻⁶. -4Evaporation was performed at Pa, the evaporation voltage was adjusted to the evaporation temperature, and the evaporation rate was controlled at 0.1 Å / S. Propylene diamine iodine was deposited onto the film with a thickness of 4 nm. After the evaporation, the annealing station temperature was set to 100 °C and annealing was performed for 8 min.

[0074] S(9), C 60 The electron transport layer 213 is prepared by evaporation onto the surface of the passivation layer 212. The thickness of the electron transport layer 213 is 20 nm, and the vacuum degree of the evaporation is 1 × 10⁻⁶. -4 Pa, evaporation temperature at 200℃, evaporation rate at 0.1 Å / S.

[0075] S(10) SnO2 is deposited onto the surface of the electron transport layer 213 using atomic layer deposition equipment to prepare the buffer layer 214. The thickness of the buffer layer 214 is 15 nm, and the vacuum degree of the deposition is 0.5 × 10⁻⁶. 4 Pa, the temperature of the deposition pipe is 70℃, and the temperature of the deposition chamber is 60℃.

[0076] S(11) The transparent electrode layer 215 is prepared on the surface of the buffer layer 214 by magnetron sputtering. The thickness of the transparent electrode layer 215 is 100 nm. The target material of the magnetron sputtering method is indium zinc oxide (IZO), the power of the magnetron sputtering method is 50 W, and the running time of the magnetron sputtering method is 1 h.

[0077] S(12) Place the substrate sample prepared in the previous step on a mask, and deposit silver (Ag) on ​​the surface of the transparent electrode layer 215 using a vapor deposition method to prepare the second metal electrode layer 217. The thickness of the second metal electrode layer 217 is 100 nm, wherein the vacuum degree of the vapor deposition is 2 × 10⁻⁶. -4 Pa, temperature 800℃, evaporation rate 0.1 Å / S.

[0078] S(13) Place the substrate sample prepared in the previous step on a mask, evaporate magnesium fluoride onto the surface of the second metal electrode layer 217 using a vapor deposition method, and anneal it to prepare the antireflection layer 216. The thickness of the antireflection layer is 100 nm, wherein the vapor deposition vacuum degree is 2 × 10⁻⁶. -4 The perovskite / crystalline silicon tandem solar cell was obtained by evaporation at 80℃, evaporation rate at 2Å / s, annealing temperature at 100℃, and annealing time at 8min.

[0079] Example 2

[0080] The fabrication process of this embodiment is the same as that of the stacked solar cell described in Embodiment 1, except that the specific steps of step S (6) in this embodiment are as follows:

[0081] S(6) An intrinsic heterojunction tunneling layer 116 is prepared on an N-type substrate doped layer 115. The intrinsic heterojunction tunneling layer 116 is prepared by solution method. An intrinsic heterojunction tunneling layer precursor solution is prepared by mixing N-type SAM material NDP and P-type SAM material MeO-4PACz at a mass ratio of 1:1 and dissolving them in the organic solvent IPA, with a concentration of 1 mg / mL. The intrinsic heterojunction tunneling layer precursor solution is uniformly coated on the surface of the N-type substrate doped layer 115 by spin coating at a speed of 6000 rpm for 120 s. Then, annealing is performed at a temperature of 100℃ for 5 min to form an ultrathin intrinsic heterojunction tunneling layer 116 with a thickness of 1 nm.

[0082] Example 3

[0083] The fabrication process of this embodiment is the same as that of the stacked solar cell described in Embodiment 1, except that the specific steps of step S (6) in this embodiment are as follows:

[0084] S(6) An intrinsic heterojunction tunneling layer 116 is prepared on an N-type substrate doped layer 115. The intrinsic heterojunction tunneling layer 116 is prepared by solution method. An intrinsic heterojunction tunneling layer precursor solution is prepared by mixing N-type SAM material NDP and P-type SAM material MeO-4PACz at a mass ratio of 1:1 and dissolving them in the organic solvent IPA, with a concentration of 2 mg / mL. The intrinsic heterojunction tunneling layer precursor solution is uniformly coated on the surface of the N-type substrate doped layer 115 by spin coating at a speed of 6000 rpm for 120 s. Then, annealing is performed at a temperature of 100℃ for 5 min to form an ultrathin intrinsic heterojunction tunneling layer 116 with a thickness of 2 nm.

[0085] Comparative Example 1

[0086] In this comparative example, the tandem solar cell uses a traditional hole transport layer fabrication process, which is basically the same as that in Example 1. The difference is that in this comparative example, step S(6) is a traditional tunneling layer + hole transport layer fabrication process. The specific steps are as follows:

[0087] S(6) Using magnetron sputtering, the sample is placed on a mask and then placed in a magnetron sputtering device. The power is controlled at 60W and the running time is 1h to form an ITO thin film with a film thickness of 40nm.

[0088] The prepared sample was treated with UV-Ozone for 15 min, and then nickel oxide (NiO) was sputtered using magnetron sputtering at a power of 30 W for 60 min. x The material is prepared on the ITO thin film with a controlled thickness of 40 nm.

[0089] The perovskite / crystalline silicon tandem solar cells obtained in Examples 1-3 and Comparative Example 1 were tested under the following conditions: a standard solar intensity calibration was performed using a solar simulator, and the solar cells with an area of ​​1.0 cm² were tested. 2 The device in this embodiment underwent a long-term IV test, with the starting voltage set to 2V, the cutoff voltage to 0V, and the range to 100mA. The results were rounded to one decimal place. The test results are shown in Table 1 below.

[0090] Table 1 shows the performance of the tandem solar cells described in Examples 1-3 and Comparative Example 1.

[0091] Devices Average light transmittance of tunnel layer Tunneling layer sheet resistance Open circuit voltage (V) <![CDATA[Short-circuit current (mA / cm 2 )]]> Photoelectric conversion efficiency (%) Annual depreciation rate (%) Example 1 97% ∞ 1.94 21.2 31.5 -0.6 Example 2 96% ∞ 1.96 21.1 32.0 -0.6 Example 3 95% ∞ 1.95 21.0 31.6 -0.6 Comparative Example 1 89% 200Ω / £ 1.94 20.8 29.9 -1.1

[0092] As shown in Table 1, compared with the traditional device (i.e. the one obtained in Comparative Example 1), the device obtained by this method (i.e. Examples 1-3) optimizes the tunneling layer design, significantly improves the light transmittance of the tunneling layer and controls its sheet resistance characteristics, effectively improving the optoelectronic performance and long-term stability of the device. This is reflected in the stacked devices of Examples 1-3, which employ the novel structure of this invention. The average transmittance of their tunneling layers reaches 97%, 96%, and 95%, respectively, all significantly higher than the 89% of Comparative Example 1, which uses a traditional tunneling layer structure. Furthermore, the sheet resistance of the tunneling layers in Examples 1-3 is ∞, exhibiting insulating characteristics, a significant difference from the 200Ω / Ω of Comparative Example 1. Correspondingly, the short-circuit currents of Examples 1-3 are 21.2 mA / cm², 21.1 mA / cm², and 21.0 mA / cm², respectively; the photoelectric conversion efficiencies reach 31.5%, 32.0%, and 31.6%, respectively; and the annual attenuation rate is -0.6%, all superior to the 20.8 mA / cm², 29.9%, and -1.1% of Comparative Example 1, respectively. The open-circuit voltage of Example 2 reaches 1.96V, also higher than the 1.94V of Comparative Example 1. Simultaneously, this invention also optimizes the performance of the tunneling layer, with Example 2 exhibiting the best overall performance. This is reflected in the photoelectric conversion efficiency of 32.0% in Example 2, which is higher than that of Comparative Example 1 (29.9%), Example 1 (31.5%), and Example 3 (31.6%). Furthermore, its open-circuit voltage, short-circuit current, and annual decay rate also remain at excellent levels, further verifying the superiority of the structure of the present invention.

[0093] The above embodiments are merely preferred embodiments of the present invention. It should be noted that, for those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle of the present invention. All technical solutions after making equivalent substitutions to the claims of the present invention fall within the protection scope of the present invention, which is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a perovskite / crystalline silicon tandem solar cell, characterized in that, The steps include: providing a crystalline silicon bottom cell, and sequentially fabricating an intrinsic heterojunction tunneling layer, a perovskite absorption layer, an electron transport layer, a transparent electrode layer, a second metal electrode layer, and an antireflection layer thereon, wherein the intrinsic heterojunction tunneling layer contains N-type SAM material and P-type SAM material; The intrinsic heterojunction tunneling layer is prepared by a solution method, including the following steps: preparing an intrinsic heterojunction tunneling layer precursor solution; mixing and dissolving N-type SAM material and P-type SAM material in an organic solvent at a mass ratio of 1:5 to 5:1; uniformly coating the intrinsic heterojunction tunneling layer precursor solution onto the surface of the crystalline silicon bottom cell by spin coating at a speed of 1000-6000 rpm for 20-120 s; and then performing annealing treatment at a temperature of 50-150℃ for 5-40 min.

2. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The N-type SAM material includes at least one of the following: naphthalimide (NI) series small molecules, N-(2,5-di-tert-butylphenyl)-N'-(methyl)-1,4,5,8-naphthalenetetracarboxydiimide phosphonic acid (PANDI), 3-[(9,10-dioxo-9,10-dihydroanthraphen-2-yl)oxy]propylphosphonic acid (PAAQ), and 3-(7-butyl-1,3,6,8-tetraoxo-3,6,7,8-tetrahydrobenzo[lmn][3,8]phenanthroline-2(1H)-yl)propylphosphonic acid (NDP).

3. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The P-type SAM material includes at least one of 2PACz, Meo-2PACz, Meo-4PACz, Me-4PACz, and Me-PhACz.

4. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The organic solvent is selected from at least one of isopropanol, ethanol, and toluene.

5. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The crystalline silicon bottom cell includes, from bottom to top, a first metal electrode layer, an anti-reflection passivation layer, a substrate passivation layer, an N-type silicon substrate, a substrate surface passivation layer, and an N-type substrate doped layer, wherein the intrinsic heterojunction tunneling layer is fabricated on the N-type substrate doped layer.

6. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, It also includes preparing a passivation layer between the perovskite absorber layer and the electron transport layer.

7. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, It also includes a buffer layer disposed between the electron transport layer and the transparent electrode layer.

8. A perovskite / crystalline silicon tandem solar cell, characterized in that, It is obtained by the preparation method according to any one of claims 1-7.

9. An application of the perovskite / crystalline silicon tandem solar cell according to claim 8 in the field of space photovoltaics.

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