A receiver synchronization system based on FPGA and implementation method thereof

Abstract

The present invention discloses a receiver synchronization system based on FPGA and an implementation method thereof, which relates to the field of information transmission technology. Aiming at the time-frequency synchronization problem of high-speed power line carrier and high-speed wireless dual-mode communication system on baseband, the present invention firstly implements improved timing and frequency synchronization schemes for wired and wireless based on FPGA (field programmable gate array), and proposes an adaptive frequency offset compensation idea, and finally outputs correctly synchronized wired and wireless frequency domain data.

Description

Technical Field

[0001] The present invention relates to the technical field of information transmission, and in particular to a receiver synchronization system based on FPGA and an implementation method thereof. Background Art

[0002] Communication is an important way to transmit information between people. With the development of the times, the ways of communication have become diversified. Even people and everything, everything and everything can communicate with each other. As a result, many communication methods have been born, including wired communication and wireless communication. However, the communication methods with low cost, easy installation and long transmission distance are represented by power line carrier communication and wireless communication. Power line carrier communication is a power system communication that uses transmission cables to transmit high-speed data in the form of carrier waves. It is widely used in smart homes, smart grids, and the Internet of Things. Wireless communication is a communication method that uses electromagnetic wave signals to transmit data. It can be used for long-distance transmission and communication and is used in various mobile and portable devices.

[0003] In the power system of the State Grid, the single-mode communication technology based on power line carrier communication or wireless communication is currently widely used. For single wired communication, the power line channel has the disadvantages of strong time-varying, frequency selectivity and various interference noises, which will lead to unreliable communication. Similarly, for a single wireless communication method, due to limited bandwidth, there is multipath fading in mobile communication, which will be affected by distance, terrain, obstacles, weather environment and wireless interference, resulting in a low communication success rate. It is precisely because of the significant defects of the single communication technology that the signal is unstable and the reception effect is poor. As modern communication technology enters a high-speed development stage, a more stable and effective dual-mode communication technology, which uses power lines and wireless data transmission based on OFDM (orthogonal frequency division multiplexing technology) The communication equipment was born. It can evaluate the effects of the two communication technologies according to the changes in the external channel environment, and has the effect of adaptive selection, which improves the stability, reliability and success rate of communication reception of the communication system. Whether it is a single communication system or a dual-mode communication system, synchronization technology is a key technology to verify whether the communication is effective, and synchronization efficiency is also an important indicator in high-speed communication.

[0004] Single-mode communication only needs to process data from a single channel. In order to ensure better performance, more complex algorithms are often selected to achieve frame synchronization and symbol synchronization. For frame synchronization, energy detection or delayed autocorrelation methods are often used. For symbol synchronization, algorithms such as preamble-based cross-correlation peak synchronization, synchronization based on CP (cyclic prefix) in data, and blind symbol synchronization are often used. For frequency synchronization, blind estimation algorithms and data-assisted algorithms based on preambles, CPs, or pilots are often used. For dual-mode communication systems, data from two channels needs to be processed. If conventional solutions are continued to be used to implement these algorithms, a large amount of hardware resources will inevitably be consumed. For example, the key technology research of power line communication system based on OFDM and its FPGA implementation (Wang Guorui. Xidian University, 2019. DOI: 10.27389 / d.cnki.gxadu.2019.002238.) proposed to rely on the delay correlation energy algorithm to perform grouping, and then implement the symbol synchronization algorithm by quantizing the local leading sequence. The separate implementation not only has low synchronization efficiency, but also occupies a large number of resources because the leading sequence is quantized. The wireless synchronization algorithm proposed in the research on ship wireless communication synchronization technology using OFDM orthogonal frequency division multiplexing technology (Zhang Chaoxian, Xu Fan. Ship Science and Technology, 2022, 44(16): 134-137.) will greatly occupy resources, and has not considered the problems of missed synchronization and false synchronization caused by wireless channels. In summary, for dual-mode communication systems, it is required to achieve synchronization quickly, ensure synchronization accuracy, and occupy fewer resources, which puts high demands on the design of the synchronization system.

[0005] For the synchronization method of the existing dual-mode communication system, due to the different preamble structure designs of wired and wireless data, the synchronization system needs to be designed separately. The traditional solution is to deploy the wired and wireless physical layer implementations on two platforms, or to achieve wired and wireless physical layer synchronization separately. At this time, designing the synchronization module according to the conventional algorithm will lead to greater system complexity and resource consumption. Since the OFDM system is sensitive to frequency deviation, Doppler shift and inconsistency of the transmit and receive crystal oscillators will produce frequency deviation, which destroys the orthogonality between the subcarriers, so frequency deviation compensation is required. Conventional frequency deviation estimation algorithms often compensate for data directly, and there are few solutions for adaptive configuration of local crystal oscillator frequencies. As for those solutions that modify the crystal oscillator frequency, the local crystal oscillator is frequently modified through the VCO, which not only fails to ensure the stability of the clock, but also has too high an implementation cost. Based on this, the synchronization method proposed in the present invention makes full use of the ingenuity of the preamble design, combines energy detection and the high-speed parallelism of FPGA, improves the efficiency and accuracy of frame synchronization and symbol synchronization, and appropriately simplifies the synchronization algorithm of the power line high-speed carrier and high-speed wireless, reduces the complexity and resource consumption of the dual-mode synchronization system with a small performance loss, and combines with adaptive technology to use the estimated frequency to adaptively adjust the clock frequency of the receiving end to meet the set frequency deviation range, thereby realizing an adaptive, high-efficiency, low-power and low-cost synchronization architecture on the FPGA. Summary of the invention

[0006] The purpose of the present invention is to provide a receiver synchronization system based on FPGA and an implementation method to solve the above technical problems.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] A method for implementing a receiver synchronization system based on FPGA includes the following steps:

[0009] (1) FPGA initializes the configuration of AD;

[0010] (2) The decoupled power line carrier signal is processed to obtain wired frequency domain data;

[0011] (3) After wireless signal processing, wireless frequency domain data is obtained.

[0012] As a further solution of the present invention: the specific steps in step (2) are as follows:

[0013] The power line carrier signal passes through the first AD channel to obtain wired baseband data. The approximate position of a frame is detected by the energy detection module and the wired frame synchronization module. After the correct position is detected by the wired symbol synchronization module, the frequency synchronization module uses the statistical averaging method to estimate the accurate frequency deviation and compensate for it. The frequency deviation obtained at this time can be fed back to the AD by the FPGA, and finally the wired frequency domain data of the accurate position is output.

[0014] As a further solution of the present invention: the wired frame synchronization module implements frame synchronization specifically as follows: after the wired leading signal is processed, a positive peak value and a negative peak value are generated, and the wired frame synchronization module can determine the approximate position according to the positive peak value to complete the frame synchronization;

[0015] As a further solution of the present invention: the wired symbol synchronization module determines the exact position when the peak value changes from positive to negative, completes the symbol synchronization, and the autocorrelation peak value is calculated as follows:

[0016]

[0017] As a further solution of the present invention: the specific steps in step (3) are as follows:

[0018] The antenna of the second AD channel starts to receive wireless signals and obtains wireless baseband data after down-conversion. After the approximate position of a frame is detected by the energy detection module and the wireless frame synchronization module, the frequency synchronization module uses the statistical averaging method to perform multiple estimates and compensation using a short training sequence. The frequency deviation obtained at this time can also be fed back to the AD by the FPGA. Finally, the wireless frequency domain data of the accurate position is obtained by the wireless symbol synchronization module.

[0019] As a further solution of the present invention: the wireless frame synchronization module implements the wireless frame synchronization. The specific operation is as follows: combining the leading short training S symbol to complete the packet detection, performing cross-correlation operation on the received IQ path data and the S symbol and squaring them to obtain the peak value C t 2 The calculation is as follows:

[0020]

[0021] As a further solution of the present invention: the hardware implementation of the wireless symbol synchronization module includes: first, the data obtained by the wireless frame synchronization module is cached through RAM, each data corresponds to an address, and then a high-speed clock that is much larger than the data rate is used to perform 3n high-speed serial cross-correlation operations from (Dn*N2) to position D, and then the obtained correlation peaks are compared to find the address corresponding to the maximum value, and the data in the RAM is taken out from this address to accurately complete the symbol synchronization.

[0022] As a further solution of the present invention: the frequency synchronization module includes carrier synchronization and sampling synchronization; the specific operation of the carrier synchronization includes: firstly, according to the carrier frequency deviation angle obtained by cross-correlation between the input data and the local preamble, the carrier frequency deviation compensation is performed on the input data cached in the RAM to complete the carrier synchronization;

[0023] The specific operations of the sampling synchronization include: then transforming the time domain data into the frequency domain through FFT, then extracting the pilot data therefrom, performing cross-correlation operation with the local pilot to obtain the sampling frequency deviation angle, and performing sampling frequency deviation compensation on the frequency domain data cached in the RAM; performing sampling frequency deviation compensation on the sampling frequency deviation angle and the data cached in the RAM, and then adjusting the data sequence back to the sequence before IFFT to complete sampling synchronization; sending the output sampling frequency deviation angle to the module for configuring the AD clock of the FPGA to reduce the sampling error, and setting the deviation of the sampling clock within ±0.5ppm. If the estimated sampling frequency deviation exceeds this range, the AD sampling clock is adjusted through the proportional integral differential controller to correct the deviation. When the next frame of data arrives, the sampling clock of the receiving end will become more and more accurate until the sampling clock deviation is adjusted to within ±0.5ppm.

[0024] A receiver synchronization system based on FPGA, implementing any one of the above implementation methods, the receiver system comprising:

[0025] High-speed AD (analog-to-digital converter) module, used to achieve high-speed acquisition of wired and wireless baseband data;

[0026] Energy detection module, used to realize automatic control of the amplitude of received data and determination of dynamic threshold;

[0027] The wired synchronization module is used to realize the frame synchronization, symbol synchronization and frequency synchronization of the wired baseband data and detect the accurate starting position of a frame of data;

[0028] The wireless synchronization module is used to achieve frame synchronization, symbol synchronization and frequency synchronization of wireless baseband data and detect the accurate starting position of a frame of data.

[0029] Beneficial effects of the present invention:

[0030] The present invention combines the design structure of the leader and proposes an improved method based on the existing synchronization method. The wired and wireless synchronization architectures are implemented together, and a specific implementation method for FPGA is given; first, the wireless frame synchronization is based on the implementation of the cross-correlation algorithm, combined with the energy detection algorithm, and the threshold dynamic processing is used as the judgment condition to solve the problem of threshold uncertainty caused by changes in the channel environment, and realize a frame synchronization algorithm that adapts to the channel environment. The present invention improves the wired symbol synchronization algorithm. On the basis of frame synchronization, the leader design structure is used to quickly implement the symbol synchronization algorithm, which improves the synchronization efficiency and saves hardware resources.

[0031] The present invention improves the wireless symbol synchronization method, adopts the cross-correlation method of 3n groups of N2 points to save resources, and in order to avoid missed and wrong synchronization, 3n such cross-correlation calculations are performed through a high-speed clock, which can quickly compare the maximum value to obtain the accurate position, greatly improving the synchronization accuracy. Finally, the frequency synchronization adopts the statistical averaging method to reduce the estimation error, and proposes a low-cost adaptive frequency offset compensation scheme to improve the ability of the synchronization system to adapt to the environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention will be further described below in conjunction with the accompanying drawings.

[0033] Figure 1 It is a schematic diagram of the power line high-speed carrier and high-speed wireless receiver synchronization system of the present invention;

[0034] Figure 2 It is the power line high-speed carrier preamble symbol structure of the present invention;

[0035] Figure 3 It is a high-speed wireless preamble symbol structure of the present invention;

[0036] Figure 4 It is the wired frame synchronization and symbol synchronization module of the present invention;

[0037] Figure 5 It is a wired synchronous correlation peak simulation diagram of the present invention;

[0038] Figure 6 It is a wireless frame synchronization module of the present invention;

[0039] Figure 7 It is a simulation diagram of the wireless synchronization correlation peak of the present invention;

[0040] Figure 8 It is the wireless symbol synchronization module of the present invention;

[0041] Fig. 9 The invention relates to a wired and wireless frequency synchronization module. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] See also Figure 1-9 As shown, the present invention is a receiver synchronization system based on FPGA and an implementation method, the overall architecture is as follows Figure 1 As shown, a receiver synchronization system based on FPGA includes a high-speed AD (analog-to-digital converter) module, an energy detection module, a wired synchronization module and a wireless synchronization module.

[0044] First, FPGA initializes the configuration of AD, including receiving gain, carrier frequency, sampling frequency, bandwidth and other parameters. Then, the decoupled power line carrier signal passes through the first AD channel to obtain wired baseband data. The approximate position of a frame is detected by the energy detection module and the wired frame synchronization module. After the correct position is detected by the wired symbol synchronization module, the wired frequency synchronization module needs to use the statistical averaging method to estimate the accurate frequency deviation and make compensation. At this time, the obtained frequency deviation can be fed back to AD by FPGA, and finally the wired frequency domain data of the accurate position is output.

[0045] At the same time, the antenna of the second AD channel starts to receive wireless signals and obtains wireless baseband data after down-conversion. After the approximate position of a frame is detected by the energy detection module and the wireless frame synchronization module, the wireless frequency synchronization module needs to use the statistical averaging method to perform multiple estimates and compensation using a short training sequence. The frequency deviation obtained at this time can also be fed back to the AD by the FPGA, and finally the wireless frequency domain data of the accurate position is obtained by the wireless symbol synchronization module.

[0046] The design differences between wired and wireless preamble structures are as follows Figure 2 , Figure 3 As shown, since the preamble sequence structure is repeated, the wired training sequence interval is M1 point, the wireless short training sequence interval is M2 point, and the long training sequence interval is N2 point. Therefore, the peaks obtained by using the preamble-based cross-correlation algorithm will also be spaced at M1 and M2 respectively. The accurate synchronization position can be found based on this feature. The present invention mainly gives specific descriptions of the FPGA implementation methods of wired and wireless synchronization, respectively.

[0047] 1) Wired frame synchronization and symbol synchronization module

[0048] Depend on Figure 2As shown, the wired pilot signal is composed of 10.5 SYNCP symbols and 2.5 negative SYNCP symbols. The first 10 SYNCP symbols will produce a positive correlation peak when their correlation values ​​are calculated, and the last 2 negative SYNCP symbols will produce a negative correlation peak when their correlation values ​​are calculated. Therefore, the wired can determine the approximate position based on the positive correlation peak to complete frame synchronization, and then determine the exact position at the moment when the peak changes from positive to negative to complete symbol synchronization. Therefore, the wired frame synchronization and symbol synchronization can be implemented in the same module. The autocorrelation peak calculation is as follows: (* indicates taking the conjugate, M1 is the length of the cross-correlation sequence)

[0049]

[0050] Where M1 is the length of the wired cross-correlation sequence, r t+m is the input signal at the current time t and after time m, so m takes values ​​from 0 to M1-1, S m * is the conjugate of the local leader, C t is the cross-correlation peak.

[0051] The numerator in the above formula represents the conjugate cross-correlation sum of the wired received data and the local pilot data at point M1, and the denominator represents the energy of the received signal. Since the wired pilot interval is generally large, and the input data bit width is also large, as long as the sign bit of the received data is correct, the peak value of the cross-correlation with the local pilot will not be wrong, and the received data can be correctly synchronized. In order to facilitate the implementation of the above algorithm in hardware and reduce resource consumption, the above formula is improved, and the input data is quantized, with positive numbers as 1 and negative numbers as -1. The formula of the data quantization function P is defined as follows:

[0052]

[0053] Quantizing the received data will transform the complex cross-correlation operation into addition and subtraction operations, saving a large number of multipliers. It is only necessary to use the sign bit of the input data as the judgment condition to accumulate and sum the leading data values. This not only greatly reduces the amount of calculation, but also improves the synchronization efficiency. The quantized formula is as follows:

[0054]

[0055] Where M1 is the length of the wired cross-correlation sequence, r t+m is the input signal at the current time t and after time m, so m takes values ​​from 0 to M1-1, S m * is the conjugate of the local leader, C t is the cross-correlation peak.

[0056] The hardware implementation block diagram of wired synchronization is as follows: Figure 4 As shown in the figure, the received data is first quantized to {-1,1}, and the quantized signal is cross-correlated with the local SYNCP symbol at point M1, that is, the adder and register array resources of the FPGA are used, and the symbol of the received data is used as the judgment condition. Then, the sum of M1 leading data is calculated through the for command, and then the sum of M1 / 2 data is calculated, and then the sum of M1 / 4 data is calculated, and so on. Finally, the sum of the two numbers is calculated, so that the simplified M1 point cross-correlation operation is realized within log2(M1) clocks. Figure 5 As shown, since the received data is quantized, the quantization threshold is fixed. The fixed threshold menxian_set can be set to 6000-9000 and does not need to be changed. As shown in the figure, there are 10 positive peaks and 2 negative peaks. The state machine is used to search for positive peaks. First, the state machine is in the initial state. If it is greater than the threshold menxian_set, it is considered that a positive peak is detected. If the next peak differs from the first peak by (M1±4) points, it is considered to be a related peak, and the state machine switches to the next state. Otherwise, it is determined that the first peak is caused by interference, and the state machine returns to the initial state. Similarly, if the next peak differs from the second peak by (M1±4) points, it is considered to be a related peak, and the state machine switches to the next state. Otherwise, it returns to the initial state until 5 positive peaks can be correctly detected, which means that frame synchronization is completed, and the state machine also returns to the initial state. Then the valid data and enable signal are sent to the negative peak search module. If it is less than the threshold -menxian_set, it is considered that a negative peak is detected. Another state machine is used to search for the transition from the positive peak to the negative peak, which is the accurate starting position of the data, indicating that the wired symbol synchronization is completed. Finally, the wired time domain data at the accurate position is output, and the synchronization enable signal is pulled high at the same time. In addition, according to the detected data energy value, the amplitude of its valid data is automatically controlled to ensure that no matter how large the signal input is, the amplitude of the synchronization module output is always within a certain range, which also brings convenience to the design of subsequent modules.

[0057] 2) Wireless frame synchronization

[0058] Wireless frame synchronization can be combined with the leading short training S symbol to complete packet detection, and the received IQ data and S symbol are cross-correlated and squared to obtain the peak value C. t 2 , as shown below: (* indicates conjugation, M2 is the length of the cross-correlation sequence)

[0059]

[0060] Where M2 is the length of the wireless cross-correlation sequence, r t+mis the input signal at the current time t and after time m, so m takes values ​​from 0 to M2-1, S m * is the conjugate of the local leader, C t 2 is the square of the cross-correlation peak.

[0061] Using hardware to directly implement the above formula will consume a lot of resources and cause large delays, which will affect the synchronization performance. The sign bit of the wireless preamble sequence is fixed, so it is necessary to quantize the local short training S symbol, with a positive number of 1 and a negative number of -1. The formula of the preamble symbol quantization function P is defined as follows:

[0062]

[0063] Quantizing the leading data will transform the complex cross-correlation operation into addition and subtraction operations, greatly reducing the amount of calculation and making the synchronization more efficient. The quantized formula is as follows:

[0064]

[0065] Due to the harsh wireless channel environment, it will be affected by various fading, especially with the increase of propagation distance, resulting in serious attenuation of the signal. t 2 The peak value of the received signal will fluctuate under its influence, thus affecting the selection of the decision threshold. In order to reduce this influence, a threshold is dynamically established using the actual received signal energy and the peak value. The energy formula for calculating the data at point M2 is as follows:

[0066]

[0067] Where P t Represents the energy value of the received data from the current time t to the time t+m, where m ranges from 0 to M2-1;

[0068] The hardware implementation block diagram of wireless frame synchronization is as follows: Figure 6 As shown in the figure, firstly, the short training symbol data is quantized to {-1,1}, and then the M2 point cross-correlation operation is performed. The same as the wired summation idea, the FPGA adder and register array resources are used, and the simplified M2 point cross-correlation operation is calculated using the for command, and the energy value of the accumulated result is calculated to obtain the peak value C t 2 .like Figure 7As shown, the maximum value of the main peak is around 20000, so it is best to set the fixed threshold th between 10000 and 18000. Since the size of the correlation peak at point M2 is positively correlated with the energy Pt of the received data at point M2, and the energy P0 of the received signal at this time is used as a reference, the threshold at this time can be dynamically determined as: menxian_set = th*P t / P0. The dynamic threshold menxian_set is used as the only condition for judging the peak value. If the correlation and result are greater than menxian_set, it is considered that a peak value is detected. Then the state machine is used to search for the peak value. First, the state machine is in the initial state. If the next peak value differs from the first peak value by (M2±4) points, it is considered to be a related peak value, and the state machine switches to the next state. Otherwise, it is determined that the first peak value is caused by interference, and the state machine returns to the initial state. The state machine continues to work until 5 peak values ​​in the correct position are detected. In this case, this frame of data is considered to be valid data, and the state machine returns to the initial state. Then the frame synchronization enable signal is pulled high, and valid data is output at the same time. In addition, according to the detected data energy value, the amplitude of its valid data is automatically controlled to ensure that no matter how large the signal input is, the amplitude of the frame synchronization module output is always within a certain range, which also brings convenience to the design of subsequent modules.

[0069] 3) Wireless symbol synchronization module

[0070] The long training sequence L designed for wireless communication can be used to achieve wireless symbol synchronization immediately after the short training sequence. Since the number of points N2 of the long training symbol L is generally much larger than the length of the short training symbol S, if the exact position is determined by continuing to calculate the peak value through cross-correlation, it will greatly consume resources and reduce the synchronization efficiency. According to the strategy of wireless frame synchronization, the interval D between the start of the L symbol and the S symbol is fixed. Considering that noise will cause the correlation peak to shift left and right by one point, the received data and the long training symbol L are cross-correlated by N2 points at intervals (D-1), D, and (D+1) after frame synchronization, and the maximum values ​​are compared to determine the exact starting position of the data. Considering that the wireless channel environment is relatively poor and peak leakage may occur, in order to avoid false synchronization, 3n groups of N2 point cross-correlations are performed at intervals (Dn*N2-1), (Dn*N2), and (Dn*N2+1) after frame synchronization, and then the 3n cross-correlation values ​​are compared, and the maximum value is selected as the exact position of symbol synchronization.

[0071] The hardware implementation block diagram of wireless symbol synchronization is as follows: Figure 8As shown, first, the data after frame synchronization is cached through RAM, each data corresponds to an address, and then a high-speed clock that is much larger than the data rate is used to perform 3n high-speed serial cross-correlation operations from (Dn*N2) to position D. Then, the obtained correlation peaks are compared to find the address corresponding to the maximum value, and the data in RAM is taken out from this address to accurately complete symbol synchronization.

[0072] 4) Frequency synchronization module

[0073] like Fig. 9 As shown, it is a hardware implementation block diagram of the frequency synchronization module. For wired or wireless, the frequency synchronization algorithm can adopt a conventional algorithm, and the carrier frequency deviation is calculated and compensated according to the preamble, and the sampling frequency deviation is calculated and compensated according to the pilot. The present invention makes improvements on this basis. First, two groups of delayed cross-correlation operations are performed on the input data, and the two results are respectively input into the CORDIC-IP core, which is configured in the "arctan" mode to obtain two estimated carrier frequency deviation angles, and the average is calculated to obtain a more accurate frequency deviation angle, and then it is sent to the CORDIC-IP core configured in the "rotate" mode together with the RAM cached data to complete the carrier synchronization. Then, the time domain data is transformed into the frequency domain through FFT (fast Fourier transform), the loaded pilot information is extracted, and then a cross-correlation operation is performed with the local pilot. The accumulated result is also input into the CORDIC-IP core configured in the "arctan" mode to calculate the sampling frequency deviation angle. On the one hand, the calculated sampling frequency deviation angle is sent to the CORDIC-IP core configured in the "rotate" mode together with the data cached in the RAM to compensate for the sampling frequency deviation of the data. Since the OFDM symbol adjusts the data before IFFT (Inverse Fast Fourier Transform), the data order needs to be adjusted back to the order before IFFT, thus completing the sampling synchronization; on the other hand, the output sampling frequency deviation angle is sent to the module that configures the AD clock of the FPGA. Since the AD clock crystal has an accuracy range, generally ±10ppm, in order to reduce the sampling error, the deviation of the sampling clock is set within ±0.5ppm. If the estimated sampling frequency deviation exceeds this range, the AD sampling clock is adjusted through the PID (Proportional Integral Differential Controller) controller to correct the deviation. When the next frame of data arrives, the sampling clock of the receiving end will be more accurate until the sampling clock deviation is adjusted to within ±0.5ppm, at which time the AD clock will no longer be adjusted. This not only avoids adjusting the AD PLL too frequently, but also makes corresponding compensation for the sampling frequency deviation within the allowable range, making the entire frequency deviation compensation module more stable and the system response faster.

[0074] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for implementing a receiver synchronization system based on FPGA, characterized in that: The steps include: (1) FPGA initializes the configuration of AD; (2) The decoupled power line carrier signal is processed to obtain the wired frequency domain data; (3) After processing the wireless signal, wireless frequency domain data is obtained; The specific steps in step (2) are as follows: The power line carrier signal passes through the first AD channel to obtain wired baseband data. The approximate position of a frame is detected by the energy detection module and the wired frame synchronization module. After the correct position is detected by the wired symbol synchronization module, the frequency synchronization module uses the statistical averaging method to estimate the accurate frequency deviation and make compensation. The frequency deviation obtained at this time can be fed back to the AD by the FPGA, and finally the wired frequency domain data of the accurate position is output; The wired symbol synchronization module determines the exact position when the peak value changes from positive to negative, completes the symbol synchronization, and the autocorrelation peak value calculation is as follows: ； Where M1 is the length of the wired cross-correlation sequence, r t+m is the input signal at the current time t and after time m, so m takes values ​​from 0 to M1-1, S m * is the conjugate of the local leader, C t is the cross-correlation peak, P(r t+m ) is r t+m The quantitative value of The specific steps in step (3) are as follows: The antenna of the second AD channel starts to receive wireless signals and obtains wireless baseband data after down-conversion. Similarly, the energy detection module and the wireless frame synchronization module detect the approximate position of a frame. The frequency synchronization module uses the statistical averaging method to perform multiple estimations and compensation using short training sequences. The frequency deviation obtained at this time can also be fed back to the AD by the FPGA. Finally, the wireless symbol synchronization module obtains the wireless frequency domain data of the accurate position. The hardware implementation of the wireless symbol synchronization module includes: first, the data obtained by the wireless frame synchronization module is cached through RAM, each data corresponds to an address, and then a high-speed clock that is much larger than the data rate is used to perform 3n high-speed serial cross-correlation operations from (Dn*N2) to position D, and then the obtained correlation peaks are compared to find the address corresponding to the maximum value, and the data in the RAM is retrieved from this address to accurately complete the symbol synchronization.

2. The method for implementing a receiver synchronization system based on FPGA according to claim 1, characterized in that: The specific operations of the wired frame synchronization module to achieve frame synchronization are as follows: the wired leading signal is processed to generate a positive peak and a negative peak. The wired frame synchronization module can determine the approximate position according to the positive peak to complete the frame synchronization.

3. The method for implementing a receiver synchronization system based on FPGA according to claim 1, characterized in that: The wireless frame synchronization module implements the following specific operations to achieve wireless frame synchronization: combine the leading short training S symbol to complete the packet detection, perform cross-correlation operation on the received IQ data and S symbol and square them to obtain the peak value C t 2 , the calculation is as follows: ； Where M2 is the length of the wireless cross-correlation sequence, r t+m is the input signal at the current time t and after time m, so m takes values ​​from 0 to M2-1, S m is the local pilot signal, C t 2 is the square of the cross-correlation peak value, P(S m ) is S m Quantified value of .

4. The method for implementing a receiver synchronization system based on FPGA according to claim 1, characterized in that: The frequency synchronization module includes carrier synchronization and sampling synchronization; the specific operation of the carrier synchronization includes: firstly, according to the carrier frequency deviation angle obtained by cross-correlation between the input data and the local pilot, the carrier frequency deviation compensation is performed on the input data cached in the RAM to complete the carrier synchronization; The specific operations of the sampling synchronization include: then transforming the time domain data into the frequency domain through FFT, then extracting the pilot data therefrom, performing cross-correlation operation with the local pilot to obtain the sampling frequency deviation angle, and performing sampling frequency deviation compensation on the frequency domain data cached in the RAM; performing sampling frequency deviation compensation on the sampling frequency deviation angle and the data cached in the RAM, and then adjusting the data sequence back to the sequence before IFFT to complete sampling synchronization; sending the output sampling frequency deviation angle to the module for configuring the AD clock of the FPGA to reduce the sampling error, and setting the deviation of the sampling clock within ±0.5ppm. If the estimated sampling frequency deviation exceeds this range, the AD sampling clock is adjusted through the proportional integral differential controller to correct the deviation. When the next frame of data arrives, the sampling clock of the receiving end will become more and more accurate until the sampling clock deviation is adjusted to within ±0.5ppm.

5. A receiver synchronization system based on FPGA, implementing the implementation method according to any one of claims 1 to 4, characterized in that: The receiver system comprises: High-speed AD (analog-to-digital converter) module, used to achieve high-speed acquisition of wired and wireless baseband data; Energy detection module, used to realize automatic control of the amplitude of received data and determination of dynamic threshold; The wired synchronization module is used to realize the frame synchronization, symbol synchronization and frequency synchronization of the wired baseband data and detect the accurate starting position of a frame of data; The wireless synchronization module is used to achieve frame synchronization, symbol synchronization and frequency synchronization of wireless baseband data and detect the accurate starting position of a frame of data.

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