Merged branch target buffer entries

Abstract

The merge branch target buffer entry includes an entry maintained in the branch target buffer corresponding to the first branch instruction, wherein the entry identifies the first branch target address of the first branch instruction and the second branch target address of the second branch instruction; and an entry accessed based on the first branch instruction.

Description

Background Technology

[0001] The branch target predictor predicts the target of a branch instruction before the processor's execution unit computes the target of that branch instruction. The branch target predictor maintains a branch target buffer to store previously computed branch information based on its corresponding branch instruction index. Attached Figure Description

[0002] Figure 1 This is a block diagram of an exemplary processor for a merged branch target buffer entry according to some implementation schemes.

[0003] Figure 2 This is a flowchart of an exemplary method for merging branch target buffer entries according to some implementation schemes.

[0004] Figure 3 This is a flowchart of an exemplary method for merging branch target buffer entries according to some implementation schemes.

[0005] Figure 4 This is a flowchart of an exemplary method for merging branch target buffer entries according to some implementation schemes.

[0006] Figure 5 This is a flowchart of an exemplary method for merging branch target buffer entries according to some implementation schemes.

[0007] Figure 6 This is a flowchart of an exemplary method for merging branch target buffer entries according to some implementation schemes.

[0008] Figure 7 This is an exemplary computer-readable storage medium for merged branch target buffer entries according to some implementation schemes. Detailed Implementation

[0009] In some implementations, the method of merging branch target buffers includes maintaining an entry in the branch target buffer corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and accessing the entry based on the first branch instruction.

[0010] In some embodiments, the method includes storing data indicating a first branch target address and a second branch target address in a prediction queue based on entries. In some embodiments, the prediction queue is communicatively coupled to an instruction fetching unit configured to load multiple instructions based on the first branch target address and the second branch target address. In some embodiments, the method further includes: receiving a first redirection indicating a first branch instruction and a first branch target address; and storing an entry in a branch target buffer as an identifier for the first branch target address. In some embodiments, the method includes: receiving a second redirection indicating a second branch instruction and a second branch target address; and modifying the entry to identify the second branch target address and the first branch target address. In some embodiments, the method includes determining the modified entry to identify the second branch target address and the first branch target address based on one or more merging rules. In some embodiments, the one or more merging rules are based on at least one of: the branch type of the first branch instruction, the branch type of the second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction. In some embodiments, determining the modified entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0011] In some implementations, the branch target predictor of the merged branch target buffer entries performs the following steps: maintaining an entry in the branch target buffer corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and accessing the entry based on the first branch instruction.

[0012] In some embodiments, the step further includes storing data indicating the first branch target address and the second branch target address in a prediction queue based on entries. In some embodiments, the prediction queue is communicatively coupled to an instruction fetching unit that loads multiple instructions based on the first branch target address and the second branch target address. In some embodiments, the step further includes: receiving a first redirection indicating the first branch instruction and the first branch target address; and storing an entry in a branch target buffer as an identifier for the first branch target address. In some embodiments, the step further includes receiving a second redirection indicating the second branch instruction and the second branch target address; and modifying the entry to identify the second branch target address and the first branch target address. In some embodiments, the step further includes determining to modify the entry to identify the second branch target address and the first branch target address based on one or more merging rules. In some embodiments, the one or more merging rules are based on at least one of the following: the branch type of the first branch instruction, the branch type of the second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction. In some embodiments, determining to modify the entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0013] In some implementations, the processor for the merged branch target buffer entries includes: a branch target predictor that performs the steps of: maintaining an entry in the branch target buffer corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and accessing the entry based on the first branch instruction.

[0014] In some embodiments, the step further includes storing data indicating the first branch target address and the second branch target address in a prediction queue based on entries. In some embodiments, the processor further includes an instruction fetching unit that loads multiple instructions based on the first branch target address and the second branch target address, and the prediction queue is communicatively coupled to the instruction fetching unit. In some embodiments, the step further includes: receiving a first redirection indicating a first branch instruction and a first branch target address; and storing an entry in a branch target buffer as an identifier of the first branch target address. In some embodiments, the step further includes receiving a second redirection indicating a second branch instruction and a second branch target address; and modifying the entry to identify the second branch target address and the first branch target address. In some embodiments, the step further includes determining to modify the entry to identify the second branch target address and the first branch target address based on one or more merging rules. In some embodiments, the one or more merging rules are based on at least one of the following: the branch type of the first branch instruction, the branch type of the second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction. In some embodiments, determining to modify the entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0015] In some embodiments, the means for merging branch target buffer entries includes: a processor including a branch target predictor that performs the steps of: maintaining an entry in the branch target buffer corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and accessing the entry based on the first branch instruction.

[0016] In some embodiments, the step further includes storing data indicating the first branch target address and the second branch target address in a prediction queue based on entries. In some embodiments, the processor further includes an instruction fetching unit that loads multiple instructions based on the first branch target address and the second branch target address, and the prediction queue is communicatively coupled to the instruction fetching unit. In some embodiments, the step further includes: receiving a first redirection indicating a first branch instruction and a first branch target address; and storing an entry in a branch target buffer as an identifier of the first branch target address. In some embodiments, the step further includes receiving a second redirection indicating a second branch instruction and a second branch target address; and modifying the entry to identify the second branch target address and the first branch target address. In some embodiments, the step further includes determining to modify the entry to identify the second branch target address and the first branch target address based on one or more merging rules. In some embodiments, the one or more merging rules are based on at least one of the following: the branch type of the first branch instruction, the branch type of the second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction. In some embodiments, determining to modify the entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0017] Figure 1 This is a block diagram of a non-limiting example of a device or apparatus 101 including processor 100. Device 1 and / or processor 100 can implement various embodiments of the invention. Exemplary processor 100 can be included in various devices 1, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, etc. Processor 100 includes a branch predictor 102. Branch predictor 102 is a combination of logic and / or circuitry that predicts the direction or path a branch instruction will take before execution. Branch predictor 102 includes a branch target predictor 104. Branch target predictor 104 is a combination of logic and / or circuitry that predicts the target address of the branch taken by the branch instruction before calculating the target address during execution of the branch instruction. Although branch target predictor 104 is shown as a sub-component of branch predictor 102, it should be understood that branch target predictor 104 can also be implemented as a separate component.

[0018] Branch target predictor 104 maintains branch target buffer 106. Branch target 106 is typically part of dedicated memory (e.g., cache memory) that stores the target address of the branch taken by a branch instruction, hereinafter referred to as the "branch target address". Each entry in branch target buffer 106 includes an identifier field. In some embodiments, the identifier includes the instruction address of the corresponding branch instruction (e.g., "branch instruction address"). In other embodiments, the identifier field includes a prediction address. The prediction address includes a prediction-leading program counter (e.g., the most recent program counter in the processor pipeline). The prediction address is used as the starting address of the predicted block. Therefore, each entry in branch target buffer 106 is indexed according to the identifier field.

[0019] Each entry in the branch target buffer 106 also includes a target field. The target field of the branch target buffer 106 entry stores an identifier of the branch target address corresponding to the branch instruction. The branch target address includes the start address of the prediction block. A prediction block is a block of consecutive instruction bytes that can be fetched by the instruction fetching unit. Each prediction block must be contained within a memory region called a prediction window. In some embodiments, the prediction window includes cache lines. In some embodiments, the prediction block is specified by (e.g., indicated in the branch target buffer 106 entry) the following: 1) a start address that specifies the first byte of the prediction block within the memory space, thus specifying that the prediction block is part of it; 2) an end address (e.g., an offset within the prediction window); and 3) one or more branch types that specify whether each branch within the prediction block is called, returned, or skipped (e.g., a branch that is neither called nor returned). In some embodiments, each branch target buffer 106 entry also indicates whether each branch is predicted to be taken. These entry attributes are described in further detail below.

[0020] Existing methods for implementing branch target buffers require that branch target buffer entries store an identifier for a single branch target address, or that the pair of branch target addresses are in the same prediction block (e.g., the same pBlock n pair). In contrast, the entries of branch target buffer 106, configured for merging branch target buffer entries, store identifiers for one or more branches (e.g., one or more branch target addresses), thereby allowing multiple branch target addresses to be referenced in a single entry without needing to be in the same prediction block. For example, suppose the 32-bit target field of the branch target buffer 106 entry uses up to 32 bits to reference a single branch target address. An entry referencing two branch target addresses assigns a first subset of the bits in the target field (e.g., the first 16 bits) to the first branch target address and a second subset of the bits in the target field (e.g., the second 16 bits) to the second branch target address. For each referenced branch target address, the target field of branch target buffer 106 also includes an identifier of the last byte of the prediction block starting at the corresponding branch target address.

[0021] The bits allocated to the target field for a given branch target address are the lowest-order bits of that branch target address. To compute a given branch target address, the remaining bits (e.g., the highest-order bits) of the given branch target address are copied from the highest-order bits of the branch instruction address of the entry. For example, assuming 32-bit addressing and 16 bits of the target field are allocated to a given branch target address, the given branch target address will be computed as the first 16 bits of the branch instruction address (e.g., 16 highest-order bits), appended with the 16 bits allocated to the target field. As another example, assuming 32-bit addressing and 20 bits of the target field are allocated to a given branch target address, the given branch target address will be computed as the first 12 bits of the branch instruction address (e.g., 12 highest-order bits), appended with the 20 bits allocated to the target field. The reader will understand that the bits in the target field can be distributed equally or unequally among the identified branch target addresses (e.g., the first branch target address may be allocated 20 bits, while the second branch target address may be allocated 12 bits).

[0022] In some implementations, for the first branch "Br0", the entry has a "sequential before" attribute, which specifies whether the branch target address is in the same prediction window as the prediction address, or whether it is N prediction windows later. For example, if Br0 is in the next prediction window (i.e., SequentialBefore = 1), then the branch predictor 102 will predict the first prediction block Pblk0, which starts at the prediction address and ends at the end of the prediction window (Pw0) containing the prediction address. Simultaneously, the branch predictor 102 will predict the second prediction block Pblk1, which starts at the beginning of the subsequent prediction window (Pw1). Pblk1 contains Br0. If Br0 is predicted to be taken, then Pblk1 ends at the last byte of Br0. Otherwise, Pblk1 may contain bytes up to the last byte of Pw1.

[0023] For the second branch in entry "Br1", the entry specifies whether the branch is (a) on the taken path of Br0 or (b) on the untaken path of Br0. In both cases, the entry specifies whether Br1 is in the prediction window at the taken / untaken target of Br0 or in a subsequent prediction window. Br1 is predicted as follows:

[0024] • If Br1 is on the path taken by Br0 and Br0 is predicted to be non-taken, then Br1 is not used for prediction.

[0025] • If Br1 is on the non-taken path of Br0 and Br0 is predicted to be taken, then Br1 is not used for prediction.

[0026] If Br1 is on the path taken by Br0 and Br0 is predicted to be taken, then Br1 is used for prediction. For example, assuming PblkN ends at the last byte of Br0, the prediction engine will predict PblkN+1 starting at the target address of Br0. Br1 has a SequentialBefore attribute, which specifies whether it is in the prediction window at the target of Br0 or in a subsequent prediction window. If SequentialBefore = 0, then Br1 is part of PblkN+1. Otherwise, PblkN+1 contains no prediction branch and ends at the last byte of the prediction window.

[0027] If Br1 is on the non-taken path of Br0 and Br0 is predicted as non-taken, then Br1 is used for prediction. Br1 can be in the same prediction window as Br0, in which case it is counted as a factor in the same Pblk as Br0. Alternatively, it can be in a subsequent prediction window, as specified by the SequentialBefore attribute. For example, in the case where Br0 is in PblkN. Br1SequentialBefore = 0 means Br1 is in the same prediction window as Br0. Br1SequentialBefore = M means Br1 is in M ​​prediction windows after Br0. If M = 2, the prediction engine will predict simultaneously:

[0028] • PblkN, which contains Br0 and ends at the last byte of the prediction window (i.e., PwN) containing Br0.

[0029] • PblkN+1, which consists of the full prediction window (i.e., PwN+1) immediately following PwN.

[0030] composition

[0031] • PblkN+2, which begins with the first byte of PwN+2 and contains Br1. If Br1 is predicted to be taken, then PblkN+2 ends with the last byte of Br1. Otherwise, it may contain bytes up to the last byte of PwN+2.

[0032] Each entry can store information for more than two branches. For each branch Br_i, there are attributes specifying the following characteristics:

[0033] ·Br_i is on the taken or untaken path of another branch Br_j (j <i)

[0034] • Br_i SequentialBefore, which specifies the number of prediction windows that do not have branches that separate Br_i and Br_j.

[0035] • The end address of Br_i within the prediction window

[0036] ·Branch type of Br_i

[0037] As described above, the entries in the branch target buffer 106 also store an identifier for the branch type of the corresponding branch instruction in the "Branch Type Field" for each branch target address identified in the target field. For example, suppose the branch instruction falls into one of a predefined enumeration of branch types. The branch type can indicate the specific type of the branch instruction and the relationship between that branch and other branches referenced in the entry. Suppose the entries in the branch target buffer 106 support up to two branch target addresses in the target field corresponding to the first branch instruction "Br0" and the second branch instruction "Br1", then the branch type field can indicate the type of instruction (e.g., call, conditional skip, unconditional skip, variable or fixed target, etc.) and whether "Br0" exists for "Br0"; and whether "Br1" is on the path taken by "Br0", on the path not taken by "Br0", or in the same prediction window as "Br0" (e.g., the instruction block accessed when loaded from the branch target address of "Br0").

[0038] In some implementations, the Br0SequentialBefore attribute has a maximum value that determines how many branchless prediction blocks are predicted when there is a miss in the branch target buffer 106. For example, if Br0SequentialBefore is set to have a maximum value of 2, each prediction stream that misses in the branch target buffer 106 can predict 3 prediction blocks: the first prediction block begins at the prediction address and ends at the last byte of the prediction window, and the second and third prediction blocks are the next two full prediction windows. The next prediction stream will use the prediction address, which is the first byte of the prediction window after the last predicted block. This is important because it enables increased prediction bandwidth and reduced power consumption in predicting prediction blocks, even in code without many branches.

[0039] Therefore, the branch type field then includes the number of bits required to represent any branch type in the enumeration multiplied by the number of branch target address codes. For example, suppose the branch instruction falls into one of fourteen different branch types that require four bits to represent. Assuming that up to two branch target instructions can be identified in the target field, the branch type field includes 2 * 4 = 8 bits.

[0040] When the branch target predictor 104 is queried with the prediction address corresponding to the first branch instruction (e.g., the prediction address before the first branch instruction) or the address of the first branch instruction, it depends on which address is used to index the entry in the branch target buffer 106. If no such entry is found, the branch instruction continues to be executed through the instruction pipeline. If an entry is found, the branch target predictor 104 accesses that entry.

[0041] Branch target predictor 104 calculates a branch target address for each branch target address referenced in the target field of an entry. For example, assuming a first branch target address is referenced by a first set of bits and a second branch target address is referenced by a second set of bits, branch target predictor 104 calculates the first branch target address by appending the first set of bits to the number of highest-order bits required to satisfy the number of bits in the instruction address. Branch target predictor 104 calculates the second branch target address by appending the second set of bits to the number of highest-order bits required to satisfy the number of bits in the instruction address. Branch target predictor 104 then stores the calculated branch target addresses (e.g., the first branch target address and the second branch target address) in prediction queue 108. For example, for each branch target address (e.g., for the first branch target address and the second branch target address), the branch target predictor stores a corresponding prediction block. The prediction block includes a start address (e.g., the branch target address) and a series of instruction addresses ending at an end address. The end address of the prediction block is identified in the branch target buffer entry (e.g., by using the offset or number of instructions to determine the end address, or by an identifier of the address of the last instruction in the prediction block), or by a default end address corresponding to the start of the new prediction window for the instruction.

[0042] Prediction queue 108 is part of memory and is allocated to maintain a queue of prediction blocks of instructions (e.g., branch target addresses and subsequent instructions within the same prediction block). Prediction queue 108 is communicatively coupled to instruction fetch unit 114. Instruction fetch unit 114 loads one or more instructions from memory and stores the loaded instructions in instruction queue 112. Thus, instruction fetch unit 114 accesses prediction queue 108 for branch target addresses and loads multiple instructions starting at the branch target address into instruction queue 112. In some embodiments, the number of sequential instruction blocks (e.g., prediction blocks) inserted into instruction queue 112 is equal to a defined maximum number of prediction blocks that can be inserted for a hit against an entry in branch target buffer 106. For example, instruction fetch unit 114 loads instruction blocks starting at branch target addresses to fill cache lines in instruction queue 112. Such blocks of addresses are referred to as prediction blocks. As multiple branch target addresses (e.g., multiple prediction blocks) have been added to prediction queue 108 in response to a single access to branch target buffer 106, branch prediction throughput increases, allowing more instructions to be fetched and executed per loop. Instructions from instruction queue 112 are then provided to decoding unit 116 by instruction fetching unit 114 and executed by execution unit 118.

[0043] To generate the merged branch target buffer 106 entries, the branch target predictor 104 receives a first redirection (e.g., from the decoding unit 116 or the execution unit 118) for the first branch instruction. For example, when the first branch instruction is first fetched, there is no entry in the branch target buffer 106. Therefore, the first branch target address of the first branch instruction will be calculated by the decoding unit 116 and / or the execution unit 118, depending on whether the first branch is conditional or indirect. Thus, the redirection to the branch target predictor 104 includes a description of the first branch instruction (e.g., branch type), the first branch instruction address, and the first branch target address. The branch target predictor 104 then stores entries in the branch target buffer 106 that identify the branch instruction address in the identifier field and the branch target address in the target field. The generated entries also identify the branch type of the first branch instruction in the branch type field. Since there are no references to other branch instructions in the target field, the type field will not reflect the relationship between the first branch instruction and another branch instruction.

[0044] The branch target predictor 104 then receives a second redirection for the second branch instruction. The second redirection includes a description of the second branch instruction (e.g., branch type), the second branch instruction address, and the second branch target address. The branch target predictor 104 then determines whether to modify entries (e.g., the entry's type field, identifier field, and target field) to identify both the second branch target address and the first branch target address. For example, the branch target predictor 104 determines to modify entries to identify both the second branch target address and the first branch target address based on one or more merge rules.

[0045] The merging rule can be based on the instruction address of the second branch instruction. For example, branch target predictor 104 can determine modification entries to identify the second branch target address and the first branch target address in response to the instruction address of the second branch instruction being included in the prediction window of the first branch target address. For example, suppose instruction fetch unit 114 loads a 64-byte instruction block starting at a given target address into instruction queue 112. Therefore, each branch target address corresponds to a 64-byte prediction window. The instruction address of the second branch instruction is within the prediction window of the first branch target address, where the second branch instruction address is within the 64 bytes of the first branch target address. Branch target predictor 104 can also determine modification entries to identify the second branch target address and the first branch target address in response to the instruction address of the second branch instruction being included in the next prediction window (e.g., the next 64-byte block) following the prediction window of the first branch target address.

[0046] Merge rules can also be based on the branch types of the first and second branch instructions. For example, specific combinations of branch instructions can be preferentially selected to modify entries that identify the second branch target address and the first branch target address. Merge rules can also prevent modifications to entries that identify certain combinations of branch types, such as the second branch target address and the first branch target address. As a non-limiting example, if the first branch instruction is a call, the merge rule can prevent modifications to entries when the second branch instruction is a call or a return, to avoid any call / call, call / return, return / call, or return / return combinations not supported by the return address stack.

[0047] The branch target predictor 104 also determines to modify the entry to identify the second branch target address and the first branch target address based on the number of bits required to identify the first branch target address and the second branch target address in the entry (e.g., the target field). For example, suppose a 32-bit addressing scheme is used where the first branch target address and the first branch instruction address share the same 16 highest-order bits, but differ starting from the 17th highest-order bit. Therefore, the first branch target address requires 16 bits to identify the target field. If the second branch target address differs from the first branch instruction address which starts at the 13th highest-order bit, the second branch target address requires 12 bits to identify the target field. Therefore, the 32-bit target field can indicate both the first branch target address (using the 16 lowest-order bits of the first branch target address) and the second branch target address (using the 12 lowest-order bits of the second branch target address).

[0048] In contrast, assuming the second branch target address differs from the first branch instruction address (used to index the entry) starting at bit 21, the second branch target address requires 20 bits to be identified in the target field. When the first branch target address requires 16 bits, neither the first nor the second branch target address can be represented in the target field. Therefore, the branch target predictor 106 will determine not to modify the entry. Instead, a new entry for the second branch instruction will be created in the branch target buffer 106 if the entry is determined not to be modified.

[0049] Modifying entries to identify the second branch target address and the first branch target address includes adding the number of the lowest order bits of the second branch target address, which differs from the first branch instruction address, to the target field of the entry. Modifying entries to identify the second branch target address and the first branch target address includes adding an indication of the second branch type to the branch type field and modifying the branch type field to reflect the relationship between the first branch target instruction and the second branch target instruction.

[0050] For another example regarding the merging rules, assume that each entry can record two branches (Br0 and Br1), and that the maximum value of SequentialBefore is one, such that two Pblks are generated when there is a miss in the branch target buffer 106. Further assume that the prediction window is a 64-byte aligned memory line. Each prediction block is assigned the following characteristics:

[0051] • Used to find the prediction address of BTB when predicting Pblk

[0052] • The end address of the branch found in BTB when predicting Pblk

[0053] • Specifies the descriptor of the position of the prediction block relative to each branch found in the BTB when predicting Pblk.

[0054] For this example, assume the prediction address = 0x005, and assume the branch type and target size always allow two branches to be paired into a single entry:

[0055] • A prediction miss in branch target buffer 106 generates Pblk0 with StartAddr=0x005 and EndAddr=0x03f and Pblk1 with StartAddr=0x040 and EndAddr=0x07f.

[0056] • Redirection on Pblk0 of BrA with EndOffset = 0x07 will cause BrA to be trained at the predicted address to be Br0 with SequentialBefore = 0.

[0057] • Redirection on Pblk1 of BrB with EndOffset = 0x01 will cause BrB to be trained at the predicted address as Br0 with SequentialBefore = 1.

[0058] • Predicted hits 106 entries in the target buffer of the branch, where a single branch Br0 has SequentialBefore=0, EndOffset=0x3e, TgtAddr=0x102, and its prediction Br0 is taken. It generates Pblk0 with StartAddr=0x005, EndAddr=0x03e and Pblk1 with StartAddr=0x102, EndAddr=0x13f.

[0059] • Redirecting on Pblk1 of BrC with EndOffset=0x03 will cause BrC to be trained at the predicted address to be Br1 with SequentialBefore=0, Br1 on the path taken by Br0.

[0060] • Predicts 106 entries in the target buffer of the branch hit, where a single branch Br0 has SequentialBefore=0, EndOffset=0x2e, TgtAddr=0x102, and its prediction Br0 is not taken. It generates Pblk0 with StartAddr=0x005, EndAddr=0x03f and Pblk1 with StartAddr=0x040, EndAddr=0x07f.

[0061] • Redirecting on Pblk0 of BrD with EndOffset=0x34 will cause BrD to be trained at the predicted address as Br1 with SequentialBefore=0, Br1 on the non-take path of Br0.

[0062] • Redirecting on Pblk1 of BrE with EndOffset=0x05 will cause BrE to be trained at the predicted address to Br1 with SequentialBefore=1, Br1 on the non-take path of Br0.

[0063] To further explain, Figure 2 A flowchart illustrating an exemplary method for merging branch target buffer entries is provided. This method includes maintaining, 202, an entry 204 corresponding to a first branch instruction in a branch target buffer 106 (e.g., by a branch target predictor 104 of branch predictor 102), wherein the entry 204 identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction. Each entry in the branch target buffer 106 includes an identifier field that stores identifiers such as branch target addresses or prediction addresses. Therefore, each entry in the branch target buffer 106 is indexed according to the identifier field.

[0064] Each entry in the branch target buffer 106 also includes a target field. Therefore, the target field identifies the first branch target address of the first branch instruction and the second branch target address of the second branch instruction. The bits allocated to the target field for a given branch target address are the lowest-order bits of the given branch target address. To compute a given branch target address, the remaining bits (e.g., the highest-order bits) of the given branch target address are copied from the highest-order bits of the branch instruction address of the entry (e.g., the identifier field). For example, assuming 32-bit addressing and 16 bits of the target field are allocated to the first branch target address, the first branch target address will be computed as the first 16 bits (e.g., 16 highest-order bits) of the branch instruction address, appended with the 16 bits allocated to the target field. The reader will understand that the bits in the target field can be equally or unequally distributed among the identified branch target addresses (e.g., the first branch target address may be allocated 20 bits, while the second branch target address may be allocated 12 bits).

[0065] Each entry in the branch target buffer 106 also stores an identifier for the branch type of the corresponding branch instruction in the "Branch Type Field" for each branch target address identified in the target field. For example, suppose the branch instruction falls into one of a predefined enumeration of branch types. The branch type can indicate the specific type of the branch instruction, and the relationship between that branch, the prediction address, and other branches referenced in the entry. Suppose the entry in the branch target buffer 106 supports up to two branch target addresses in the target field corresponding to the first branch instruction "Br0" and the second branch instruction "Br1", then the branch type field can indicate the type of instruction (e.g., call, conditional skip, unconditional skip, variable or fixed, etc.) and whether "Br0" exists for "Br0"; whether "Br0" is in the prediction window pointed to by the prediction address or in a subsequent prediction window; whether "Br1" is on the path taken by "Br0", on the path not taken by "Br0", or in the same prediction window as "Br0" (e.g., in the instruction block accessed when loaded from the branch target address of "Br0").

[0066] Figure 2 The method also includes accessing entry 204 based on a first branch instruction (e.g., by branch target predictor 104 of branch predictor 102). For example, branch target predictor 104 is queried using either the prediction address corresponding to the first branch instruction (e.g., the prediction address prior to the first branch instruction) or the address of the first branch instruction, depending on which address is used to index the entry in branch target buffer 106. Branch target predictor 104 then identifies the corresponding entry in branch target buffer 106 as entry 204.

[0067] To further explain, Figure 3A flowchart illustrating an exemplary method for merging branch target buffer entries is provided, the method comprising maintaining an entry 204 corresponding to a first branch instruction in a branch target buffer 106 (e.g., by a branch target predictor 104 of branch predictor 102), wherein the entry 204 identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and accessing entry 204 of 206 based on the first branch instruction (e.g., by a branch target predictor 104 of branch predictor 102).

[0068] Figure 3 Methods and Figure 2 The difference is Figure 3 The method also includes storing 302, based on entry 204, data 304 indicating the first branch target address and the second branch target address in prediction queue 108. Prediction queue 108 is part of memory allocated to maintain a queue of branch target addresses (e.g., prediction blocks of addresses). Prediction queue 108 is communicatively coupled to instruction fetch unit 114. Instruction fetch unit 114 loads one or more instructions from memory and stores the loaded instructions in instruction queue 112. Thus, instruction fetch unit 114 accesses prediction queue 108 for branch target addresses and loads multiple instructions starting at the branch target address into instruction queue 112. For example, instruction fetch unit 114 loads a block of instructions starting at the branch target address to fill a cache line in instruction queue 112. Such a block of addresses is called a prediction block. When multiple branch target addresses are added to prediction queue 108 in response to a single access to branch target buffer 106, instruction fetch unit 114 can store multiple prediction blocks in instruction queue 112. This improves efficiency because more instructions can be fetched in a given loop.

[0069] Branch target predictor 104 calculates a first branch target address and a second branch target address based on the target field of entry 204. For example, assuming the first branch target address is referenced by a first set of bits and the second branch target address is referenced by a second set of bits, branch target predictor 104 calculates the first branch target address by appending the first set of bits to the number of highest-order bits required to satisfy the number of bits in the instruction address. Branch target predictor 104 calculates the second branch target address by appending the second set of bits to the number of highest-order bits required to satisfy the number of bits in the instruction address. Branch target predictor 104 then stores the calculated branch target addresses (e.g., the first branch target address and the second branch target address) in prediction queue 108.

[0070] To further explain, Figure 4A flowchart illustrating an exemplary method for merging branch target buffer entries is provided, the method comprising maintaining an entry 204 corresponding to a first branch instruction in a branch target buffer 106 (e.g., by a branch target predictor 104 of branch predictor 102), wherein the entry 204 identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and accessing entry 204 of 206 based on the first branch instruction (e.g., by a branch target predictor 104 of branch predictor 102).

[0071] Figure 4 Methods and Figure 2 The difference is Figure 4 The method also includes (e.g., a first redirection 404 from execution unit 112 by branch target predictor 104 of branch predictor 102) receiving an indication of a first branch instruction and a first branch instruction address. For example, when the first branch instruction is first fetched, there is no entry in the branch target buffer 106. Therefore, the first branch target address of the first branch instruction will be calculated by decoding unit 116 and / or execution unit 118, depending on whether the first branch is conditional or indirect. Therefore, the first redirection 404 to branch target predictor 104 includes a description of the first branch instruction (e.g., branch type), the first branch instruction address, and the first branch target address.

[0072] Figure 4 The method also includes (e.g., by branch target predictor 104 of branch predictor 102) storing 406 entries 204 as identifiers of the first branch target address. For example, entry 204 is stored to identify the first branch instruction address in the identifier field and the first branch target address in the target field. The generated entry also identifies the branch type of the first branch instruction in the branch type field, which includes information about whether the first branch target address is in the same prediction window as the first branch instruction address or in a subsequent prediction window. Since there are no references to other branch instructions in the target field, the type field will not reflect the relationship between the first branch instruction and another branch instruction (e.g., a second branch instruction).

[0073] To further explain, Figure 5A flowchart illustrating an exemplary method for merging branch target buffer entries is provided, the method comprising (e.g., by branch target predictor 104 of branch predictor 102 from execution unit 112) receiving 402 a first redirection 404 indicating a first branch instruction and a first branch instruction address; (e.g., by branch target predictor 104 of branch predictor 102) storing 406 entry 204 as an identifier of the first branch target address; maintaining 202 an entry 204 corresponding to the first branch instruction in branch target buffer 106 (e.g., by branch target predictor 104 of branch predictor 102), wherein the entry 204 identifies the first branch target address of the first branch instruction and the second branch target address of the second branch instruction; and accessing 206 entry 204 based on the first branch instruction (e.g., by branch target predictor 104 of branch predictor 102).

[0074] Figure 5 Methods and Figure 4 The difference is Figure 5 The method also includes a second redirection 504 (e.g., from execution unit 112 by branch target predictor 104 of branch predictor 102) receiving 502 an indication of a second branch instruction and a second branch target address. The second redirection 504 includes descriptions of: the second branch instruction (e.g., branch type), whether the second branch target instruction is at a taken path of the first branch or at a non-taken path of the first branch, whether the second branch target instruction is in the same prediction window as the first branch target instruction or in a subsequent prediction window, the address of the second branch instruction, and the address of the second branch target instruction.

[0075] Figure 5 The method also includes (e.g., by branch target predictor 104 of branch predictor 102) modifying entry 205 of 506 to identify the second branch target address and the first branch target address. Modifying entry 204 of 506 to identify the second branch target address and the first branch target address includes adding the number of the lowest order bits of the second branch target address, which differs from the address of the first branch instruction, to the target field of entry 204. Modifying entry 204 of 506 to identify the second branch target address and the first branch target address includes adding an indication of the second branch type to the branch type field of entry 204 and modifying the branch type field to reflect the relationship between the first branch target instruction and the second branch target instruction.

[0076] To further explain, Figure 6A flowchart illustrating an exemplary method for merging branch target buffer entries is provided, the method comprising (e.g., by branch target predictor 104 of branch predictor 102 from execution unit 112) receiving a first redirection 404 indicating a first branch instruction and a first branch instruction address; (e.g., by branch target predictor 104 of branch predictor 102) storing an entry 204 406 as an identifier of the first branch target address; and (e.g., by branch target predictor 104 of branch predictor 102 from execution unit 112) receiving a second redirection indicating a second branch instruction and a second branch target address. 504; (e.g., by the branch target predictor 104 of branch predictor 102) modify entry 205 of 506 to identify the second branch target address and the first branch target address; maintain entry 204 of 202 corresponding to the first branch instruction in the branch target buffer 106 (e.g., by the branch target predictor 104 of branch predictor 102), wherein the entry 204 identifies the first branch target address of the first branch instruction and the second branch target address of the second branch instruction; and access entry 204 of 206 based on the first branch instruction (e.g., by the branch target predictor 104 of branch predictor 102).

[0077] Figure 6 Methods and Figure 5 The difference is Figure 6 The method also includes (e.g., by branch target predictor 104 of branch predictor 102) determining 602 to modify entry 204 (e.g., the target field of entry 204) to identify the second branch target address and the first branch target address. For example, branch target predictor 104 determines the modification entry to identify the second branch target address and the first branch target address based on one or more merge rules.

[0078] The merging rule can be based on the instruction address of the second branch instruction. For example, branch target predictor 104 determines modification entries to identify the second branch target address and the first branch target address in response to the instruction address of the second branch instruction being included in the prediction window of the first branch target address. For example, suppose instruction fetch unit 114 loads a 64-byte instruction block starting at a given target address into instruction queue 112. Therefore, each branch target address corresponds to a 64-byte prediction window. The instruction address of the second branch instruction is within the prediction window of the first branch target address, where the second branch instruction address is within the 64 bytes of the first branch target address. Branch target predictor 104 can also determine modification entries to identify the second branch target address and the first branch target address in response to the instruction address of the second branch instruction being included in the next prediction window (e.g., the next 64-byte block) following the prediction window of the first branch target address.

[0079] Merging rules can also be based on the branch types of the first and second branch instructions. For example, specific combinations of branch instructions can be preferentially selected to modify entries to identify the second branch target address and the first branch target address. Merging rules can also prevent modifications to entries to identify certain combinations of branch types for the second and first branch target addresses. As a non-limiting example, if the first branch instruction is a call, merging rules can prevent modifications to entries when the second branch instruction is a call or a return, to avoid any call / call, call / return, return / call, or return / return combinations not supported by the return address stack. In some implementations, the maximum number of prediction blocks that can be hit for the branch target buffer 106 entries is a limitation on merging.

[0080] The branch target predictor 104 also determines, based on the number of bits required to identify the first branch target address and the second branch target address in the entry (e.g., the target field), to modify the entry 602 to identify the second branch target address and the first branch target address. For example, suppose a 32-bit addressing scheme is used where the first branch target address is the same as the first branch instruction address in its 16 highest-order bits, but different starting from the 17th bit. Therefore, the first branch target address requires 16 bits to identify the target field. In the case where the second branch target address differs from the first branch instruction address (used to index the entry) starting at the 13th bit, the second branch target address requires 12 bits to identify the target field. Therefore, the 32-bit target field can indicate both the first branch target address (using the 16 lowest-order bits of the first branch target address) and the second branch target address (using the 12 lowest-order bits of the second branch target address).

[0081] In light of the foregoing explanation, the reader will recognize that the benefits of the merged branch target buffer entries according to the embodiments of this disclosure include, in some embodiments and under certain circumstances, the following:

[0082] • Improved computational system performance by providing improved prediction bandwidth, thereby allowing multiple instruction blocks at a branch target address to be loaded into the instruction queue in a single access to the branch target buffer; and / or

[0083] • Improve the performance of the computing system by providing increased storage efficiency through branch target buffers; and / or

[0084] • Improve the performance of the computational system executing the software by generating multiple predicted instruction blocks from a single branch target buffer entry, thereby improving efficiency and power usage during software execution.

[0085] The advantages and features of this disclosure can be further described by the following statements:

[0086] 1. A method for merging branch target buffer entries, the method comprising: maintaining an entry in a branch target buffer corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of a second branch instruction; and accessing the entry based on the first branch instruction.

[0087] 2. The method according to statement 1 further includes storing data indicating the first branch target address and the second branch target address in a prediction queue based on entries.

[0088] 3. The method according to any one of statements 1 to 2, wherein the prediction queue is communicatively coupled to the instruction fetching unit, which is configured to load multiple instructions based on a first branch target address and a second branch target address.

[0089] 4. The method according to any one of statements 1 to 3 further includes: receiving a first redirection indicating a first branch instruction and a first branch target address; and storing an entry in a branch target buffer as an identifier for the first branch target address.

[0090] 5. The method according to any one of statements 1 to 4 further includes: receiving a second redirection indicating a second branch instruction and a second branch target address; and modifying an entry to identify the second branch target address and the first branch target address.

[0091] 6. The method according to any one of statements 1 to 5 further includes determining the modification entry to identify the second branch target address and the first branch target address based on one or more merge rules.

[0092] 7. The method according to any one of statements 1 to 6, wherein one or more merge rules are based on at least one of the following: the branch type of the first branch instruction, the branch type of the second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction.

[0093] 8. The method according to any one of statements 1 to 7, wherein determining the modification entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0094] 9. An apparatus comprising: a branch target predictor of merged branch target buffer entries, the branch target predictor being configured to: maintain in the branch target buffer an entry corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of a second branch instruction; and access the entry based on the first branch instruction.

[0095] 10. The branch target predictor according to statement 9 is further configured to store data indicating the first branch target address and the second branch target address in a prediction queue based on entries.

[0096] 11. The branch target predictor according to any one of statements 9 to 10, wherein the prediction queue is communicatively coupled to an instruction fetching unit configured to load a plurality of instructions based on a first branch target address and a second branch target address.

[0097] 12. The branch target predictor according to any one of statements 9 to 11, further configured to: receive a first redirection indicating a first branch instruction and a first branch target address; and store an entry in a branch target buffer as an identifier for the first branch target address.

[0098] 13. The branch target predictor according to any one of statements 9 to 12, further configured to: receive a second redirection indicating a second branch instruction and a second branch target address; and modify entries to identify the second branch target address and the first branch target address.

[0099] 14. The branch target predictor according to any one of statements 9 to 13, further configured to determine modification entries to identify the second branch target address and the first branch target address based on one or more merge rules.

[0100] 15. A branch target predictor according to any one of statements 9 to 14, wherein one or more merge rules are based on at least one of the following: the branch type of a first branch instruction, the branch type of a second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction.

[0101] 16. The branch target predictor according to any one of statements 9 to 15, wherein determining the modification entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0102] 17. A computing device comprising: a memory storing computer-readable instructions; and a processor communicating with the memory and comprising:

[0103] The processor core includes:

[0104] A branch target predictor for merged branch target buffer entries, the branch target predictor being configured to: maintain an entry in the branch target buffer corresponding to a first branch instruction of the computer-readable instructions, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of the second branch instruction; and access the entry based on the first branch instruction.

[0105] 18. The computing device according to statement 17, wherein the processor includes a system-on-a-chip.

[0106] 19. A method of operating a computing device to improve efficiency, the computing device including a memory and a processor in communication with the memory, the memory storing computer-readable instructions that execute on the processor, the method comprising: maintaining an entry in a branch target buffer of the processor for a first branch instruction corresponding to the computer-readable instructions, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of a second branch instruction; and accessing the entry based on the first branch instruction.

[0107] 20. The method according to statement 19 further includes storing data indicating the first branch target address and the second branch target address in a prediction queue based on entries.

[0108] 21. An apparatus for merging branch target buffer entries, the apparatus comprising: a processor including a branch target predictor configured to: maintain in a branch target buffer an entry corresponding to a first branch instruction, wherein the entry identifies a first branch target address of the first branch instruction and a second branch target address of a second branch instruction; and access the entry based on the first branch instruction.

[0109] 22. The apparatus according to statement 21, wherein the branch target predictor is further configured to store data indicating the first branch target address and the second branch target address in a prediction queue based on entries.

[0110] 23. The apparatus according to any one of statements 21 to 22, wherein the branch target predictor is further configured to: receive a first redirection indicating a first branch instruction and a first branch target address; and store an entry in a branch target buffer as an identifier of the first branch target address.

[0111] 24. The apparatus according to any one of statements 21 to 23, wherein the branch target predictor is further configured to:

[0112] Receives a second redirection indicating the second branch instruction and the second branch target address; and modifies the entries to identify the second branch target address and the first branch target address.

[0113] 25. The apparatus according to any one of statements 21 to 24, wherein the branch target predictor is further configured to determine a modification entry to identify the second branch target address and the first branch target address based on one or more merge rules.

[0114] 26. The apparatus according to any one of statements 21 to 25, wherein one or more merging rules are based on at least one of: the branch type of the first branch instruction, the branch type of the second branch instruction, the prediction window of the first branch instruction, or the instruction address of the second branch instruction.

[0115] 27. The apparatus according to any one of statements 21 to 26, wherein determining the modification entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

[0116] The exemplary embodiments of this disclosure are described primarily in the context of a fully functional computer system with merged branch target buffer entries. However, those skilled in the art will recognize that this disclosure can also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium can be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include disks in hard disk drives or floppy disks, optical disks in optical disk drives, magnetic tapes, and other media conceivable to those skilled in the art. Those skilled in the art will readily recognize that any computer system with appropriate programming means will be able to perform the steps of the methods of this disclosure as embodied in a computer program product. Those skilled in the art will also recognize that while some exemplary embodiments described in this specification are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or hardware are also within the scope of this disclosure.

[0117] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to perform aspects of this disclosure.

[0118] Figure 7 An exemplary computer-readable storage medium 700 according to an embodiment of the present disclosure is described. Figure 7The exemplary computer-readable storage medium 700 may include any type of computer-readable storage medium 700, including optical disc 702 (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray disc, etc.), magnetic disk 704 (e.g., floppy disk, compact disk), hard disk 706, solid-state drive (SSD) 708, random access memory (RAM) 710, etc. The computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be (e.g., but not limited to) electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A less complete list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanically encoded devices (such as punched cards or raised structures in slots on which instructions are recorded), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0119] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0120] Computer-readable program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet through an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions, specifically by using state information from the computer-readable program instructions to personalize the electronic circuitry to perform aspects of this disclosure.

[0121] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0122] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to obtain a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, form components for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. The computer apparatus (the processor may be embodied as a system-on-a-chip or a SoC) may include one or more processor cores. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of writing containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0123] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to obtain a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0124] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0125] As will be understood from the foregoing description, modifications and changes can be made to various embodiments of this disclosure. The description in this specification is for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is defined only by the language of the appended claims.

Claims

1. An apparatus comprising: The branch target predictor for the merged branch target buffer entries, the branch target predictor being configured as follows: An entry corresponding to the first branch instruction is maintained in the branch target buffer, wherein the entry includes a reduced first branch target address of the first branch instruction and a reduced second branch target address of the second branch instruction, wherein a different number of bits are allocated to each of the reduced first branch target address and the reduced second branch target address within the branch target buffer; and Access the entry based on the first branch instruction.

2. The apparatus of claim 1, wherein the branch target predictor is further configured to store data indicating the first branch target address and the second branch target address in a prediction queue based on the entry.

3. The apparatus of claim 2, wherein the prediction queue is communicatively coupled to the instruction extraction unit, the instruction extraction unit being configured to load a plurality of instructions based on the first branch target address and the second branch target address.

4. The apparatus of claim 1, wherein the branch target predictor is further configured to: Receive a first redirection indicating the first branch instruction and the first branch target address; and The entry is stored in the branch target buffer as an identifier for the first branch target address.

5. The apparatus of claim 4, wherein the branch target predictor is further configured to: Receive a second redirection indicating the second branch instruction and the second branch target address; and Modify the entries to identify the second branch target address and the first branch target address.

6. The apparatus of claim 5, wherein the branch target predictor is further configured to determine, based on one or more merging rules, to modify the entry to identify the second branch target address and the first branch target address.

7. The apparatus of claim 6, wherein the one or more merging rules are based on at least one of: the branch type of the first branch instruction, the branch type of the second branch instruction, or the instruction address of the second branch instruction, the instruction address being included in the next prediction window following the prediction window of the first branch instruction.

8. The apparatus of claim 6, wherein determining to modify the entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

9. A computing device, comprising: Memory, the memory storing computer-readable instructions; as well as A processor, which communicates with the memory and includes: Processor core, the processor core comprising: The branch target predictor for the merged branch target buffer entries, the branch target predictor being configured as follows: An entry corresponding to a first branch instruction of the computer-readable instructions is maintained in a branch target buffer, wherein the entry includes a reduced first branch target address of the first branch instruction and a reduced second branch target address of the second branch instruction, wherein a different number of bits are allocated to each of the reduced first branch target address and the reduced second branch target address within the branch target buffer; and Access the entry based on the first branch instruction.

10. The computing device of claim 9, wherein the processor comprises a system-on-a-chip.

11. An apparatus for merging branch target buffer entries, the apparatus comprising: The processor includes a branch target predictor, the branch target predictor being configured to: An entry corresponding to a first branch instruction is maintained in the branch target buffer, wherein the entry identifies the first branch target address of the first branch instruction and the second branch target address of the second branch instruction, wherein the entry further includes a field identifying the instruction type of the first branch instruction and the relationship type between the first branch instruction and the second branch instruction, wherein the relationship type indicates whether the second branch instruction is on the path taken by the first branch instruction or whether the first branch instruction is in a different prediction window than the second branch instruction; and Access the entry based on the first branch instruction.

12. The apparatus of claim 11, wherein the branch target predictor is further configured to store data indicating the first branch target address and the second branch target address in a prediction queue based on the entry.

13. The apparatus of claim 11, wherein the branch target predictor is further configured to: Receive a first redirection indicating the first branch instruction and the first branch target address; and The entry is stored in the branch target buffer as an identifier for the first branch target address.

14. The apparatus of claim 11, wherein the branch target predictor is further configured to: Receive a second redirection indicating the second branch instruction and the second branch target address; and Modify the entries to identify the second branch target address and the first branch target address.

15. The apparatus of claim 11, wherein the branch target predictor is further configured to determine, based on one or more merging rules, to modify the entry to identify the second branch target address and the first branch target address.

16. The apparatus of claim 15, wherein the one or more merging rules are based on at least one of: the branch type of the first branch instruction, the branch type of the second branch instruction, or the instruction address of the second branch instruction, the instruction address being included in the next prediction window following the prediction window of the first branch instruction.

17. The apparatus of claim 15, wherein determining to modify the entry to identify the second branch target address and the first branch target address is further based on the number of bits required to identify the first branch target address and the second branch target address in the entry.

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