Pixel circuit and driving method thereof, display panel and driving method thereof

Abstract

A pixel circuit (10) and a driving method thereof, a display panel and a driving method thereof, wherein the pixel circuit (10) is configured to drive a light-emitting element to emit light, and comprises: a current control subcircuit and a duration control subcircuit; the current control subcircuit is electrically connected to a current data terminal (DataI), a scan signal terminal (Gate), a reset signal terminal (Reset), an initial signal terminal (Vint), a light-emitting signal terminal (EM), a first power terminal (VDD), a first node (N1) and a second node (N2); the duration control subcircuit is electrically connected to a first control terminal (CT1), a second control terminal ( CT2), a time data terminal (DataT), a ground terminal (GND), a light signal terminal (EM), a high frequency input terminal (Hf) and a first node (N1) are electrically connected; the time when the first control terminal (CT1) receives the effective level signal is within the time when the reset signal terminal (Reset) receives the effective level signal, the time when the second control terminal (CT2) receives the effective level signal is within the time when the reset signal terminal (Reset) receives the effective level signal, and the time when the first control terminal (CT1) receives the effective level signal does not overlap with the time when the second control terminal (CT2) receives the effective level signal.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a pixel circuit and a driving method thereof, a display panel and a driving method thereof. Background Art

[0002] The display market is currently booming, and as consumer demand for a variety of display products such as laptops, smartphones, TVs, tablets, smart watches and fitness bands continues to increase, more new display products will emerge in the future. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure further provides a pixel circuit configured to drive a light-emitting element to emit light, comprising: a current control subcircuit and a duration control subcircuit;

[0005] The current control subcircuit is electrically connected to the current data terminal, the scan signal terminal, the reset signal terminal, the initial signal terminal, the light emitting signal terminal, the first power supply terminal, the first node and the second node respectively, and is configured to provide a driving current to the second node under the control of the current data terminal, the scan signal terminal, the reset signal terminal, the initial signal terminal, the light emitting signal terminal, the first power supply terminal and the first node;

[0006] The duration control subcircuit is electrically connected to the first control terminal, the second control terminal, the duration data terminal, the ground terminal, the light signal terminal, the high-frequency input terminal and the first node, respectively, and is configured to provide the first node with a signal from the light signal terminal or a signal from the high-frequency input terminal under the control of the first control terminal, the second control terminal, the duration data terminal and the ground terminal;

[0007] The light emitting element is electrically connected to the second node and the second power supply terminal respectively;

[0008] The time when the first control end receives the valid level signal is within the time when the reset signal end receives the valid level signal, the time when the second control end receives the valid level signal is within the time when the reset signal end receives the valid level signal, and the time when the first control end receives the valid level signal does not overlap with the time when the second control end receives the valid level signal.

[0009] In some possible implementations, the current control subcircuit includes: a node control subcircuit, a writing subcircuit, a driving subcircuit, and a light emitting control subcircuit;

[0010] The node control subcircuit is electrically connected to the scan signal terminal, the reset signal terminal, the initial signal terminal, the second node, the third node, the fourth node and the first power supply terminal respectively, and is configured to provide the signal of the initial signal terminal to the second node and the third node, and provide the signal of the third node to the fourth node under the control of the reset signal terminal and the scan signal terminal;

[0011] The writing subcircuit is electrically connected to the scanning signal terminal, the current data terminal and the fifth node respectively, and is configured to provide a signal of the current data terminal to the fifth node under the control of the scanning signal terminal;

[0012] The driving subcircuit is electrically connected to the third node, the fourth node and the fifth node respectively, and is configured to provide a driving current to the fourth node under the control of the third node and the fifth node;

[0013] The light-emitting control subcircuit is electrically connected to the light-emitting signal terminal, the first node, the second node, the fourth node, the fifth node and the first power supply terminal, respectively, and is configured to provide a signal from the first power supply terminal to the fifth node and a signal from the fourth node to the second node under the control of the first node and the light-emitting signal terminal.

[0014] In some possible implementations, the node control subcircuit includes: a first transistor, a second transistor, a third transistor and a first capacitor, the writing subcircuit includes: a fourth transistor, the driving subcircuit includes: a fifth transistor, and the light emitting control subcircuit includes: a sixth transistor, a seventh transistor and an eighth transistor;

[0015] The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0016] The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0017] The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node;

[0018] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal;

[0019] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal;

[0020] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0021] The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0022] The control electrode of the seventh transistor is electrically connected to the light emitting signal terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

[0023] The control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node;

[0024] The first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are switch transistors, and the fifth transistor is a driving transistor.

[0025] In some possible implementations, the node control subcircuit includes: a first transistor, a second transistor, a third transistor and a first capacitor, the writing subcircuit includes: a fourth transistor, the driving subcircuit includes: a fifth transistor, and the light emitting control subcircuit includes: a sixth transistor and an eighth transistor;

[0026] The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0027] The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0028] The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node;

[0029] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal;

[0030] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal;

[0031] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0032] The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0033] The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the second node;

[0034] The first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor are switch transistors, and the fifth transistor is a driving transistor.

[0035] In some possible implementations, the duration control subcircuit includes: a first control subcircuit and a second control subcircuit;

[0036] The first control subcircuit is electrically connected to the duration data terminal, the second control terminal, the ground terminal, the light emitting signal terminal and the first node respectively, and is configured to provide a signal of the light emitting signal terminal to the first node under the control of the duration data terminal, the second control terminal and the ground terminal;

[0037] The second control subcircuit is electrically connected to the duration data terminal, the first control terminal, the ground terminal, the high-frequency input terminal and the first node, respectively, and is configured to provide a signal from the high-frequency input terminal to the first node under the control of the duration data terminal, the first control terminal and the ground terminal.

[0038] In some possible implementations, the first control subcircuit includes: a ninth transistor, a tenth transistor, and a second capacitor; the second control subcircuit includes: an eleventh transistor, a twelfth transistor, and a third capacitor;

[0039] The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the light emitting signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0040] The control electrode of the tenth transistor is electrically connected to the second control terminal, the first electrode of the tenth transistor is electrically connected to the duration data terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node;

[0041] The first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the ground terminal;

[0042] The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the high frequency input terminal, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0043] The control electrode of the twelfth transistor is electrically connected to the first control terminal, the first electrode of the twelfth transistor is electrically connected to the duration data terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node;

[0044] The first end of the third capacitor is electrically connected to the seventh node, and the second end of the third capacitor is electrically connected to the ground terminal;

[0045] The ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are switch transistors.

[0046] In some possible implementations, the current control subcircuit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the duration control subcircuit includes: a ninth transistor, a tenth transistor, a second capacitor, an eleventh transistor, a twelfth transistor, and a third capacitor;

[0047] The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0048] The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0049] The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node;

[0050] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal;

[0051] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal;

[0052] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0053] The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0054] The control electrode of the seventh transistor is electrically connected to the light emitting signal terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

[0055] The control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node;

[0056] The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the light emitting signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0057] The control electrode of the tenth transistor is electrically connected to the second control terminal, the first electrode of the tenth transistor is electrically connected to the duration data terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node;

[0058] The first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the ground terminal;

[0059] The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the high frequency input terminal, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0060] The control electrode of the twelfth transistor is electrically connected to the first control terminal, the first electrode of the twelfth transistor is electrically connected to the duration data terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node;

[0061] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the ground.

[0062] In some possible implementations, the current control subcircuit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor, and an eighth transistor; the duration control subcircuit includes: a ninth transistor, a tenth transistor, a second capacitor, an eleventh transistor, a twelfth transistor, and a third capacitor;

[0063] The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0064] The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0065] The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node;

[0066] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal;

[0067] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal;

[0068] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0069] The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0070] The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the second node;

[0071] The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the light emitting signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0072] The control electrode of the tenth transistor is electrically connected to the second control terminal, the first electrode of the tenth transistor is electrically connected to the duration data terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node;

[0073] The first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the ground terminal;

[0074] The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the high-frequency input terminal, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0075] The control electrode of the twelfth transistor is electrically connected to the first control terminal, the first electrode of the twelfth transistor is electrically connected to the duration data terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node;

[0076] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the ground.

[0077] In some possible implementations, the duration data terminal receives the valid level signal at one of the times when the first control terminal receives the valid level signal or the times when the second control terminal receives the valid level signal.

[0078] In some possible implementations, when the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the time for the duration data terminal to receive the valid level signal is within the time for the second control terminal to receive the valid level signal.

[0079] When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the time when the duration data terminal receives the effective level signal is within the time when the first control terminal receives the effective level signal.

[0080] In a second aspect, the present disclosure further provides a display panel, comprising: M rows and N columns of pixel units, N current data lines arranged in sequence along the row direction, and N duration data lines arranged in sequence along the row direction, each pixel unit comprising a pixel circuit and a light-emitting element, the pixel circuit being the pixel circuit according to any one of claims 1 to 10;

[0081] The i-th column current data line and the i-th column duration data line are respectively located on both sides of the i-th column pixel unit, the current data end of the pixel circuit of the i-th column pixel unit is electrically connected to the i-th column current data line, and the duration data end of the pixel circuit of the i-th column pixel unit is electrically connected to the i-th column duration data line, 1≤i≤N;

[0082] The two current data lines between two adjacent columns of pixel units, and / or the two duration data lines between two adjacent columns of pixel units, and / or the duration data line and current data line between two adjacent columns of pixel units, do not overlap in the time when they receive effective level signals.

[0083] In some possible implementations, the method further includes: a first current selection signal line, a second current selection signal line, a first duration selection signal line, and a second duration selection signal line;

[0084] Two adjacent columns of current data lines are electrically connected to the first current selection signal line and the second current selection signal line, respectively, and two adjacent columns of duration data lines are electrically connected to the first duration selection signal line and the second duration selection signal line, respectively;

[0085] The time when the first duration selection signal line receives the valid level signal is within the time when the duration data line connected to the first duration selection signal line is connected to the reset signal end in the pixel circuit to receive the valid level signal, the time when the second duration selection signal line receives the valid level signal is within the time when the duration data line connected to the second duration selection signal line is connected to the reset signal end in the pixel circuit to receive the valid level signal, the time when the first current selection signal line receives the valid level signal is within the time when the current data line connected to the first current selection signal line is connected to the scanning signal end in the pixel circuit to receive the valid level signal, and the time when the second current selection signal line receives the valid level signal is within the time when the current data line connected to the second current selection signal line is connected to the scanning signal end in the pixel circuit to receive the valid level signal;

[0086] The time when the first duration selection signal line receives the effective level signal does not coincide with the time when the second duration selection signal line receives the effective level signal, and the time when the first current selection signal line receives the effective level signal does not coincide with the time when the second current selection signal line receives the effective level signal.

[0087] In some possible implementations, the method further includes: M scan signal lines sequentially arranged along the column direction, M reset signal lines sequentially arranged along the column direction, and M light emitting signal lines sequentially arranged along the column direction;

[0088] For each pixel circuit in the mth row of pixel units, the scan signal terminal of the pixel circuit is electrically connected to the mth row of scan signal lines, the reset signal terminal of the pixel circuit is electrically connected to the mth row of reset signal lines, and the light-emitting signal terminal of the pixel circuit is electrically connected to the mth row of light-emitting signal lines, 1≤m≤M.

[0089] In some possible implementations, the method further includes: 4M control signal lines arranged sequentially along the column direction, the pixel circuits in the m-th row of pixel units are electrically connected to the 4m-3-th row of control signal lines, the 4m-2-th row of control signal lines, the 4m-1-th row of control signal lines and the 4m-th row of control signal lines, respectively, 1≤m≤M;

[0090] When the mth row of pixel units is displayed, the time when the 4m-3th row of control signal lines receives the valid level signal, the time when the 4m-2th row of control signal lines receives the valid level signal, the time when the 4m-1th row of control signal lines receives the valid level signal and the time when the 4mth row of control signal lines receives the valid level signal are within the time when the reset signal terminal in the pixel circuit in the pixel unit receives the valid level signal, and the time when the 4m-3th row of control signal lines receives the valid level signal, the time when the 4m-2th row of control signal lines receives the valid level signal, the time when the 4m-1th row of control signal lines receives the valid level signal and the time when the 4mth row of control signal lines receives the valid level signal do not overlap.

[0091] In some possible implementations, the first control terminal of the pixel circuit in the pixel unit in the odd column of the mth row is electrically connected to the control signal line in the 4m-3th row, and the second control terminal of the pixel circuit in the pixel unit in the odd column of the mth row is electrically connected to the control signal line in the 4m-2th row;

[0092] The first control terminal of the pixel circuit in the even-numbered column pixel unit of the mth row is electrically connected to the 4m-1th row control signal line, and the second control terminal of the pixel circuit in the even-numbered column pixel unit of the mth row is electrically connected to the 4mth row control signal line.

[0093] In some possible implementations, the method further includes: 2M control signal lines arranged sequentially along the column direction, the first control end of the pixel circuit in the pixel unit in the mth row is electrically connected to the control signal line in the 2m-1th row, the second control end of the pixel circuit in the pixel unit in the mth row is electrically connected to the control signal line in the 2mth row, 1≤m≤M;

[0094] When the mth row of pixel units is displayed, the time when the 2m-1th row of control signal lines receives the valid level signal and the time when the 2mth row of control signal lines receives the valid level signal are within the time when the reset signal terminal in the pixel circuit in the pixel unit receives the valid level signal, and the time when the 2m-1th row of control signal lines receives the valid level signal and the time when the 2mth row of control signal lines receives the valid level signal do not overlap.

[0095] In some possible implementations, the method further includes: a multi-channel output selection circuit, K current data output lines arranged in sequence along the column direction, and K duration data output lines arranged in sequence along the column direction, where K=N / 2;

[0096] The multi-channel output selection circuit is electrically connected to N current data lines, N duration data lines, K current data output lines, K duration data output lines, a first current selection signal line, a second current selection signal line, a first duration selection signal line, and a second duration selection signal line, respectively, and is configured to output the data signals of the K current data output lines to the N current data lines in a time-sharing manner, and output the data signals of the K duration data output lines to the N duration data lines in a time-sharing manner, under the control of the first current selection signal line, the second current selection signal line, the first duration selection signal line, and the second duration selection signal line.

[0097] In some possible implementations, the multi-channel output selection circuit includes: K first current selection transistors, K second current selection transistors, K first time length selection transistors, and K second time length selection transistors;

[0098] The control electrode of the kth first current selection transistor is electrically connected to the first current selection signal line, the first electrode of the kth first current selection transistor is electrically connected to the 2k-1th column current data line, and the second electrode of the kth first current selection transistor is electrically connected to the kth column current data output line, 1≤k≤N / 2;

[0099] The control electrode of the kth second current selection transistor is electrically connected to the second current selection signal line, the first electrode of the kth second current selection transistor is electrically connected to the 2kth column current data line, and the second electrode of the kth second current selection transistor is electrically connected to the kth column current data output line;

[0100] The control electrode of the kth first duration selection transistor is electrically connected to the first duration selection signal line, the first electrode of the kth first duration selection transistor is electrically connected to the 2k-1th column duration data line, and the second electrode of the kth first duration selection transistor is electrically connected to the kth column duration data output line;

[0101] The control electrode of the kth second duration selection transistor is electrically connected to the second duration selection signal line, the first electrode of the kth second duration selection transistor is electrically connected to the 2kth column duration data line, and the second electrode of the kth second duration selection transistor is electrically connected to the kth column duration data output line;

[0102] The first current selection transistor, the second current selection transistor, the first time length selection transistor, and the second time length selection transistor are switch transistors.

[0103] In a third aspect, the present disclosure further provides a method for driving a pixel circuit, which is configured to drive the above-mentioned pixel circuit, and the method includes:

[0104] The node control subcircuit provides the signal of the initial signal terminal to the second node and the third node under the control of the reset signal terminal;

[0105] The node control subcircuit provides the signal of the third node to the fourth node under the control of the scan signal terminal, the write subcircuit provides the signal of the current data terminal to the fifth node under the control of the scan signal terminal, and the drive subcircuit provides the drive current to the fourth node under the control of the third node and the fifth node;

[0106] The light emitting control subcircuit provides the signal of the first power supply terminal to the fifth node and provides the signal of the fourth node to the second node under the control of the first node and the light emitting signal line;

[0107] When the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the method further comprises: the first control subcircuit provides a signal of the light-emitting signal terminal to the first node under the control of the current data terminal, the second control terminal and the ground terminal;

[0108] When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the method further includes: the second control subcircuit provides a signal of the high-frequency input terminal to the first node under the control of the duration data terminal, the first control terminal and the ground terminal.

[0109] In a fourth aspect, the present disclosure further provides a method for driving a display panel, which is configured to drive the above-mentioned display panel, and the method includes:

[0110] Signals are provided to N current data lines and along N time data lines, so that the time when two current data lines located between two adjacent columns of pixel units, and / or two time data lines located between two adjacent columns of pixel units, and / or the time data line and current data line located between two adjacent columns of pixel units receive effective level signals does not overlap.

[0111] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0113] Figure 1 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure;

[0114] Figure 2 A schematic diagram of the structure of a current control subcircuit provided by an exemplary embodiment;

[0115] Figure 3 An equivalent circuit diagram of a current control subcircuit provided for an exemplary embodiment;

[0116] Figure 4 An equivalent circuit diagram of a current control subcircuit provided for another exemplary embodiment;

[0117] Figure 5 A schematic diagram of the structure of a duration control subcircuit provided by an exemplary embodiment;

[0118] Figure 6 An equivalent circuit diagram of a duration control subcircuit provided for an exemplary embodiment;

[0119] Figure 7 An equivalent circuit diagram of a pixel circuit provided for an exemplary embodiment;

[0120] Figure 8 An equivalent circuit diagram of a pixel circuit provided for another exemplary embodiment;

[0121] Fig. 9 for Figure 7 A working timing diagram of a pixel circuit is provided;

[0122] Fig.10 for Figure 7 Another working timing diagram of the pixel circuit provided;

[0123] Fig.11 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0124] Fig.12 Another schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0125] Fig.13 A schematic diagram of the structure of a pixel unit provided by an exemplary embodiment;

[0126] Fig.14 A timing diagram of a plurality of selection signal lines provided for an exemplary embodiment;

[0127] Fig.15 A schematic structural diagram of a display panel provided by an exemplary embodiment;

[0128] Fig.16 for Fig.15 A timing diagram of the control signal lines in the provided display panel;

[0129] Fig.17 Another schematic structural diagram of a display panel provided by an exemplary embodiment;

[0130] Fig.18 for Fig.17 A timing diagram of the control signal lines in the provided display panel;

[0131] Fig.19 An equivalent circuit diagram of a multi-channel output selection circuit provided for an exemplary embodiment;

[0132] Fig. 20 A timing diagram of a display panel provided for an exemplary embodiment;

[0133] Fig.21 Another timing diagram of a display panel provided by an exemplary embodiment. DETAILED DESCRIPTION

[0134] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0135] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0136] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0137] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0138] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0139] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0140] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0141] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0142] For high-resolution display products, among multiple pixels arranged in an array, pixels located in the same column share a signal line, thereby saving wiring space and reducing the difficulty of process implementation.

[0143] In the case where the pixels of the high-resolution display product include a micro inorganic light-emitting diode, the micro inorganic light-emitting diode is a current-type driving element. When driven by a lower current density, color coordinate drift and low external quantum efficiency will occur, resulting in poor brightness uniformity, so that it is difficult to accurately display low grayscale by controlling the amplitude of the current alone. Therefore, it is necessary to control the current time length provided to the micro inorganic light-emitting diode while controlling the amplitude of the current provided to the micro inorganic light-emitting diode to achieve accurate grayscale display. It can be understood that in some embodiments, the pixel circuit used to provide a driving signal (current signal) to the micro inorganic light-emitting diode includes at least two types of data terminals: a current data terminal and a duration data terminal, wherein the current data terminal is configured to provide a current signal of different amplitudes to the micro inorganic light-emitting diode, and the duration data terminal is configured to control the time length of providing the above current signal to the micro light-emitting diode. The inventors found that when displaying low grayscale, after a short period of light emission in one frame, the micro inorganic light-emitting diode will enter a black state, so that the human eye can clearly feel the flicker, reducing the display effect of the display product.

[0144] Figure 1Schematic diagram of a pixel circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the pixel circuit 10 provided in the embodiment of the present disclosure is configured to drive a light-emitting element, and the pixel circuit includes: a current control subcircuit and a duration control subcircuit.

[0145] The current control subcircuit is electrically connected to the current data terminal DataI, the scan signal terminal Gate, the reset signal terminal Reset, the initial signal terminal Vint, the light-emitting signal terminal EM, the first power terminal VDD, the first node N1 and the second node N2, respectively, and is configured to provide a driving current to the second node N2 under the control of the current data terminal DataI, the scan signal terminal Gate, the reset signal terminal Reset, the initial signal terminal Vint, the light-emitting signal terminal EM, the first power terminal VDD and the first node N1. The duration control subcircuit is electrically connected to the first control terminal CT1, the second control terminal CT2, the duration data terminal DataT, the ground terminal GND, the light-emitting signal terminal EM, the high-frequency input terminal Hf and the first node N1, respectively, and is configured to provide a signal of the light-emitting signal terminal EM or a signal of the high-frequency input terminal Hf to the first node N1 under the control of the first control terminal CT1, the second control terminal CT2, the duration data terminal DataT and the ground terminal GND. The light-emitting element is electrically connected to the second node N2 and the second power terminal VSS, respectively.

[0146] The time when the first control terminal CT1 receives the valid level signal is within the time when the reset signal terminal Reset receives the valid level signal. The time when the second control terminal CT2 receives the valid level signal is within the time when the reset signal terminal Reset receives the valid level signal, and the time when the first control terminal CT1 receives the valid level signal and the time when the second control terminal CT2 receives the valid level signal do not overlap. Exemplarily, when the signal of the reset signal terminal Reset is a valid level signal, the signal of the first control terminal CT1 is a valid level signal, the signal of the second control terminal CT2 is a valid level signal, and the signal of the first control terminal CT1 and the signal of the second control terminal CT2 are not valid level signals at the same time.

[0147] In an exemplary embodiment, the signal at the duration data terminal DataT is written when the signal at the reset signal terminal Reset is a valid level signal.

[0148] In an exemplary embodiment, the first power supply terminal VDD is configured to transmit a DC voltage signal and continuously provide a high level signal, such as a DC high voltage. The second power supply terminal VSS is configured to transmit a DC voltage signal and continuously provide a low level signal, such as a DC low voltage.

[0149] In an exemplary embodiment, the signal of the high-frequency input terminal Hf is a pulse signal. For example, within an image frame, the signal of the high-frequency input terminal Hf has a plurality of pulses. Exemplarily, the frequency of the signal of the high-frequency input terminal Hf is greater than the frequency of the signal of the luminous signal terminal EM. For example, within a unit time, the number of times that the signal of the high-frequency input terminal has an effective level time period is greater than the number of times that the signal of the luminous signal terminal has an effective level time period.

[0150] In an exemplary embodiment, the signal of the high-frequency input terminal Hf is a high-frequency pulse signal. For example, the frequency of the signal of the high-frequency input terminal Hf is between 3000 Hz and 60000 Hz, for example, 3000 Hz or 60000 Hz. For example, the frequency of the light-emitting signal terminal EM is between 60 Hz and 120 Hz, for example, 60 Hz or 120 Hz. For example, the frame frequency of the display panel is 60 Hz, that is, within 1 second, the display panel can display 60 frames of images, and the display duration of each frame of the image is equal. In this way, when the signal frequency of the high-frequency input terminal Hf is 3000 Hz and the signal frequency of the light-emitting signal terminal EM is 60 Hz, in an image frame, if a light-emitting element is to emit low grayscale brightness, the light-emitting element can receive approximately 50 effective time periods of the high-frequency signal during the light-emitting stage (that is, the time period when the light-emitting signal terminal EM provides an effective signal).

[0151] In an exemplary embodiment, by controlling the duration control subcircuit to transmit the signal of the light-emitting signal terminal or the signal of the high-frequency input terminal to the current control subcircuit, controlling the conduction (opening) frequency of the current control subcircuit, and controlling the frequency of the conductive path formed between the pixel circuit and the light-emitting element, the frequency of the drive current transmitted to the light-emitting element can be controlled, and the sum of the durations of forming the conductive path is the total duration of the light-emitting element working, and the total duration of the light-emitting element working is the superposition of the sub-durations of the light-emitting element working when the conductive path is formed multiple times. In this way, the luminous intensity of the light-emitting element can be controlled by controlling the amplitude of the drive current, thereby realizing the grayscale display of the pixel unit.

[0152] In an exemplary embodiment, the range of the amplitude of the driving current can be within the range where the light-emitting element operates with high and stable luminous efficiency, good color coordinate uniformity and stable main wavelength of light output, for example, an interval with a larger driving current amplitude; therefore, the signal provided by the current data terminal when the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale can be the same as the signal value range provided by the current data terminal when the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale.

[0153] In an exemplary embodiment, when the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the duration control subcircuit transmits the signal of the light-emitting signal end to the current control subcircuit, and the current control subcircuit is always in an on state under the control of the light-emitting signal end. The pixel circuit and the light-emitting element always form a conductive path, and the driving current is continuously transmitted to the light-emitting element. Since the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the amplitude of the driving current corresponding to the driving current is relatively high, so that the light-emitting element can work under the drive of a driving signal with a higher amplitude, thereby ensuring the working efficiency of the light-emitting element.

[0154] In an exemplary embodiment, when the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the duration control subcircuit transmits the signal of the high-frequency input terminal to the current control subcircuit, and the current control subcircuit is in an alternating state of on and off under the control of the high-frequency pulse signal of the high-frequency input terminal, so that the driving current is intermittently transmitted to the light-emitting element, and the light-emitting element periodically receives the driving current, for example, the light-emitting element stops for a period of time after receiving the driving current for a period of time, and stops for a period of time after receiving the driving current for a period of time. In this way, the time for the pixel circuit and the light-emitting element to form a conductive path is shortened, and the time for the driving current to be transmitted to the light-emitting element is shortened. Therefore, when the grayscale displayed by the pixel unit where the pixel circuit is located is less than the threshold grayscale, the amplitude of the driving current can be maintained within a higher value range or maintained at a larger fixed amplitude, and the pixel unit can realize the corresponding low grayscale display by changing the working duration of the light-emitting element, thereby improving the working efficiency of the light-emitting element, avoiding the problem of low working efficiency and high power consumption of the light-emitting element when the low grayscale display is realized with a small current amplitude, avoiding the decrease in the uniformity of the displayed grayscale, avoiding the color deviation of the display, and improving the display effect of the display panel.

[0155] Exemplarily, the magnitude of the driving current is related to the current data signal received at the current data terminal, and the current data signal may be a signal that enables the light-emitting element to have a higher working efficiency, for example, the current data signal may be a signal that varies within a higher amplitude range or a signal with a higher fixed amplitude. In this case, the pixel circuit controls the time and frequency of the driving current transmitted to the light-emitting element through the current control subcircuit and the duration control subcircuit to control the grayscale display corresponding to the pixel unit.

[0156] In an image frame, when the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the human eye can clearly feel the flicker compared to when the light-emitting element works for a short time and then does not work for a long time. The light-emitting element in the embodiment of the present invention is intermittently in a working state, that is, the working state and the non-working state of the light-emitting element alternate with a large frequency, that is, the light-emitting element has a high frequency of alternating between light and dark, and the human eye is not easy to observe the flicker, thereby improving the display effect.

[0157] The pixel circuit provided by the embodiment of the present disclosure is configured to drive the light-emitting element to emit light, and includes: a current control subcircuit and a duration control subcircuit; the current control subcircuit is electrically connected to a current data terminal, a scan signal terminal, a reset signal terminal, an initial signal terminal, a light-emitting signal terminal, a first power supply terminal, a first node, and a second node, respectively, and is configured to provide a driving current to the second node under the control of the current data terminal, the scan signal terminal, the reset signal terminal, the initial signal terminal, the light-emitting signal terminal, the first power supply terminal, and the first node; the duration control subcircuit is electrically connected to a first control terminal, a second control terminal, a duration data terminal, a ground terminal, a light-emitting signal terminal, a high-frequency input terminal, and a first node, respectively, and is configured to provide a signal from the light-emitting signal terminal or a signal from the high-frequency input terminal to the first node under the control of the first control terminal, the second control terminal, the duration data terminal, and the ground terminal; the light-emitting element is electrically connected to the second node and the second power supply terminal, respectively; the time when the first control terminal receives the effective level signal is within the time when the reset signal terminal receives the effective level signal, the time when the second control terminal receives the effective level signal is within the time when the reset signal terminal receives the effective level signal, and the time when the first control terminal receives the effective level signal does not overlap with the time when the second control terminal receives the effective level signal. The present invention cooperates with the current control subcircuit and the duration control subcircuit to make the light-emitting element connected to the pixel circuit display a low gray scale with a higher frequency of alternating between bright and dark, making it difficult for the human eye to observe flicker, thereby improving the display effect of the display product.

[0158] In an exemplary embodiment, the first electrode of the light emitting element is electrically connected to the second node N2, the second electrode of the light emitting element is electrically connected to the second power supply terminal VSS, the first electrode of the light emitting element is the anode of the light emitting element, and the second electrode of the light emitting element is the cathode of the light emitting element.

[0159] Figure 2 FIG. 1 is a schematic diagram of a current control subcircuit provided by an exemplary embodiment. Figure 2As shown, in an exemplary embodiment, the current control subcircuit may include: a node control subcircuit, a write subcircuit, a drive subcircuit and a light control subcircuit. The node control subcircuit is electrically connected to the scan signal terminal Gate, the reset signal terminal Reset, the initial signal terminal Vint, the second node N2, the third node N3, the fourth node N4 and the first power supply terminal VDD, respectively, and is configured to provide the signal of the initial signal terminal Vint to the second node N2 and the third node N3 under the control of the reset signal terminal Reset and the scan signal terminal Gate, and to provide the signal of the third node N3 to the fourth node N4. The write subcircuit is electrically connected to the scan signal terminal Gate, the current data terminal DataI and the fifth node N5, respectively, and is configured to provide the signal of the current data terminal DataI to the fifth node N5 under the control of the scan signal terminal Gate. The drive subcircuit is electrically connected to the third node N3, the fourth node N4 and the fifth node N5, respectively, and is configured to provide a drive current to the fourth node N4 under the control of the third node N3 and the fifth node N5. The light-emitting control subcircuit is electrically connected to the light-emitting signal terminal EM, the first node N1, the second node N2, the fourth node N4, the fifth node N5 and the first power supply terminal VDD, respectively, and is configured to provide a signal from the first power supply terminal VDD to the fifth node N5 and a signal from the fourth node N4 to the second node N2 under the control of the first node N1 and the light-emitting signal terminal EM.

[0160] Figure 3 FIG. 1 is an equivalent circuit diagram of a current control subcircuit provided by an exemplary embodiment. Figure 3 As shown, in a current control subcircuit provided in an exemplary embodiment, the node control subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1, the write subcircuit may include: a fourth transistor T4, the drive subcircuit may include: a fifth transistor T5, and the light emitting control subcircuit may include: a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0161] The control electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal Vint, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the reset signal terminal Reset, the first electrode of the second transistor T2 is electrically connected to the initial signal terminal Vint, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the scan signal terminal Gate, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4. The first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first power supply terminal VDD. The control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the current data terminal DataI. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the light emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the light emitting signal terminal EM, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0162] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be switch transistors.

[0163] In an exemplary embodiment, the fifth transistor T5 may be a driving transistor.

[0164] Figure 4 FIG. 1 is an equivalent circuit diagram of a current control subcircuit provided for another exemplary embodiment. Figure 4As shown, in a current control subcircuit provided by an exemplary embodiment, the node control subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1, the write subcircuit may include: a fourth transistor T4, the drive subcircuit may include: a fifth transistor T5, and the light emitting control subcircuit may include: a sixth transistor T6 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal Vint, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the reset signal terminal Reset, the first electrode of the second transistor T2 is electrically connected to the initial signal terminal Vint, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the scan signal terminal Gate, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4. The first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first power supply terminal VDD. The control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the current data terminal DataI. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the light emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected to the first node N1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0165] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the sixth transistor T6 , and the eighth transistor T8 may be switch transistors.

[0166] In an exemplary embodiment, the fifth transistor T5 may be a driving transistor.

[0167] Figure 3 and Figure 4 An exemplary structure of the current control subcircuit is shown, but the implementation of the current control subcircuit is not limited thereto.

[0168] Figure 5 FIG. 1 is a schematic diagram of a time control subcircuit provided by an exemplary embodiment. Figure 5As shown, an exemplary embodiment provides a duration control subcircuit including: a first control subcircuit and a second control subcircuit. The first control subcircuit is electrically connected to the duration data terminal DataT, the second control terminal CT2, the ground terminal GND, the light emitting signal terminal EM and the first node N1, respectively, and is configured to provide the signal of the light emitting signal terminal EM to the first node N1 under the control of the duration data terminal DataT, the second control terminal CT2 and the ground terminal GND. The second control subcircuit is electrically connected to the duration data terminal DataT, the first control terminal CT1, the ground terminal GND, the high-frequency input terminal Hf and the first node N1, respectively, and is configured to provide the signal of the high-frequency input terminal Hf to the first node N1 under the control of the duration data terminal DataT, the first control terminal CT1 and the ground terminal GND.

[0169] Figure 6 FIG. 1 is an equivalent circuit diagram of a duration control subcircuit provided by an exemplary embodiment. Figure 6 As shown, an exemplary embodiment provides a duration control subcircuit, in which the first control subcircuit may include: a ninth transistor T9, a tenth transistor T10 and a second capacitor C2; the second control subcircuit may include: an eleventh transistor T11, a twelfth transistor T12 and a third capacitor C3.

[0170] The control electrode of the ninth transistor T9 is electrically connected to the sixth node N6, the first electrode of the ninth transistor T9 is electrically connected to the light emitting signal terminal EM, and the second electrode of the ninth transistor T9 is electrically connected to the first node N1. The control electrode of the tenth transistor T10 is electrically connected to the second control terminal CT2, the first electrode of the tenth transistor T10 is electrically connected to the duration data terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6. The first end of the second capacitor C2 is electrically connected to the sixth node N6, and the second end of the second capacitor C2 is electrically connected to the ground terminal GND. The control electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, the first electrode of the eleventh transistor T11 is electrically connected to the high frequency input terminal Hf, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1. The control electrode of the twelfth transistor T12 is electrically connected to the first control terminal CT1, the first electrode of the twelfth transistor T12 is electrically connected to the duration data terminal DataT, and the second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7. A first end of the third capacitor C3 is electrically connected to the seventh node N7, and a second end of the third capacitor C3 is electrically connected to the ground terminal GND.

[0171] In an exemplary embodiment, the ninth transistor T9 , the tenth transistor T10 , the eleventh transistor T11 , and the twelfth transistor T12 may be switch transistors.

[0172] Figure 6 An exemplary structure of the duration control subcircuit is shown, but the implementation of the duration control subcircuit is not limited thereto.

[0173] In an exemplary embodiment, the light-emitting element includes a current-driven device, and a current-type light-emitting diode may be used, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED) or an organic light-emitting diode (Organic Light Emitting Diode, OLED) or a quantum dot light-emitting diode (Quantum Light Emitting Diode, QLED).

[0174] Figure 7 FIG. 1 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment. Figure 7 As shown, a current control subcircuit in a pixel circuit provided by an exemplary embodiment may include: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8; the duration control subcircuit may include: a ninth transistor T9, a tenth transistor T10, a second capacitor C2, an eleventh transistor T11, a twelfth transistor T12 and a third capacitor C3.

[0175] The control electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal Vint, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the reset signal terminal Reset, the first electrode of the second transistor T2 is electrically connected to the initial signal terminal Vint, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the scan signal terminal Gate, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4. The first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first power supply terminal VDD. The control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the current data terminal DataI. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the light emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The control electrode of the seventh transistor T7 is electrically connected to the light emitting signal terminal EM, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The control electrode of the ninth transistor T9 is electrically connected to the sixth node N6, the first electrode of the ninth transistor T9 is electrically connected to the light emitting signal terminal EM, and the second electrode of the ninth transistor T9 is electrically connected to the first node N1. The control electrode of the tenth transistor T10 is electrically connected to the second control terminal CT2, the first electrode of the tenth transistor T10 is electrically connected to the duration data terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6. The first end of the second capacitor C2 is electrically connected to the sixth node N6, and the second end of the second capacitor C2 is electrically connected to the ground terminal GND. The control electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, the first electrode of the eleventh transistor T11 is electrically connected to the high frequency input terminal Hf, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1. The control electrode of the twelfth transistor T12 is electrically connected to the first control terminal CT1, the first electrode of the twelfth transistor T12 is electrically connected to the duration data terminal DataT, and the second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7. The first end of the third capacitor C3 is electrically connected to the seventh node N7, and the second end of the third capacitor C3 is electrically connected to the ground terminal GND.

[0176] In an exemplary embodiment, the first transistor T1 to the twelfth transistor T12 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.

[0177] In some possible implementations, the first transistor T1 to the twelfth transistor T12 may include P-type transistors and N-type transistors.

[0178] Figure 8 FIG. 1 is an equivalent circuit diagram of a pixel circuit provided by another exemplary embodiment. Figure 8 As shown, a current control subcircuit in a pixel circuit provided by an exemplary embodiment may include: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8. A duration control subcircuit may include: a ninth transistor T9, a tenth transistor T10, a second capacitor C2, an eleventh transistor T11, a twelfth transistor T12 and a third capacitor C3.

[0179] The control electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal Vint, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the reset signal terminal Reset, the first electrode of the second transistor T2 is electrically connected to the initial signal terminal Vint, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the scan signal terminal Gate, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4. The first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first power supply terminal VDD. The control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the current data terminal DataI. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the light emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The control electrode of the eighth transistor T8 is electrically connected to the first node N1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The control electrode of the ninth transistor T9 is electrically connected to the sixth node N6, the first electrode of the ninth transistor T9 is electrically connected to the light emitting signal terminal EM, and the second electrode of the ninth transistor T9 is electrically connected to the first node N1. The control electrode of the tenth transistor T10 is electrically connected to the second control terminal CT2, the first electrode of the tenth transistor T10 is electrically connected to the duration data terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6. The first end of the second capacitor C2 is electrically connected to the sixth node N6, and the second end of the second capacitor C2 is electrically connected to the ground terminal GND. The control electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, the first electrode of the eleventh transistor T11 is electrically connected to the high-frequency input terminal Hf, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1. The control electrode of the twelfth transistor T12 is electrically connected to the first control terminal CT1, the first electrode of the twelfth transistor T12 is electrically connected to the duration data terminal DataT, and the second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7. The first end of the third capacitor C3 is electrically connected to the seventh node N7, and the second end of the third capacitor C3 is electrically connected to the ground terminal GND.

[0180] In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 and the eighth transistor T8 to the twelfth transistor T12 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.

[0181] In an exemplary embodiment, the first to sixth transistors T1 to T6 and the eighth to twelfth transistors T8 to T12 may include P-type transistors and N-type transistors.

[0182] In an exemplary embodiment, the duration data terminal DataT receives the valid level signal at one of the time when the first control terminal CT1 receives the valid level signal or the time when the second control terminal CT2 receives the valid level signal. The signal of the duration data terminal DataT is not a valid level signal at the time when the first control terminal CT1 receives the valid level signal and the time when the second control terminal CT2 receives the valid level signal.

[0183] In an exemplary embodiment, when the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the time when the duration data terminal receives the valid level signal is within the time when the second control terminal receives the valid level signal. Exemplarily, when the light-emitting element connected to the pixel circuit displays a medium or high grayscale, when the signal of the second control terminal is a valid level signal, the signal of the duration data terminal is a valid level signal.

[0184] In an exemplary embodiment, when the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the time when the duration data terminal receives the valid level signal is within the time when the first control terminal receives the valid level signal. Exemplarily, when the light-emitting element connected to the pixel circuit displays a low grayscale, when the signal of the first control terminal is a valid level signal, the signal of the duration data terminal is a valid level signal, and a control signal can be provided to the first node through the high-frequency input terminal, and the light-emitting duration can be controlled through the high-frequency pulse signal of the high-frequency input terminal, so that the short light-emitting duration is dispersed into one frame time, and the flickering when the grayscale of the content displayed by the pixel unit is less than the threshold grayscale is reduced.

[0185] The following describes a pixel circuit provided by an exemplary embodiment through the working process of the pixel circuit.

[0186] by Figure 7 In the pixel circuit provided, the first transistor T1 to the twelfth transistor T12 are all P-type transistors. Fig. 9 for Figure 7 A working timing diagram of a pixel circuit is provided, Fig.10 for Figure 7 Another operating timing diagram of a pixel circuit is provided. Fig. 9The timing diagram of the pixel circuit when the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, Fig.10 The timing diagram of the pixel circuit when the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale. Figure 7 , Fig. 9 and Fig.10 As shown, a pixel circuit involved in an exemplary embodiment includes: 11 switching transistors (T1 to T4, T6 to T12), 1 driving transistor (T5), 3 capacitor units (C1 to C3), 9 input terminals (Gate, DataT, DataI, Reset, Vint, EM, Hf, CT1 and CT2) and 3 power supply terminals (GND, VDD and VSS).

[0187] When the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, such as Figure 7 and Fig. 9 As shown, the working process of the pixel circuit includes: an initialization stage, a writing stage and a light-emitting stage.

[0188] The first phase P11 is an initialization phase, and includes a first sub-phase p11 and a second sub-phase p12.

[0189] In the first sub-phase p11, the signal of the reset signal terminal Reset is a low-level signal, the first transistor T1 is turned on, so that the signal of the initial signal terminal Vint is written into the third node N3 to reset the third node N3 and charge the first capacitor C1, the second transistor T2 is turned on, so that the signal of the initial signal terminal Vint is written into the second node N2, the second node N2 is electrically connected to the anode of the light-emitting element L, the anode of the light-emitting element L is reset, and the residual charge of the anode of the light-emitting element L is eliminated. The signal of the first control terminal CT1 is a low-level signal, the twelfth transistor T12 is turned on, so that the signal of the duration data terminal DataT is written into the seventh node N7, and the third capacitor C3 is charged. Since the signal of the duration data terminal DataT is a high-level signal, the eleventh transistor T11 is turned off, and the signal of the high-frequency input terminal Hf cannot be written into the first node N1. In this stage, the signal of the second control terminal CT2 is a high-level signal, and the tenth transistor T10 is turned off.

[0190] In the second sub-phase p12, the signal of the reset signal terminal Reset is a low-level signal, the first transistor T1 is turned on, so that the signal of the initial signal terminal Vint is written into the third node N3 to reset the third node N3 and charge the first capacitor C1, the second transistor T2 is turned on, so that the signal of the initial signal terminal Vint is written into the second node N2, the second node N2 is electrically connected to the anode of the light-emitting element L, the anode of the light-emitting element L is reset, and the residual charge of the anode of the light-emitting element L is eliminated. The signal of the second control terminal CT2 is a low-level signal, the tenth transistor T10 is turned on, so that the signal of the duration data terminal DataT is written into the sixth node N6, and the second capacitor C2 is charged, and since the signal of the duration data terminal DataT is a low-level signal, the ninth transistor T9 is turned on, and the signal of the light-emitting signal terminal EM is written into the first node N1.

[0191] In the second stage P12, i.e., the writing stage, the signal of the scanning signal terminal Gate is a low-level signal, the fourth transistor T4 is turned on, the signal of the current data terminal DataI is written into the fifth node N5, and the third transistor T3 is turned on. At this time, the level V5 of the fifth node N5 is Vd, where Vd is the voltage value of the signal of the current data terminal DataI, and the first capacitor C1 begins to discharge to charge the third node N3 until the level V3 of the third node N3 is Vd+Vth, where Vth is the threshold voltage of the fifth transistor T5. At this time, the fifth transistor T5 is turned off. The second capacitor C2 keeps the potential of the signal of the sixth node N6 unchanged, and the ninth transistor T9 remains turned on. The signal of the luminous signal terminal EM is written into the first node N1.

[0192] In the third stage P13, i.e., the light-emitting stage, the signal at the light-emitting signal terminal EM is a low-level signal, the sixth transistor T6 is turned on, at this time, the level V5 of the fifth node N5 is Vdd, Vdd is the voltage value of the signal at the first power supply terminal VDD, the seventh transistor T7 is turned on, the second capacitor C2 keeps the potential of the signal at the sixth node N6 unchanged, the ninth transistor T9 remains turned on, the signal at the light-emitting signal terminal EM is written into the first node N1, and the eighth transistor T8 is turned on. Since the voltage value V3 of the third node N3 is Vd+Vth, the fifth transistor T5 is turned on, and the driving current flows into the light-emitting element L.

[0193] According to the current formula of the driving transistor when saturated, the driving current I flowing through the light-emitting element L can be obtained. OLED satisfy:

[0194] I OLED =(1 / 2)K(V GS –Vth) 2

[0195] =(1 / 2)K(V3–V5–Vth) 2

[0196] =(1 / 2)K(Vd+Vth-Vdd-Vth) 2

[0197] =(1 / 2)K(Vd-Vdd) 2

[0198] Where K is a fixed constant related to the process parameters and geometric dimensions of the driver transistor, V GS is the gate-source voltage difference of the driving transistor.

[0199] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current output by the fifth transistor T5 is no longer affected by the threshold voltage of the fifth transistor T5, but is only related to the signal at the current data end and the signal at the first power supply end, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current, ensuring the uniform display brightness of the display product and improving the display effect.

[0200] The pixel circuit is Figure 7 The working process of the pixel circuit is similar to Figure 8 The working process of the pixel circuit is roughly the same and will not be repeated here.

[0201] When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, such as Figure 7 and Fig.10 As shown, the working process of the pixel circuit includes: an initialization stage, a writing stage and a light-emitting stage.

[0202] The first phase P21 is an initialization phase, and includes a first sub-phase p21 and a second sub-phase p22.

[0203] In the first sub-phase p11, the signal of the reset signal terminal Reset is a low-level signal, the first transistor T1 is turned on, so that the signal of the initial signal terminal Vint is written into the third node N3 to reset the third node N3 and charge the first capacitor C1, the second transistor T2 is turned on, so that the signal of the initial signal terminal Vint is written into the second node N2, the second node N2 is electrically connected to the anode of the light-emitting element L, the anode of the light-emitting element L is reset, and the residual charge of the anode of the light-emitting element L is eliminated. The signal of the first control terminal CT1 is a low-level signal, the twelfth transistor T12 is turned on, so that the signal of the duration data terminal DataT is written into the seventh node N7, and the third capacitor C3 is charged. Since the signal of the duration data terminal DataT is a low-level signal, the eleventh transistor T11 is turned on, and the signal of the high-frequency input terminal Hf is written into the first node N1. In this stage, the signal of the second control terminal CT2 is a high-level signal, and the tenth transistor T10 is turned off.

[0204] In the second sub-phase p12, the signal of the reset signal terminal Reset is a low-level signal, the first transistor T1 is turned on, so that the signal of the initial signal terminal Vint is written into the third node N3 to reset the third node N3 and charge the first capacitor C1, the second transistor T2 is turned on, so that the signal of the initial signal terminal Vint is written into the second node N2, the second node N2 is electrically connected to the anode of the light-emitting element L, the anode of the light-emitting element L is reset, and the residual charge of the anode of the light-emitting element L is eliminated. The signal of the second control terminal CT2 is a low-level signal, the tenth transistor T10 is turned on, so that the signal of the duration data terminal DataT is written into the sixth node N6, and the second capacitor C2 is charged, because the signal of the duration data terminal DataT is a high-level signal, the ninth transistor T9 is turned off, and the signal of the light-emitting signal terminal EM cannot be written into the first node N1.

[0205] In the second stage P22, i.e., the writing stage, the signal of the scanning signal terminal Gate is a low-level signal, the fourth transistor T4 is turned on, the signal of the current data terminal DataI is written into the fifth node N5, the third transistor T3 is turned on, at this time, the level V5 of the fifth node N5 is Vd, Vd is the voltage value of the signal of the current data terminal DataI, the first capacitor C1 starts to discharge to charge the third node N3, until the level V3 of the third node N3 is Vd+Vth, Vth is the threshold voltage of the fifth transistor T5, at this time the fifth transistor T5 is turned off. The third capacitor C3 keeps the signal potential of the seventh node N7 unchanged, the eleventh transistor T11 is always turned on, and the signal of the high-frequency input terminal Hf is written into the first node N1.

[0206] In the third stage P23, i.e., the light-emitting stage, the signal at the light-emitting signal terminal EM is a low-level signal, the sixth transistor T6 is turned on, at this time, the level V5 of the fifth node N5 is Vdd, Vdd is the voltage value of the signal at the first power supply terminal VDD, the seventh transistor T7 is turned on, the third capacitor C3 keeps the signal potential of the seventh node N7 unchanged, the eleventh transistor T11 is always turned on, the signal at the light-emitting signal terminal EM is written into the first node N1, and the eighth transistor T8 is turned on. Since the voltage value V3 of the third node N3 is Vd+Vth, the fifth transistor T5 is turned on, and the driving current flows into the light-emitting element L.

[0207] According to the current formula of the driving transistor when saturated, the driving current I flowing through the light-emitting element L can be obtained. L satisfy:

[0208] I L =(1 / 2)K(V GS –Vth) 2

[0209] =(1 / 2)K(V3–V5–Vth) 2

[0210] =(1 / 2)K(Vd+Vth-Vdd-Vth) 2

[0211] =(1 / 2)K(Vd-Vdd) 2

[0212] Where K is a fixed constant related to the process parameters and geometric dimensions of the driver transistor, V GS is the gate-source voltage difference of the driving transistor.

[0213] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current output by the fifth transistor T5 is no longer affected by the threshold voltage of the fifth transistor T5, but is only related to the signal at the current data end and the signal at the first power supply end, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current, ensuring the uniform display brightness of the display product and improving the display effect.

[0214] In an exemplary embodiment, in the writing stage, the longer the time of writing the signal at the current data terminal is, the longer the time of threshold compensation of the pixel circuit can be extended. The time of writing the signal at the current data terminal depends on the time of the current selection signal line connected to the current data line connected to the current data terminal being in the effective level signal. The longer the time of the current selection signal line being in the effective level signal, the longer the time of writing the signal at the current data terminal is.

[0215] In an exemplary embodiment, when the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, a control signal is provided to the first node through the light-emitting signal terminal, and at this time, the grayscale of the light-emitting element is controlled by the driving current. When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, a control signal is provided to the first node through the high-frequency input terminal, and at this time, the grayscale of the light-emitting element is controlled by the driving current and the light-emitting duration. In an exemplary embodiment, the light-emitting duration is controlled by a high-frequency pulse signal at the high-frequency input terminal, and the short light-emitting duration is dispersed into one frame time, thereby reducing the flickering that occurs when the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, thereby improving the display effect of the display product.

[0216] The embodiment of the present disclosure also provides a display panel. Fig.11 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure is shown in FIG. Fig.12 Another schematic diagram of the structure of the display panel provided in the embodiment of the present disclosure is shown in FIG. Fig.13 FIG. 1 is a schematic diagram of a pixel unit structure provided by an exemplary embodiment. Figures 11 to 13 As shown, the display panel provided by the embodiment of the present disclosure includes: M rows and N columns of pixel units P, N current data lines DI1 to DI2 arranged in sequence along the row direction.N , N time-length data lines DT1 to DT arranged in sequence along the row direction N , each pixel unit P includes a pixel circuit 10 and a light emitting element 20 .

[0217] The i-th column current data line DI i and the i-th column duration data line DT i are respectively located on both sides of the pixel unit of the i-th column, the current data end of the pixel circuit of the pixel unit of the i-th column and the current data line DI of the i-th column i The duration data terminal of the pixel circuit of the i-th column pixel unit is electrically connected to the duration data line DT of the i-th column i Electrical connection, 1≤i≤N. The two current data lines between two adjacent columns of pixel units, and / or the two duration data lines between two adjacent columns of pixel units, and / or the duration data line and current data line between two adjacent columns of pixel units, do not overlap in the time when receiving effective level signals.

[0218] The pixel circuit is the pixel circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0219] like Fig.11 As shown, in an exemplary embodiment, the display panel may further include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a plurality of scan signal lines (S1 to S M ) and multiple light signal lines (E1 to E M ).

[0220] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, can provide clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light emitting signal driver to the light emitting signal driver.

[0221] In an exemplary embodiment, the data signal driver may generate a grayscale value and a control signal received from the timing controller to be provided to the current data lines DI1, DI2, . . . , DI N The data voltage is provided to a plurality of time-length data lines DT1, DT2, ..., DT N data voltage, N can be a natural number.

[0222] In an exemplary embodiment, the scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, . . . and S by receiving a clock signal, a scan start signal, etc. from the timing controller. MFor example, the scan signal driver may sequentially provide scan signals to the scan signal lines S1 to S2. M For example, the scan signal driver may be composed of a plurality of cascaded shift registers, and each shift register may generate a scan signal sequentially under the control of a clock signal, and M may be a natural number.

[0223] In an exemplary embodiment, the light emitting signal driver may generate a signal to be provided to the light emitting signal lines E1, E2, E3, . . . and E4 by receiving a clock signal from a timing controller, transmitting a stop signal, etc. M For example, the light emitting signal driver may sequentially provide light emitting signals to the light emitting signal lines E1 to E2. M For example, the light emitting signal driver may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate a light emitting signal under the control of a clock signal, and M may be a natural number.

[0224] In an exemplary embodiment, the display panel may further include a base substrate, and the pixel circuit and the light emitting element are both located on the base substrate.

[0225] In an exemplary embodiment, the substrate substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0226] In an exemplary embodiment, the pixel unit may be any one of a red (R) pixel unit, a green (G) pixel unit, a blue (B) pixel unit, and a white pixel unit, which is not limited in the present disclosure. When the display panel includes a red (R) pixel unit, a green (G) pixel unit, and a blue (B) pixel unit, the three pixel units may be arranged in parallel horizontally, in parallel vertically, or in a herringbone manner. When the display panel includes a red (R) pixel unit, a green (G) pixel unit, a blue (B) pixel unit, and a white pixel unit, the four pixel units may be arranged in parallel horizontally, in parallel vertically, or in an array manner, which is not limited in the present disclosure.

[0227] In an exemplary embodiment, the pixel circuit in the same pixel unit is electrically connected to the light emitting element and is configured to provide a driving signal to the light emitting element to drive the light emitting element to operate.

[0228] When a light-emitting element emits light, since the brightness of the light-emitting element when emitting light is related to its light-emitting duration and driving current, the brightness of the light-emitting element can be controlled by adjusting its light-emitting duration and driving current. For example, if the driving currents of two light-emitting elements are the same but the light-emitting durations are different, the brightness displayed by the two light-emitting elements is different; if the driving currents of the two light-emitting elements are different but the light-emitting durations are the same, the brightness displayed by the two light-emitting elements is also different; if the driving currents and light-emitting durations of the two light-emitting elements are different, whether the brightness displayed by the two light-emitting elements is the same remains to be analyzed.

[0229] In an exemplary embodiment, the light-emitting element in the red pixel unit is a red light-emitting diode, the light-emitting element in the blue pixel unit is a blue light-emitting diode, the light-emitting element in the green pixel unit is a green light-emitting diode, or the light-emitting elements of the red pixel unit, the blue pixel unit, the green pixel unit and the white pixel unit are all blue light-emitting diodes, and the corresponding colors of red, blue, green and white are achieved by combining color conversion materials (such as quantum dots, phosphors and other materials).

[0230] In an exemplary embodiment, the i-th column current data line DI i and the i-th column duration data line DT i The two sides of the pixel unit of the i-th column may include: the pixel unit of the i-th column and the pixel unit of the i+1th column are provided with the time-length data line DT of the i-th column i and the i+1th column current data line DI i+1 , or the i-th column current data line DI i and the i+1th column current data line DI i+1 , or the length of the data line DT in the i-th column i and the i+1th column duration data line DT i+1 , or the i-th column current data line DI i and the i+1th column duration data line DT i+1 . Figure 2 The i-th column duration data line DT is arranged between the i-th column pixel unit and the i+1-th column pixel unit. i and the i+1th column current data line DI i+1 This is explained as an example.

[0231] The present invention uses two current data lines located between two adjacent columns of pixel units, and / or two duration data lines located between two adjacent columns of pixel units, and / or a duration data line and a current data line located between two adjacent columns of pixel units, so that the times of receiving effective level signals do not overlap, thereby reducing crosstalk of signal lines between adjacent pixel units, avoiding poor column-wise brightness differences, and improving the display effect of the display product.

[0232] Fig.14 FIG. 1 is a timing diagram of multiple selection signal lines provided by an exemplary embodiment. Fig.12 and Fig.14 As shown, in an exemplary embodiment, the display panel may further include: a first current selection signal line DI_MUX1, a second current selection signal line DI_MUX2, a first time length selection signal line DT_MUX1, and a second time length selection signal line DT_MUX2. Two adjacent columns of current data lines are electrically connected to the first current selection signal line DI_MUX1 and the second current selection signal line DI_MUX2, respectively, and two adjacent columns of time length data lines are electrically connected to the first time length selection signal line DT_MUX1 and the second time length selection signal line DT_MUX2, respectively.

[0233] In an exemplary embodiment, the time when the first duration selection signal line DT_MUX1 receives the valid level signal is within the time when the duration data line connected to the first duration selection signal line DT_MUX1 is connected to the reset signal terminal in the pixel circuit to receive the valid level signal. When a row of pixels is displayed, the signal of the first duration selection signal line DT_MUX1 in the initialization stage is a valid level signal.

[0234] In an exemplary embodiment, the time when the second duration selection signal line DT_MUX2 receives the valid level signal is within the time when the duration data line connected to the second duration selection signal line DT_MUX1 is connected to the reset signal terminal in the pixel circuit to receive the valid level signal. When a row of pixels is displayed, the signal of the second duration selection signal line DT_MUX2 in the initialization stage is a valid level signal.

[0235] In an exemplary embodiment, the time when the first current selection signal line DI_MUX1 receives the valid level signal is within the time when the current data line connected to the first current selection signal line DI_MUX1 is connected to the scanning signal terminal in the pixel circuit to receive the valid level signal. When a row of pixels is displayed, the signal of the first current selection signal line DI_MUX1 in the writing stage is a valid level signal.

[0236] In an exemplary embodiment, the time when the second current selection signal line DI_MUX2 receives the valid level signal is within the time when the current data line connected to the second current selection signal line DI_MUX2 is connected to the scanning signal terminal in the pixel circuit to receive the valid level signal. When a row of pixels is displayed, the signal of the second current selection signal line DI_MUX2 in the writing stage is a valid level signal.

[0237] The time when the first duration selection signal line DT_MUX1 receives the valid level signal does not coincide with the time when the second duration selection signal line DT_MUX2 receives the valid level signal, and the time when the first current selection signal line DI_MUX1 receives the valid level signal does not coincide with the time when the second current selection signal line DI_MUX2 receives the valid level signal.

[0238] In an exemplary embodiment, the current data line coupled to the odd-numbered column pixel circuit is electrically connected to the first current selection signal line, and the duration data line coupled to the odd-numbered column pixel circuit is electrically connected to the first duration selection signal line. The current data line coupled to the even-numbered column pixel circuit is electrically connected to the second current selection signal line, and the duration data line coupled to the even-numbered column pixel circuit is electrically connected to the second duration selection signal line. Figure 2 The description is made by taking the example that the current data line coupled to the odd-numbered column pixel circuit is electrically connected to the first current selection signal line, the time length data line coupled to the odd-numbered column pixel circuit is electrically connected to the first time length selection signal line, the current data line coupled to the even-numbered column pixel circuit is electrically connected to the second current selection signal line, and the time length data line coupled to the even-numbered column pixel circuit is electrically connected to the second time length selection signal line.

[0239] In an exemplary embodiment, the current data line coupled to the even-numbered column pixel circuit is electrically connected to the first current selection signal line, the time length data line coupled to the even-numbered column pixel circuit is electrically connected to the first time length selection signal line, the current data line coupled to the odd-numbered column pixel circuit is electrically connected to the second current selection signal line, and the time length data line coupled to the odd-numbered column pixel circuit is electrically connected to the second time length selection signal line.

[0240] Since two adjacent columns of current data lines are electrically connected to different current selection signal lines, and two adjacent columns of duration data lines are electrically connected to different duration selection signal lines, the time when the first duration selection signal line DT_MUX1 receives the effective level signal does not coincide with the time when the second duration selection signal line DT_MUX2 receives the effective level signal, and the time when the first current selection signal line DI_MUX1 receives the effective level signal does not coincide with the time when the second current selection signal line DI_MUX2 receives the effective level signal. Therefore, in the writing phase of a row of pixel circuits, when one of the signal lines between the pixel unit in the i-th column and the pixel unit in the i+1-th column is in a floating state, the voltage of the signal of the other signal line has already completed the high and low level switching, that is, there will be no level change in the writing phase, avoiding interference between adjacent signal lines.

[0241] In an exemplary embodiment, Fig.12 and Fig.13 As shown, the display panel may further include: M reset signal lines (not shown in the figure) arranged in sequence along the column direction.

[0242] For each pixel circuit in the mth row of pixel units, the scanning signal terminal of the pixel circuit is connected to the scanning signal line S of the mth row. m The reset signal terminal of the pixel circuit is electrically connected to the reset signal line of the mth row, and the light emitting signal terminal of the pixel circuit is electrically connected to the light emitting signal line E of the mth row. m Electrical connection, 1≤m≤M.

[0243] The scanning signal terminals in the same row of pixel circuits are connected to the same scanning signal line, the reset signal terminals in the same row of pixel circuits are connected to the same reset signal line, the light-emitting signal terminals in the same row of pixel circuits are connected to the same signal line, and the initialization phase, writing phase and light-emitting phase of all pixel circuits in the same row of pixel circuits occur at the same time.

[0244] In an exemplary embodiment, Fig.15 A schematic diagram of the structure of a display panel provided by an exemplary embodiment is shown in FIG. Fig.16 for Fig.15 The timing diagram of the control signal lines in the display panel is provided. Fig.15 and 16 As shown, a display panel provided by an exemplary embodiment further includes: 4M control signal lines CTL1 to CTL 4M The pixel circuits 10 in the mth row of pixel units are respectively connected to the 4m-3th row of control signal lines CTL 4m-3 , 4m-2 row control signal line CTL 4m-2 , 4m-1 row control signal line CTL 4m-1 and the 4mth row control signal line CTL 4m Electrical connection, 1≤m≤M.

[0245] When the pixel unit of the mth row is displayed, the control signal line CTL of the 4m-3th row 4m-3 The time when the effective level signal is received, the 4m-2 row control signal line CTL 4m-2 The time when the effective level signal is received, the 4m-1 row control signal line CTL 4m-1 The time to receive the valid level signal and the 4mth row control signal line CTL 4m The time for receiving the effective level signal is within the time for the reset signal terminal in the pixel circuit in the pixel unit to receive the effective level signal. The 4m-3 row control signal line CTL connected to the pixel circuit in the same row 4m-3 , 4m-2 row control signal line CTL 4m-2 , 4m-1 row control signal line CTL 4m-1 and the 4mth row control signal line CTL 4m The effective level signal is received at least once in the initialization phase of the pixel circuit.

[0246] 4m-3 row control signal line CTL 4M-3 The time when the effective level signal is received, the time when the 4m-2th row control signal line receives the effective level signal, the time when the 4m-1th row control signal line receives the effective level signal and the time when the 4mth row control signal line receives the effective level signal do not overlap.

[0247] In an exemplary embodiment, the first control terminal CT1 of the pixel circuit in the odd-numbered column pixel unit of the mth row is connected to the control signal line CTL of the 4m-3th row. 4m-3 The second control terminal CT2 of the pixel circuit in the odd-numbered column pixel unit of the mth row is electrically connected to the control signal line CTL of the 4m-2th row. 4m-2 The first control terminal CT1 of the pixel circuit in the even-numbered column pixel unit of the mth row is electrically connected to the control signal line CTL of the 4m-1th row. 4m-1 The second control terminal CT2 of the pixel circuit in the even-numbered column pixel unit of the mth row is electrically connected to the control signal line CTL of the 4mth row. 4m Electrical connection.

[0248] like Fig.15 As shown, the working process of each pixel circuit in the i-th row of pixel units includes: initialization phase P1_i, writing phase P2_i and light-emitting phase P3_i. The initialization phase P1_i+1 and writing phase P2_i+1 of each pixel circuit in the i+1-th row of pixel units occur during the light-emitting phase P3_i of each pixel circuit in the i-th row of pixel units.

[0249] The first row control signal line CTL1 is an effective level signal in the first row pixel circuit initialization phase P1_1, the second row control signal line CTL2 is an effective level signal in the first row pixel circuit initialization phase P1_1, the third row control signal line CTL3 is an effective level signal in the first row pixel circuit initialization phase P1_1, and the fourth row control signal line CTL4 is an effective level signal in the first row pixel circuit initialization phase P1_1.

[0250] 1 is a valid level signal. The fifth row control signal line CTL5 is a valid level signal in the second row pixel circuit initialization stage P1_2, the sixth row control signal line CTL6 is a valid level signal in the second row pixel circuit initialization stage P1_2, the seventh row control signal line CTL7 is a valid level signal in the second row pixel circuit initialization stage P1_2, the eighth row control signal line CTL8 is a valid level signal in the second row pixel circuit initialization stage P1_2, and so on.

[0251] In an exemplary embodiment, Fig.17 Another schematic diagram of the structure of a display panel provided by an exemplary embodiment is shown in FIG. Fig.18 for Fig.17The timing diagram of the control signal lines in the display panel is provided. Fig.17 and Fig.18 As shown, a display panel provided by an exemplary embodiment further includes: 2M control signal lines CTL1 to CTL 2M The first control terminal of the pixel circuit 10 in the pixel unit of the mth row is connected to the control signal CTL of the 2m-1th row. 2m-1 The second control terminal of the pixel circuit in the mth row of pixel units is electrically connected to the 2mth row of control signal line CTL 2m Electrical connection, 1≤m≤M.

[0252] When the pixel unit of the mth row is displayed, the control signal line CTL of the 2m-1th row 2m-1 The time to receive the valid level signal and the 2mth row control signal line CTL 2m The time for receiving the effective level signal is within the time for the reset signal terminal in the pixel circuit in the pixel unit to receive the effective level signal. The 2m-1th row control signal line CTL connected to the pixel circuit in the same row 2m-1 and the 2mth row control signal line CTL 2m The effective level signal is received at least once in the initialization phase of the pixel circuit.

[0253] The time when the control signal line of the 2m-1th row receives the effective level signal does not coincide with the time when the control signal line of the 2mth row receives the effective level signal.

[0254] like Fig.18 As shown, the working process of each pixel circuit in the i-th row of pixel units includes: initialization phase P1_i, writing phase P2_i and light-emitting phase P3_i. The initialization phase P1_i+1 and writing phase P2_i+1 of each pixel circuit in the i+1-th row of pixel units occur during the light-emitting phase P3_i of each pixel circuit in the i-th row of pixel units.

[0255] The first row control signal line CTL1 is an effective level signal in the first row pixel circuit initialization phase P1_1, the second row control signal line CTL2 is an effective level signal in the first row pixel circuit initialization phase P1_1, the third row control signal line CTL3 is an effective level signal in the second row pixel circuit initialization phase P1_2, and the fourth row control signal line CTL4 is an effective level signal in the second row pixel circuit initialization phase P1_

[0256] 2 is a valid level signal, and so on.

[0257] In an exemplary embodiment, Fig.12 As shown, the display panel may further include: a multi-channel output selection circuit 20 and K current data output lines SI1 to SI2 arranged in sequence along the column direction. Kand K time-length data output lines ST1 to ST K , K=N / 2.

[0258] The multi-channel output selection circuit 20 is respectively connected to the N current data lines DI1 to DI N 、N length data lines DT1 to DT N , a first current selection signal line DI_MUX1, a second current selection signal line DI_MUX2, a first time length selection signal line DT_MUX1, a second time length selection signal line DT_MUX2, K current data output lines and K time length data output lines are electrically connected, and are configured to output data signals of the K current data output lines to N current data lines in a time-sharing manner, and output data signals of the K time length data output lines to N time length data lines in a time-sharing manner, under the control of the first current selection signal line DI_MUX1, the second current selection signal line DI_MUX2, the first time length selection signal line DT_MUX1 and the second time length selection signal line DT_MUX2.

[0259] like Fig.19 FIG. 1 is an equivalent circuit diagram of a multi-channel output selection circuit provided by an exemplary embodiment. Fig.19 As shown, in an exemplary embodiment, the multi-channel output selection circuit includes: K first current selection transistors MI1, K second current selection transistors MI2, K first time length selection transistors MT1, and K second time length selection transistors MT2.

[0260] The control electrode of the kth first current selection transistor MI1 is electrically connected to the first current selection signal line DI_MUX1, and the first electrode of the kth first current selection transistor MI1 is electrically connected to the 2k-1th column current data line DI 2k-1 The second electrode of the kth first current selection transistor MI1 is electrically connected to the kth column current data output line SI k Electrically connected, 1≤k≤N / 2. The control electrode of the first first current selection transistor MI1 is electrically connected to the first current selection signal line DI_MUX1, the first electrode of the first first current selection transistor MI1 is electrically connected to the first column current data line DI1, the second electrode of the first first current selection transistor MI1 is electrically connected to the first column current data output line SI1, the control electrode of the second first current selection transistor MI1 is electrically connected to the first current selection signal line DI_MUX1, the first electrode of the second first current selection transistor MI1 is electrically connected to the third column current data line DI3, the second electrode of the second first current selection transistor MI1 is electrically connected to the first column current data output line SI2, and so on.

[0261] The control electrode of the kth second current selection transistor MI2 is electrically connected to the second current selection signal line DI_MUX2, and the first electrode of the kth second current selection transistor MI2 is electrically connected to the 2kth column current data line DI 2k The second electrode of the kth second current selection transistor MI2 is electrically connected to the kth column current data output line SI k The control electrode of the first second current selection transistor MI2 is electrically connected to the second current selection signal line DI_MUX2, the first electrode of the first second current selection transistor MI2 is electrically connected to the second column current data line DI2, and the second electrode of the first second current selection transistor MI2 is electrically connected to the first column current data output line SI1. The control electrode of the second second current selection transistor MI2 is electrically connected to the second current selection signal line DI_MUX2, the first electrode of the second second current selection transistor MI2 is electrically connected to the fourth column current data line DI4, and the second electrode of the second second current selection transistor MI2 is electrically connected to the second column current data output line SI2, and so on.

[0262] The control electrode of the kth first duration selection transistor MT1 is electrically connected to the first duration selection signal line DT_MUX1, and the first electrode of the kth first duration selection transistor MT1 is electrically connected to the 2k-1th column duration data line DT 2k-1 The second electrode of the kth first time length selection transistor MT1 is electrically connected to the kth column time length data output line ST k Electrical connection. The control electrode of the first first time length selection transistor MT1 is electrically connected to the first time length selection signal line DT_MUX1, the first electrode of the first first time length selection transistor MT1 is electrically connected to the first column time length data line DT1, and the second electrode of the first first time length selection transistor MT1 is electrically connected to the first column time length data output line ST1. The control electrode of the second first time length selection transistor MT1 is electrically connected to the first time length selection signal line DT_MUX1, the first electrode of the second first time length selection transistor MT1 is electrically connected to the third column time length data line DT3, and the second electrode of the second first time length selection transistor MT1 is electrically connected to the third column time length data output line ST3, and so on.

[0263] The control electrode of the kth second duration selection transistor MT2 is electrically connected to the second duration selection signal line DT_MUX2, and the first electrode of the kth second duration selection transistor MT2 is electrically connected to the 2kth column duration data line DT 2k The second electrode of the kth second time length selection transistor MT2 is electrically connected to the kth column time length data output line ST kThe control electrode of the first second time length selection transistor MT2 is electrically connected to the second time length selection signal line DT_MUX2, the first electrode of the first second time length selection transistor MT2 is electrically connected to the second column time length data line DT2, and the second electrode of the first second time length selection transistor MT2 is electrically connected to the first column time length data output line ST1. The control electrode of the second second time length selection transistor MT2 is electrically connected to the second time length selection signal line DT_MUX2, the first electrode of the second second time length selection transistor MT2 is electrically connected to the fourth column time length data line DT4, and the second electrode of the second second time length selection transistor MT2 is electrically connected to the second column time length data output line ST2.

[0264] In an exemplary embodiment, the duration data output line ST i Time-sharing to the 2i-1th column time length data line DT 2i-1 and the 2ith column duration data line DT 2i Provides data signal. Current data output line SI i Time-sharing current to the 2i-1th column current data line DI 2i-1 and the 2ith column current data line DI 2i Provides data signal.

[0265] In an exemplary embodiment, the first current selection transistor MI1 , the second current selection transistor MI2 , the first time length selection transistor MT1 , and the second time length selection transistor MT2 may be switch transistors.

[0266] The first current selection transistor MI1 , the second current selection transistor MI2 , the first time length selection transistor MT1 , and the second time length selection transistor MT2 may all be P-type transistors, or may all be N-type transistors.

[0267] Taking the first current selection transistor MI1, the second current selection transistor MI2, the first time selection transistor MT1 and the second time selection transistor MT2 as P-type transistors as an example, Fig. 20 A timing diagram of a display panel provided for an exemplary embodiment. Fig. 20 The display panel provided is Fig.15 The corresponding display panel. Fig. 20 As shown, E i is the light emitting signal line connected to the light emitting signal terminal of each pixel circuit in the i-th row of pixel units, RL i is the reset signal line connected to the reset signal terminal of each pixel circuit in the i-th row of pixel units, S i is the scanning signal line connected to the scanning signal terminal of each pixel circuit in the i-th row of pixel units, CTL 4i-3 is a control signal line connected to the first control terminal of the pixel circuit in the pixel unit of the i-th row and the n-th column, CTL4i-2 is a control signal line connected to the second control terminal of the pixel circuit in the pixel unit in the i-th row and the n-th column, CTL 4i-1 is a control signal line connected to the first control terminal of the pixel circuit in the pixel unit in the i-th row and the n+1-th column, CTL 4i The control signal line connected to the second control terminal of the pixel circuit in the pixel unit of the i-th row and the n+1-th column. The operation process of each pixel circuit in the pixel unit of the i-th row includes: an initialization phase P1_i, a writing phase P2_i and a light emitting phase P3_i. i In the initialization phase, P1_i is a valid level signal, S i In the writing phase, P2_i is a valid level signal, E i In the light-emitting stage, P3_i is a valid level signal. CTL 4i-3 , CTL 4i-2 , CTL 4i-1 and CTL 4i When the pixel unit in the i-th row is in the initialization phase P1_i, it is a valid level signal, and CTL 4i-3 , CTL 4i-2 , CTL 4i-1 and CTL 4i They are not valid level signals at the same time.

[0268] like Fig. 20 As shown, E i+1 The light emitting signal line connected to the light emitting signal terminal of each pixel circuit in the pixel unit of the i+1th row, RL i+1 is the reset signal line connected to the reset signal terminal of each pixel circuit in the pixel unit of the i+1th row, S i+1 The scanning signal line connected to the scanning signal terminal of each pixel circuit in the pixel unit of the i+1th row, CTL 4i+1 The control signal line CTL is connected to the first control terminal of the pixel circuit in the pixel unit in the i+1th row and the nth column. 4i+2 is a control signal line connected to the second control terminal of the pixel circuit in the pixel unit in the i+1th row and the nth column, CTL 4i+3 The control signal line CTL is connected to the first control terminal of the pixel circuit in the pixel unit in the i+1th row and the n+1th column. 4i+4 The control signal line connected to the second control terminal of the pixel circuit in the pixel unit in the i+1th row and the n+1th column. The operation process of each pixel circuit in the pixel unit in the i+1th row includes: an initialization phase P1_i+1, a writing phase P2_i+2 and a light emitting phase. i+1 In the initialization phase, P1_i+1 is a valid level signal, S i+1 In the writing phase, P2_i+1 is a valid level signal, E i+1In the light-emitting stage, P3_i+1 is a valid level signal. CTL 4i-3 , CTL 4i-2 , CTL 4i-1 and CTL 4i When the pixel unit in the i+1th row is in the initialization phase P1_i+1, it is a valid level signal, and CTL 4i-3 , CTL 4i-2 , CTL 4i-1 and CTL 4i They are not valid level signals at the same time.

[0269] like Fig. 20 As shown, the initialization phase P1_i+1 of each pixel circuit in the i+1th row of pixel units occurs during the light emitting phase P3_i of each pixel circuit in the i-th row of pixel units.

[0270] like Fig. 20 As shown, DI n is the current data line connected to the current data terminal in the pixel circuit in the pixel unit in the i-th row and the n-th column, DT n is the duration data line connected to the duration data terminal in the pixel circuit in the pixel unit in the i-th row and the n-th column, DI n+1 is the current data line connected to the current data terminal in the pixel circuit in the pixel unit in the i-th row and the n+1-th column, DT n+1 The duration data line connected to the duration data terminal in the pixel circuit in the pixel unit in the i-th row and the n+1-th column, ST m For DT n and DT n+1 The connected duration data output line, SI m For DI n and DI n+1 The connected current data output line, m=(n+1) / 2, n is an odd number.

[0271] For the pixel unit in the i-th row and n-th column and the pixel unit in the i-th row and n+1-th column, DT n Electrically connected to the first time length selection signal line DT_MUX1, DT n+1 Electrically connected to the second time length selection signal line DT_MUX2, DI n Electrically connected to the first duration selection signal line DI_MUX1, DI n+1 Electrically connected to the second duration selection signal line DI_MUX2, DI n and DT n+1 Take the pixel unit located at the i-th row and n-th column and the pixel unit located at the i-th row and n+1-th column as an example. Fig. 20 As shown, the light emitting signal line E connected to the pixel circuit in the pixel unit in the i-th row and the n-th column and the pixel circuit in the pixel unit in the i-th row and the n+1-th column i, reset signal line RL i and scanning signal line G i is the same signal line. That is, the pixel circuit in the pixel unit of the i-th row and the n-th column and the pixel circuit in the pixel unit of the i-th row and the n+1-th column simultaneously and sequentially undergo the initialization phase, the writing phase and the light-emitting phase. Since the first time-length selection signal line DT_MUX1 and the second time-length selection signal line DT_MUX2 are valid level signals in the initialization phase P1_i of each pixel circuit of the i-th row pixel unit, and the first current selection signal line DI_MUX1 and the second time-length selection signal line DI_MUX2 are valid level signals in the writing phase P2_i of each pixel circuit of the i-th row pixel unit, therefore, when DI n+1 When the writing phase is in the floating state (i.e., the period when DI_MUX2 is at an invalid level), DT n The signal or DT n+1 The signal will not have voltage fluctuations, that is, DT n The signal or DT n+1 The signal has completed the corresponding voltage signal change, which can avoid DI n+1 The signal is affected by DT n+1 The disturbance caused by the change of signal level can avoid the poor difference between the brightness and darkness of the columns and improve the display effect of the display product. n When the writing phase is in the floating state (i.e., the period when DI_MUX1 is at an invalid level), DT n-1 The signal or DT n The signal will not have voltage fluctuations, that is, DT n The signal or DT n-1 The signal has completed the change of the corresponding voltage signal, which can avoid DI n The signal is affected by DT n-1 The disturbance caused by the change of signal level can avoid the poor brightness difference in the column direction and improve the display effect of the display product.

[0272] In an exemplary embodiment, Fig. 20 As shown, for the pixel circuit in the i-th row, the time when the first time selection signal line DT_MUX1 and the second time selection signal line DT_MUX2 receive the effective level signal is within the initialization phase P1_i of the pixel circuit in the i-th row. 4i-3 and CTL 4i-2 The time for receiving the effective level signal is within the time for the first time length selection signal line DT_MUX1 to receive the effective level signal. The time for CTL4i-1 and CTL4i to receive the effective level signal is within the time for the second time length selection signal line DT_MUX2 to receive the effective level signal. The time length data line DT n In CTL4i-3 The voltage value when receiving the effective level signal is connected to the length of time the pixel circuit in the i-th row and the n-th column is connected to the data line at CTL 4i-2 The voltage value when receiving the effective level signal is different. The pixel circuit in the i-th row and the n+1-th column is connected to the time-length data line DT n+1 In CTL 4i-1 The voltage value when receiving the effective level signal and the length of time the data line is connected to the pixel circuit of the i-th row and the n+1-th column at CTL 4i The voltage value when receiving a valid level signal is different.

[0273] Taking the first current selection transistor MI1, the second current selection transistor MI2, the first time selection transistor MT1 and the second time selection transistor MT2 as P-type transistors as an example, Fig.21 Another timing diagram of a display panel provided by an exemplary embodiment. Fig.21 The display panel provided is Fig.17 The corresponding display panel. Fig.21 As shown, E i is the light emitting signal line connected to the light emitting signal terminal of each pixel circuit in the i-th row of pixel units, RL i is the reset signal line connected to the reset signal terminal of each pixel circuit in the i-th row of pixel units, S i is the scanning signal line connected to the scanning signal terminal of each pixel circuit in the i-th row of pixel units, CTL 2i-1 is a control signal line connected to the first control terminal of the pixel circuit in the pixel unit of the i-th row, CTL 2i The control signal line connected to the second control terminal of the pixel circuit in the i-th row of pixel units. The operation process of each pixel circuit in the i-th row of pixel units includes: an initialization phase P1_i, a writing phase P2_i and a light emitting phase P3_i. i In the initialization phase, P1_i is a valid level signal, S i In the writing phase, P2_i is a valid level signal, E i In the light-emitting stage, P3_i is a valid level signal. CTL 2i-1 and CTL 2i When the pixel unit in the i-th row is in the initialization phase P1_i, it is a valid level signal, and CTL 2i-1 and CTL 2i They are not valid level signals at the same time.

[0274] like Fig.21 As shown, E i+1 The light emitting signal line connected to the light emitting signal terminal of each pixel circuit in the pixel unit of the i+1th row, RL i+1 is the reset signal line connected to the reset signal terminal of each pixel circuit in the pixel unit of the i+1th row, Si+1 The scanning signal line connected to the scanning signal terminal of each pixel circuit in the pixel unit of the i+1th row, CTL 2i+1 The control signal line CTL is connected to the first control terminal of the pixel circuit in the pixel unit of the i+1th row. 2i A control signal line connected to the second control terminal of the pixel circuit in the i+1th row of pixel units. The operation process of each pixel circuit in the i+1th row of pixel units includes: an initialization phase P1_i+1, a writing phase P2_i+1 and a light emitting phase P3_i+1. RL i+1 In the initialization phase, P1_i+1 is a valid level signal, S i+1 In the writing phase, P2_i+1 is a valid level signal, E i+1 In the light-emitting stage, P3_i+1 is a valid level signal. CTL 2i+1 and CTL 2i When the pixel unit in the i+1th row is in the initialization phase P1_i+1, it is a valid level signal, and CTL 2i+1 and CTL 2i They are not valid level signals at the same time.

[0275] like Fig.21 As shown, the initialization phase P1_i+1 of each pixel circuit in the i+1th row of pixel units occurs during the light emitting phase P3_i of each pixel circuit in the i-th row of pixel units.

[0276] like Fig.21 As shown, DI n is the current data line connected to the current data terminal in the pixel circuit in the pixel unit in the i-th row and the n-th column, DT n is the duration data line connected to the duration data terminal in the pixel circuit in the pixel unit in the i-th row and the n-th column, DI n+1 is the current data line connected to the current data terminal in the pixel circuit in the pixel unit in the i-th row and the n+1-th column, DT n+1 The duration data line connected to the duration data terminal in the pixel circuit in the pixel unit in the i-th row and the n+1-th column, ST m For DT n and DT n+1 The connected duration data output line, SI m For DI n and DI n+1 The connected current data output line, m=(n+1) / 2, n is an odd number.

[0277] For the pixel unit in the i-th row and n-th column and the pixel unit in the i-th row and n+1-th column, DT n Electrically connected to the first time length selection signal line DT_MUX1, DT n+1Electrically connected to the second time length selection signal line DT_MUX2, DI n Electrically connected to the first duration selection signal line DI_MUX1, DI n+1 Electrically connected to the second duration selection signal line DI_MUX2, DI n and DT n+1 Take the pixel unit located at the i-th row and n-th column and the pixel unit located at the i-th row and n+1-th column as an example. Fig. 20 As shown, the light emitting signal line E connected to the pixel circuit in the pixel unit in the i-th row and the n-th column and the pixel circuit in the pixel unit in the i-th row and the n+1-th column i , reset signal line RL i and scanning signal line G i is the same signal line. That is, the pixel circuit in the pixel unit of the i-th row and the n-th column and the pixel circuit in the pixel unit of the i-th row and the n+1-th column simultaneously and sequentially undergo the initialization phase, the writing phase and the light-emitting phase. Since the first time-length selection signal line DT_MUX1 and the second time-length selection signal line DT_MUX2 are valid level signals in the initialization phase P1_i of each pixel circuit of the i-th row pixel unit, and the first current selection signal line DI_MUX1 and the second time-length selection signal line DI_MUX2 are valid level signals in the writing phase P2_i of each pixel circuit of the i-th row pixel unit, therefore, when DI n+1 When the writing phase is in the floating state (i.e., the period when DI_MUX2 is at an invalid level), DT n The signal or DT n+1 The signal will not have voltage fluctuations, that is, DT n The signal or DT n+1 The signal has completed the corresponding voltage signal change, which can avoid DI n+1 The signal is affected by DT n+1 The disturbance caused by the change of signal level can avoid the poor difference between the brightness and darkness of the columns and improve the display effect of the display product. n When the writing phase is in the floating state (i.e., the period when DI_MUX1 is at an invalid level), DT n-1 The signal or DT n The signal will not have voltage fluctuations, that is, DT n The signal or DT n-1 The signal has completed the change of the corresponding voltage signal, which can avoid DI n The signal is affected by DT n-1 The disturbance caused by the change of signal level can avoid the poor brightness difference in the column direction and improve the display effect of the display product.

[0278] In an exemplary embodiment, Fig.21As shown, for the pixel circuit of the i-th row, the time when the first time selection signal line DT_MUX1 and the second time selection signal line DT_MUX2 receive the effective level signal is within the initialization phase P1_i of the pixel circuit of the i-th row. The time when the first time selection signal line DT_MUX1 receives the effective level signal is within CTL 2i-1 The time to receive a valid level signal or CTL 2i The second time length selects the time for the signal line DT_MUX2 to receive the valid level signal during CTL 2i-1 The time to receive a valid level signal or CTL 2i The time when the first time length selection signal line DT_MUX1 receives the effective level signal does not coincide with the time when the second time length selection signal line DT_MUX2 receives the effective level signal. The time length data line DT connected to the pixel circuit of the i-th row and the n-th column n In CTL 2i-1 The voltage value when receiving the effective level signal is connected to the length of time the pixel circuit in the i-th row and the n-th column is connected to the data line at CTL 2i The voltage value when receiving a valid level signal is different.

[0279] The embodiment of the present disclosure further provides a display device, including: a display panel.

[0280] The display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0281] In an exemplary embodiment, the display device may be any device that displays, whether in motion (e.g., video) or fixed (e.g., still image) and whether text or image. More specifically, the display device may be one of a variety of electronic devices, and may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PS1), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above-mentioned display devices.

[0282] The embodiment of the present disclosure further provides a driving method for a pixel circuit, and the driving method for a pixel circuit is configured to drive the pixel circuit. The driving method for a pixel circuit provided by the embodiment of the present disclosure includes:

[0283] The node control subcircuit provides the signal of the initial signal terminal to the second node and the third node under the control of the reset signal terminal.

[0284] The node control subcircuit provides the signal of the third node to the fourth node under the control of the scan signal terminal, the write subcircuit provides the signal of the current data terminal to the fifth node under the control of the scan signal terminal, and the drive subcircuit provides the drive current to the fourth node under the control of the third node and the fifth node.

[0285] Under the control of the first node and the light emitting signal line, the light emitting control subcircuit provides the signal of the first power supply terminal to the fifth node and provides the signal of the fourth node to the second node.

[0286] The pixel circuit is a display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0287] When the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, a driving method of the pixel circuit provided in an exemplary embodiment may also include: the first control subcircuit provides a signal of the light-emitting signal terminal to the first node under the control of the current data terminal, the second control terminal and the ground terminal.

[0288] When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, a driving method of the pixel circuit provided in an exemplary embodiment may also include: the second control subcircuit provides a signal of the high-frequency input terminal to the first node under the control of the duration data terminal, the first control terminal and the ground terminal.

[0289] The embodiment of the present disclosure further provides a method for driving a display panel, and the method for driving a display panel is configured to drive a display panel. The method for driving a display panel provided by the embodiment of the present disclosure includes:

[0290] Signals are provided to N current data lines and along N time data lines, so that the time when two current data lines located between two adjacent columns of pixel units, and / or two time data lines located between two adjacent columns of pixel units, and / or the time data line and current data line located between two adjacent columns of pixel units receive effective level signals does not overlap.

[0291] The display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0292] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0293] Although the implementation methods disclosed in the utility model are as above, the above contents are only implementation methods adopted to facilitate the understanding of the utility model, and are not used to limit the utility model. Any technician in the field to which the utility model belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the utility model, but the scope of patent protection of the utility model shall still be based on the scope defined in the attached claims.

Claims

1. A pixel circuit, configured to drive a light-emitting element to emit light, comprising: A current control subcircuit and a duration control subcircuit; The current control subcircuit is electrically connected to the current data terminal, the scan signal terminal, the reset signal terminal, the initial signal terminal, the light emitting signal terminal, the first power supply terminal, the first node and the second node respectively, and is configured to provide a driving current to the second node under the control of the current data terminal, the scan signal terminal, the reset signal terminal, the initial signal terminal, the light emitting signal terminal, the first power supply terminal and the first node; The duration control subcircuit is electrically connected to the first control terminal, the second control terminal, the duration data terminal, the ground terminal, the light signal terminal, the high-frequency input terminal and the first node, respectively, and is configured to provide the first node with a signal from the light signal terminal or a signal from the high-frequency input terminal under the control of the first control terminal, the second control terminal, the duration data terminal and the ground terminal; The light emitting element is electrically connected to the second node and the second power supply terminal respectively; The time when the first control terminal receives the effective level signal is within the time when the reset signal terminal receives the effective level signal, the time when the second control terminal receives the effective level signal is within the time when the reset signal terminal receives the effective level signal, and the time when the first control terminal receives the effective level signal and the time when the second control terminal receives the effective level signal do not overlap; The current control subcircuit comprises: a node control subcircuit, a writing subcircuit, a driving subcircuit and a light emitting control subcircuit; The node control subcircuit is electrically connected to the scan signal terminal, the reset signal terminal, the initial signal terminal, the second node, the third node, the fourth node and the first power supply terminal respectively, and is configured to provide the signal of the initial signal terminal to the second node and the third node, and provide the signal of the third node to the fourth node under the control of the reset signal terminal and the scan signal terminal; The writing subcircuit is electrically connected to the scanning signal terminal, the current data terminal and the fifth node respectively, and is configured to provide a signal of the current data terminal to the fifth node under the control of the scanning signal terminal; The driving subcircuit is electrically connected to the third node, the fourth node and the fifth node respectively, and is configured to provide a driving current to the fourth node under the control of the third node and the fifth node; The light-emitting control subcircuit is electrically connected to the light-emitting signal terminal, the first node, the second node, the fourth node, the fifth node and the first power supply terminal, respectively, and is configured to provide a signal from the first power supply terminal to the fifth node and provide a signal from the fourth node to the second node under the control of the first node and the light-emitting signal terminal; The duration control subcircuit comprises: a first control subcircuit and a second control subcircuit; The first control subcircuit is electrically connected to the duration data terminal, the second control terminal, the ground terminal, the light emitting signal terminal and the first node respectively, and is configured to provide a signal of the light emitting signal terminal to the first node under the control of the duration data terminal, the second control terminal and the ground terminal; The second control subcircuit is electrically connected to the duration data terminal, the first control terminal, the ground terminal, the high-frequency input terminal and the first node, respectively, and is configured to provide a signal from the high-frequency input terminal to the first node under the control of the duration data terminal, the first control terminal and the ground terminal.

2. The pixel circuit according to claim 1, wherein: The node control subcircuit includes: a first transistor, a second transistor, a third transistor and a first capacitor, the writing subcircuit includes: a fourth transistor, the driving subcircuit includes: a fifth transistor, and the light emitting control subcircuit includes: a sixth transistor, a seventh transistor and an eighth transistor; The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal; The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the light emitting signal terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; The control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node; The first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are switch transistors, and the fifth transistor is a driving transistor.

3. The pixel circuit according to claim 1, wherein: The node control subcircuit includes: a first transistor, a second transistor, a third transistor and a first capacitor, the writing subcircuit includes: a fourth transistor, the driving subcircuit includes: a fifth transistor, and the light emitting control subcircuit includes: a sixth transistor and an eighth transistor; The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal; The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the second node; The first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor are switch transistors, and the fifth transistor is a driving transistor.

4. The pixel circuit according to claim 1, wherein: The first control subcircuit includes: a ninth transistor, a tenth transistor and a second capacitor; the second control subcircuit includes: an eleventh transistor, a twelfth transistor and a third capacitor; The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the light emitting signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node; The control electrode of the tenth transistor is electrically connected to the second control terminal, the first electrode of the tenth transistor is electrically connected to the duration data terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node; The first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the ground terminal; The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the high frequency input terminal, and the second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the twelfth transistor is electrically connected to the first control terminal, the first electrode of the twelfth transistor is electrically connected to the duration data terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node; The first end of the third capacitor is electrically connected to the seventh node, and the second end of the third capacitor is electrically connected to the ground terminal; The ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are switch transistors.

5. The pixel circuit according to claim 1, wherein: The current control subcircuit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the duration control subcircuit includes: a ninth transistor, a tenth transistor, a second capacitor, an eleventh transistor, a twelfth transistor and a third capacitor; The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal; The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the light emitting signal terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; The control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node; The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the light emitting signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node; The control electrode of the tenth transistor is electrically connected to the second control terminal, the first electrode of the tenth transistor is electrically connected to the duration data terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node; The first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the ground terminal; The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the high frequency input terminal, and the second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the twelfth transistor is electrically connected to the first control terminal, the first electrode of the twelfth transistor is electrically connected to the duration data terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node; A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the ground.

6. The pixel circuit according to claim 1, wherein: The current control subcircuit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor and an eighth transistor; the duration control subcircuit includes: a ninth transistor, a tenth transistor, a second capacitor, an eleventh transistor, a twelfth transistor and a third capacitor; The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the reset signal terminal, the first electrode of the second transistor is electrically connected to the initial signal terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the first power supply terminal; The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the current data terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the second node; The control electrode of the ninth transistor is electrically connected to the sixth node, the first electrode of the ninth transistor is electrically connected to the light emitting signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node; The control electrode of the tenth transistor is electrically connected to the second control terminal, the first electrode of the tenth transistor is electrically connected to the duration data terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node; The first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the ground terminal; The control electrode of the eleventh transistor is electrically connected to the seventh node, the first electrode of the eleventh transistor is electrically connected to the high frequency input terminal, and the second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the twelfth transistor is electrically connected to the first control terminal, the first electrode of the twelfth transistor is electrically connected to the duration data terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node; A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the ground.

7. The pixel circuit according to claim 5 or 6, wherein: The duration data terminal receives the valid level signal at one of the time when the first control terminal receives the valid level signal or the time when the second control terminal receives the valid level signal.

8. The pixel circuit according to claim 7, wherein: When the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the time for the duration data terminal to receive the effective level signal is within the time for the second control terminal to receive the effective level signal. When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the time when the duration data terminal receives the effective level signal is within the time when the first control terminal receives the effective level signal.

9. A display panel, comprising: M rows and N columns of pixel units, N current data lines arranged in sequence along the row direction, and N duration data lines arranged in sequence along the row direction, each pixel unit comprises a pixel circuit and a light-emitting element, and the pixel circuit is the pixel circuit according to any one of claims 1 to 8; The i-th column current data line and the i-th column duration data line are respectively located on both sides of the i-th column pixel unit, the current data end of the pixel circuit of the i-th column pixel unit is electrically connected to the i-th column current data line, and the duration data end of the pixel circuit of the i-th column pixel unit is electrically connected to the i-th column duration data line, 1≤i≤N; The two current data lines between two adjacent columns of pixel units, and / or the two duration data lines between two adjacent columns of pixel units, and / or the duration data line and current data line between two adjacent columns of pixel units, do not overlap in the time when they receive effective level signals.

10. The display panel according to claim 9, further comprising: a first current selection signal line, a second current selection signal line, a first duration selection signal line, and a second duration selection signal line; Two adjacent columns of current data lines are electrically connected to the first current selection signal line and the second current selection signal line, respectively, and two adjacent columns of duration data lines are electrically connected to the first duration selection signal line and the second duration selection signal line, respectively; The time when the first duration selection signal line receives the valid level signal is within the time when the duration data line connected to the first duration selection signal line is connected to the reset signal end in the pixel circuit to receive the valid level signal, the time when the second duration selection signal line receives the valid level signal is within the time when the duration data line connected to the second duration selection signal line is connected to the reset signal end in the pixel circuit to receive the valid level signal, the time when the first current selection signal line receives the valid level signal is within the time when the current data line connected to the first current selection signal line is connected to the scanning signal end in the pixel circuit to receive the valid level signal, and the time when the second current selection signal line receives the valid level signal is within the time when the current data line connected to the second current selection signal line is connected to the scanning signal end in the pixel circuit to receive the valid level signal; The time when the first duration selection signal line receives the effective level signal does not coincide with the time when the second duration selection signal line receives the effective level signal, and the time when the first current selection signal line receives the effective level signal does not coincide with the time when the second current selection signal line receives the effective level signal.

11. The display panel according to claim 10, further comprising: M scanning signal lines arranged in sequence along the column direction, M reset signal lines arranged in sequence along the column direction, and M light emitting signal lines arranged in sequence along the column direction; For each pixel circuit in the mth row of pixel units, the scan signal terminal of the pixel circuit is electrically connected to the mth row of scan signal lines, the reset signal terminal of the pixel circuit is electrically connected to the mth row of reset signal lines, and the light-emitting signal terminal of the pixel circuit is electrically connected to the mth row of light-emitting signal lines, 1≤m≤M.

12. The display panel according to claim 9, further comprising: 4M control signal lines are sequentially arranged along the column direction, and the pixel circuits in the pixel units in the mth row are electrically connected to the control signal line in the 4m-3th row, the control signal line in the 4m-2th row, the control signal line in the 4m-1th row, and the control signal line in the 4mth row, respectively, 1≤m≤M; When the mth row of pixel units is displayed, the time when the 4m-3th row of control signal lines receives the valid level signal, the time when the 4m-2th row of control signal lines receives the valid level signal, the time when the 4m-1th row of control signal lines receives the valid level signal and the time when the 4mth row of control signal lines receives the valid level signal are within the time when the reset signal terminal in the pixel circuit in the pixel unit receives the valid level signal, and the time when the 4m-3th row of control signal lines receives the valid level signal, the time when the 4m-2th row of control signal lines receives the valid level signal, the time when the 4m-1th row of control signal lines receives the valid level signal and the time when the 4mth row of control signal lines receives the valid level signal do not overlap.

13. The display panel according to claim 12, wherein: The first control terminal of the pixel circuit in the odd-numbered column pixel unit of the mth row is electrically connected to the 4m-3th row control signal line, and the second control terminal of the pixel circuit in the odd-numbered column pixel unit of the mth row is electrically connected to the 4m-2th row control signal line; The first control terminal of the pixel circuit in the even-numbered column pixel unit of the mth row is electrically connected to the 4m-1th row control signal line, and the second control terminal of the pixel circuit in the even-numbered column pixel unit of the mth row is electrically connected to the 4mth row control signal line.

14. The display panel according to claim 9, further comprising: 2M control signal lines are sequentially arranged along the column direction, the first control end of the pixel circuit in the m-th row of pixel units is electrically connected to the 2m-1-th row of control signal lines, and the second control end of the pixel circuit in the m-th row of pixel units is electrically connected to the 2m-th row of control signal lines, 1≤m≤M; When the mth row of pixel units is displayed, the time when the 2m-1th row of control signal lines receives the valid level signal and the time when the 2mth row of control signal lines receives the valid level signal are within the time when the reset signal terminal in the pixel circuit in the pixel unit receives the valid level signal, and the time when the 2m-1th row of control signal lines receives the valid level signal and the time when the 2mth row of control signal lines receives the valid level signal do not overlap.

15. The display panel according to claim 9, further comprising: A multi-channel output selection circuit, K current data output lines arranged in sequence along the column direction, and K duration data output lines arranged in sequence along the column direction, K=N / 2; The multi-channel output selection circuit is electrically connected to N current data lines, N duration data lines, K current data output lines, K duration data output lines, a first current selection signal line, a second current selection signal line, a first duration selection signal line, and a second duration selection signal line, respectively, and is configured to output the data signals of the K current data output lines to the N current data lines in a time-sharing manner, and output the data signals of the K duration data output lines to the N duration data lines in a time-sharing manner, under the control of the first current selection signal line, the second current selection signal line, the first duration selection signal line, and the second duration selection signal line.

16. The display panel according to claim 15, wherein: The multi-channel output selection circuit includes: K first current selection transistors, K second current selection transistors, K first time length selection transistors, and K second time length selection transistors; The control electrode of the kth first current selection transistor is electrically connected to the first current selection signal line, the first electrode of the kth first current selection transistor is electrically connected to the 2k-1th column current data line, and the second electrode of the kth first current selection transistor is electrically connected to the kth column current data output line, 1≤k≤N / 2; The control electrode of the kth second current selection transistor is electrically connected to the second current selection signal line, the first electrode of the kth second current selection transistor is electrically connected to the 2kth column current data line, and the second electrode of the kth second current selection transistor is electrically connected to the kth column current data output line; The control electrode of the kth first duration selection transistor is electrically connected to the first duration selection signal line, the first electrode of the kth first duration selection transistor is electrically connected to the 2k-1th column duration data line, and the second electrode of the kth first duration selection transistor is electrically connected to the kth column duration data output line; The control electrode of the kth second duration selection transistor is electrically connected to the second duration selection signal line, the first electrode of the kth second duration selection transistor is electrically connected to the 2kth column duration data line, and the second electrode of the kth second duration selection transistor is electrically connected to the kth column duration data output line; The first current selection transistor, the second current selection transistor, the first time length selection transistor, and the second time length selection transistor are switch transistors.

17. A method for driving a pixel circuit, configured to drive the pixel circuit according to any one of claims 1 to 8, the method comprising: The node control subcircuit provides the signal of the initial signal terminal to the second node and the third node under the control of the reset signal terminal; The node control subcircuit provides the signal of the third node to the fourth node under the control of the scan signal terminal, the write subcircuit provides the signal of the current data terminal to the fifth node under the control of the scan signal terminal, and the drive subcircuit provides the drive current to the fourth node under the control of the third node and the fifth node; The light emitting control subcircuit provides the signal of the first power supply terminal to the fifth node and provides the signal of the fourth node to the second node under the control of the first node and the light emitting signal line; When the grayscale displayed by the light-emitting element connected to the pixel circuit is greater than the threshold grayscale, the method further comprises: the first control subcircuit provides a signal of the light-emitting signal terminal to the first node under the control of the current data terminal, the second control terminal and the ground terminal; When the grayscale displayed by the light-emitting element connected to the pixel circuit is less than the threshold grayscale, the method further includes: the second control subcircuit provides a signal of the high-frequency input terminal to the first node under the control of the duration data terminal, the first control terminal and the ground terminal.

18. A method for driving a display panel, configured to drive the display panel according to any one of claims 9 to 16, the method comprising: Signals are provided to N current data lines and along N time data lines, so that the time when two current data lines located between two adjacent columns of pixel units, and / or two time data lines located between two adjacent columns of pixel units, and / or the time data line and current data line located between two adjacent columns of pixel units receive effective level signals does not overlap.

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