Discrete equipment control system
Through the discrete equipment control system, multiple processors are used to process the control commands of nuclear power equipment, which solves the problems of low processing efficiency and poor system linkage capability in the existing technology, and realizes more efficient system linkage and fault tolerance.
Patent Information
- Application Number
- CN202211350561.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-31
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2042-10-31
AI Technical Summary
The existing nuclear power equipment control system has low processing efficiency and poor system linkage capability, and CPU failure will cause control system abnormalities.
A discrete device control system is adopted, in which three processors (first processor, second processor and third processor) are used to process different types of control commands respectively. A priority logic unit and a latch logic unit are set in the third processor to ensure the priority and interlocking of commands, thereby improving the processing efficiency and linkage capability of the system.
It improves the processing efficiency and linkage capability of the nuclear power equipment control system and prevents system anomalies caused by CPU failure.
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Figure CN115685834B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of nuclear power plant control, and in particular to a discrete equipment control system. Background Art
[0002] Currently, existing nuclear power equipment control systems are all based on the CPU (central processing unit) and use a serial method to process control commands issued by external devices. They are unable to achieve parallel processing of multiple control commands issued simultaneously. Once the CPU fails, it will cause the entire control system to become abnormal and unable to perform other operations. Therefore, the existing nuclear power equipment control system has the problems of low processing efficiency and poor system linkage capability. Summary of the Invention
[0003] The technical problem to be solved by the present disclosure is to provide a discrete equipment control system in order to overcome the defects of low processing efficiency and poor system linkage capability in the nuclear power equipment control system in the prior art.
[0004] The present disclosure solves the above technical problems through the following technical solutions:
[0005] A discrete device control system, the control system comprising:
[0006] The first processor is configured to receive a first data packet broadcast by the host computer, parse the first data packet to obtain a first type of control command, and send the first type of control command to the third processor;
[0007] a second processor, configured to receive a second data packet broadcast by the host computer, parse the second data packet to obtain a second type of control command, and send the second type of control command to the third processor;
[0008] The third processor is electrically connected to the first processor and the second processor respectively, and the third processor controls the nuclear power equipment to perform a first operation corresponding to the first type of control command and a second operation corresponding to the second type of control command respectively.
[0009] Preferably, the third processor is also used to send a first feedback signal and a second feedback signal to the first processor, so that the first processor determines the current state of the nuclear power equipment based on the first feedback signal and the second feedback signal; wherein the first feedback signal is a signal generated after the nuclear power equipment performs the first operation; and the second feedback signal is a signal generated after the nuclear power equipment performs the second operation.
[0010] Preferably, the third processor includes:
[0011] A priority logic unit is configured to execute the first type of control command and the second type of control command according to a preset priority when the third processor receives the first type of control command and the second type of control command at the same time.
[0012] Preferably, the third processor further includes:
[0013] The latch logic unit is used to set interlocking logic for the first type of control commands and the second type of control commands.
[0014] Preferably, the third processor further includes:
[0015] An output encoding unit is configured to encode the first feedback signal and the second feedback signal, and send the encoded first feedback signal and the encoded second feedback signal to the first processor.
[0016] Preferably, the first processor is further configured to, upon receiving multiple groups of first data packets, determine whether the multiple groups of first data packets are identical, and if so, parse the first data packets into the first type of control commands;
[0017] And / or, the first processor is further configured to feed back the abnormality to the host computer if the judgment result is negative.
[0018] Preferably, the second processor includes a main channel and a backup channel, the main channel is used to receive the second data packet, and when the main channel is damaged, the backup channel is automatically switched to receive the second data packet.
[0019] Preferably, the first processor further comprises: a first command processing unit, configured to pre-process the first type of control command and send the pre-processed first type of control command to the third processor; the pre-processing comprises filtering processing and / or verification processing; the verification processing verifies the identifier carried by the first type of control command;
[0020] And / or, the second processor also includes: a second command processing unit, used to preprocess the second type of control command and send the preprocessed second type of control command to the third processor; the preprocessing includes filtering processing and / or verification processing; the verification processing verifies the identifier carried by the second type of control command.
[0021] Preferably, the first processor includes:
[0022] A receiving test unit, configured to receive a third data packet broadcast by the host computer, parse a test command from the third data packet, and send the test command to the third processor;
[0023] a data monitoring unit, configured to monitor and display the first feedback signal, the second feedback signal, and the alarm information fed back by the third processor;
[0024] And / or, the third processor also includes: an output test unit, which is used to receive the test command and inject the test command through testing to verify whether the nuclear power equipment is abnormal. If so, locate the abnormality and send an alarm message to the data monitoring unit.
[0025] Preferably, the control system includes a serial port, and the serial port is used to receive the first data packet, the second data packet and the third data packet broadcast from the host computer.
[0026] The positive progressive effect of the present disclosure is that the present disclosure provides a discrete equipment control system for controlling nuclear power equipment, which distributes nuclear power equipment control commands among different processors for discrete processing, thereby improving the processing efficiency and linkage capability of the control system. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 This is a module schematic diagram of a discrete device control system according to Example 1 of the present disclosure;
[0028] Figure 2 This is another module schematic diagram of a discrete device control system according to Example 1 of the present disclosure. DETAILED DESCRIPTION
[0029] The present disclosure is further illustrated below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0030] Example 1
[0031] This embodiment provides a discrete device control system. Figure 1 A schematic diagram of a module of a discrete device control system provided in Example 1 of the present disclosure is shown as follows: Figure 1 As shown, the control system includes:
[0032] The first processor 1 is configured to receive a first data packet broadcasted by the host computer, parse the first data packet to obtain a first type of control command, and send the first type of control command to the third processor 3;
[0033] The second processor 2 is configured to receive a second data packet broadcasted by the host computer, parse the second data packet to obtain a second type of control command, and send the second type of control command to the third processor 3;
[0034] The third processor 3 is electrically connected to the first processor 1 and the second processor 2 respectively, and the third processor 3 controls the nuclear power equipment to execute a first operation corresponding to the first type of control command and a second operation corresponding to the second type of control command respectively.
[0035] In a specific implementation, the first processor 1 uses a FPGA (Field Programmable Gate Array) chip, and the second processor 2 and the third processor 3 use two CPLD (Complex Programmable Logic Device) chips respectively.
[0036] Among them, the three processors can be expanded to a solution using only FPGA chips or CPLD chips, or a combination of different numbers of FPGA chips and CPLD chips.
[0037] Among them, the host computer is the superior command system that controls the valve switches of nuclear power equipment, which mainly includes safety systems and non-safety systems.
[0038] In the specific implementation, the first processor 1 receives the first data packet sent from the security system to the control system via the serial port broadcast and parses it into the first type of control command, i.e., the security command; the second processor 2 receives the second data packet sent from the non-security system to the control system via the serial port broadcast and parses it into the second type of control command, i.e., the non-security command.
[0039] In an optional embodiment, the third processor 3 is also used to send the first feedback signal and the second feedback signal to the first processor 1, so that the first processor 1 determines the current state of the nuclear power equipment based on the first feedback signal and the second feedback signal; wherein the first feedback signal is a signal generated after the nuclear power equipment performs the first operation; the second feedback signal is a signal generated after the nuclear power equipment performs the second operation.
[0040] In specific implementation, the three processors can interact with each other based on the same communication protocol. The first processor 1 sends the parsed safety command to the third processor 3, and the second processor 2 sends the parsed non-safety command to the third processor 3. The third processor 3 is used to execute the operation instructions for controlling the nuclear power equipment corresponding to the safety commands and non-safety commands, and feed back the signals and status corresponding to the nuclear power equipment executing the first operation and the second operation to the first processor 1.
[0041] In an optional embodiment, if Figure 2 As shown, the third processor 3 includes:
[0042] The priority logic unit 31 is configured to execute the first and second type of control commands according to a preset priority when the third processor 3 receives the first and second type of control commands simultaneously.
[0043] In specific implementation, when the third processor 3 receives a safety command and a non-safety command at the same time, it executes the safety command first and then the non-safety command according to the security authority level to prevent abnormal equipment operation caused by command conflict in the control system.
[0044] In specific implementation, the control commands for controlling nuclear power equipment also include local commands directly controlled on site and Z commands injected through hard wiring. When the commands arrive at the same time, the priority logic unit 31 takes effect and prioritizes them according to the order of local commands, safety commands, non-safety commands and Z commands. When the commands are issued at the same time, the higher-level commands are used as output commands.
[0045] In an optional implementation, the third processor 3 further includes:
[0046] The latch logic unit 32 is used to set interlocking logic for the first type of control commands and the second type of control commands.
[0047] In specific implementation, when the control system receives multiple device control commands at the same time, if the priority logic unit 31 has an abnormality that causes the nuclear power equipment to have an abnormal operating condition, the control system will automatically adjust the interlocking of the nuclear power equipment. For example, the process of turning the equipment on and off is not an instantaneous process, and it takes a certain amount of time. Therefore, the nuclear power equipment is set to three states: on, off, and stopped. For on, it means that the nuclear power equipment gradually turns on, turns on completely, and then remains in a fully on state; for off, it means that the nuclear power equipment gradually turns off, turns off completely, and then remains in a fully off state; for stop, it means that the nuclear power equipment is in an intermediate state between the on or off state, and the nuclear power equipment is kept at the current opening and no other operations are performed. Therefore, in order to prevent the control commands from simultaneously issuing the two mutually exclusive commands of on and off, an interlocking logic design is adopted. Specifically, when the third processor 3 detects that both on and off are valid, the nuclear power equipment is controlled to remain in a stopped state.
[0048] In an optional implementation, the third processor 3 further includes:
[0049] The output encoding unit 33 is configured to encode the first feedback signal and the second feedback signal, and send the encoded first feedback signal and the encoded second feedback signal to the first processor 1 .
[0050] During specific implementation, after the nuclear power equipment executes the operation corresponding to the control command, the third processor 3 receives the corresponding feedback signal and sends it to the first processor 1. In order to prevent data from being stolen, the third processor 3 will encode the feedback signal and then send the encoded feedback signal to the first processor 1. After receiving it, the first processor 1 uses a decoder to decode the encoded feedback signal, effectively improving the security of the system.
[0051] In an optional embodiment, the first processor 1 is further configured to, when receiving multiple groups of first data packets, determine whether the multiple groups of first data packets are the same, and parse the first data packets into first-type control commands if the determination is yes.
[0052] And / or, the first processor is further configured to, if the determination is negative, feed back the abnormality to the host computer.
[0053] In specific implementations, for security commands issued by the security system, two sets of identical signals exist under normal security command conditions, and two sets of identical commands are output simultaneously under normal device operating conditions. Therefore, when the first processor 1 receives the first data packet issued by the upper-level security system, it determines whether the two sets of commands contained in the first data packet are identical. If so, it parses them into security commands and sends the parsed security commands to the third processor 3. If not, it determines that the first data packet is abnormal and feeds back the abnormality to the upper-level security system.
[0054] In an optional embodiment, the second processor 2 includes a main channel and a backup channel. The main channel is used to receive the second data packet. When the main channel is damaged, the backup channel is automatically switched to receive the second data packet.
[0055] The second processor 2 mainly executes non-safety commands issued by the non-safety system.
[0056] In an optional embodiment, the first processor 1 also includes: a first command processing unit 11, which is used to preprocess the first type of control command and send the preprocessed first type of control command to the third processor 3; the preprocessing includes filtering processing and / or verification processing; the verification processing verifies the identifier carried by the first type of control command.
[0057] In an optional embodiment, the second processor 2 also includes: a second command processing unit, which is used to preprocess the second type of control command and send the preprocessed second type of control command to the third processor 3; the preprocessing includes filtering processing and / or verification processing; the verification processing verifies the identifier carried by the second type of control command.
[0058] During implementation, safety commands and non-safety commands are sent to the control system via serial communication. The underlying serial data communication protocol is used, and filtering is performed on the serial data communication protocol to prevent erroneous data from being collected due to poor signal quality, accompanied by data jitter and signal overshoot. Furthermore, to prevent the non-safety system from being mistakenly connected to the first processor 1 due to wiring errors, different synchronization words are used for synchronization of safety commands and non-safety commands. This ensures that the first processor 1 is not mistakenly connected to the non-safety system, which could cause control system anomalies.
[0059] In an optional embodiment, the first processor 1 includes:
[0060] A receiving test unit 12 is configured to receive a third data packet broadcast by the host computer, parse a test command from the third data packet, and send the test command to the third processor 3;
[0061] The data monitoring unit 13 is used to monitor and display the first feedback signal, the second feedback signal and the alarm information fed back by the third processor 3;
[0062] The third processor 3 further includes: an output test unit 34 for receiving a test command and injecting the test command into the test to verify whether the nuclear power equipment is abnormal. If so, the abnormality is located and an alarm message is sent to the data monitoring unit 13 .
[0063] In specific implementation, the first processor 1 is also used to test and monitor the status of nuclear power equipment. The upper computer sends a third data packet to the control system. The first processor 1 parses the test command from the third data packet and sends the test command to the third processor 3. The output test unit 34 of the third processor 3 receives the test command and verifies whether the command output of the control system and the status of the nuclear power equipment are normal through test injection. If an abnormality occurs, the abnormality is located and the alarm information is sent to the data monitoring unit 13.
[0064] The data monitoring unit 13 is used to display alarm information and signals fed back by nuclear power equipment, ensuring a consistent status display of the entire control system. In the event that a test command and a safety command are issued simultaneously, the first processor 1 prioritizes responding to the safety command until the safety command disappears, and then continues executing the test command.
[0065] In an optional embodiment, the control system includes a serial port, and the serial port is used to receive the first data packet, the second data packet, and the third data packet broadcasted from the host computer.
[0066] The discrete equipment control system provided in this embodiment improves the processing efficiency and linkage capability of the control system by distributing nuclear power equipment control commands among different processors for discrete processing.
[0067] While specific embodiments of the present disclosure have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of protection of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, and such changes and modifications are intended to fall within the scope of protection of the present disclosure.
Claims
1. A discrete device control system, characterized in that: The control system includes: The first processor is configured to receive a first data packet broadcast by the host computer, parse the first data packet to obtain a first type of control command, and send the first type of control command to the third processor; a second processor, configured to receive a second data packet broadcast by the host computer, parse the second data packet to obtain a second type of control command, and send the second type of control command to the third processor; The third processor is electrically connected to the first processor and the second processor, respectively, and the third processor controls the nuclear power equipment to perform a first operation corresponding to the first type of control command and a second operation corresponding to the second type of control command; the third processor is further configured to send a first feedback signal and a second feedback signal to the first processor, so that the first processor determines the current state of the nuclear power equipment based on the first feedback signal and the second feedback signal; wherein the first feedback signal is a signal generated after the nuclear power equipment performs the first operation; and the second feedback signal is a signal generated after the nuclear power equipment performs the second operation; The first processor includes: A receiving test unit, configured to receive a third data packet broadcast by the host computer, parse a test command from the third data packet, and send the test command to the third processor; a data monitoring unit, configured to monitor and display the first feedback signal, the second feedback signal, and the alarm information fed back by the third processor; The third processor includes: an output test unit, which is used to receive the test command and inject the test command through testing to verify whether the nuclear power equipment is abnormal. If so, it locates the abnormality and sends an alarm message to the data monitoring unit.
2. The discrete device control system according to claim 1, characterized in that: The third processor includes: A priority logic unit is configured to execute the first type of control command and the second type of control command according to a preset priority when the third processor receives the first type of control command and the second type of control command at the same time.
3. The discrete device control system according to any one of claims 1 or 2, characterized in that: The third processor further includes: The latch logic unit is used to set interlocking logic for the first type of control commands and the second type of control commands.
4. The discrete device control system according to claim 1, wherein: The third processor further includes: An output encoding unit is configured to encode the first feedback signal and the second feedback signal, and send the encoded first feedback signal and the encoded second feedback signal to the first processor.
5. The discrete device control system according to claim 1, wherein: The first processor is further configured to, upon receiving multiple groups of first data packets, determine whether the multiple groups of first data packets are identical, and if so, parse the first data packets into the first type of control commands; And / or, the first processor is further configured to feed back the abnormality to the host computer if the judgment result is negative.
6. The discrete device control system according to claim 1, characterized in that: The second processor includes a main channel and a backup channel. The main channel is used to receive the second data packet. When the main channel is damaged, the backup channel is automatically switched to receive the second data packet.
7. The discrete device control system according to claim 1, wherein: The first processor further includes: a first command processing unit, configured to pre-process the first type of control command and send the pre-processed first type of control command to the third processor; the pre-processing includes filtering processing and / or verification processing; the verification processing verifies the identifier carried by the first type of control command; And / or, the second processor includes: a second command processing unit, used to preprocess the second type of control command and send the preprocessed second type of control command to the third processor; the preprocessing includes filtering processing and / or verification processing; the verification processing verifies the identifier carried by the second type of control command.
8. The discrete device control system according to claim 1, wherein: The control system includes a serial port, and the serial port is used to receive the first data packet, the second data packet and the third data packet broadcasted from the host computer.
Citation Information
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