Virtualized in-chip execution method, apparatus, system, device and storage medium
By sharing storage space between virtual read-only memory and virtual flash memory, the target instructions can be directly obtained, solving the problem of slow execution speed of virtualization chip in virtual machine system and achieving more efficient instruction fetching and execution speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2022-10-13
- Publication Date
- 2026-06-19
AI Technical Summary
In existing virtual machine systems, the speed of executing functions within the virtualization chip is relatively slow. In particular, when using the QEMU virtual machine system, the slow instruction fetching speed of the CPU leads to a significant decrease in the speed of the virtual machine system when executing XIP functions.
By adopting a shared storage space approach between virtual read-only memory and virtual flash memory, the target instruction can be directly obtained through virtual read-only memory, avoiding serial-to-parallel conversion through the virtual serial peripheral interface controller, thereby improving the instruction fetching speed.
It significantly improves the execution efficiency of virtualization chip-based execution functions in virtual machine systems, increases instruction fetching speed, and improves the overall execution performance of virtual machine systems.
Smart Images
Figure CN115686743B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, the field of virtual machine technology, and in particular to a virtualization in-chip execution method, apparatus, electronic device and storage medium, as well as a virtual machine system. Background Technology
[0002] With the continuous development of computer technology, virtual machine systems have emerged to fully meet the needs of various software and hardware adaptations. A virtual machine system simulates a complete computer system with full hardware system functionality, running in an isolated environment. To keep pace with the continuous development of computer hardware and system technologies, virtual machine solutions also need to evolve to achieve virtual functions consistent with real computer hardware and software systems.
[0003] With the maturity of virtual machine technology, more and more virtual machine systems are being formally applied to actual production and life. Therefore, improving the execution efficiency of various virtual hardware functions of virtual machines is the direction for continuous improvement of virtual machine technology. Summary of the Invention
[0004] This disclosure provides a virtualized in-chip execution method, apparatus, electronic device, and storage medium, as well as a virtual machine system. Based on a virtual read-only memory (ROM) created by sharing storage space with a virtual flash memory (FLASH), the system utilizes the virtual ROM to read target instructions to realize the in-chip execution function of the virtual FLASH, significantly improving the execution efficiency of the virtualized in-chip execution function in the virtual machine system.
[0005] This disclosure provides a virtualized in-chip execution method, including:
[0006] Based on the virtual processor's first access request, the target instruction is retrieved from the virtual read-only memory of the virtual machine system and executed;
[0007] According to the second access request of the virtual processor, the target data is obtained from the virtual flash memory through the virtual serial peripheral interface controller of the virtual machine system;
[0008] The virtual read-only memory and the virtual flash memory share all or part of the storage space of the virtual flash memory, and the target instruction is stored in all or part of the storage space.
[0009] The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
[0010] This disclosure also provides a virtualized in-chip execution device, including:
[0011] The first execution module is configured to retrieve and execute the target instruction from the virtual read-only memory of the virtual machine system according to the first access request of the virtual processor.
[0012] The second execution module is configured to obtain target data from the virtual flash memory through the virtual serial peripheral interface controller of the virtual machine system according to the second access request of the virtual processor.
[0013] The virtual read-only memory and the virtual flash memory share all or part of the storage space of the virtual flash memory, and the target instruction is stored in all or part of the storage space.
[0014] The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
[0015] This disclosure also provides a virtual machine system, including:
[0016] Virtual processor, virtual read-only memory, virtual flash memory, virtual bus controller, and virtual serial peripheral interface controller;
[0017] The virtual bus controller is configured to forward a first access request sent by the virtual processor to the virtual read-only memory; and to forward a second access request sent by the virtual processor to the virtual serial peripheral interface controller.
[0018] The virtual read-only memory is configured to return a target instruction based on the first access request;
[0019] The virtual serial peripheral interface controller is configured to access the virtual flash memory to obtain target data according to the second access request and return it.
[0020] The virtual processor is configured to receive and execute the target instruction; and to receive the target data.
[0021] The virtual read-only memory and the virtual flash memory share all or part of the storage space of the virtual flash memory, and the target instruction is stored in all or part of the storage space.
[0022] The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
[0023] This disclosure also provides an electronic device, including:
[0024] One or more processors;
[0025] Storage device for storing one or more programs.
[0026] When the one or more programs are executed by the one or more processors, the one or more processors implement the virtualized in-chip execution method as described in any embodiment of this disclosure.
[0027] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the virtualization in-chip execution method as described in any embodiment of this disclosure.
[0028] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0030] Figure 1 This is a flowchart of a virtualized in-chip execution method provided in an embodiment of the present invention;
[0031] Figure 2 This is a flowchart of another virtualization in-chip execution method provided in an embodiment of the present invention;
[0032] Figure 3 This is a schematic diagram of the structure of a virtual machine system provided in an embodiment of the present invention;
[0033] Figure 4 This is a schematic diagram of another virtual machine system provided in an embodiment of the present invention.
[0034] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0036] It should be noted that in this invention, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0037] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0038] Execute-In-Place (XIP), also known as on-chip execution, is a mechanism that allows code to be executed directly in flash memory (FLASH) without being loaded into random access memory (RAM). In other words, the CPU's instruction fetch module can directly retrieve instructions from FLASH for use by subsequent decoding and execution modules. In relevant computer systems, considering implementation complexity and flexibility, XIP functionality is typically implemented by a Serial Peripheral Interface (SPI) controller to convert the serial FLASH bus to a parallel bus within the computer system.
[0039] SPI is a high-speed, full-duplex, synchronous serial communication bus that operates in a master-slave mode and contains at least four signal lines: SCLK, MOSI, MISO, and CS. SCLK is the clock signal line, enabling synchronous data transmission; CS is the chip select signal, indicating that SPI supports one-to-many connections; MOSI and MISO are two data lines, implementing simplex data transmission from master to slave and from slave to master, respectively. However, because MOSI and MISO allow simultaneous data transmission, SPI supports full-duplex communication. To accelerate data transmission speed, SPI's MOSI and MISO can be extended to enable bidirectional half-duplex master-slave communication, transmitting two bits of data simultaneously, thus doubling the data transmission speed. This extension is called Dual-SPI, or DSPI for short. The original version is called Standard SPI, also known as Single-Wire SPI, or SSPI for short. Further extending the data lines to four doubles the data transmission speed again compared to Dual-SPI; this extension is called Quad-SPI, or QSPI for short.
[0040] Among the relevant feasible solutions, the XIP function (mode) is implemented using QSPI connection or non-flash memory (Nor FLASH), which allows the CPU to access data in FLASH in the same way as memory access. When the QSPI controller supports the XIP function (mode), it converts the data access request received from the CPU into an SPI Nor FLASH command sequence, and then sends the required data to the CPU after receiving it from the FLASH.
[0041] Consistent with this, each virtual machine system also simulated XIP's behavior in software, exactly as XIP would. Taking the QEMU virtual machine system as an example, when simulating QSPI XIP, it needs to convert each CPU access request into a sequence of SPI Nor FLASH commands to interact with the Nor FLASH virtual device. This results in the instruction fetching speed of each CPU instruction being many times slower than fetching instructions from virtual RAM, causing a significant speed drop when the virtual machine system executes XIP functions.
[0042] With the widespread use of XIP functionality, whether using virtual machine systems for various simulation tests or as a formal business / application runtime environment, it is essential to improve the implementation of XIP functionality in virtual machine systems to enhance on-chip execution speed.
[0043] Unless otherwise specified, the hardware modules or sub-devices included in the virtual machine system described in the embodiments of this disclosure are all virtual hardware modules or virtual sub-devices, such as virtual CPU, virtual FLASH, virtual system bus, etc. The specific virtual scheme of each hardware module or sub-device can be implemented according to the corresponding functions or configurations provided by the corresponding virtual machine software, and is not limited to specific virtual machine software or specific implementation methods, nor will it be discussed in detail in this application.
[0044] This disclosure provides a virtualized in-chip execution method, such as... Figure 1 As shown, it includes:
[0045] Step 110: Based on the first access request of the virtual processor, retrieve the target instruction from the virtual read-only memory (ROM) of the virtual machine system and execute it;
[0046] Step 120: Based on the second access request of the virtual processor, obtain the target data from the virtual flash memory (FLASH) through the virtual serial peripheral interface controller of the virtual machine system;
[0047] The virtual read-only memory shares all or part of the storage space of the virtual FLASH with the virtual FLASH, and the target instruction is stored in all or part of the storage space.
[0048] The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
[0049] It should be noted that steps 110 and 120 above are not limited to a specific execution order; in some exemplary embodiments, they can be executed in the order of the first / second access requests.
[0050] In some exemplary embodiments, such as Figure 2 As shown, the method further includes:
[0051] Step 100: Determine whether the access request from the virtual processor is a first access request or a second access request based on the stored first address range and / or second address range.
[0052] For example, if a first address range has been stored, then an access request whose address falls within the first address range is a first access request, and others are second access requests; or, if a second address range has been stored, then an access request whose address falls within the second address range is a second access request, and others are first access requests; or, if a first address range and a second address range have been stored, then an access request whose address falls within the first address range is a first access request, and an access request whose address falls within the second address range is a second access request.
[0053] It should be noted that in this embodiment, the first access request and the second access request are address access requests from the CPU to retrieve target data from the target memory, and are also referred to as: the first address access request and the second address access request; the target memory returns the corresponding data according to the access address in the first access request or the second access request. The target data includes: instruction data or non-instruction data, and the instruction data is referred to as the target instruction.
[0054] As can be seen, compared to the XIP scheme in some feasible virtual machine systems that uses an SPI controller to perform serial-to-parallel conversion to obtain instructions that can be executed on the chip from the virtual FLASH and then further execute the instructions, the XIP scheme provided in this disclosure adopts a virtual ROM scheme, which allows the CPU to directly obtain the target instructions through the virtual ROM without having to use a virtual SPI controller to perform serial-to-parallel conversion to obtain the target instructions from the FLASH. This can significantly improve the instruction fetching speed when the virtual machine implements the XIP function and improve the overall on-chip execution speed.
[0055] In some exemplary embodiments, the virtual ROM and the virtual FLASH share all the storage space in the virtual FLASH; or, the virtual ROM and the virtual FLASH share a portion of the storage space in the virtual FLASH. These shared storage spaces store target instructions that can be further executed by the CPU.
[0056] In some exemplary embodiments, the virtual ROM and the virtual FLASH share a portion of the storage space in the virtual FLASH. This shared storage space stores the target instruction corresponding to the first access request that can be further executed by the CPU; the unshared storage space in the virtual FLASH stores the target data corresponding to the second access request.
[0057] In some exemplary embodiments, the virtual ROM and the virtual FLASH share all or part of the storage space in the virtual FLASH to store target data, which includes instruction data or non-instruction data;
[0058] Accordingly, step 110 includes: obtaining target data from the virtual read-only memory according to the first access request of the virtual processor;
[0059] If the target data includes instruction data, the instruction is executed.
[0060] It is understood that by adopting the solution provided in the embodiments of this disclosure, instruction or non-instruction data can be obtained through a virtual ROM.
[0061] As can be seen from step 120, the in-chip execution scheme proposed in this embodiment of the present disclosure also retains other data storage functions of the virtual FLASH, and supports the function of obtaining target data through the virtual SPI controller in related schemes.
[0062] In some exemplary embodiments, step 110 includes:
[0063] The virtual bus controller of the virtual machine system forwards the first access request from the virtual processor to the virtual read-only memory to obtain the target instruction and return it to the virtual processor.
[0064] The virtual processor receives and executes the target instruction.
[0065] In some exemplary embodiments, step 120 includes:
[0066] The virtual bus controller of the virtual machine system forwards the second access request from the virtual processor to the virtual serial peripheral interface controller to obtain the target data.
[0067] The target data includes either instruction data or non-instruction data.
[0068] As can be seen, depending on the range of the access address, the address access request is routed to the virtual SPI controller or the virtual ROM. Among them, the executable target instructions related to the XIP function are obtained from the shared virtual FLASH storage space through the virtual ROM. At this time, when the virtual machine system executes the XIP function, it uses the virtual ROM to fetch instructions, which significantly improves the instruction fetching speed. At the same time, the data read and write methods of the SPI controller corresponding to other data storage functions of the virtual FLASH are retained.
[0069] It should also be noted that the virtual read-only memory (ROM) in this embodiment is characterized by the ability to retain information for a long time after it is written into the memory, and the information will not be lost due to power failure. During the operation of the computer system, information can only be read from the read-only memory and cannot be written to it at will. It is a memory relative to (virtual) RAM, and is not a traditional read-only memory that cannot be written to. Under certain circumstances, it can be rewritten.
[0070] The virtual ROM in this embodiment is a ROM functional module simulated by software based on the read and write function constraints of the actual ROM, achieving the same application effect as the actual ROM for the processor.
[0071] It is understood that the virtualization in-chip execution scheme proposed in this disclosure can be applied to a variety of virtual machine systems. The specific details of the scheme are implemented by using the ROM virtualization function, access address routing function, virtual ROM and virtual FLASH shared storage space function provided by each virtual machine system, and are not limited to a specific virtual machine software or virtual machine system.
[0072] The virtual ROM is created according to the virtual ROM creation function provided by each virtual machine system, and the virtual FLASH is created according to the virtual FLASH creation function provided by each virtual machine system. The virtual ROM shares all or part of the storage space of the virtual FLASH, which is also realized according to the relevant creation parameters or configuration parameters. The specific creation and configuration details of different virtual machine systems are different, and will not be listed here.
[0073] This disclosure also provides a virtualized in-chip execution device, including:
[0074] The first execution module is configured to retrieve and execute the target instruction from the virtual read-only memory of the virtual machine system according to the first access request of the virtual processor.
[0075] The second execution module is configured to obtain target data from the virtual flash memory through the virtual serial peripheral interface controller of the virtual machine system according to the second access request of the virtual processor.
[0076] The virtual read-only memory shares all or part of the storage space of the virtual FLASH with the virtual FLASH, and the target instruction is stored in all or part of the storage space.
[0077] The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
[0078] In some exemplary embodiments, the virtual FLASH includes: a virtual NOR gate flash memory (Nor FLASH) or a virtual NAND gate flash memory (Nand FLASH).
[0079] The virtual Nor FLASH can be implemented based on an actual Nor FLASH, or on Double Data Rate Synchronous Dynamic Random Access Memory (DDR); or on other memory types, without limitation. Similarly, the virtual Nand FLASH also employs a corresponding virtual scheme, implemented based on the actual memory device. It can be understood that since the virtual ROM shares all or part of the storage space of the virtual FLASH, it means that the actual memory corresponding to the virtual ROM is the same as the actual memory corresponding to the virtual FLASH.
[0080] In some exemplary embodiments, the virtual serial peripheral interface controller includes: a virtual four-wire serial peripheral interface (QSPI) controller, a virtual two-wire serial peripheral interface (DSPI) controller, or a virtual single-wire serial peripheral interface (SSPI) controller.
[0081] In some exemplary embodiments, the virtual machine system includes: QEMU virtual machine, VMware virtual machine, VirtualBox virtual machine, Parallels virtual machine or Hyper-V virtual machine; or other virtual machine systems.
[0082] This disclosure also provides a virtual machine system, such as Figure 3 As shown, it includes:
[0083] Virtual processor 310, virtual read-only memory 320, virtual flash memory 330, virtual bus controller 340 and virtual serial peripheral interface controller 350;
[0084] The virtual bus controller 340 is configured to forward the first access request sent by the virtual processor 310 to the virtual read-only memory 320; and to forward the second access request sent by the virtual processor 310 to the virtual serial peripheral interface controller 350.
[0085] The virtual read-only memory 320 is configured to return a target instruction based on the first access request.
[0086] The virtual serial peripheral interface controller 350 is configured to access the virtual flash memory 330 to obtain target data according to the second access request and return it.
[0087] The virtual processor 310 is configured to receive and execute the target instruction.
[0088] The virtual read-only memory 320 and the virtual flash memory 330 share all or part of the storage space 3301 of the virtual flash memory, and the target instruction is stored in all or part of the storage space.
[0089] The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
[0090] In some exemplary embodiments, the virtual bus controller 340 is configured to forward the first access request to the virtual read-only memory 320 according to the access address corresponding to the first access request;
[0091] And / or,
[0092] Based on the access address corresponding to the second access request, the second access request is forwarded to the virtual serial peripheral interface controller 350.
[0093] In some exemplary embodiments, the first address range is the address range used by the XIP function in the computer system.
[0094] For example, the first address range is 0xFC00_0000 to 0xFCFF_FFFF, and the second address range is 0x4000_0000 to 0x4000_1000.
[0095] In some exemplary embodiments, the virtual serial peripheral interface controller 350 is further configured to receive the second access request and convert the second access request into an SPI FLASH command sequence;
[0096] The virtual serial peripheral interface controller 350 is further configured to interact with the virtual FLASH 330 using the SPI FLASH command sequence to obtain the target data and send the target data to the virtual processor 310.
[0097] In some exemplary embodiments, the virtual serial peripheral interface controller includes: a virtual four-wire serial peripheral interface (QSPI) controller, a virtual two-wire serial peripheral interface (DSPI) controller, or a virtual single-wire serial peripheral interface (SSPI) controller.
[0098] Taking the QEMU virtual machine system as an example, this disclosure also provides a virtual machine system, such as... Figure 4 As shown, including
[0099] Virtual processor 410, virtual read-only memory ROM 420, virtual Nor FLASH 430, virtual bus controller 440, virtual bus 441 and virtual QSPI controller 450;
[0100] The virtual bus controller 440 is configured to forward the first access request sent by the virtual processor 410 to the virtual read-only memory 420.
[0101] The virtual bus controller 440 is further configured to forward the second access request sent by the virtual processor 410 to the virtual QSPI controller 450;
[0102] The virtual read-only memory 420 is configured to return a target instruction based on the first access request.
[0103] The virtual processor 410 is configured to receive and execute the target instruction returned by the virtual ROM; it is also configured to receive the target data returned by the QSPI controller 450.
[0104] The virtual QSPI controller 450 is configured to receive the second access request and convert the second access request into an SPI Nor FLASH command sequence;
[0105] The virtual QSPI controller 450 is further configured to send the SPI Nor FLASH command sequence to the virtual Nor FLASH 430;
[0106] The virtual QSPI controller 450 is further configured to receive response data from the virtual Nor FLASH 430, convert it into the target data, and send it to the virtual processor 410;
[0107] The virtual read-only memory 420 and the virtual Nor FLASH 430 share a portion of the storage space 4301 of the virtual Nor FLASH, where the target instruction is stored; the target data is stored in the other storage spaces of the virtual Nor FLASH 430 besides the portion of storage space 4301.
[0108] The first address range corresponding to the first access request is 0xFC00_0000~0xFCFF_FFFF, and the second address range corresponding to the second access request is 0x4000_0000~0x4000_1000.
[0109] In some exemplary embodiments, the virtual bus controller 440 includes: a memory address mapping table (MemoryMap) 4401;
[0110] The storage address mapping table records the correspondence between address ranges and target devices.
[0111] For example:
[0112] Serial Number Address range Target equipment 1 0xFC00_0000~0xFCFF_FFFF Virtual ROM 2 0x4000_0000~0x4000_1000 Virtual QSPI Controller
[0113] Those skilled in the art can also use other forms to record mapping relationship data, and the virtual bus controller 440 forwards access requests according to the storage address mapping table, not limited to the aspects described in the embodiments of this disclosure.
[0114] It is understandable that during the operation of the QEMU virtual machine, the virtual processor 410 sends an access request to the virtual bus 441, and the virtual bus controller 440 forwards the access instruction according to the configured memory address mapping table.
[0115] Among them, access instructions with access addresses in the range of 0x4000_0000 to 0x4000_1000 are forwarded to the virtual QSPI controller 450, which converts them into SPI Nor FLASH sequences and sends them to the virtual FLASH. After obtaining the response data, it is converted into target data (or target instructions) and returned to the virtual processor 410.
[0116] Access instructions with addresses in the range of 0xFC00_0000 to 0xFCFF_FFFF are forwarded to the virtual ROM 420, which then returns the target data (or target instruction) to the virtual processor 410 based on the virtual ROM data fetching function.
[0117] As can be seen, the virtual ROM420 and the virtual FLASH share data related to the XIP function. When executing the XIP function, there is no need to obtain data from the FLASH through serial-to-parallel conversion via the QSPI controller. Instead, the data is obtained using the virtual ROM, which significantly accelerates the execution speed of the XIP function in the QEMU virtual machine system.
[0118] This disclosure also provides an electronic device, including:
[0119] One or more processors;
[0120] Storage device for storing one or more programs.
[0121] When the one or more programs are executed by the one or more processors, the one or more processors implement the virtualized in-chip execution method as described in any embodiment of this disclosure.
[0122] In some exemplary embodiments, the electronic device includes: a mobile terminal, a personal computer, or a server, etc.
[0123] This disclosure also includes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the virtualization in-chip execution method as described in any embodiment of this disclosure.
[0124] The virtualization in-chip execution scheme provided in this disclosure changes the conventional mechanism of the XIP execution scheme in the virtual machine system. It distributes access requests according to the access addresses involved in the in-chip execution function and adopts a virtual ROM scheme that shares storage with FLASH to obtain the target data required by the in-chip execution function. This overcomes the shortcomings of related feasible schemes that use the SPI controller to obtain the required target data, significantly improves the instruction fetching speed of the in-chip execution function in the virtual machine system, and improves the performance of the virtual machine.
[0125] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0126] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A virtualized in-chip execution method, characterized in that, include: Based on the virtual processor's first access request, the target instruction is retrieved from the virtual read-only memory of the virtual machine system and executed; According to the second access request of the virtual processor, the target data is obtained from the virtual flash memory through the virtual serial peripheral interface controller of the virtual machine system; The virtual read-only memory and the virtual flash memory share all or part of the storage space of the virtual flash memory, and the target instruction is stored in all or part of the storage space. The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
2. The virtualization in-chip execution method as described in claim 1, characterized in that, The method further includes: Based on the stored first address range and / or second address range, determine whether the access request from the virtual processor is a first access request or a second access request.
3. The virtualization in-chip execution method as described in claim 1 or 2, characterized in that, The step of retrieving and executing the target instruction from the virtual read-only memory of the virtual machine system according to the first access request of the virtual processor includes: The virtual bus controller of the virtual machine system forwards the first access request from the virtual processor to the virtual read-only memory to obtain the target instruction and return it to the virtual processor. The virtual processor receives and executes the target instruction.
4. A virtualized in-chip execution device, characterized in that, include: The first execution module is configured to retrieve and execute the target instruction from the virtual read-only memory of the virtual machine system according to the first access request of the virtual processor. The second execution module is configured to obtain target data from the virtual flash memory through the virtual serial peripheral interface controller of the virtual machine system according to the second access request of the virtual processor. The virtual read-only memory and the virtual flash memory share all or part of the storage space of the virtual flash memory, and the target instruction is stored in all or part of the storage space. The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
5. The virtualized in-chip execution device as described in claim 4, characterized in that, The virtual flash memory includes: a virtual NOR gate flash memory or a virtual NAND gate flash memory.
6. The virtualized in-chip execution device as described in claim 4, characterized in that, The virtual serial peripheral interface controller includes: a virtual four-wire serial peripheral interface controller, a virtual two-wire serial peripheral interface controller, or a virtual single-wire serial peripheral interface controller.
7. The virtualized on-chip execution device according to any one of claims 4-6, characterized in that, The virtual machine system includes: QEMU virtual machine, VMware virtual machine, VirtualBox virtual machine, Parallels virtual machine, or Hyper-V virtual machine.
8. A virtual machine system, characterized in that, include: Virtual processor, virtual read-only memory, virtual flash memory, virtual bus controller, and virtual serial peripheral interface controller; The virtual bus controller is configured to forward the first access request sent by the virtual processor to the virtual read-only memory; The second access request sent by the virtual processor is forwarded to the virtual serial peripheral interface controller. The virtual read-only memory is configured to return a target instruction based on the first access request; The virtual serial peripheral interface controller is configured to access the virtual flash memory to obtain target data according to the second access request and return it. The virtual processor is configured to receive and execute the target instruction. The virtual read-only memory and the virtual flash memory share all or part of the storage space of the virtual flash memory, and the target instruction is stored in all or part of the storage space. The access address corresponding to the first access request is within a first address range, and the access address corresponding to the second access request is within a second address range; the addresses included in the first address range are different from the addresses included in the second address range.
9. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the virtualization in-chip execution method as described in any one of claims 1-3.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the virtualized in-chip execution method as described in any one of claims 1-3.