Reconfigurable logic gate based on synthetic antiferromagnetic coupled skyrmions and control method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN CITY UNIV
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-19
Smart Images
Figure CN122247408A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of field programmable gate array (FPGA), quantum computing, reversible computing and spintronic devices, and in particular to a reconfigurable logic gate based on synthetic antiferromagnetically coupled skyrmions and its control method. Background Technology
[0002] As integrated circuit feature sizes approach physical limits, the "memory wall" and "power wall" problems caused by the separation of processor and memory in the traditional von Neumann architecture are becoming increasingly severe. Developing "in-memory computing" devices that combine non-volatile memory and logic computing capabilities is a key path to overcome these bottlenecks and achieve next-generation high-energy-efficiency computing. Among these, reconfigurable logic gates can dynamically implement multiple logic functions on the same hardware, greatly improving hardware flexibility and resource utilization, and are the core unit for building adaptive computing systems.
[0003] Magnetic skyrmions, as topology-protected nanomagnetic domain structures, possess advantages such as non-volatility, low drive current, and high stability, and are widely considered ideal information carriers for realizing nanoscale "logic memory." Numerous theoretical proposals exist for reconfigurable logic gates based on ferromagnetic skyrmions. However, ferromagnetic skyrmions are significantly affected by the skyrmion Hall effect (SKHE) under current driving, resulting in lateral drift perpendicular to the driving direction. This drift easily causes skyrmions to deviate from their predetermined nanotracks, annihilating upon collision with boundaries or producing erroneous logic outputs, severely limiting device reliability. Furthermore, many existing schemes rely on "generating" and "annihilating" skyrmions before and after each computation cycle. These operations typically require high current or magnetic field thresholds, increasing not only energy consumption and timing complexity but also disrupting information continuity, making it difficult to achieve truly reversible computation and efficient cascading.
[0004] It is evident that suppressing the skyrmion Hall effect, improving device reliability, further reducing device power consumption, and enhancing the flexibility of logic gates have become key issues. Summary of the Invention
[0005] This invention provides a reconfigurable logic gate based on a synthetic antiferromagnetically coupled skyrmion and its control method, which can improve the reliability of the device, reduce the power consumption of the device, and enhance the flexibility of the logic gate.
[0006] This invention provides a reconfigurable logic gate based on a synthetic antiferromagnetically coupled skyrmion. In the planar structure of the reconfigurable logic gate, the reconfigurable logic gate includes a storage area, a reconfigurable functional area, and an output area, wherein the reconfigurable functional area is located between the storage area and the output area.
[0007] The storage area includes a first region and a second region that are independent of each other. Synthetic antiferromagnetic coupled skyrmions are pre-set in both the first region and the second region. The synthetic antiferromagnetic coupled skyrmions are information carriers for logical function operations.
[0008] The output region includes a third region and a fourth region that are independent of each other. Both the third region and the fourth region are provided with a detection unit for detecting the synthetic antiferromagnetic coupled skyrmion. The presence or absence of the synthetic antiferromagnetic coupled skyrmion represents logic '1' and '0', respectively.
[0009] The reconfigurable functional area includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is located near the first area, the second switch is located near the second area, the third switch is located near the third area, and the fourth switch is located near the fourth area.
[0010] The first switch, the second switch, the third switch, and the fourth switch are used to control the energy barrier at their respective locations, so that the synthesized antiferromagnetic coupled skyrmions in the storage area move to the output area along different paths, and the state of each switch is associated with the binary input, and the state of each switch depends on the logic input.
[0011] Optionally, the reconfigurable functional area is a rectangular area, the first switch is located in the first right-angled area of the reconfigurable functional area, the second switch is located in the second right-angled area of the reconfigurable functional area, the third switch is located in the third right-angled area of the reconfigurable functional area, and the fourth switch is located in the fourth right-angled area of the reconfigurable functional area. The first right-angled area, the second right-angled area, the third right-angled area, and the fourth right-angled area are adjacent vertex areas in the reconfigurable functional area in a counterclockwise direction.
[0012] Optionally, the first switch, the second switch, the third switch, and the fourth switch are all voltage-controlled magnetic anisotropic (VCMA) switches.
[0013] Optionally, in the thickness direction of the reconfigurable logic gate, the reconfigurable logic gate includes: a composite structure layer and a heavy metal layer, wherein the composite structure layer includes a first ferromagnetic layer, a non-magnetic layer and a second ferromagnetic layer stacked sequentially, and the heavy metal layer is disposed on the composite structure layer on the side close to the first ferromagnetic layer;
[0014] The magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer, and both are perpendicular to the non-magnetic layer. The synthesized antiferromagnetic coupled skyrmions are generated by injecting spin-polarized current into the composite structure layer.
[0015] This invention also provides a method for controlling reconfigurable logic gates based on synthetic antiferromagnetically coupled skyrmions, applied to the aforementioned reconfigurable logic gates based on synthetic antiferromagnetically coupled skyrmions, the method comprising:
[0016] Based on the current binary input and the target logic function, control the state of each switch in the reconfigurable functional area to adjust the energy barrier of the right-angle region where each switch is located. The target logic function is used to implement at least one of AND, OR, NOT, AND NOT NAND, OR NOT NOR.
[0017] A driving current along a first direction is injected into the heavy metal layer of the reconfigurable logic gate to drive the synthetic antiferromagnetic coupled skyrmions in the storage region to move toward the output region. The movement of the synthetic antiferromagnetic coupled skyrmions is affected by the energy barrier of the right-angle region where each switch is located. The synthetic antiferromagnetic coupled skyrmions are generated by injecting spin polarization current into the composite structure layer of the reconfigurable logic gate.
[0018] The detection result of the detection unit in the output area is read, and the detection result represents the binary output corresponding to the current binary input under the target logic function.
[0019] Optionally, the step of controlling the state of each switch in the reconfigurable functional area based on the current binary input and the target logic function, in order to adjust the energy barrier of the right-angle region where each switch is located, specifically includes:
[0020] When it is determined that the target logic function is used to implement AND and OR operations, the state of the fourth switch is always controlled to be on.
[0021] The state of the first switch and the state of the third switch are switched according to the logic value of the first input, and the first switch and the third switch are linked to adjust the energy barrier of the right-angle region where the first switch and the third switch are located.
[0022] The state of the second switch is switched according to the logic value of the second input to adjust the energy barrier of the right-angle region where the second switch is located;
[0023] The current binary input includes the first input and the second input. When the switch is in the "on" state, no voltage is applied to the right-angle region where the switch is located. When the switch is in the "off" state, a voltage is applied to the right-angle region where the switch is located. For example, logic inputs "0" and "1" represent applying a high-level voltage and not applying a voltage to the corresponding right-angle region where the switch is located, respectively. That is, inputs "0" and "1" represent the off and on states, respectively. The energy barrier of the right-angle region where a voltage is applied is greater than the energy barrier of the right-angle region where no voltage is applied.
[0024] Optionally, the step of controlling the state of each switch in the reconfigurable functional area based on the current binary input and the target logic function, in order to adjust the energy barrier of the right-angle region where each switch is located, specifically includes:
[0025] When it is determined that the target logic function is used to implement NAND and NOR operations, the state of the third switch is always controlled to be on.
[0026] The state of the first switch is switched according to the logic value of the first input, so as to adjust the energy barrier of the right-angle region where the first switch is located;
[0027] The state of the second switch and the state of the fourth switch are switched according to the logic value of the second input, and the second switch and the fourth switch are linked to adjust the energy barrier of the right-angle region where the second switch and the fourth switch are located;
[0028] The current binary input includes the first input and the second input. When the switch is in the open state, no voltage is applied to the right-angle region where the switch is located. When the switch is in the closed state, a voltage is applied to the right-angle region where the switch is located. For example, logic inputs "1" and "0" respectively represent applying a high-level voltage and not applying a voltage to the right-angle region where the corresponding switch is located. That is, inputs "1" and "0" respectively represent the switch being closed and open.
[0029] Optionally, controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located includes:
[0030] When it is determined that the target logic function is used to implement NOT operation, the state of the first switch group and the state of the second switch group are switched according to the third input to adjust the energy barrier of the right-angle region where each switch in the first switch group is located, and the energy barrier of the right-angle region where each switch in the second switch group is located.
[0031] The current binary input includes the third input; the first switch group includes the first switch and the third switch, with the first switch and the third switch being linked; the second switch group includes the second switch and the fourth switch, with the second switch and the fourth switch being linked.
[0032] Optionally, before controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located, the method further includes:
[0033] Based on the preset binary input and the target logic function, construct the association between the state of each switch in the reconfigurable functional area and the preset binary input.
[0034] Specifically, when the third input logic value is "0", a high-level voltage is applied to the right-angle area where the switch in the first switch group is located, indicating that the switch is closed; no high-level voltage is applied to the right-angle area where the switch in the second switch group is located, indicating that the switch is open. When the third input logic value is "1", a high-level voltage is applied to the right-angle area where the switch in the second switch group is located, indicating that the switch is closed; no high-level voltage is applied to the right-angle area where the switch in the first switch group is located, indicating that the switch is open.
[0035] Optionally, after reading the detection result of the detection unit in the output area, the method further includes:
[0036] A driving current along a second direction is injected into the heavy metal layer of the reconfigurable logic gate to drive the synthesized antiferromagnetically coupled skyrmion back to the memory region.
[0037] In this embodiment of the invention, the planar structure of the reconfigurable logic gate based on the synthetic antiferromagnetically coupled skyrmion includes a storage area, a reconfigurable functional area, and an output area. The storage area includes a first region and a second region, which are independent of each other and used to pre-set and store the synthetic antiferromagnetically coupled skyrmion as the information carrier. By using the synthetic antiferromagnetically coupled skyrmion as the information carrier, the antiparallel arrangement of the upper and lower magnetic moments of the reconfigurable logic gate effectively cancels out the Magnus force, thereby completely suppressing the skyrmion Hall effect and possessing topological protection characteristics, further improving information reliability.
[0038] Based on the state of the logic input control switch, the combined drive current precisely controls the movement path of the synthesized antiferromagnetic skyrmion to perform logic operations, avoiding the need to generate the synthesized antiferromagnetic skyrmion for each logic operation. Simultaneously, after the logic operation is completed, the reverse drive current drives the reversible recombination of the synthesized antiferromagnetic skyrmion, avoiding the high energy consumption required for annihilation synthesis. This further reduces the device's energy consumption and simplifies operation.
[0039] On the same hardware, different logic functions can be reconfigured by flexibly using programming to set switch combinations according to the needs of the logic function, which further increases the flexibility of the device; furthermore, the logic input is represented by the high and low levels of the switch combination, without relying on the generation of synthesized antiferromagnetic coupled skyrmions, which makes it easier to cascade and integrate with other logic devices, improving hardware utilization and flexibility.
[0040] The reconfigurable logic gates described above are non-volatile storage and computation integrated: the logic state is stored by non-volatile synthetic antiferromagnetically coupled skyrmions, and the computation is performed directly on the storage unit, naturally integrating storage and computation functions, providing an ideal physical basis for building non-von Neumann computing architectures. Attached Figure Description
[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a schematic diagram of the reconfigurable logic gate based on the synthetic antiferromagnetically coupled skyrmion provided in an embodiment of the present invention;
[0043] Figure 2 This is a flowchart illustrating the reconfigurable logic gate control method based on synthesized antiferromagnetically coupled skyrmions provided in an embodiment of the present invention.
[0044] Figure 3 This is one of the schematic diagrams of the movement of the synthetic antiferromagnetic coupled skyrmion in a reconfigurable logic gate based on the synthetic antiferromagnetic coupled skyrmion provided in the embodiments of the present invention;
[0045] Figure 4 This is the second schematic diagram of the movement of the synthetic antiferromagnetic coupled skyrmion in a reconfigurable logic gate based on the synthetic antiferromagnetic coupled skyrmion provided in the embodiments of the present invention;
[0046] Figure 5 This is the third schematic diagram of the movement of the synthesized antiferromagnetically coupled skyrmion in a reconfigurable logic gate based on the synthesized antiferromagnetically coupled skyrmion provided in the embodiments of the present invention. Detailed Implementation
[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0048] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such usage can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0049] This invention provides a reconfigurable logic gate based on a synthetic antiferromagnetically coupled skyrmion, such as... Figure 1 As shown; the planar structure of the reconfigurable logic gate is inverted "H" shape, including: a storage area, a reconfigurable functional area and an output area, wherein the reconfigurable functional area is located between the storage area and the output area;
[0050] The storage area includes a first region 101 and a second region 102 that are independent of each other. Synthetic antiferromagnetic coupled skyrmions 1, i.e., synthetic antiferromagnetic coupled (SyAFM) skyrmions, are pre-set in both the first region 101 and the second region 102.
[0051] The output region includes a third region 103 and a fourth region 104 that are independent of each other. Both the third region 103 and the fourth region 104 are provided with a detection unit 2 for detecting the synthetic antiferromagnetic coupled skyrmion.
[0052] The reconfigurable functional area includes a first switch 201, a second switch 202, a third switch 203, and a fourth switch 204. The first switch 201 is located near the first area 101, the second switch 202 is located near the second area 102, the third switch 203 is located near the third area 103, and the fourth switch 204 is located near the fourth area 104.
[0053] The first switch 201, the second switch 202, the third switch 203, and the fourth switch 204, according to the switch combination and the switch state controlled by the logic input value, control the synthetic antiferromagnetic coupled skyrmion 1 to move along different paths to the output area, thereby realizing the logic operation.
[0054] In this embodiment, the planar structure of the reconfigurable logic gate based on the synthetic antiferromagnetic coupled skyrmion includes a storage area, a reconfigurable functional area, and an output area. The storage area includes a first region 101 and a second region 102, which are independent of each other and used to pre-set and store the synthetic antiferromagnetic coupled skyrmion 1 as an information carrier. By using the synthetic antiferromagnetic coupled skyrmion as the information carrier, the antiparallel arrangement of the upper and lower magnetic moments of the reconfigurable logic gate effectively cancels out the Magnus force, thereby suppressing the skyrmion Hall effect. Logic operations are achieved by controlling the movement of the synthetic antiferromagnetic coupled skyrmion, avoiding the need to generate the synthetic antiferromagnetic coupled skyrmion for each logic operation, thus reducing the device's energy consumption.
[0055] A reconfigurable functional area is set between the storage and output regions, making the planar structure of the reconfigurable logic gates an inverted "H" shape. This symmetrical planar structure enables reversible operation by changing the direction of the drive current. In other words, injecting a drive current in a first direction (+x direction) into the reconfigurable logic gate causes the synthesized antiferromagnetic skyrmions in the storage region to move towards the output region. After the logic operation ends, injecting a drive current in a second direction (-x direction) opposite to the first direction causes the synthesized antiferromagnetic skyrmions to return to the storage region along the opposite path of the original logic operation, achieving a reversible reset of the operational state. Throughout the entire computation cycle, the information carrier (i.e., the synthesized antiferromagnetic skyrmions) always exists and is not annihilated. This avoids the high-energy-consuming topology generation / annihilation process required for each computation, supports reversible information flow, improves device reliability, and reduces device energy consumption.
[0056] The output region has two independent regions, a third region 103 and a fourth region 104, each equipped with a detection unit 2 integrating tunneling magnetoresistance (TMR). The location of the detection unit 2 can be defined as the output terminal, used to detect the presence or absence of a synthesized antiferromagnetic skyrmion. Different logic output bits are set according to the target logic function. For example, when implementing OR and AND functions, the third region 103 is the output bit for logical OR, and the fourth region 104 is the output bit for logical AND. For example, the presence or absence of a synthesized antiferromagnetic skyrmion can be determined by integrating a magnetic tunnel junction (MTJ) in the output region and utilizing the tunneling magnetoresistance (TMR) effect: an output "1" indicates that a synthesized antiferromagnetic skyrmion has been detected, and an output "0" indicates that no synthesized antiferromagnetic skyrmion has been detected.
[0057] Furthermore, a first switch 201, a second switch 202, a third switch 203, and a fourth switch 204 are configured in the reconfigurable functional area, with the state of each switch associated with the binary input. Each switch applies (or does not apply) a voltage according to its corresponding binary input to modulate the perpendicular magnetic anisotropy constant at its location. This allows the switching between "on" (forming a channel) and "off" (high anisotropy, forming an energy barrier) states to control the energy barrier at the switch's location, causing the synthesized antiferromagnetic coupled skyrmion 1 in the storage area to move along different paths to the output area, thereby realizing logical operations. On the same hardware, different logic functions can be reconfigured by flexibly using programmed switch combinations according to the needs of the logic function, increasing the device's flexibility.
[0058] Optionally, in the thickness direction of the reconfigurable logic gate, the reconfigurable logic gate includes: a composite structure layer and a heavy metal layer 3. The composite structure layer includes a first ferromagnetic layer 4, a non-magnetic layer 5 and a second ferromagnetic layer 6 stacked sequentially. The heavy metal layer 3 is disposed on the composite structure layer on the side close to the first ferromagnetic layer 4.
[0059] The magnetization direction of the first ferromagnetic layer 4 is opposite to that of the second ferromagnetic layer 6, and both are perpendicular to the non-magnetic layer 5. The synthetic antiferromagnetic coupled skyrmion 1 is generated by injecting spin polarization current into the composite structure layer.
[0060] In this embodiment, in the thickness direction of the reconfigurable logic gate, a heavy metal layer 3 (e.g., Pt, 5nm thick), a first ferromagnetic layer 4 (e.g., Co, 1nm thick), a non-magnetic layer 5 (e.g., Ru, 1nm thick), and a second ferromagnetic layer 6 (e.g., Co, 1nm thick) are stacked sequentially from bottom to top. The first ferromagnetic layer 4, the non-magnetic layer 5, and the second ferromagnetic layer 6 constitute a composite structure layer. The planar structure can be formed into an inverted "H" shape using electron beam lithography and ion etching, with a total size of 240nm × 120nm.
[0061] The saturation magnetization of both the first ferromagnetic layer 4 and the second ferromagnetic layer 6 can be 5.8 × 10⁻⁶. 5 A / m, the initial magnetization direction of the first ferromagnetic layer 4 is set along the +z axis, and the initial magnetization direction of the second ferromagnetic layer 6 is set along the -z axis. They both exhibit perpendicular magnetic anisotropy (Ku = 0.8 × 10⁻⁶). 6 J / m 3 The antiferromagnetic coupling constant (J) generated by the two ferromagnetic layers through the non-magnetic layer 5. AF =-0.001 J / m 2 The interface DMI constant is 3×10. -3 J / m 2 The material parameters are based on experimental values of the Pt / Co / Ru / Co structure and are mainly used for micromagnetic simulation.
[0062] The generation of the synthesized antiferromagnetically coupled skyrmions can be described as follows:
[0063] The first and second ferromagnetic layers can be made of the same material and have the same thickness, with a non-magnetic layer between them. The magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer, both perpendicular to the non-magnetic layer. By vertically injecting spin-polarized current into the composite structure layer of the storage region, the first skyrmions generated in the first ferromagnetic layer and the second skyrmions generated in the second ferromagnetic layer form a synthetic antiferromagnetic skyrmion. Furthermore, because the magnetic skyrmions (i.e., the first and second skyrmions) in the two ferromagnetic layers (i.e., the first and second skyrmions) have opposite polarities, they are coupled together through interlayer antiferromagnetic coupling. The Markovnikov forces caused by the opposite polarities of the two ferromagnetic skyrmions are opposite in direction and equal in magnitude. There is no skyrmion Hall effect during movement, meaning they always move along the driving direction, do not deviate from the track, and do not cause skyrmions to deviate from the track and annihilate upon contact with the edge of the device. Furthermore, the synthetic antiferromagnetically coupled skyrmion, which serves as an information carrier, possesses topological protection, and the antiferromagnetic coupling interaction between the two ferromagnetic layers gives it higher stability and reliability.
[0064] In one example, when a drive current in a first direction is injected into the heavy metal layer, a spin current is generated based on the spin Hall effect. This spin current is vertically injected into the first ferromagnetic layer through spin-orbit coupling, thereby generating a spin torque on the first skyrmion in the first ferromagnetic layer, driving the first skyrmion to move from the storage region towards the output region. Simultaneously, the corresponding second skyrmion in the second ferromagnetic layer moves synchronously with the first skyrmion under the antiferromagnetic coupling effect. In other words, when a drive current in the first direction is injected into the heavy metal layer, a synthesized antiferromagnetically coupled skyrmion moves from the storage region towards the output region. The movement of the synthesized antiferromagnetically coupled skyrmion is used to manipulate logic gate operations.
[0065] Furthermore, after the logic gate operation is completed, a driving current in a second direction can be injected into the heavy metal layer, causing the synthesized antiferromagnetic coupled skyrmions to move from the storage region towards the input region. In other words, the synthesized antiferromagnetic coupled skyrmions return to their initial positions for the next logic operation, achieving reversible operation. This avoids generating skyrmions for each logic operation, reducing the number of operation steps and lowering device power consumption. The reverse process only requires injecting a driving current in the second direction, making the control method very simple, and it eliminates the need for large currents to clear the skyrmions, further reducing logic gate power consumption.
[0066] Optionally, the reconfigurable functional area is a rectangular area, the first switch 201 is located in the first right-angled area 301 of the reconfigurable functional area, the second switch 202 is located in the second right-angled area 302 of the reconfigurable functional area, the third switch 203 is located in the third right-angled area 303 of the reconfigurable functional area, and the fourth switch 204 is located in the fourth right-angled area 304 of the reconfigurable functional area. The first right-angled area 301, the second right-angled area 302, the third right-angled area 303, and the fourth right-angled area 304 are adjacent vertex areas in the reconfigurable functional area in a counterclockwise direction.
[0067] In this embodiment, the reconfigurable functional area is a rectangular region, such as... Figure 1 As shown, the rectangular region, from the upper left right angle, consists of the first right-angle region 301, the second right-angle region 302, the third right-angle region 303, and the fourth right-angle region 304, arranged counterclockwise. Each right-angle side can be 60 nm. Furthermore, the first switch 201 is located in the first right-angle region 301, the second switch 202 in the second right-angle region 302, the third switch 203 in the third right-angle region 303, and the fourth switch 204 in the fourth right-angle region 304. Thus, each switch applies (or does not apply) a voltage to its corresponding right-angle region based on its corresponding binary input, modulating the perpendicular magnetic anisotropy constant of the right-angle region where the switch is located. This controls the energy barrier of the right-angle region, causing the synthesized antiferromagnetically coupled skyrmion 1 in the storage region to move to the output region along different paths.
[0068] In one example, the state of the first switch 201 is controlled to be "on", the state of the second switch 202 is "off", the state of the third switch 203 is "on", and the state of the fourth switch 204 is "off". Since the state of the first switch 201 is "on", no voltage is applied to the first right-angle region 301, causing the pre-placed synthetic antiferromagnetic coupled skyrmions in the first region 101 to move towards the output region; while since the state of the second switch 202 is "off", a voltage is applied to the second right-angle region 302 to form an energy barrier in the second right-angle region 302, so that the pre-placed synthetic antiferromagnetic coupled skyrmions in the second region 102 are blocked in the second region 102.
[0069] In the process of the pre-set synthetic antiferromagnetic coupled skyrmions in the first region 101 moving toward the output region, since the state of the fourth switch 204 is "closed", an energy barrier will be formed in the fourth right-angle region 304. This causes the moving synthetic antiferromagnetic coupled skyrmions to be guided toward the third region 103 by the repulsive effect of the hypotenuse barrier in the fourth right-angle region 304. Since the state of the third switch 203 is "open", the synthetic antiferromagnetic coupled skyrmions can enter the third region 103 through the third right-angle region 303.
[0070] Thus, the detection unit in the third region 103 detects the presence of a synthetic antiferromagnetic coupled skyrmion, and outputs "1"; while the detection unit in the fourth region 104 does not detect the presence of a synthetic antiferromagnetic coupled skyrmion, and outputs "0".
[0071] In another example, the state of the first switch 201 is controlled to be "on", the state of the second switch 202 is "off", and the state of the fourth switch 204 is "on". Since the state of the first switch 201 is "on", no voltage is applied to the first right-angle region 301, causing the pre-placed synthetic antiferromagnetic coupled skyrmions in the first region 101 to move toward the output region; while since the state of the second switch 202 is "off", a voltage is applied to the second right-angle region 302 to form an energy barrier in the second right-angle region 302, so that the pre-placed synthetic antiferromagnetic coupled skyrmions in the second region 102 are blocked in the second region 102.
[0072] The state of the third switch 203 can be either "closed" or "open". The synthesized antiferromagnetic coupled skyrmion preset in the first region 101 is less affected by the third right-angle region 303 as it moves toward the output region. Since the state of the fourth switch 204 is "open", the synthesized antiferromagnetic coupled skyrmion can enter the fourth region 104 through the fourth right-angle region 304.
[0073] It should be understood that in some other embodiments, the same technical effect can be achieved by controlling other combinations of switches so that the synthesized antiferromagnetically coupled skyrmions in the storage area can move to the output area along different paths, which will not be elaborated here.
[0074] In this way, by controlling the energy barrier of each switch at its location, the synthesized antiferromagnetically coupled skyrmions in the storage area can move to the output area along different paths, thus enabling different logical operations. Based on this, on the same hardware, by setting different switch combinations through programming and controlling the state of each switch based on the logic input, various basic logic gates such as "AND", "OR", "NOT", "NAND", and "NOR" can be implemented, providing excellent flexibility.
[0075] Optionally, the first switch 201, the second switch 202, the third switch 203 and the fourth switch 204 are all voltage-controlled magnetic anisotropy (VCMA) switches.
[0076] In this embodiment, the first switch 201, the second switch 202, the third switch 203, and the fourth switch 204 are all VCMA switches. VCMA switches can precisely modulate the perpendicular magnetic anisotropy of their respective right-angle regions by applying voltage. By switching between "on" and "off" states, the energy barrier of the right-angle region is controlled, causing the synthesized antiferromagnetic skyrmion 1 in the storage region to move along different paths to the output region, thus realizing logic operations. Furthermore, under the reversible mechanism (with reverse drive current), the synthesized antiferromagnetic skyrmion returns to its initial position (i.e., the storage region) and is used as the information carrier for the next logic operation. During logic operations, the generation and annihilation of the synthesized antiferromagnetic skyrmion are avoided, saving energy and truly realizing a low-energy device.
[0077] like Figure 2 As shown, this embodiment of the invention also provides a method for controlling reconfigurable logic gates based on synthetic antiferromagnetically coupled skyrmions, applied to the aforementioned reconfigurable logic gates based on synthetic antiferromagnetically coupled skyrmions. The method includes:
[0078] The reconfigurable logic gate uses a synthetic antiferromagnetically coupled skyrmion as an information carrier. The synthetic antiferromagnetically coupled skyrmion is generated by injecting a spin-polarized current into the composite structure layer of the reconfigurable logic gate during its first use (or at the start of preparation) and is stored in the storage region. The synthetic antiferromagnetically coupled skyrmion is formed by coupling two magnetic structures with different polarities and opposite magnetization vectors through antiferromagnetic coupling exchange interaction. Therefore, there is no skyrmion Hall effect during its movement. It always moves along the direction of the driving current. Compared with magnetic skyrmions, it is less likely to touch the edge of the device and be annihilated, further improving the reliability of logic operations.
[0079] Step S1: Based on the current binary input and the target logic function, control the state of each switch in the reconfigurable functional area to adjust the energy barrier of the right-angle region where each switch is located. The target logic function is used to implement at least one of AND, OR, NOT, NAND, and NOR operations.
[0080] In this step, different switch combinations and corresponding switch states for binary logic can be set according to the target logic function. Logic operations are achieved by controlling the movement of the synthesized antiferromagnetic skyrmion. During logic operations, generating a synthesized antiferromagnetic skyrmion for each operation is eliminated, reducing device power consumption. Furthermore, based on preset switch state combinations corresponding to different logic functions, without changing the physical structure of the hardware, the spatial distribution of the energy barrier is dynamically configured, allowing the synthesized antiferromagnetic skyrmion 1 in the storage area to move to the output area along different paths, improving the accuracy of the movement trajectory and thus enhancing device reliability. In this way, the same hardware can adapt to the operational requirements of different logic functions, realizing dynamic reconfiguration of logic gates and improving hardware resource utilization.
[0081] For example, VCMA switches (i.e., first switch 201, second switch 202, third switch 203, and fourth switch 204) are respectively set in the right-angle regions corresponding to the reconfigurable functional area (i.e., the first right-angle region 301, the second right-angle region 302, the third right-angle region 303, and the fourth right-angle region 304). According to the target logic function, different switch combinations are set, and each switch combination is set with the corresponding binary logic "1" and "0" corresponding switch states. The closed state of the switch corresponds to the application of a high-level voltage on the switch. Due to the VCMA effect, the magnetic anisotropy of the right-angle region corresponding to the switch will increase, thereby forming an energy barrier. When the synthesized antiferromagnetically coupled skyrmion approaches the barrier, it will be subjected to dynamic repulsive force, thereby blocking or modulating the movement path of the synthesized antiferromagnetically coupled skyrmion.
[0082] Step S2: Inject a driving current along the first direction into the heavy metal layer of the reconfigurable logic gate to drive the synthetic antiferromagnetic coupled skyrmions in the storage region to move toward the output region. The movement of the synthetic antiferromagnetic coupled skyrmions is affected by the energy barrier of the right-angle region where each switch is located. The synthetic antiferromagnetic coupled skyrmions are generated by injecting spin polarization current into the composite structure layer of the reconfigurable logic gate.
[0083] For example, in this step, a driving current in the first direction (i.e., the +x direction) is injected into the reconfigurable logic gate to generate a spin current in the vertically injected synthetic antiferromagnetic composite structure using the spin Hall effect. The torque of the spin current will drive the synthetic antiferromagnetic coupled skyrmion in the storage area to move toward the output area. During the movement, the synthetic antiferromagnetic skyrmion will be controlled by the switching state, thereby reaching different output areas and realizing different logic operations.
[0084] Step S3: Read the detection result of the detection unit of the output area. The detection result represents the binary output corresponding to the current binary input under the target logic function.
[0085] In this step, the magnetic tunnel junction detection unit based on the tunneling magnetoresistance effect integrated in the output region is used to detect whether a synthetic antiferromagnetic coupled skyrmion physically exists in the output region. If a synthetic antiferromagnetic coupled skyrmion is detected, the output is binary '1', otherwise it is '0'.
[0086] In this embodiment, the state of each switch in the reconfigurable functional area is controlled according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located, thereby accurately planning the motion path. Combined with the characteristic of synthesizing antiferromagnetically coupled skyrmions to eliminate the skyrmion Hall effect, the calculation error caused by the motion trajectory deviation is reduced, and the reliability of the logic operation is improved.
[0087] Furthermore, by using synthetic antiferromagnetically coupled skyrmions as non-volatile information carriers, computation is completed by driving their movement with current, eliminating the need for energy-intensive repeated generation / annihilation operations on the skyrmions. The switching state and energy barrier distribution are dynamically adjusted based on the actual binary input and target logic function, allowing for instantaneous switching of various basic logic functions (AND, OR, NOT, NAND, NOR) on the same device without altering the hardware physical structure, thus improving hardware resource utilization.
[0088] Optionally, before controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located, the method further includes:
[0089] Based on the preset binary input and the target logic function, construct the association between the state of each switch in the reconfigurable functional area and the preset binary input.
[0090] In this embodiment, for the target logic functions such as AND, OR, NOT, NAND, and NOR, a pre-established correspondence between the state of each switch in the reconfigurable functional area and the preset binary input is formed by combining preset binary inputs (0 / 1). This determines the switch state configuration scheme corresponding to different preset input values, i.e., how each switch should be adjusted to form the corresponding energy barrier or conduction channel under different binary inputs. This provides a unified configuration basis for quickly and accurately adjusting the switch state according to the actual current binary input, avoiding deviations and confusion in temporary adjustments, and ensuring the standardization and response efficiency of switch state configuration when switching between different logic functions. In this way, subsequent energy barrier adjustments and logic operations can be carried out in an orderly manner strictly following preset rules, improving the computational accuracy and process smoothness of the entire control method.
[0091] The truth table for implementing logical functions using reconfigurable logic gates provided in this embodiment is shown in Table 1 below:
[0092] Table 1
[0093]
[0094] To implement the above logical functions, please refer to the following description:
[0095] Optionally, controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located includes:
[0096] When it is determined that the target logic function is used to implement AND and OR operations, the state of the fourth switch is always controlled to be on.
[0097] The current binary input includes the first input and the second input. The state of the first switch and the state of the third switch are switched according to the logic value of the first input, and the first switch and the third switch are linked. The state of the second switch is switched according to the logic value of the second input. When the switch is in the open state, no voltage is applied to the right-angle region where the switch is located. When the switch is in the closed state, a voltage is applied to the right-angle region where the switch is located. The energy barrier of the right-angle region where the voltage is applied is greater than the energy barrier of the right-angle region where no voltage is applied.
[0098] In this embodiment, to implement the "AND" and "OR" dual-input logic operations, the fourth switch 204 can be always set to "on" (i.e., the state of the fourth switch 204 does not need to be adjusted with changes in the binary input), thus establishing a fixed basic conduction channel for the synthesis of antiferromagnetically coupled skyrmions. Specifically, a binary input "0" indicates that a high-level voltage is applied to the corresponding switch (i.e., the switch is in the "off" state), and a binary input "1" indicates that no high-level voltage is applied to the corresponding switch (i.e., the switch is in the "on" state).
[0099] In this embodiment, the first input corresponds to the state of the first switch 201 and the state of the third switch 203, and the first switch 201 and the third switch 203 are linked (i.e., synchronously adjusted). The second input corresponds to the state of the second switch 202. See the following description for details:
[0100] The current binary inputs include the first input A and the second input B. The fourth switch 204 is always "on". The states of the first switch 201 and the third switch 203 are associated with the first input A (A=1, switch is "on"; A=0, switch is "off"). The state of the second switch 202 is associated with the second input B (B=1, switch is "on"; B=0, switch is "off"). Furthermore, the fourth region 104 of the output area is configured to detect OR results, and the third region 103 is configured to detect AND results. The SyAFM skyrmion motion trajectory diagram in the AND and OR logic function implementation is shown below. Figure 3 As shown.
[0101] When inputs A=0 and B=0, the states of the first switch 201, the second switch 202, and the third switch 203 are all "closed". Therefore, the first right-angle region 301, the second right-angle region 302, and the third right-angle region 303 all form energy barriers. Even if the fourth switch 204 is "open", the SyAFM skyrmion is still confined to the storage region and cannot move to the output region. At this time, neither the third region 103 nor the fourth region 104 can detect the SyAFM skyrmion, so the AND and OR outputs are both 0. That is, the AND operation (0,0) → (0) and the OR operation (0,0) → (0) are implemented.
[0102] When input A=0 and B=1, the first switch 201 and the third switch 203 are both "closed," the second switch 202 is "open," and the fourth switch 204 is "open." Therefore, both the first right-angle region 301 and the third right-angle region 303 form energy barriers, blocking the SyAFM skyrmions preset in the first region 101. The SyAFM skyrmions preset in the second region 102 can move towards the output region through the channel of the second right-angle region 302. During this movement, the SyAFM skyrmions are guided towards the fourth region 104 by the repulsive effect of the hypotenuse barrier in the third right-angle region 303. At this time, the third region 103 cannot detect the SyAFM skyrmions, while the fourth region 104 detects them. Therefore, the OR output is 1, and the AND output is 0. This implements the OR operation (0, 1) → (1) and the AND operation (0, 1) → (0).
[0103] When input A=1 and B=0, the first switch 201 and the third switch 203 are both "on", the second switch 202 is "off", and the fourth switch 204 is "on". Therefore, no energy barrier is formed in the first right-angle region 301, the third right-angle region 303, and the fourth right-angle region 304, while an energy barrier is formed in the second right-angle region 302. The SyAFM skyrmions preset in the second region 102 are blocked in the second region 102; while the SyAFM skyrmions preset in the first region 101 can move towards the output region through the channel of the first right-angle region 301 and enter the fourth region 104 through the channel of the fourth right-angle region 304. At this time, the third region 103 cannot detect SyAFM skyrmions, while the fourth region 104 detects SyAFM skyrmions; therefore, the OR output is 1, and the AND output is 0. This implements the OR operation (1, 0) → (1) and the AND operation (1, 0) → (0).
[0104] When input A=1 and B=1, the states of the first switch 201, the second switch 202, and the third switch 203 are all "on", and the fourth switch 204 is also "on". Therefore, no energy barrier is formed in the first right-angle region 301, the second right-angle region 302, the third right-angle region 303, and the fourth right-angle region 304. The SyAFM skyrmions preset in the first region 101 can move towards the fourth region 104 through the channels of the first right-angle region 301 and the fourth right-angle region 304; the SyAFM skyrmions preset in the second region 102 can move towards the third region 103 through the channels of the second right-angle region 302 and the third right-angle region 303. At this time, both the third region 103 and the fourth region 104 detect SyAFM skyrmions, so the AND and OR outputs are both 1. That is, the AND operation of (1,1)→(1) and the OR operation of (1,1)→(1) are realized.
[0105] Optionally, controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located includes:
[0106] When it is determined that the target logic function is used to implement NAND and NOR operations, the state of the third switch is always controlled to be on.
[0107] The current binary input includes the first input and the second input. The state of the first switch is switched according to the first input logic value. The states of the second switch and the fourth switch are switched according to the second input logic value, and the second switch and the fourth switch are linked. When the switch is in the open state, no voltage is applied to the right-angle region where the switch is located. When the switch is in the closed state, a voltage is applied to the right-angle region where the switch is located. The energy barrier of the right-angle region where the voltage is applied is greater than the energy barrier of the right-angle region where no voltage is applied.
[0108] In this embodiment, to implement the dual-input logic operation of "NAND" and "NOR", the third switch 203 can be always set to "on" (i.e., the state of the third switch 203 does not need to be adjusted with changes in binary input), thus establishing a fixed basic conduction channel for the synthesis of antiferromagnetically coupled skyrmions. Specifically, a binary input "1" indicates that a high-level voltage is applied to the corresponding switch (i.e., the switch is in the "off" state, forming an energy barrier), and a binary input "0" indicates that no high-level voltage is applied to the corresponding switch (i.e., the switch is in the "on" state, and no energy barrier is formed).
[0109] In this embodiment, based on the association between the states of each switch in the reconfigurable functional area and the binary input, the state of the first input corresponds to the state of the first switch 201, and the state of the second input corresponds to the states of the second switch 202 and the fourth switch 204. Furthermore, the second switch 202 and the fourth switch 204 are linked (i.e., their states are adjusted synchronously). See the following description for details:
[0110] The current binary inputs include the first input A and the second input B. The third switch 203 is always "on". The state of the first switch 201 is associated with the first input A (A=0, switch is "on"; A=1, switch is "off"). The states of the second switch 202 and the fourth switch 204 are associated with the second input B (B=0, switch is "on"; B=1, switch is "off"). Furthermore, the fourth region 104 of the output area is configured to detect NOR results, and the third region 103 is configured to detect NAND results. The SyAFM skyrmion motion trajectory diagram in the NAND and NOR logic function implementation is shown below. Figure 4 As shown.
[0111] When input A=0 and B=0, the states of the first switch 201, the second switch 202, and the fourth switch 204 are all "on", and the state of the third switch 203 is also "on". Therefore, no energy barrier is formed in the first right-angle region 301, the second right-angle region 302, the third right-angle region 303, and the fourth right-angle region 304. The SyAFM skyrmions preset in the first region 101 can move towards the fourth region 104 through the channels of the first right-angle region 301 and the fourth right-angle region 304; the SyAFM skyrmions preset in the second region 102 can move towards the third region 103 through the channels of the second right-angle region 302 and the third right-angle region 303. At this time, both the third region 103 and the fourth region 104 detect SyAFM skyrmions, so the NAND and NOR outputs are both 1. That is, the NAND operation of (0,0)→(1) and the NOR operation of (0,0)→(1) are realized.
[0112] When input A=0 and B=1, the first switch 201 and the third switch 203 are both "on," while the second switch 202 and the fourth switch 204 are both "off." Therefore, neither the first right-angle region 301 nor the third right-angle region 303 forms an energy barrier, while the second right-angle region 302 and the fourth right-angle region 304 do. The SyAFM skyrmions preset in the second region 102 are blocked in the second region 102; however, the SyAFM skyrmions preset in the first region 101 can move towards the output region through the channel of the first right-angle region 301. During this movement, the SyAFM skyrmions are guided towards the third region 103 by the repulsive effect of the hypotenuse barrier in the fourth right-angle region 304. At this point, the third region 103 detects the SyAFM skyrmions, while the fourth region 104 cannot detect them; therefore, the NOR output is 0, and the NAND output is 1. This implements the NOR operation (0, 1) → (0) and the NAND operation (0, 1) → (1).
[0113] When input A=1 and B=0, the first switch 201 is controlled to be "closed," and the second switch 202 and the fourth switch 204 are both controlled to be "open," while the third switch 203 is also "open." Therefore, no energy barrier is formed in the second right-angle region 302, the third right-angle region 303, and the fourth right-angle region 304, while an energy barrier is formed in the first right-angle region 301. The SyAFM skyrmions preset in the first region 101 are blocked in the first region 101; however, the SyAFM skyrmions preset in the second region 102 can move towards the output region through the channel of the second right-angle region 302 and enter the third region 103 through the channel of the third right-angle region 303. At this time, the third region 103 detects the SyAFM skyrmions, while the fourth region 104 cannot detect them; therefore, the NOR output is 0, and the NAND output is 1. This implements the NOR operation (1,0) → (0) and the NAND operation (1,0) → (1).
[0114] When inputs A=1 and B=1, the states of the first switch 201, the second switch 202, and the fourth switch 204 are all "closed". Therefore, the first right-angle region 301, the second right-angle region 302, and the fourth right-angle region 304 all form energy barriers. Even if the third switch 203 is "open", the SyAFM skyrmions are still confined to the storage region and cannot move to the output region. At this time, neither the third region 103 nor the fourth region 104 can detect SyAFM skyrmions, so the NAND and NOR outputs are both 0. That is, the NAND operation of (1,1)→(0) and the NOR operation of (1,1)→(0) are realized.
[0115] Optionally, controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located includes:
[0116] When it is determined that the target logic function is used to implement NOT operation, the state of the first switch group and the state of the second switch group are switched according to the third input to adjust the energy barrier of the right-angle region where each switch in the first switch group is located, and the energy barrier of the right-angle region where each switch in the second switch group is located.
[0117] The current binary input includes the third input; the first switch group includes the first switch and the third switch, with the first switch and the third switch being linked; the second switch group includes the second switch and the fourth switch, with the second switch and the fourth switch being linked.
[0118] In this embodiment, for implementing the "NOT" single-input logic operation, a binary input "0" can be defined as applying a high-level voltage to the corresponding switch (i.e., the switch is in the "closed" state, forming an energy barrier), and a binary input "1" can be defined as not applying a high-level voltage to the corresponding switch (i.e., the switch is in the "open" state, and no energy barrier is formed).
[0119] Then, based on the association between the states of each switch in the reconfigurable functional area and the preset binary input, the states of the first and second switch groups corresponding to the third input are determined. The first switch group includes the first switch 201 and the third switch 203 in a synchronous adjustment state, and the second switch group includes the second switch 202 and the fourth switch 204 in a synchronous adjustment state. Therefore, the states of the first and second switch groups can be switched according to the third input to adjust the energy barriers of the right-angled regions (i.e., the first right-angled region 301 and the third right-angled region 303) where the first switch 201 and the third switch 203 are located, and to adjust the energy barriers of the right-angled regions (i.e., the second right-angled region 302 and the fourth right-angled region 304) where the second switch 202 and the fourth switch 204 are located, thus jointly constructing an energy barrier distribution adapted to NOT logic. This allows for coordinated control of the motion of the synthesized antiferromagnetically coupled skyrmions, realizing the NOT function. See the following description for details:
[0120] The current binary input includes a third input C. The states of the first and second switch groups are associated with the third input C (C=1, the first switch group is "on" and the second switch group is "off"; C=0, the first switch group is "off" and the second switch group is "on"). Furthermore, the fourth region 104 of the output area is configured to detect NOT results. The SyAFM skyrmion trajectory diagram in the NOT logic function implementation is shown below. Figure 5As shown. It should be understood that the third input C in this embodiment can share the same input terminal as the first input A in the other embodiments described above.
[0121] When input C=0, the first switch group is controlled to be "closed" and the second switch group is controlled to be "open," meaning that the states of the first switch 201 and the third switch 203 are both "closed," and the states of the second switch 202 and the fourth switch 204 are both "open." Therefore, energy barriers are formed in both the first right-angle region 301 and the third right-angle region 303, blocking the SyAFM skyrmions preset in the first region 101. However, no energy barriers are formed in the second right-angle region 302 and the fourth right-angle region 304, allowing the SyAFM skyrmions preset in the second region 102 to move towards the output region through the channel. During this movement, the SyAFM skyrmions are guided towards the fourth region 104 by the repulsive effect of the hypotenuse barrier in the third right-angle region 303. At this point, the third region 103 cannot detect the SyAFM skyrmions, while the fourth region 104 can, therefore the NOT output is 1. This achieves the NOT operation of (0) → (1).
[0122] When input C=1, the first switch group is "on" and the second switch group is "off," meaning the first switch 201 and the third switch 203 are both "on," and the second switch 202 and the fourth switch 204 are both "off." Therefore, energy barriers are formed in both the second right-angle region 302 and the fourth right-angle region 304, blocking the SyAFM skyrmions preset in the second region 102. However, no energy barriers are formed in the first right-angle region 301 and the third right-angle region 303, allowing the SyAFM skyrmions preset in the first region 101 to move towards the output region through the channel. During this movement, the SyAFM skyrmions are guided towards the third region 103 by the repulsive effect of the hypotenuse barrier in the fourth right-angle region 304. At this point, the third region 103 detects the SyAFM skyrmions, while the fourth region 104 cannot detect them, resulting in a NOT output of 0. This achieves the NOT operation of (1) → (0).
[0123] Optionally, after reading the detection result of the detection unit in the output area, the method further includes:
[0124] A driving current along a second direction is injected into the heavy metal layer of the reconfigurable logic gate to drive the synthesized antiferromagnetically coupled skyrmion back to the memory region.
[0125] In this embodiment, after the logic operation is completed, a second-direction driving current, opposite to the first direction driving the SyAFM skyrmion to move towards the output region, is injected into the heavy metal layer. Utilizing the spin current generated by the spin Hall effect, the SyAFM skyrmion that has moved to the output region is driven back to the storage region along a reverse path. This achieves the cyclic reuse of the SyAFM skyrmion, reducing power consumption over the entire operation cycle. Simultaneously, it restores the SyAFM skyrmion to its initial preset position, preparing the hardware for subsequent new binary inputs and the operation of the target logic function, ensuring that the logic gate can continuously and reversibly perform multiple logic operations.
[0126] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0127] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.
Claims
1. A reconfigurable logic gate based on a synthetic antiferromagnetically coupled skyrmion, characterized in that, In the planar structure of the reconfigurable logic gate, the reconfigurable logic gate includes: a storage area, a reconfigurable functional area, and an output area, wherein the reconfigurable functional area is located between the storage area and the output area; The storage area includes a first region and a second region that are independent of each other. Synthetic antiferromagnetic coupled skyrmions are pre-set in both the first region and the second region. The synthetic antiferromagnetic coupled skyrmions are information carriers for logical function operations. The output region includes a third region and a fourth region that are independent of each other. Both the third region and the fourth region are provided with detection units for detecting the synthetic antiferromagnetic coupled skyrmions. The reconfigurable functional area includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is located near the first area, the second switch is located near the second area, the third switch is located near the third area, and the fourth switch is located near the fourth area. The first switch, the second switch, the third switch, and the fourth switch are used to control the energy barrier at their respective locations, so that the synthesized antiferromagnetic coupled skyrmions in the storage area move to the output area along different paths, and the state of each switch is associated with the binary input.
2. The reconfigurable logic gate according to claim 1, characterized in that, The reconfigurable functional area is a rectangular area. The first switch is located in the first right-angled area of the reconfigurable functional area, the second switch is located in the second right-angled area of the reconfigurable functional area, the third switch is located in the third right-angled area of the reconfigurable functional area, and the fourth switch is located in the fourth right-angled area of the reconfigurable functional area. The first right-angled area, the second right-angled area, the third right-angled area, and the fourth right-angled area are adjacent vertex areas in the reconfigurable functional area in a counterclockwise direction.
3. The reconfigurable logic gate according to claim 1, characterized in that, The first switch, the second switch, the third switch, and the fourth switch are all voltage-controlled magnetic anisotropic (VCMA) switches.
4. The reconfigurable logic gate according to any one of claims 1 to 3, characterized in that, In the thickness direction of the reconfigurable logic gate, the reconfigurable logic gate includes: a composite structure layer and a heavy metal layer. The composite structure layer includes a first ferromagnetic layer, a non-magnetic layer and a second ferromagnetic layer stacked sequentially. The heavy metal layer is disposed on the composite structure layer on the side close to the first ferromagnetic layer. The magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer, and both are perpendicular to the non-magnetic layer. The synthesized antiferromagnetic coupled skyrmions are generated by injecting spin-polarized current into the composite structure layer.
5. A method for controlling reconfigurable logic gates based on synthetic antiferromagnetically coupled skyrmions, characterized in that, The method, applied to a reconfigurable logic gate based on a synthetic antiferromagnetically coupled skyrmion as described in any one of claims 1 to 4, comprises: Based on the current binary input and the target logic function, control the state of each switch in the reconfigurable functional area to adjust the energy barrier of the right-angle region where each switch is located. The target logic function is used to implement at least one of AND, OR, NOT, AND NOT NAND, OR NOT NOR. A driving current along a first direction is injected into the heavy metal layer of the reconfigurable logic gate to drive the synthetic antiferromagnetic coupled skyrmions in the storage region to move toward the output region. The movement of the synthetic antiferromagnetic coupled skyrmions is affected by the energy barrier of the right-angle region where each switch is located. The synthetic antiferromagnetic coupled skyrmions are generated by injecting spin polarization current into the composite structure layer of the reconfigurable logic gate. The detection result of the detection unit in the output area is read, and the detection result represents the binary output corresponding to the current binary input under the target logic function.
6. The method according to claim 5, characterized in that, The step of controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function, so as to adjust the energy barrier of the right-angle region where each switch is located, includes: When it is determined that the target logic function is used to implement AND and OR operations, the state of the fourth switch is always controlled to be on. The state of the first switch and the state of the third switch are switched according to the first input, and the first switch and the third switch are linked to adjust the energy barrier of the right-angle region where the first switch and the third switch are located. The state of the second switch is switched according to the second input to adjust the energy barrier in the right-angle region where the second switch is located; The current binary input includes the first input and the second input. When the switch is in the open state, no voltage is applied to the right-angle region where the switch is located. When the switch is in the closed state, a voltage is applied to the right-angle region where the switch is located. The energy barrier of the right-angle region where the voltage is applied is greater than the energy barrier of the right-angle region where no voltage is applied.
7. The method according to claim 5, characterized in that, The step of controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function, so as to adjust the energy barrier of the right-angle region where each switch is located, includes: When it is determined that the target logic function is used to implement NAND and NOR operations, the state of the third switch is always controlled to be on. The state of the first switch is switched according to the first input to adjust the energy barrier of the right-angle region where the first switch is located; The state of the second switch and the state of the fourth switch are switched according to the second input, and the second switch and the fourth switch are linked to adjust the energy barrier of the right-angle region where the second switch and the fourth switch are located; The current binary input includes the first input and the second input. When the switch is in the open state, no voltage is applied to the right-angle region where the switch is located. When the switch is in the closed state, a voltage is applied to the right-angle region where the switch is located. The energy barrier of the right-angle region where the voltage is applied is greater than the energy barrier of the right-angle region where no voltage is applied.
8. The method according to claim 5, characterized in that, The step of controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function, so as to adjust the energy barrier of the right-angle region where each switch is located, includes: When it is determined that the target logic function is used to implement NOT operation, the state of the first switch group and the state of the second switch group are switched according to the third input to adjust the energy barrier of the right-angle region where each switch in the first switch group is located, and the energy barrier of the right-angle region where each switch in the second switch group is located. The current binary input includes the third input; the first switch group includes the first switch and the third switch, with the first switch and the third switch being linked; the second switch group includes the second switch and the fourth switch, with the second switch and the fourth switch being linked.
9. The method according to any one of claims 5 to 8, characterized in that, Before controlling the state of each switch in the reconfigurable functional area according to the current binary input and the target logic function to adjust the energy barrier of the right-angle region where each switch is located, the method further includes: Based on the preset binary input and the target logic function, construct the association between the state of each switch in the reconfigurable functional area and the preset binary input.
10. The method according to any one of claims 5 to 8, characterized in that, After reading the detection results of the detection unit in the output area, the method further includes: A driving current along a second direction is injected into the heavy metal layer of the reconfigurable logic gate to drive the synthesized antiferromagnetically coupled skyrmion back to the memory region.