A multi-person voter design and implementation method based on 1T1M memristor array structure

Abstract

A multi-person voter design and implementation method based on a 1T1M memristor array structure are provided. The system and method examples disclosed in the paper include a 1T1M memristor array, a signal input module, a voting logic unit, and an output module, which have the functions of efficient data collection, logical operation, and voting result output in a multi-person voting scene.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and more specifically, relates to a design and implementation method of a multi-voter based on a 1T1M memristor array structure. Background Technology

[0002] In the era of big data, emerging data-intensive applications such as cloud computing, the Internet of Things, and artificial intelligence are booming. Within the traditional von Neumann architecture framework of memory-computing separation, core challenges such as the "memory wall" bottleneck, the slowdown in Moore's Law's growth rate, and the failure of Dennard scaling are becoming increasingly prominent. Simultaneously, the traditional irreversible computing paradigm will also face the constraint of the thermodynamic wall. These factors collectively lead to chip computing performance being limited by key issues such as energy consumption, latency, and heat dissipation. Memristors, as a new type of semiconductor memory device, possess outstanding advantages such as small device size, fast read / write speeds, low power consumption, and high compatibility with CMOS processes, providing a solid hardware foundation for research in the field of in-memory computing. In recent years, with a deeper understanding of memristors, their use has expanded beyond simply being a new type of storage material; their potential in logic operations is being continuously explored.

[0003] Since the application potential of memristors as novel switching devices has been gradually discovered, research on voting devices based on memristor switches has flourished. Scholars have continuously proposed improvements such as optimizing circuit topology, refining signal control mechanisms, and developing voting implementation logic adapted to the characteristics of memristor switches to alleviate the problems of low integration, high power consumption, and limited response speed in traditional voting devices. However, current research remains largely at the basic level of simple structure demonstrations or reliance on complex peripheral circuits. It rarely involves the design of simplified voting devices with NMOS as the control core and pure memristor switching functionality. This is because existing solutions do not fully combine the signal gating advantages of NMOS with the efficient switching characteristics of memristors, resulting in insufficient coordination between control signals and switching actions, cumbersome multi-unit linkage logic, and difficulty in suppressing signal crosstalk. This hinders the development of memristor-based voting devices towards higher reliability and lower complexity, making it difficult to efficiently achieve simplified structure and precise control in voting functions. Summary of the Invention

[0004] To address the aforementioned problems, the purpose of this invention is to provide a design and implementation method for a multi-voting device based on a 1T1M memristor array structure. Its key feature is the integration of an input unit corresponding to the number of voters, a memristor array, a voting logic unit, and an output unit; each voting participant corresponds to an input unit, and the multi-voting result is achieved through vector operations using the 1T1M memristor array structure, taking a three-person voting device as an example.

[0005] According to the aforementioned multi-voting device, each voltage source in the memristor array serves as an input signal corresponding to one voting participant. The voting signal of the array is transmitted through the input signals of each NMOS transistor. Using memristors as switches to determine whether the circuit is on or off provides sufficient stability and timeliness. The high-resistance state of the memristor is defined as the circuit being off, i.e., logic "0"; the low-resistance state is defined as the circuit being on, i.e., logic "1". The voting signal, after being output from the NMOS transistor, enters the memristor as its input signal. The output signal of the memristor serves as the input to the next NMOS transistor, thereby integrating the voting signals from the two NMOS inputs. The final output signal is obtained by connecting the corresponding three branch outputs.

[0006] According to the multi-person voting device, the input module is characterized in that it receives voting operation signals transmitted by each input unit, the electrical signals are mapped to the memristor array (e.g., "for" corresponds to electrical signal 1, "against" corresponds to electrical signal 0), and the converted signals are transmitted to the corresponding units of the memristor array.

[0007] According to the aforementioned multi-voting device, the logical relationship of the three-person voting device is Y=AB+AC+BC, where A, B, and C are combined using AND and OR operations to obtain the output result. The multi-voting device can be analogous to the logical relationship of the three-person voting device, and a similar structure can be used to design a multi-voting device.

[0008] According to the aforementioned multi-person voting device, the number of input units is matched with the number of voting participants, each input unit is equipped with a voltage source for input, and the voting signal is transmitted to the NMOS transistor for calculation through multiple channels to avoid signal interference from the operation of other participants. Attached Figure Description

[0009] Figure 1 This is a truth diagram of the AND-OR operation of the present invention.

[0010] Figure 2 This is a schematic diagram of the array structure of the present invention.

[0011] Figure 3 This is a schematic diagram of the structure of the multi-voting device of the present invention.

[0012] Figure 4 This is a schematic diagram of the simulation results of the present invention. Specific implementation method definition

[0013] To more clearly illustrate the purpose, technical solution, and advantages of this invention, the following detailed description, using schematic diagrams, will provide a comprehensive overview of the specific implementation details. The advantages and features of this invention will be fully demonstrated through the following description and claims. It should be noted that all accompanying drawings are highly simplified and not precisely proportioned; their sole purpose is to aid in understanding the essence of the embodiments of this invention in a visually clear manner. It is hereby stated that the specific embodiments shown herein are merely illustrative of the invention and not intended to limit its scope of application.

[0014] The 1T1M multi-voteer is the core unit structure of the memristor in-memory computing array. Each independent memristor is integrated in series with a MOS field-effect transistor to form a series basic unit of "transistor + memristor". It is an essential structure for large array, high reliability and in-memory computing applications.

[0015] The principle of this multi-person voting machine is based on a three-person voting machine with the logical relationship Y=AB+AC+BC, which is achieved by performing an AND operation on AB, AC, and BC followed by an OR operation.

[0016] The function of this multi-voting device is as follows: each input unit collects the voting operation signal of the corresponding participant, inputs it to the corresponding NMOS transistor, and then the output signal is connected to the memristor array and provides input to the NMOS transistors of the subsequent array, forming a 2*1 branch to realize the logical AND operation of AB; the memristor acts as a switch to control the on and off of the NMOS transistors in each column of the array; after the output of the three 2*1 branches is connected, a 0V (corresponding to logic "0") or 100uV (corresponding to logic "1") output signal is obtained, thus completing the presentation of the voting result.

[0017] Figure 2 This is a schematic diagram of the overall structure of the invention. Figure 3 This is a schematic diagram of the multi-voting device of the invention. The invention will now be described in detail with reference to the embodiments and accompanying drawings.

[0018] like Figure 2 As shown in the diagram, the three-person voting device based on the 1T1M memristor array structure is characterized by the following: the diagram clearly illustrates the specific circuit topology of the three-person voting device according to claim 1, wherein the three voting signals (A, B, C) correspond to three independent signal processing branches, each branch is configured with two series-connected NMOS transistors and a matching 1T1M memristor unit, and each voting signal is input to the input terminals of the two NMOS transistors of its own branch through two independent transmission paths:

[0019] The branch corresponding to voting signal A: Route a is the first transmission path of signal A, through which signal A is input to the input terminal of the first-stage NMOS transistor in branch A; Route b is the second transmission path of signal A, through which signal A is input to the input terminal of the first-stage NMOS transistor in branch B; both NMOS transistors in branch A are configured with independent memristor units, forming a series topology of "first-stage 1T1M unit + second-stage 1T1M unit"; The branch corresponding to voting signal B: Route c is the first transmission path of signal B, through which signal B is input to the input terminal of the second-stage NMOS transistor in branch A; Route d is the second transmission path of signal A. The second transmission path of branch B inputs signal B to the input terminal of the first-stage NMOS transistor in branch C. The two NMOS transistors in branch B are also configured with independent memristor units, and their 1T1M unit series configuration is identical to that of branch A. The branches corresponding to voting signal C are as follows: path e is the first transmission path for signal C, inputting signal C to the input terminal of the second-stage NMOS transistor in branch B; path f is the second transmission path for signal C, inputting signal C to the input terminal of the second-stage NMOS transistor in branch C. The 1T1M unit configuration and series topology of branch C are consistent with branches A and B. The output terminal of the first-stage 1T1M unit is connected to the control terminal of the second-stage 1T1M unit, controlling the conduction state of the second-stage NMOS transistor through the switching characteristics of the memristor. The output terminals of the second-stage 1T1M units of the three branches are connected to the same OUTPUT node, realizing the convergence and output of the logic operation results of each branch. The entire circuit topology strictly follows the Y=AB+AC+BC voting logic described in claim 4.

[0020] like Figure 4 The simulation result diagram, and the corresponding functional simulation result waveform diagram, are characterized in that the diagram is a record of the voltage signal waveform during the operation of the voter.

[0021] Correspondence between curves and target signals: Curve A corresponds to voting signal A as described in claim 1, curve B corresponds to voting signal B, curve C corresponds to voting signal C, and OUTPUT curve corresponds to OUTPUT output signal as described in claim 1.

[0022] Coordinate axis configuration: The horizontal axis is the time axis, covering the working time range from 0ms to 500ms; the vertical axis is the voltage axis, where the voltage fluctuation range of the voting signal is from 0V to 2.0V, and the voltage fluctuation range of the OUTPUT output signal is from 0uV to 500uV.

[0023] Taking the period between 0ms and 50ms as an example, when the voting signals A, B, and C are low, high, and low respectively, corresponding to logic "0", "1", and "0", the OUTPUT output signal is low, corresponding to logic "0", that is, the voting result is disagreement.

[0024] When at least two of the voting signals A, B, and C are at a high level, the OUTPUT output signal is at a high level, corresponding to logic "1".

[0025] When less than two of the voting signals A, B, and C are at a high level, the OUTPUT output signal is at a low level, corresponding to logic "0".

[0026] The five- or more-user voting device based on a 1T1M memristor array structure is characterized in that the implementation of this type of multi-user voting device can completely replicate the structure, signal transmission, and logic operation of the aforementioned three-user voting device:

[0027] Each new voting participant adds a new signal processing branch that is completely identical to the voting signal branches A, B, and C. This branch must contain a multi-stage series structure of "VTEAM memristor module + NMOS transistor", and the connection order of the components must be consistent with the existing branches.

[0028] In the five-person voting scenario, the rule of "output is valid if at least three people agree" is followed. Its logical relationship can replicate the operation logic of three-person voting, corresponding to the sum of all three, four, and five people who agree. The hardware implementation of this logic relies on the replicated 1T1M memristor array, and is completed through the AND operation of each branch and the OR operation of the output terminal.

[0029] In voting machines with five or more users, the output terminals of the second-stage NMOS transistors of all newly added branches must be connected to the OUTPUT output terminal of the original three-user voting machine to ensure that the summarization method of the multi-branch operation results is consistent with the three-user scenario and to ensure the logical validity of the output signal.

[0030] The replication and expansion method of the five-person or more multi-person voting machine is characterized in that the device parameters (such as the resistance threshold of the memristor and the conduction voltage of the NMOS transistor) of the newly added branch must be consistent with the corresponding components of the original three-person voting machine to ensure the uniformity of the signal operation of multiple branches and the accuracy of the logic results.

[0031] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A multi-voting device based on a 1T1M memristor array structure, characterized in that, It integrates an input unit, a memristor array, a voting logic unit, and an output unit corresponding to the number of voters; each voting participant corresponds to an input unit, and the result of multi-person voting is realized through vector operation of the 1T1M memristor array structure, taking a three-person voting device as an example.

2. The multi-voting device according to claim 1, characterized in that, In the memristor array, each input signal corresponds to a voting participant. The voting signal of the array is transmitted through the input signals of each NMOS transistor. Using memristors as switches to control whether the circuit is on or off provides sufficient stability and timeliness. After each input unit inputs the voting operation signal of the corresponding participant into the NMOS transistor, it outputs to the memristor vector to provide data input for the next array of NMOS transistors, forming a 2*1 branch to realize the logical AND operation of AB. The memristors act as switches to control each column of array NMOS transistors, realizing the circuit's cutoff and conduction. Through the output connection of the three 2*1 branches, different amplitude voltages are output, representing logic 0 and 1 respectively, which can display the voting results.

3. The multi-voting device according to claim 1, characterized in that, A multi-voting machine can be compared to a three-voting machine in terms of logical relationship, and a multi-voting machine can be designed using a similar logical relationship.

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