Bandwidth management method and system, device and medium for guaranteeing bandwidth lower limit

Abstract

This application discloses a bandwidth management method, system, device, and medium for ensuring a bandwidth lower limit. The bandwidth management method includes: configuring a corresponding preset bandwidth lower limit and a preset priority for each target COSID according to user requirements; determining the current system operating state based on the actual bandwidth corresponding to all target COSIDs; if the operating state is the first state, determining the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a bandwidth lower limit of 0 based on the actual bandwidth of each target COSID and its corresponding preset bandwidth lower limit; and determining and executing a thread bandwidth intelligent control strategy based on the total bandwidth requirement, the sum of actual bandwidths, and the priority of all target COSIDs with a bandwidth lower limit not equal to 0. This method enables dynamic management of the bandwidth lower limit independent of the bandwidth upper limit, with a fast response speed and highly sensitive control over real-time bandwidth.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a bandwidth management method, system, device, and medium for ensuring a lower bandwidth limit. Background Technology

[0002] Current high-performance processors are typically multi-core, multi-threaded processors, with dozens or even hundreds of threads often working simultaneously. These threads compete for shared resources on the chip, interfering with each other's performance. Furthermore, these threads require different response speeds or execution performances due to the different tasks they perform. Therefore, resource allocation needs to prioritize and ensure the allocation of resources to high-priority threads. This is also known as Quality of Service (QoS). The main management objects of QoS are cache capacity and memory access bandwidth, monitoring and allocating these shared resources.

[0003] A multi-core, multi-threaded chip often contains multiple core groups, each sharing the Last Level cache (LLC). Therefore, this core group also shares the memory access exit points of the LLC. Regarding memory bandwidth allocation, AMD's current approach involves managing the memory bandwidth cap for each LLC separately. Specifically, it limits the upper limit of low-priority bandwidth to ensure the lower limit of high-priority bandwidth, rendering the setting of the lower-priority bandwidth cap ineffective and preventing the simultaneous setting of both upper and lower bandwidth limits. Intel uses a unified bandwidth management mechanism, which can adjust both upper and lower bandwidth limits, but this is done through a combination of hardware and software at the L2 cache level, resulting in a longer overall response time. Summary of the Invention

[0004] In view of this, the present disclosure provides a bandwidth management method, system, device, and medium for ensuring the lower limit of bandwidth, which can solve the problems of existing solutions being unable to simultaneously take into account real-time performance and control accuracy.

[0005] In a first aspect, embodiments of this disclosure provide a bandwidth management method for ensuring a lower bandwidth limit, including: According to user requirements, configure corresponding bandwidth lower limit association information for each target COSID. The bandwidth lower limit association information includes a preset bandwidth lower limit and a preset priority of the bandwidth lower limit. The current operating status of the system is determined based on the actual bandwidth corresponding to all the target COSIDs. If the operating state is the first state, the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit are determined based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit. Based on the total bandwidth requirement, the actual bandwidth, and the preset priority of all target COSIDs whose preset bandwidth lower limit is not 0, a dynamic thread bandwidth control strategy is determined and executed.

[0006] Secondly, this disclosure also provides a bandwidth management system for ensuring a lower bandwidth limit, including a Core-Cluster, local memory, and a software configuration unit, wherein the Core-Cluster includes one or more processor cores and a cache layer; The cache hierarchy includes multiple cache levels and a QoS bandwidth allocation circuit, which is at the same level as the last cache level. The QoS bandwidth allocation circuit includes a QoS bandwidth master controller, a bandwidth upper limit management circuit, and a bandwidth lower limit management circuit. The bandwidth upper limit management circuit is used to manage the bandwidth upper limit of each target COSID, and the bandwidth lower limit management circuit operates independently of the bandwidth upper limit management circuit. The QoS bandwidth controller is used to obtain the configured preset bandwidth lower limit and the preset priority of the bandwidth lower limit; The bandwidth lower limit management circuit is used to determine the current system operating state based on the actual bandwidth corresponding to all target COSIDs. If the operating state is the first state, the circuit determines the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit of 0 based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit in the QoS bandwidth controller. Based on the total bandwidth requirement, the sum of the actual bandwidths, and the preset priority of all target COSIDs with a preset bandwidth lower limit of 0 in the QoS bandwidth controller, the circuit determines and executes a dynamic thread bandwidth control strategy.

[0007] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform any of the bandwidth management methods described above for ensuring a lower bandwidth limit.

[0008] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions; the computer instructions are used to cause a computer to execute any of the bandwidth management methods described above for ensuring a lower bandwidth limit.

[0009] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0010] The bandwidth management method disclosed in this application for ensuring a bandwidth floor includes: configuring corresponding bandwidth floor association information for each target COSID according to user needs, the bandwidth floor association information including a preset bandwidth floor and a preset priority of the bandwidth floor; determining the current system operating status based on the actual bandwidth corresponding to all target COSIDs; if the operating status is the first state (i.e., busy), determining the total bandwidth demand of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth floor of 0 based on the actual bandwidth of each target COSID and the corresponding preset bandwidth floor; determining and executing a dynamic thread bandwidth control strategy based on the total bandwidth demand, the sum of actual bandwidths, and the preset priority of all target COSIDs with a preset bandwidth floor of non-zero. This method can dynamically analyze the real-time total demand, actual usage, and priority when the system is busy. Unlike simple fixed-ratio allocation or strict priority queues, it can satisfy all services with a bandwidth floor while allocating the remaining bandwidth to other services fairly or on demand. It can simultaneously consider multiple objectives such as ensuring a baseline, respecting priorities, and alleviating congestion, thus ensuring both real-time performance and control accuracy, and achieving optimal resource utilization.

[0011] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating a bandwidth management method for ensuring a lower bandwidth limit, provided in an embodiment of this disclosure.

[0014] Figure 2 This is a flowchart illustrating a method for determining the current operating state of a system as provided in an embodiment of this disclosure.

[0015] Figure 3This is a flowchart illustrating the method for obtaining the dynamic control strategy for thread bandwidth provided in this embodiment of the disclosure.

[0016] Figure 4 This is a flowchart illustrating a method for determining and executing a thread bandwidth dynamic control strategy as the first control strategy, as provided in an embodiment of this disclosure.

[0017] Figure 5 This is a schematic diagram illustrating regulation via a throttling controller, provided as an embodiment of this disclosure.

[0018] Figure 6 This is a schematic diagram illustrating regulation via a first throttling controller, provided as an embodiment of this disclosure.

[0019] Figure 7 This is a flowchart illustrating the method for determining and executing a second dynamic control strategy for thread bandwidth according to an embodiment of the present disclosure.

[0020] Figure 8 This is a schematic diagram illustrating the process of intelligently adjusting the bandwidth of a COSID whose preset bandwidth lower limit is not 0 from low to high, as provided in this embodiment of the disclosure.

[0021] Figure 9 This is a schematic diagram illustrating regulation via a second throttling controller, provided as an embodiment of this disclosure.

[0022] Figure 10 This is a schematic diagram of the framework of a bandwidth management system for ensuring a lower bandwidth limit, provided in an embodiment of this disclosure.

[0023] Figure 11 for Figure 10 A schematic diagram of the bandwidth lower limit management circuit.

[0024] Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0026] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0028] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0030] In this application, a multi-core, multi-threaded chip often contains multiple groups of cores, each group of cores sharing the LastLevel cache (LLC, often L3 cache). Therefore, this group of cores also shares the LLC's memory access exit. In some implementations, this group of shared resources is also called the Quality of Service Domain. QoS aims to provide two functions: 1) to monitor certain shared resources within the QoS domain; 2) to allocate certain shared resources within the QoS domain, usually referring to the monitoring and allocation of LLC cache and LLC external bandwidth. QoS defines the COSID to assign a service level to the processor, which is used to control the allocation of shared resources.

[0031] Each COSID corresponds to a set of resource control policies, limiting the total amount and range of resources that the current thread can use. For LLC cache, the COSID can specify the number of cache ways that the thread can use; for memory access bandwidth, the COSID can specify the bandwidth range that the thread can use. The method disclosed in this application allocates bandwidth to threads based on COSID, ensuring precise control over the lower limit of bandwidth while maintaining the upper limit functionality.

[0032] Reference Figure 1 This application discloses a thread bandwidth management method for ensuring a lower bandwidth limit, comprising: S100 configures corresponding bandwidth lower limit association information for each target COSID according to user needs.

[0033] The bandwidth lower limit information includes the preset bandwidth lower limit and the preset priority of the bandwidth lower limit. The preset priority of the bandwidth lower limit is the priority of the corresponding COSID.

[0034] It should be noted that the target COSID is configured by the software, and one or more threads in the system are configured with one target COSID. Each target COSID corresponds to a set of bandwidth attribute information. Each set of bandwidth attribute information includes a preset bandwidth upper limit, a preset bandwidth lower limit, and a preset priority of the bandwidth lower limit. The preset bandwidth upper limit is already in the system, while the preset bandwidth lower limit and the preset priority of the bandwidth lower limit are additionally configured by the user according to actual needs. Moreover, the bandwidth lower limit association information is configured independently of the bandwidth upper limit, thereby easily achieving diverse Quality of Service (QoS) goals and adapting to different needs from critical real-time services to background elastic tasks.

[0035] S200 determines the current operating status of the system based on the actual bandwidth corresponding to all target COSIDs.

[0036] S300, if the running state is the first state (i.e. busy state), determine the total bandwidth requirement of the current system and the actual bandwidth of all target COSIDs with a preset bandwidth lower limit based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit.

[0037] S400 determines and executes a dynamic bandwidth control strategy for threads based on the total bandwidth requirement, the actual bandwidth, and the preset priority of all target COSIDs whose preset bandwidth lower limit is not 0.

[0038] If the running state is the second state (i.e., the current system bandwidth is idle), remove the restrictions on all target COSIDs. Specifically, it is preferable to set the Throttle value of the corresponding COSID to 0. In this state, all restrictions are removed, allowing any thread to make full use of the idle bandwidth. This can effectively solve the problem of resource idleness caused by long-term bandwidth reservation to ensure peak demand in the traditional static reservation scheme, and realize the ideal state of full sharing when idle and guaranteed when congested.

[0039] In this application, the determination of the operating status (idle / busy) is based on the sum of the actual bandwidth of all COSIDs, enabling the system to quickly identify the critical point that requires intervention. It is simple, accurate, and efficient. The non-intervention strategy in the idle state directly avoids all control overhead, allowing the system to handle the business load at full capacity.

[0040] For S100, this specifically includes: obtaining all target threads in the system; configuring (i.e. binding) a target COSID for one or more target threads, and configuring bandwidth attribute information for the target COSID. Multiple threads can be bound to the same COSID and share the resource quota under that label. By binding threads to target COSIDs, the hardware can know the management policies corresponding to the resource requests of these threads, which directly affect the shared resources on the QoS domain at the core cluster level.

[0041] In this context, configuring a target COSID for one or more target threads means that if multiple threads have the same COSID and run within the same cluster, they will share the entire resource quota corresponding to that COSID. Threads bound to different COSIDs will have their resource usage subject to their own independent quota limits, thus achieving isolation. In this embodiment, for each process / thread, the operating system maintains a data structure that records the mapping relationship between each process / thread and a COSID. When a thread of a process is scheduled to execute on a CPU core, the operating system writes the COSID corresponding to this thread into a specific model register of that CPU core during the context switch loading phase. From then on, until the next scheduling occurs, all cache access requests and memory access requests generated by this hardware thread (i.e., the physical pipeline executing on that core) will automatically carry this COSID tag.

[0042] Furthermore, both the upper and lower limits are set as absolute values, with increments of 1 / 8 GB / s or 1 GB / s. The bandwidth management circuit limits the bandwidth of these threads corresponding to each target COSID to the preset upper and lower limits based on the configured information, prioritizing the lower limit of the bandwidth for higher priority COSIDs.

[0043] Reference Figure 2 The method for S200, which "determines the current system operating status based on the actual bandwidth corresponding to all target COSIDs," specifically includes the following methods for determining the current system operating status: S210, obtain the actual bandwidth of all target COSIDs.

[0044] S220 determines the system bandwidth quota based on the system's maximum bandwidth capacity.

[0045] Wherein, the system bandwidth quota = system maximum bandwidth capacity × bandwidth adjustment coefficient. In this embodiment, the bandwidth adjustment coefficient can be flexibly set according to the actual needs of the system, all of which are within the protection scope of this application.

[0046] Specifically, the bandwidth adjustment coefficient can be flexibly set by the programmer to determine the busy state of the system's bandwidth resources. The larger the coefficient, the higher the busy threshold of the system's bandwidth resources, and the later the bandwidth lower limit management algorithm intervenes, which is more conducive to ensuring the overall bandwidth utilization rate of the system. The smaller the coefficient, the lower the busy threshold of the system's bandwidth resources, and the earlier the bandwidth lower limit management algorithm intervenes, which is more conducive to ensuring the bandwidth lower limit of high-priority COSIDs, but will reduce the overall bandwidth utilization rate of the system to some extent.

[0047] S230 determines the current system's bandwidth overrun information based on the actual bandwidth and the system bandwidth quota.

[0048] Bandwidth overage information : ,in, The actual bandwidth for all target COSIDs. For the first The actual bandwidth of each target COSID This is for system bandwidth quotas.

[0049] S240 determines the current operating status of the system based on bandwidth excess information.

[0050] If the bandwidth excess information is less than 0, that is < If the system bandwidth resources are available, the restriction on all COSIDs will be lifted.

[0051] If the bandwidth excess information is not less than 0, that is ≥ This indicates that the system bandwidth is strained, and further analysis is needed.

[0052] For S300, if the operating state is in the first state, it means that the current system bandwidth is busy. The method for determining the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit, based on the actual bandwidth of each target COSID and its corresponding preset bandwidth lower limit, specifically includes: S310 obtains the guarantee gap for each target COSID based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit.

[0053] Among them, the The protection gap for each target COSID is , For the first A preset bandwidth lower limit for each target COSID. In this embodiment, the bandwidth lower limit is obtained. The maximum value of 0 is used to determine whether each target COSID has received a sufficient quota.

[0054] S320 determines the total bandwidth requirement based on all guarantee gaps.

[0055] Total bandwidth requirement is : .

[0056] S330: Determine all target COSIDs with a preset bandwidth lower limit of 0, denoted as non-critical COSIDs, and obtain the actual bandwidth of all non-critical COSIDs.

[0057] The actual bandwidth of all non-critical COSIDs is : In this embodiment, all COSIDs with a preset bandwidth lower limit Li of 0 are observed. These COSIDs do not require a minimum bandwidth guarantee, and their bandwidth can be reduced first.

[0058] The steps for obtaining the actual bandwidth and the steps for obtaining the total bandwidth requirement are not sequential and are both within the scope of protection of this application.

[0059] In this application, the input to the control strategy includes the actual bandwidth and preset lower limit for each COSID. This allows decisions to closely follow real-time demand changes, rather than being based on a rough allocation of fixed proportions or absolute values. Under busy conditions, by ensuring bandwidth requirements for services with non-zero lower limits and intelligently allocating remaining bandwidth based on priority, resources are ensured to flow to the most needed services, achieving efficient utilization with a guaranteed minimum and no waste.

[0060] In this application, a preset bandwidth minimum of 0 means that the system does not guarantee to provide any minimum resources for this type of service. The resources it obtains depend entirely on the current availability of resources and scheduling policies of the system. This type of COSID is usually a lowest priority or best-effort service.

[0061] Reference Figure 3 The method for S400 to "determine the dynamic control strategy for thread bandwidth based on the total bandwidth requirement, the actual bandwidth, and the priority of all target COSIDs whose preset bandwidth lower limit is not zero" specifically includes the following methods for obtaining the dynamic control strategy for thread bandwidth: S410, if the total bandwidth requirement Not greater than the actual bandwidth of all non-critical COSIDs and (R0≥needall), determine the thread bandwidth dynamic control strategy as the first control strategy and execute it.

[0062] In this step, if R0≥needall, it means that this part of the bandwidth can meet the lower limit of the overall system bandwidth requirement. Then, by suppressing this part of the bandwidth, the released bandwidth can be allocated to COSIDs that cannot meet the lower limit of the bandwidth.

[0063] S420, if the total bandwidth requirement Greater than the actual bandwidth of all non-critical COSIDs and The thread bandwidth dynamic control strategy is determined as the second control strategy and executed.

[0064] This step explains that even after suppressing this portion of bandwidth, it is still impossible to meet the overall system bandwidth minimum requirement.

[0065] Reference Figure 4For S410 (i.e., for the intelligent control case where R0 ≥ needall), the method for determining and executing the thread bandwidth dynamic control strategy as the first control strategy specifically includes: A100, based on total bandwidth requirements And the actual bandwidth of all non-critical COSIDs and This determines the first bandwidth gap in the current system.

[0066] In this embodiment, the determined first bandwidth gap is the first target bandwidth of the first throttling controller.

[0067] The first target bandwidth is Target: Target = R0 - needall.

[0068] A200 intelligently adjusts the actual bandwidth of all non-critical COSIDs based on the first bandwidth gap.

[0069] Reference Figure 5 and Figure 6 Specifically, the actual bandwidth of all non-critical COSIDs is adjusted to the first target bandwidth. Further, based on the PID algorithm, the sum of the actual bandwidths R0 of COSIDs with a preset lower limit of 0 is adjusted to the value corresponding to the first target bandwidth of the first throttling controller (i.e., throttle_controller0). The output bandwidth limit level Throttle_level_0 is used to throttle all COSIDs with a lower limit of 0. In this embodiment, the bandwidth allocation of a set of specific services is dynamically adjusted through the PID control algorithm to ensure that the actual total bandwidth R0 accurately tracks the first target bandwidth value.

[0070] Specifically, the PID algorithm includes: Where e(k) represents the error between the current input and the control target, and u(k) is the calculated throttle intensity; the proportion in the PID algorithm during the early modeling and optimization stage ( ),integral( Ki ),differential( Kd These three parameters are used to calculate the corresponding throttle value within a suitable sampling period in bandwidth lower limit management, gradually adjusting the input to the target value.

[0071] In this embodiment, the most stringent restrictions are uniformly applied to tasks without resource guarantees (i.e., the preset bandwidth lower limit is not 0), ensuring that when resource contention occurs, the performance of these tasks is sacrificed first, thereby protecting those tasks with minimum resource guarantees; all unguaranteed requests are classified into one category and managed with the same set of the most stringent rules, which is simple in logic and highly efficient in hardware implementation.

[0072] Reference Figure 7, for S420 (i.e., for the intelligent regulation scenario where R0 < needall), that is, the method for determining and executing the thread bandwidth dynamic regulation strategy as the second regulation strategy specifically includes: B100, according to the total bandwidth demand and the sum of the actual bandwidths of all non-critical COSIDs , determine the second bandwidth gap of the current system.

[0073] In this embodiment, the determined second bandwidth gap is the second target bandwidth of the second throttle controller.

[0074] The second bandwidth gap is Need_Pri_total: .

[0075] B200, according to the priority order and the second target bandwidth, intelligently regulate the bandwidths of COSIDs with a non-zero preset bandwidth lower limit from low to high.

[0076] Refer to Figure 8 , for the method of "intelligently regulating the bandwidths of COSIDs with a non-zero preset bandwidth lower limit from low to high" in B200, specifically includes: B210, determine the COSID with the lowest priority from all COSIDs with a non-zero lower limit, denoted as the to-be-processed COSID; B220, according to the actual bandwidth of the to-be-processed COSID and its corresponding preset bandwidth lower limit, obtain the required bandwidth of the to-be-processed COSID.

[0077] In this embodiment, the required bandwidth of the to-be-processed COSID is Need_Pri_j: Need_Pri_j = max(Lj - Rj, 0); where Lj is the preset bandwidth lower limit corresponding to the COSID with the lowest priority among COSIDs with a non-zero lower limit, and Rj is the actual bandwidth of the corresponding COSID.

[0078] B230, if the second bandwidth gap is greater than the required bandwidth of the to-be-processed COSID, obtain the updated bandwidth gap according to the second bandwidth gap and the required bandwidth of the to-be-processed COSID.

[0079] Among them, the updated bandwidth gap is T0: T0 = Need_Pri_total - Need_Pri_j. In this step, the demand of the COSID with the lowest priority among COSIDs with a non-zero lower limit is preferentially squeezed.

[0080] B240, if the updated bandwidth gap is not greater than the actual bandwidth of the to-be-processed COSID, intelligently regulate the actual bandwidth of the to-be-processed COSID according to the updated bandwidth gap.

[0081] In this step, if the updated bandwidth gap is not greater than the actual bandwidth of the COSID to be processed, it means that this part of the bandwidth can meet the overall bandwidth lower limit requirement of the system. Then, by completely suppressing this part of the bandwidth (i.e., the bandwidth of the lowest priority COSID among the COSIDs with a lower limit not equal to 0), the released bandwidth can be allocated to the COSIDs that cannot meet the bandwidth lower limit.

[0082] Specifically, the actual bandwidth of the COSID to be processed is intelligently adjusted according to the updated bandwidth gap, that is, the actual bandwidth of the COSID to be processed is adjusted to the value corresponding to the updated bandwidth gap; further, the actual bandwidth of the COSID to be processed is adjusted to the value corresponding to the updated bandwidth gap based on the PID algorithm.

[0083] B250: If the updated bandwidth gap is greater than the actual bandwidth of the COSID to be processed, the actual bandwidth of the COSID to be processed will be intelligently adjusted according to the updated bandwidth gap.

[0084] Specifically, based on priority ranking from low to high, the next preset bandwidth lower limit for the COSIDs to be processed is not 0. Analysis of their required bandwidth is then performed until a COSID with the corresponding priority that meets the updated bandwidth gap is determined, and the bandwidth of the corresponding COSID is dynamically adjusted. In this step, it is noted that deducting the corresponding required bandwidth is insufficient, and therefore, the corresponding actual bandwidth needs to be squeezed.

[0085] In this step, when the actual bandwidth corresponding to a COSID with a preset bandwidth lower limit of non-zero at the lowest priority does not meet the system bandwidth requirements, the next COSID is obtained from low to high priority as a pending COSID, and the process returns to execute B220 above until the condition is met, that is, until the updated bandwidth gap is not greater than the actual bandwidth of the pending COSID at the corresponding level. This indicates that the bandwidth can meet the overall bandwidth lower limit requirement of the system. Then, the bandwidth can be completely suppressed, and the released bandwidth can be allocated to the COSID that cannot meet the bandwidth lower limit. Alternatively, the next COSID can be obtained from low to high priority as a pending COSID and analyzed until the COSID with the corresponding priority that meets the condition is found, so that its bandwidth can be dynamically adjusted.

[0086] In this embodiment, when the next COSID to be processed has the highest priority, bandwidth intervention and control will not be performed. That is, if there are 16 levels in the system after sorting by priority, and after analyzing the 15th COSID to be processed, it is found that its bandwidth still does not meet the conditions, then bandwidth control will not be intervened because the next COSID to be processed has the highest priority.

[0087] Simultaneously refer to Figure 5 and Figure 9, for S520, that is, for the intelligent regulation situation where R0 < needall, it enters throttle_controller1 (i.e., the second throttle controller), and gives the corresponding throttle_level_1 to each COSID according to the priority order. The total_controller selects the throttle_level corresponding to the COSID according to the relationship between R0 and needall, and converts it into the throttle_level for each thread according to the mapping relationship between the thread and the COSID, and backpressures the sending rate of the thread to control the external memory access bandwidth of the LLC.

[0088] Specifically, in this embodiment, Pri 15 is the lowest priority. 1) If the actual bandwidth of Pri 15 does not reach the bandwidth lower limit, the demand U-Ri of Pri15 is preferentially squeezed; 2) If subtracting 1 is still not enough (i.e., not enough after subtracting the demand of Pri 15), start squeezing the actual bandwidth Ri of Pri15; 3) If subtracting 2 is still not enough, the throttle of Pri 15 is set to 4, and start squeezing the demand U-Ri of Pri14; 4) If subtracting 3 is still not enough, start squeezing the actual bandwidth Ri of Pri 14... until the COSID corresponding to the corresponding priority that meets the condition is found to perform dynamic regulation of its bandwidth; or when the priority of the next COSID to be processed is the highest, no bandwidth intervention regulation is performed.

[0089] In this embodiment, for the opposite condition of B230, that is, if the second bandwidth gap is not greater than the required bandwidth of the COSID to be processed (i.e., Need_Pri_total ≤ Need_Pri_j), no bandwidth regulation is intervened because the next resources will be allocated to high-priority threads first instead of the lowest-priority ones.

[0090] Furthermore, the bandwidth management method for ensuring the bandwidth lower limit disclosed in this application further includes: when the actual bandwidth of a certain COSID exceeds the preset bandwidth upper limit, start the corresponding bandwidth upper limit management module to limit the bandwidth of the corresponding COSID. According to different settings of the thread, the upper limit bandwidth of low-priority threads is suppressed by an independent device, which does not conflict with the bandwidth upper limit management of itself, so as to realize the simultaneous management of the upper and lower limits of a thread and provide a better interface for the management of memory access resources.

[0091] The bandwidth management method disclosed in this application for ensuring a minimum bandwidth limit can perform dynamic analysis based on real-time total demand, actual usage, and priority when the system is busy. Unlike simple fixed-ratio allocation or strict priority queues, it can satisfy all services with minimum demand while allocating the remaining bandwidth to other services fairly or on demand as much as possible. It can simultaneously take into account multiple objectives such as ensuring the minimum bandwidth limit, respecting priority, and alleviating congestion, thereby achieving optimal resource utilization.

[0092] The thread bandwidth management method disclosed in this application for ensuring a lower bandwidth limit is a method for dynamically allocating bandwidth to threads based on COSID. It can flexibly and dynamically adjust the bandwidth quota according to the actual importance, stage and needs of the application. Bandwidth management is not a simple performance monitoring, but a proactive resource control. Through the collaboration of hardware and software, it transforms the valuable and competitive shared resource of memory bandwidth into a programmable, isolated, guaranteed and predictable modern infrastructure. Under complex and dynamic modern computing loads, it turns system performance from a matter of luck into a matter of engineering, and achieves lower bandwidth limit management independent of the upper bandwidth limit.

[0093] Furthermore, by setting a preset bandwidth lower limit, low-priority but necessary background tasks (such as system updates and monitoring reports) are fundamentally prevented from being completely starved during competition. By setting a preset bandwidth upper limit and overall control under busy conditions, it is possible to prevent any service or type of service (especially services with a lower limit of 0) from consuming bandwidth without limit and affecting other services, thereby maintaining the overall stability and fairness of the system. When bandwidth cannot meet all lower limit requirements, it is allocated according to preset priorities. This is a controllable and orderly degradation strategy that ensures that the most important services are affected last, avoiding the chaotic situation of random degradation of all services during congestion.

[0094] In this application, administrators can flexibly configure the policy triple (upper limit, lower limit, priority) for different services (threads) to easily achieve diverse business objectives. For example, a high lower limit and high priority can be set for critical services, a low lower limit and medium priority for ordinary services, and a zero lower limit and low priority for elastic services. This method is suitable for complex scenarios with limited bandwidth resources and diverse needs, such as cloud computing, multi-tenant networks, edge computing, and home gateways, and can effectively balance the competitive relationship between different users and applications. The method disclosed in this application upgrades bandwidth management from a simple one-size-fits-all restriction to intelligent resource allocation that is state-aware, ensures bottom-line protection, is priority-driven, and dynamically optimized. It achieves an excellent balance between security (ensuring critical services do not fail), efficiency (improving resource utilization), fairness (preventing malicious preemption), and intelligence (reducing manual intervention), resulting in higher network resource utilization, more stable critical service experience, and more flexible and efficient system management.

[0095] Furthermore, the application can also flexibly adjust the protection level of the lower limit for high-priority COSIDs by adjusting the system idle state judgment ratio and the ratio of management cycle to sampling cycle.

[0096] There is a fundamental contradiction in existing technologies for processor QoS resource management: AMD's current mechanism essentially sets only a "budget" or "rate cap" for each type of thread (or LLC). By limiting the cap of low-priority threads, it passively and indirectly frees up resources for high-priority threads, thus ensuring their lower limit. While simple, with low hardware overhead and fast response, this comes at the cost of coarse control granularity, failing to achieve precise QoS control with independent guarantees and limit ranges for each thread. The guarantee of high priority is based on the suppression of low priority, rather than a commitment made by the system through active allocation. While Intel's solution offers precise control (with settable upper and lower limits), its mechanism resides in the L2 cache and relies on hardware and software collaboration. It elevates a control loop requiring rapid response from a simple hardware circuit to a software program executed by a general-purpose processor. This process introduces significant overhead such as interrupt latency, context switching, and serial execution of software instructions. In dynamic load scenarios requiring real-time response, this latency can cause the system to take a considerable amount of time to react and correct problems after they occur.

[0097] The thread bandwidth management method disclosed in this application for ensuring a lower bandwidth limit executes complex control strategies only when the system enters a busy state. The core calculations of the control strategy only involve summing the actual bandwidth, comparing it with a preset lower limit, and prioritizing. These operations have low computational complexity and can be efficiently completed in the operating system kernel or driver without relying on specific hardware cooperation mechanisms, thus avoiding latency and context switching overhead caused by hardware-software interaction. This method does not rely on real-time monitoring of every memory access or cache behavior, but makes decisions based on bandwidth aggregation data over a period of time (e.g., milliseconds). Although this macro-control sacrifices nanosecond-level instantaneous accuracy, it gains lower system overhead and more feasible real-time response. This application achieves a clever balance between real-time performance and control precision through state-driven hierarchical control and the principles of ensuring a bottom line and on-demand allocation. Although the control strategy in the busy state involves multiple parameters, it is essentially an arithmetic operation and logical comparison, which can be completed in a very short time on modern processors, meeting millisecond-level or even sub-millisecond-level response requirements. By setting a bandwidth lower limit for each thread and using it as a hard constraint in the calculations during the busy state, the core manifestation of control precision is ensured that critical business operations always obtain the precise minimum bandwidth. When the total bandwidth cannot meet all the lower limits, it is allocated according to the preset priority; when the bandwidth is surplus, the remaining bandwidth can be dynamically allocated according to actual needs and priorities. This policy-based allocation achieves accurate mapping of business intent.

[0098] Reference Figure 10 Secondly, this application discloses a bandwidth management system for ensuring a lower bandwidth limit, used to execute the bandwidth management method for ensuring a lower bandwidth limit disclosed in the first aspect of this application. The system includes a Core-Cluster, Main Memory, and a software configuration unit (Bandwidth Target). The Core-Cluster includes one or more processor cores and a cache layer.

[0099] The cache hierarchy contains multiple cache levels and a QoS bandwidth allocation circuit, which is at the same level as the last cache level. The QoS bandwidth allocation circuit is used to manage the access bandwidth between the LLC in the Core-Cluster hierarchy and local memory.

[0100] The QoS bandwidth allocation circuit includes a QoS bandwidth master controller, a bandwidth upper limit management circuit, and a bandwidth lower limit management circuit. The bandwidth upper limit management circuit manages the bandwidth upper limit for each target COSID, and the bandwidth lower limit management circuit operates independently of the bandwidth upper limit management circuit. The bandwidth lower limit management circuit configures a corresponding preset bandwidth lower limit and a preset priority for each target COSID according to user requirements.

[0101] In this application, the bandwidth limit management circuit sets a separate upper limit for each COSID. When the bandwidth of a COSID exceeds the set upper limit, the bandwidth limit management circuit will be activated to limit the bandwidth of that COSID. Therefore, the number of bandwidth limit management circuits is the same as the number of target COSIDs. In this application, the bandwidth lower limit management circuit needs to be managed in a coordinated manner based on the real-time bandwidth of all COSIDs, so there is only one copy. Finally, the throttle value returned to the Core is jointly determined by the upper and lower limit management circuits.

[0102] The bandwidth lower limit management circuit is used to determine the current system operating status based on the actual bandwidth corresponding to all target COSIDs. If the operating status is the first state, the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit of 0 are determined based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit in the bandwidth lower limit management circuit. Based on the total bandwidth requirement, the sum of actual bandwidths, and the preset priority of all target COSIDs with a preset bandwidth lower limit of non-zero in the bandwidth lower limit management circuit, the dynamic control strategy for thread bandwidth is determined and executed.

[0103] specifically refer to Figure 5 and Figure 11 The bandwidth lower limit management circuit includes an analysis unit, a first execution unit, and a second execution unit. The analysis unit is used to determine the current system operating status based on the actual bandwidth corresponding to all target COSIDs obtained. When the operating status is the first state (i.e., busy state), the first execution unit is triggered. When the operating status is the second state, the second execution unit is triggered.

[0104] Furthermore, the analysis unit includes an actual bandwidth acquisition unit, a system bandwidth quota acquisition unit, a bandwidth over-limit information acquisition unit, and an operating status determination unit. The actual bandwidth acquisition unit is used to acquire the actual bandwidth of all target COSIDs and obtain the sum of all actual bandwidths; the system bandwidth quota acquisition unit is used to determine the system bandwidth quota based on the system's maximum bandwidth capacity; the bandwidth over-limit information acquisition unit is used to determine the current system's bandwidth over-limit information based on the actual bandwidth sum and the system bandwidth quota; and the operating status determination unit is used to determine the current system's operating status based on the bandwidth over-limit information.

[0105] The first execution unit is used to remove restrictions on all target COSIDs. Specifically, it is preferable to set the Throttle value of the corresponding COSID to 0. In this state, all restrictions are removed, allowing any thread to make full use of the idle bandwidth. This can effectively solve the problem of resource idleness caused by long-term bandwidth reservation to ensure peak demand in the traditional static reservation scheme, and achieve the ideal state of full sharing when idle and guaranteed when congested.

[0106] The second execution unit is used to determine the total bandwidth requirement of the current system and the actual bandwidth of all target COSIDs with a preset bandwidth lower limit, based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit.

[0107] Specifically, the second execution unit includes a guarantee gap acquisition unit, a total bandwidth demand acquisition unit, a non-critical COSID actual bandwidth acquisition unit, a judgment unit, a first control unit, and a second control unit. The guarantee gap acquisition unit is used to acquire the guarantee gap for each target COSID based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit. The total bandwidth demand acquisition unit is used to determine the total bandwidth demand based on all guarantee gaps. The non-critical COSID actual bandwidth acquisition unit is used to determine all target COSIDs with a preset bandwidth lower limit of 0, denoted as non-critical COSIDs, and acquire the sum of the actual bandwidths of all non-critical COSIDs. The judgment unit is used to judge the size of the total bandwidth demand and the sum of the actual bandwidths of all non-critical COSIDs. If the total bandwidth demand is not greater than the sum of the actual bandwidths of all non-critical COSIDs, the first control unit is triggered; otherwise, the second control unit is triggered.

[0108] The first control unit is used to determine the first bandwidth gap of the current system based on the total bandwidth demand and the actual bandwidth of all non-critical COSIDs, and intelligently control the actual bandwidth of all non-critical COSIDs to the first bandwidth gap. Specifically, the first throttling controller can give the same throttle level 0 to all COSIDs with a lower limit of 0 (i.e., non-critical COSIDs) (i.e., strictly control them to avoid them consuming too many resources), so that the R0 part (i.e., the actual bandwidth of all non-critical COSIDs) can give up some bandwidth for COSIDs that do not meet the lower limit (i.e., COSIDs whose lower limit is not 0 and do not meet the lower limit).

[0109] The second control unit is used to determine the second bandwidth gap of the current system based on the total bandwidth requirement and the actual bandwidth of all non-critical COSIDs. It then intelligently controls the bandwidth of COSIDs with a preset lower bandwidth limit not equal to 0, from low to high, according to priority and the second target bandwidth. Specifically, the second throttling controller can assign a corresponding throttle_level_1 to each COSID according to priority. The total_controller selects the throttle_level corresponding to the COSID based on the relationship between R0 and needall, and converts it into a throttle_level for each thread based on the mapping relationship between threads and COSIDs, thus controlling the sending rate of the threads and achieving control over the LLC external memory access bandwidth.

[0110] In this embodiment, the intelligent Throttle controller can stabilize the bandwidth utilization near the target value through smooth, closed-loop adjustment, thereby greatly reducing tail latency and making the system response time more deterministic and predictable.

[0111] In this application, the QoS bandwidth allocation circuitry is implemented at the same level as the LLC cache within the Core-Cluster hierarchy. This means the hardware is implemented at the same physical / logical level, not integrated within each core (such as the L1 / L2 cache level) or located at the global bus level of the entire chip. Instead, it serves the entire core cluster, just like the LLC. Placing bandwidth management at the same level as the LLC allows for more efficient coordination between cache access and memory access, reducing resource contention. The bandwidth management function is implemented at the core cluster level, with its hardware circuitry at the same level as the LLC cache, jointly serving all cores within the cluster to achieve efficient resource coordination and control.

[0112] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0113] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the bandwidth management method for ensuring a lower bandwidth limit as described in the foregoing embodiments of this disclosure.

[0114] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0115] like Figure 12 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 12 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0116] like Figure 12 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0117] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 12 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0118] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the bandwidth management method for ensuring a lower bandwidth limit according to embodiments of this disclosure are performed.

[0119] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0120] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When these non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the bandwidth management methods for ensuring a lower bandwidth limit as described in the foregoing embodiments of the present disclosure are performed.

[0121] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0122] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0123] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0124] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0125] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0126] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0127] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0128] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0129] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A bandwidth management method for ensuring a lower bandwidth limit, characterized in that, include: Configure corresponding bandwidth lower limit association information for each target COSID according to user requirements. The bandwidth lower limit association information includes a preset bandwidth lower limit and a preset priority of the bandwidth lower limit. Determine the current system operating status based on the actual bandwidth corresponding to all the target COSIDs. If the operating state is the first state, the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit are determined based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit. Based on the total bandwidth requirement, the actual bandwidth, and the preset priority of all target COSIDs whose preset bandwidth lower limit is not 0, a dynamic thread bandwidth control strategy is determined and executed.

2. The bandwidth management method for ensuring a lower bandwidth limit according to claim 1, characterized in that, The step of determining the current system operating status based on the actual bandwidth corresponding to all the target COSIDs includes: Obtain the actual bandwidth for all the target COSIDs: Determine the system bandwidth quota based on the system's maximum bandwidth capacity: Based on the actual bandwidth and the system bandwidth quota, determine the current system's bandwidth over-limit information; The current operating status of the system is determined based on the bandwidth excess information.

3. The bandwidth management method for ensuring a lower bandwidth limit according to claim 2, characterized in that, If the operating state is the first state, the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit are determined based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit, including: Based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit, obtain the guarantee gap for each target COSID; Determine the total bandwidth requirement based on all the aforementioned security gaps; Identify all target COSIDs with a preset bandwidth lower limit of 0, denoted as non-critical COSIDs, and obtain the actual bandwidth of all non-critical COSIDs.

4. The bandwidth management method for ensuring a lower bandwidth limit according to claim 3, characterized in that, The step of determining and executing a dynamic thread bandwidth control strategy based on the total bandwidth requirement, the actual bandwidth, and the priority of all target COSIDs with a preset bandwidth lower limit not equal to 0 includes: If the total bandwidth requirement is not greater than the sum of the actual bandwidths of all the non-critical COSIDs, the thread bandwidth dynamic control strategy is determined as the first control strategy and executed. If the total bandwidth requirement is greater than the sum of the actual bandwidths of all the non-critical COSIDs, the thread bandwidth dynamic control strategy is determined as the second control strategy and executed.

5. The bandwidth management method for ensuring a lower bandwidth limit according to claim 4, characterized in that, The determination and execution of the thread bandwidth dynamic control strategy as the first control strategy includes: Based on the total bandwidth requirement and the actual bandwidth of all non-critical COSIDs, determine the first bandwidth gap of the current system. Based on the first bandwidth gap, the actual bandwidth of all non-critical COSIDs is intelligently adjusted.

6. The bandwidth management method for ensuring a lower bandwidth limit according to claim 4, characterized in that, The determination and execution of the dynamic control strategy for thread bandwidth is the second control strategy, including: Based on the total bandwidth requirement and the actual bandwidth of all non-critical COSIDs, determine the second bandwidth gap of the current system; Based on the priority order and the second bandwidth gap, the bandwidth of COSIDs with a preset bandwidth lower limit not being 0 is intelligently adjusted from low to high.

7. The bandwidth management method for ensuring a lower bandwidth limit according to claim 6, characterized in that, The step of intelligently adjusting the bandwidth of COSIDs with a preset bandwidth lower limit that is not 0, from low to high, based on priority order and the second bandwidth gap, includes: Determine the lowest priority COSID from all COSIDs with a lower bound that is not 0, and denote it as the COSID to be processed; Based on the actual bandwidth of the COSID to be processed and its corresponding preset bandwidth lower limit, obtain the required bandwidth of the COSID to be processed; If the second bandwidth gap is greater than the bandwidth required by the COSID to be processed, an updated bandwidth gap is obtained based on the second bandwidth gap and the bandwidth required by the COSID to be processed. If the updated bandwidth gap is not greater than the actual bandwidth of the COSID to be processed, the actual bandwidth of the COSID to be processed will be intelligently adjusted according to the updated bandwidth gap. If the updated bandwidth gap is greater than the actual bandwidth of the COSID to be processed, the bandwidth of COSIDs with a preset bandwidth lower limit not equal to 0 will be intelligently adjusted according to the updated bandwidth gap.

8. The bandwidth management method for ensuring a lower bandwidth limit according to claim 7, characterized in that, If the updated bandwidth gap is greater than the actual bandwidth of the COSID to be processed, the bandwidth of COSIDs with a preset bandwidth lower limit not equal to 0 will be intelligently adjusted according to the updated bandwidth gap, including: Based on the priority sorting from low to high, obtain the COSIDs whose next preset bandwidth lower limit is not 0, perform analysis on their required bandwidth, until determine the COSIDs with the corresponding priority that meet the updated bandwidth gap, and dynamically adjust the bandwidth of the corresponding COSIDs.

9. The bandwidth management method for ensuring a lower bandwidth limit according to claim 1, characterized in that, If the running state is the second state, the restriction on all the target COSIDs is lifted. The second state is the idle state.

10. A bandwidth management system for ensuring a lower bandwidth limit, characterized in that, It includes a Core-Cluster, local memory, and software configuration units, wherein the Core-Cluster includes one or more processor cores and a cache hierarchy; The cache hierarchy includes multiple cache levels and a QoS bandwidth allocation circuit, which is at the same level as the last cache level. The QoS bandwidth allocation circuit includes a QoS bandwidth master controller, a bandwidth upper limit management circuit, and a bandwidth lower limit management circuit. The bandwidth upper limit management circuit is used to manage the bandwidth upper limit of each target COSID, and the bandwidth lower limit management circuit operates independently of the bandwidth upper limit management circuit. The QoS bandwidth controller is used to obtain the configured preset bandwidth lower limit and the preset priority of the bandwidth lower limit; The bandwidth lower limit management circuit is used to determine the current operating status of the system based on the actual bandwidth corresponding to all target COSIDs obtained. If the operating state is the first state, the total bandwidth requirement of the current system and the sum of the actual bandwidths of all target COSIDs with a preset bandwidth lower limit of 0 are determined based on the actual bandwidth of each target COSID and the corresponding preset bandwidth lower limit in the QoS bandwidth controller; based on the total bandwidth requirement, the sum of the actual bandwidths, and the preset priority of all target COSIDs with a preset bandwidth lower limit of 0 in the QoS bandwidth controller, a dynamic thread bandwidth control strategy is determined and executed.

11. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the bandwidth management method for ensuring a lower bandwidth limit as described in any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; the computer instructions are used to cause the computer to perform the bandwidth management method for ensuring a lower bandwidth limit as described in any one of claims 1-9.

13. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the method according to any one of claims 1-9.

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