Transaction layer circuits for high speed peripheral component interconnect and methods of operation thereof
By introducing multiple transaction layer processing channels and fusion circuits into the PCIe transaction layer circuitry, the problem of processing multiple TLPs within the same clock cycle is solved, achieving more efficient data transmission.
CN115687221BActive Publication Date: 2026-07-17AICESTAR TECH SUZHOU CORP +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AICESTAR TECH SUZHOU CORP
- Filing Date
- 2021-07-22
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In high-speed peripheral component interconnect (PCIe), there is a challenge in processing multiple transaction layer messages (TLP) simultaneously within the same clock cycle.
Method used
The design employs multiple transaction layer processing channels, channel selection circuits, and fusion circuits. The channel selection circuits allocate message data to multiple transaction layer processing channels within the same clock cycle, and the fusion circuits selectively fuse the processing results.
Benefits of technology
This enables the simultaneous processing of multiple TLPs within the same clock cycle, improving data transmission efficiency and processing capacity.
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Smart Images
Figure CN115687221B_ABST
Abstract
The application provides a high-speed peripheral component interconnect express (PCIe) transaction layer circuit and an operation method thereof, and particularly relates to a PCIe transaction layer circuit, which comprises a plurality of transaction layer processing channels, a channel selection circuit and a fusion circuit. The plurality of transaction layer processing channels are coupled to a data bus, and the data bus is used to transmit at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit is configured to receive packet start position information and packet end position information of a current clock cycle from the data link layer circuit, and to distribute at least one packet data of the current clock cycle to at least one of the plurality of transaction layer processing channels according to the packet start position information and the packet end position information. The fusion circuit is coupled to the plurality of transaction layer processing channels, and the fusion circuit selectively fuses transaction layer processing results output by the plurality of transaction layer processing channels based on the distribution of the at least one packet data of the current clock cycle to the plurality of transaction layer processing channels by the channel selection circuit.
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