Display substrate and display device

Abstract

The present invention provides a display substrate and a display device. The display substrate includes a driving circuit arranged on a base substrate, and the driving circuit includes a potential control circuit; the potential control circuit is electrically connected to a first voltage line, a first node and a first output node respectively, and is used to control the connection or disconnection between the first node and the first output node according to the potential of the first node and / or the potential of the first output node under the control of a first voltage signal provided by the first voltage line. The embodiment of the present invention optimizes the bias state of the transistor in the driving circuit, avoids the risk of circuit failure after biasing, and improves the reliability of the driving circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Oxide transistors have better leakage current and better threshold voltage Vth uniformity, but when their mobility becomes higher, their Vth shift (drift) after biasing is more serious. Especially for the drive circuit, during operation, the transistors in the drive circuit will be in a certain bias state for a long time, causing the drive circuit to fail easily in signal tolerance. Summary of the invention

[0003] The main purpose of the present invention is to provide a display substrate and a display device to solve the problem in the prior art that the transistors in the driving circuit are in a certain bias state for a long time, causing the driving circuit to fail easily during reliability.

[0004] An embodiment of the present invention provides a display substrate, comprising a driving circuit disposed on a base substrate, wherein the driving circuit comprises a potential control circuit;

[0005] The potential control circuit is electrically connected to the first voltage line, the first node and the first output node, respectively, and is used to control the connection or disconnection between the first node and the first output node according to the potential of the first node and / or the potential of the first output node under the control of the first voltage signal provided by the first voltage line.

[0006] Optionally, the potential control circuit includes a first transistor;

[0007] A gate of the first transistor is electrically connected to the first voltage line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the first output node.

[0008] Optionally, the driving circuit further includes a first node control circuit and a second node control circuit;

[0009] The first node control circuit is electrically connected to the first clock signal line, the input end and the first node respectively, and is used to control the connection or disconnection between the first node and the input end under the control of the first clock signal provided by the first clock signal line;

[0010] The second node control circuit is electrically connected to the first node, the first clock signal line and the second node respectively, and is used to control the connection or disconnection between the first clock signal line and the second node under the control of the potential of the first node.

[0011] Optionally, the second node control circuit is also electrically connected to the first voltage line, and is used to control the connection or disconnection between the second node and the first voltage line under the control of the first clock signal.

[0012] Optionally, the second node is electrically connected to the second output node; or,

[0013] The driving circuit also includes a first control circuit; the first control circuit is electrically connected to the first voltage line, the second node and the second output node, respectively, and is used to control the connection or disconnection between the second node and the second output node according to the potential of the second node and / or the potential of the second output node under the control of the first voltage signal provided by the first voltage line.

[0014] Optionally, the driving circuit further includes a first output node control circuit;

[0015] The first output node control circuit is electrically connected to the second node, the third node, the first output node, the second clock signal line and the second voltage line respectively, and is used to control the connection or disconnection between the third node and the second voltage line under the control of the potential of the second node, and control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line;

[0016] The driving circuit further includes a first output circuit, a second output circuit, a first energy storage circuit and a second energy storage circuit;

[0017] The first output circuit is electrically connected to the first output node, the drive signal output terminal and the second clock signal line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second clock signal line under the control of the potential of the first output node;

[0018] The second output circuit is electrically connected to the second output node, the drive signal output terminal and the second voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0019] A first end of the first energy storage circuit is electrically connected to the first output node, a second end of the first energy storage circuit is electrically connected to the drive signal output terminal, and the first energy storage circuit is used to store electrical energy;

[0020] A first end of the second energy storage circuit is electrically connected to the second output node, a second end of the second energy storage circuit is electrically connected to the second voltage line, and the second energy storage circuit is used to store electrical energy.

[0021] Optionally, the second node control circuit includes a second transistor and a third transistor;

[0022] The gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal line, and the second electrode of the second transistor is electrically connected to the second node;

[0023] A gate of the third transistor is electrically connected to the first clock signal line, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the second node.

[0024] Optionally, the first node control circuit includes a fourth transistor;

[0025] The gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the first node;

[0026] The first output node control circuit includes a fifth transistor and a sixth transistor;

[0027] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second voltage line, and the second electrode of the fifth transistor is electrically connected to the third node;

[0028] The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first output node;

[0029] The first output circuit includes a seventh transistor, the second output circuit includes an eighth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0030] The gate of the seventh transistor is electrically connected to the first output node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0031] The gate of the eighth transistor is electrically connected to the second output node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the drive signal output terminal;

[0032] The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0033] The first plate of the second capacitor is electrically connected to the second output node, and the second plate of the second capacitor is electrically connected to the second voltage line.

[0034] Optionally, the first control circuit includes a ninth transistor;

[0035] A gate of the ninth transistor is electrically connected to the first voltage line, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the second output node.

[0036] Optionally, all transistors included in the driving circuit are oxide transistors.

[0037] Optionally, the display substrate comprises a semiconductor layer, a second gate metal layer and a first source-drain metal layer which are sequentially arranged on the base substrate;

[0038] A first voltage line is formed on a first source-drain metal layer, the semiconductor layer includes an active layer pattern of a transistor included in the potential control circuit, and an orthographic projection of the first voltage line on the substrate is located on a side of the orthographic projection of the active layer pattern of the transistor included in the potential control circuit on the substrate close to the display area;

[0039] The gate of the transistor included in the potential control circuit and the first conductive connection portion are both formed in the second gate metal layer, and the gate of the transistor included in the potential control circuit is connected to the first conductive connection portion; the first conductive connection portion is coupled to the first voltage line.

[0040] Optionally, the driving circuit further includes a first node control circuit;

[0041] The transistors included in the first node control circuit and the transistors included in the potential control circuit are arranged along a first direction.

[0042] Optionally, the transistor included in the potential control circuit is a first transistor, the transistor included in the first node control circuit is a fourth transistor, the drive circuit further includes a first output node control circuit; the first output node control circuit includes a fifth transistor and a sixth transistor;

[0043] The fourth transistor, the first transistor, the sixth transistor, and the fifth transistor are arranged along a first direction.

[0044] Optionally, the driving circuit further includes a first output circuit; the transistor included in the potential control circuit is a first transistor, the driving circuit in the display substrate further includes a second node control circuit and a first output circuit, the second node control circuit includes a second transistor; the first output circuit includes a seventh transistor;

[0045] The display substrate further includes a first gate metal layer disposed between the base substrate and the semiconductor layer;

[0046] The gate of the second transistor is formed on the first gate metal layer, and the gate of the seventh transistor and the second conductive connection portion connected to each other are formed on the second gate metal layer;

[0047] The second conductive connection portion is coupled to the gate of the second transistor;

[0048] The active layer pattern of the first transistor includes a first electrode of the first transistor, a second electrode of the first transistor, and a first channel portion disposed between the first electrode of the first transistor and the second electrode of the first transistor;

[0049] The first electrode of the first transistor is coupled to the gate of the second transistor through a third conductive connection portion formed on the first source-drain metal layer.

[0050] Optionally, the driving circuit further includes a first output node control circuit, the first output node control circuit includes a fifth transistor and a sixth transistor; the second node control circuit further includes a third transistor;

[0051] The semiconductor layer includes an active layer pattern of the fifth transistor and an active layer pattern of the sixth transistor;

[0052] The active layer pattern of the first transistor, the active layer pattern of the sixth transistor and the active layer pattern of the fifth transistor are continuous with each other;

[0053] The active layer pattern of the fifth transistor includes a first electrode of the fifth transistor, a second electrode of the fifth transistor, and a fifth channel portion disposed between the first electrode of the fifth transistor and the second electrode of the fifth transistor;

[0054] The first electrode of the fifth transistor is coupled to the second voltage line; the positive projection of the second voltage line on the substrate is located on a side of the positive projection of the first electrode of the fifth transistor on the substrate away from the display area;

[0055] The second voltage line is formed in the first source-drain metal layer;

[0056] The gate and the fourth conductive connection portion of the fifth transistor which are interconnected are both formed on the second gate metal layer, the fourth conductive connection portion is coupled to the fifth conductive connection portion formed on the first source-drain metal layer; the fifth conductive connection portion is electrically connected to the second electrode of the third transistor;

[0057] The first electrode of the third transistor is coupled to the first voltage line;

[0058] The first voltage line and the second voltage line both extend along a first direction.

[0059] Optionally, the driving circuit further includes a first node control circuit, and the first node control circuit includes a fourth transistor;

[0060] The first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the second gate metal layer;

[0061] The first gate of the third transistor is formed on the first gate metal layer, and the second gate of the third transistor is formed on the second gate metal layer;

[0062] The first gate of the fourth transistor is connected to the first gate of the third transistor, and the second gate of the fourth transistor is connected to the second gate of the third transistor;

[0063] The first gate of the fourth transistor and the second gate of the fourth transistor are both coupled to the first clock signal line;

[0064] The semiconductor layer includes an active layer pattern of the second transistor and an active layer pattern of the fourth transistor;

[0065] The active layer pattern of the second transistor includes a first electrode of the second transistor, a second electrode of the second transistor, and a second channel portion disposed between the first electrode of the second transistor and the second electrode of the second transistor;

[0066] The first electrode of the second transistor is electrically connected to the first gate of the third transistor through a connecting conductive portion formed on the first source-drain metal layer; the second electrode of the second transistor is electrically connected to the fifth conductive connecting portion;

[0067] The active layer pattern of the fourth transistor includes a first electrode of the fourth transistor, a second electrode of the fourth transistor, and a fourth channel portion arranged between the first electrode of the fourth transistor and the second electrode of the fourth transistor; the first electrode of the fourth transistor is electrically connected to an input terminal formed in the second gate metal layer through a sixth conductive connection portion formed in the first source-drain metal layer.

[0068] Optionally, the active layer pattern of the first transistor is continuous with the active layer pattern of the sixth transistor;

[0069] The active layer pattern of the first transistor, the active layer pattern of the sixth transistor, the active layer pattern of the fifth transistor and the active layer pattern of the fourth transistor constitute a first active layer pattern, and the first active layer pattern extends along a first direction.

[0070] Optionally, the gate of the sixth transistor and the seventh conductive connection portion that are connected to each other are formed in the second gate metal layer, and the seventh conductive connection portion is electrically connected to the second clock signal line;

[0071] The first clock signal line and the second clock signal line are located at a side of the second voltage line away from the display area.

[0072] Optionally, the driving circuit further includes a second output circuit, and the second output circuit includes an eighth transistor;

[0073] The gate of the sixth transistor is connected to the eighth conductive connection portion and is located in the same layer;

[0074] The eighth conductive connection portion is coupled to the first electrode of the seventh transistor;

[0075] The second electrode of the seventh transistor is electrically connected to the drive signal output terminal, and the first electrode of the seventh transistor, the second electrode of the seventh transistor and the drive signal output terminal are all formed in the first source-drain metal layer;

[0076] The gate of the eighth transistor is coupled to the fifth conductive connection portion, the second electrode of the eighth transistor is electrically connected to the drive signal output terminal, the gate of the eighth transistor is formed on the second gate metal layer, and the second electrode of the eighth transistor is formed on the first source-drain metal layer;

[0077] The seventh transistor and the eighth transistor are arranged on a side of the first voltage line close to the display area.

[0078] Optionally, the semiconductor layer includes an active layer pattern of a seventh transistor and an active layer pattern of an eighth transistor; the active layer pattern of the seventh transistor includes A seventh active layer patterns, and the active layer pattern of the eighth transistor includes A eighth active layer patterns; A is a positive integer;

[0079] The ath seventh active layer pattern and the ath eighth active layer pattern are connected to each other.

[0080] Optionally, the driving circuit further includes a first energy storage circuit and a second energy storage circuit; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; the display substrate further includes a first metal layer disposed between the base substrate and the first gate metal layer;

[0081] The first metal layer includes a first plate of a first capacitor and a first plate of a second capacitor, and the first gate metal layer includes a second plate of the first capacitor and a second plate of the second capacitor;

[0082] The first electrode plate of the second capacitor is electrically connected to the fifth conductive connecting portion, and the second electrode plate of the second capacitor is coupled to the second voltage line;

[0083] The first electrode plate of the first capacitor is coupled to the gate of the seventh transistor through a ninth conductive connection portion formed on the first source-drain metal layer;

[0084] The second electrode plate of the first capacitor is connected to the tenth conductive connection portion and is located in the same layer. The tenth conductive connection portion is electrically connected to the driving signal output terminal formed in the first source-drain metal layer.

[0085] Optionally, the first electrode plate of the first capacitor and the second electrode plate of the first capacitor both extend along the first direction;

[0086] The orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the seventh transistor on the substrate, and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the seventh transistor on the substrate.

[0087] Optionally, the orthographic projection of the first plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first voltage line on the substrate, and the orthographic projection of the second plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first voltage line on the substrate.

[0088] Optionally, the display substrate further comprises a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the base substrate;

[0089] The first clock signal line includes a first clock signal line portion and a second clock signal line portion coupled to each other, and the second clock signal line includes a third clock signal line portion and a fourth clock signal line portion coupled to each other;

[0090] The first clock signal line portion and the third clock signal line portion are both formed in a first source-drain metal layer;

[0091] The second clock signal line portion and the fourth clock signal line portion are both formed in a second source-drain metal layer;

[0092] The first clock signal line portion, the second clock signal line portion, the third clock signal line portion, and the fourth clock signal line portion all extend along a first direction.

[0093] An embodiment of the present invention further provides a display device, comprising the above-mentioned display substrate.

[0094] The embodiment of the present invention optimizes the bias state of the transistor in the driving circuit, avoids the risk of circuit failure after biasing, and improves the reliability of the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0096] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0097] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0098] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0099] Figure 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0100] Figure 6 yes Figure 5 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0101] Figure 7 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0102] Figure 8 yes Figure 5 A layout diagram of at least one embodiment of the driving circuit shown;

[0103] Fig. 9 yes Figure 8 A layout diagram of the first metal layer in FIG.

[0104] Fig.10 yes Figure 8 A layout diagram of the first gate metal layer in FIG.

[0105] Fig.11A and Fig. 11B yes Figure 8 A layout diagram of a semiconductor layer in FIG.

[0106] Fig.12 yes Figure 8 A layout diagram of a second gate metal layer in FIG.

[0107] Fig.13 yes Figure 8 A layout diagram of the first source and drain metal layer in FIG.

[0108] Fig.14 yes Figure 8 Layout diagram of the second source and drain metal layer in . DETAILED DESCRIPTION

[0109] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0110] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0111] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0112] The display substrate according to the embodiment of the present invention comprises a driving circuit arranged on a base substrate, such as Figure 1 As shown, the driving circuit includes a potential control circuit 11;

[0113] The potential control circuit 11 is electrically connected to the first voltage line V1, the first node N1-1 and the first output node N1, respectively, and is used to control the connection or disconnection between the first node N1-1 and the first output node N1 according to the potential of the first node N1-1 and / or the potential of the first output node N1 under the control of the first voltage signal provided by the first voltage line V1.

[0114] When the driving circuit in the display substrate described in the embodiment of the present invention is working, the potential control circuit 11 controls the connection or disconnection between the first node N1-1 and the first output node N1 according to the potential of the first node N1-1 and / or the potential of the first output node N1 under the control of the potential of the first voltage signal provided by the first voltage line V1, so that the potential of the first node N1-1 will not be greater than the voltage value of the first voltage signal provided by the first voltage line V1, so that the gate-source voltage of the transistor whose gate is electrically connected to the first node N1-1 in the driving circuit will not be too large, and further, the threshold voltage drift of the transistor due to the excessive gate-source voltage of the transistor will not be serious, thereby causing the driving circuit to fail.

[0115] The embodiment of the present invention optimizes the bias state of the transistor in the driving circuit, avoids the risk of circuit failure after biasing, and improves the reliability of the driving circuit.

[0116] In at least one embodiment of the present invention, the first voltage line may be a high voltage line VGH, and the voltage value of the high voltage signal provided by the high voltage line VGH may be greater than or equal to 1V and less than or equal to 20V, but is not limited thereto.

[0117] Optionally, the potential control circuit includes a first transistor;

[0118] A gate of the first transistor is electrically connected to the first voltage line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the first output node.

[0119] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a first node control circuit 21 and a second node control circuit 22;

[0120] The first node control circuit 21 is electrically connected to the first clock signal line CK, the input terminal GI and the first node N1-1 respectively, and is used to control the connection or disconnection between the first node N1-1 and the input terminal GI under the control of the first clock signal provided by the first clock signal line CK;

[0121] The second node control circuit 22 is electrically connected to the first node N1-1, the first clock signal line CK and the second node N2 respectively, and is used to control the connection or disconnection between the first clock signal line CK and the second node N2 under the control of the potential of the first node N1-1.

[0122] The present invention Figure 2 When at least one embodiment of the driving circuit shown is in operation, the first node control circuit 21 controls the connection or disconnection between the first node N1-1 and the input terminal GI under the control of the first clock signal; the second node control circuit 22 controls the connection or disconnection between the first clock signal line CK and the second node N2 under the control of the potential of the first node N1-1.

[0123] In a specific implementation, the second node control circuit may also be electrically connected to the first voltage line, and is used to control the connection or disconnection between the second node and the first voltage line under the control of the first clock signal.

[0124] like Figure 2 As shown, the second node control circuit 22 is also electrically connected to the first voltage line V1, and is used to control the connection or disconnection between the second node N2 and the first voltage line V1 under the control of the first clock signal CK.

[0125] Optionally, the second node is electrically connected to the second output node; or,

[0126] The driving circuit also includes a first control circuit; the first control circuit is electrically connected to the first voltage line, the second node and the second output node, respectively, and is used to control the connection or disconnection between the second node and the second output node according to the potential of the second node and / or the potential of the second output node under the control of the first voltage signal provided by the first voltage line.

[0127] In a specific implementation, the second node may be directly electrically connected to the second output node, or a first control circuit may be further provided between the second node and the second output node.

[0128] In the display substrate described in at least one embodiment of the present invention, the driving circuit may further include a first output node control circuit;

[0129] The first output node control circuit is electrically connected to the second node, the third node, the first output node, the second clock signal line and the second voltage line respectively, and is used to control the connection or disconnection between the third node and the second voltage line under the control of the potential of the second node, and control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line;

[0130] The driving circuit further includes a first output circuit, a second output circuit, a first energy storage circuit and a second energy storage circuit;

[0131] The first output circuit is electrically connected to the first output node, the drive signal output terminal and the second clock signal line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second clock signal line under the control of the potential of the first output node;

[0132] The second output circuit is electrically connected to the second output node, the drive signal output terminal and the second voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0133] A first end of the first energy storage circuit is electrically connected to the first output node, a second end of the first energy storage circuit is electrically connected to the drive signal output terminal, and the first energy storage circuit is used to store electrical energy;

[0134] A first end of the second energy storage circuit is electrically connected to the second output node, a second end of the second energy storage circuit is electrically connected to the second voltage line, and the second energy storage circuit is used to store electrical energy.

[0135] In a specific implementation, the driving circuit may further include a first output node control circuit, a first output circuit, a second output circuit, a first energy storage circuit, and a second energy storage circuit;

[0136] The first output node control circuit controls the potential of the first output node, the first output circuit and the second output circuit control the output of the drive signal through the drive signal output terminal, the first energy storage circuit is used to control the potential of the first output node, and the second energy storage circuit is used to control the potential of the second output node.

[0137] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a first output node control circuit 31;

[0138] The first output node control circuit 31 is electrically connected to the second node N2, the third node N3, the first output node N1, the second clock signal line CB and the second voltage line V2 respectively, and is used to control the connection or disconnection between the third node N3 and the second voltage line V2 under the control of the potential of the second node N2, and control the connection or disconnection between the third node N3 and the first output node N1 under the control of the second clock signal provided by the second clock signal line CB;

[0139] The driving circuit may further include a first output circuit 32, a second output circuit 33, a first energy storage circuit 34 and a second energy storage circuit 35;

[0140] The first output circuit 32 is electrically connected to the first output node N1, the drive signal output terminal GOUT and the second clock signal line CB respectively, and is used to control the connection or disconnection between the drive signal output terminal GOUT and the second clock signal line CB under the control of the potential of the first output node N1;

[0141] The second output circuit 33 is electrically connected to the second output node, the drive signal output terminal GOUT and the second voltage line V2 respectively, and is used to control the connection or disconnection between the drive signal output terminal GOUT and the second voltage line V2 under the control of the potential of the second output node N4;

[0142] The second output node is electrically connected to the second node N2;

[0143] A first end of the first energy storage circuit 34 is electrically connected to the first output node N1, a second end of the first energy storage circuit 34 is electrically connected to the drive signal output terminal GOUT, and the first energy storage circuit 34 is used to store electrical energy;

[0144] A first end of the second energy storage circuit 35 is electrically connected to the second output node, a second end of the second energy storage circuit 35 is electrically connected to the second voltage line V2, and the second energy storage circuit 35 is used to store electrical energy.

[0145] In a specific implementation, the driving circuit may further include a first output node control circuit, a first output circuit, a second output circuit, a first energy storage circuit, and a second energy storage circuit;

[0146] The first output node control circuit controls the potential of the first output node, the first output circuit and the second output circuit control the output of the drive signal through the drive signal output terminal, the first energy storage circuit is used to control the potential of the first output node, and the second energy storage circuit is used to control the potential of the second output node.

[0147] In at least one embodiment of the present invention, the second voltage line may be a low voltage line, but is not limited thereto.

[0148] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first control circuit 41;

[0149] The first control circuit 41 is electrically connected to the first voltage line V1, the second node N2 and the second output node N4, respectively, and is used to control the connection or disconnection between the second node N2 and the second output node N4 according to the potential of the second node N2 and / or the potential of the second output node N4 under the control of the first voltage signal provided by the first voltage line V1.

[0150] Optionally, the second node control circuit includes a second transistor and a third transistor;

[0151] The gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal line, and the second electrode of the second transistor is electrically connected to the second node;

[0152] A gate of the third transistor is electrically connected to the first clock signal line, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the second node.

[0153] Optionally, the first node control circuit includes a fourth transistor;

[0154] The gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the first node;

[0155] The first output node control circuit includes a fifth transistor and a sixth transistor;

[0156] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second voltage line, and the second electrode of the fifth transistor is electrically connected to the third node;

[0157] The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first output node;

[0158] The first output circuit includes a seventh transistor, the second output circuit includes an eighth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0159] The gate of the seventh transistor is electrically connected to the first output node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0160] The gate of the eighth transistor is electrically connected to the second output node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the drive signal output terminal;

[0161] The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0162] The first plate of the second capacitor is electrically connected to the second output node, and the second plate of the second capacitor is electrically connected to the second voltage line.

[0163] Optionally, the first control circuit includes a ninth transistor;

[0164] A gate of the ninth transistor is electrically connected to the first voltage line, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the second output node.

[0165] In at least one embodiment of the present invention, all transistors included in the driving circuit are oxide transistors, but the present invention is not limited thereto.

[0166] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown,

[0167] The potential control circuit includes a first transistor T1;

[0168] The gate of the first transistor T1 is electrically connected to the high voltage line VGH, the first electrode of the first transistor T1 is electrically connected to the first node N1-1, and the second electrode of the first transistor T1 is electrically connected to the first output node N1;

[0169] The second node control circuit includes a second transistor T2 and a third transistor T3;

[0170] The gate of the second transistor T2 is electrically connected to the first node N1-1, the first electrode of the second transistor T2 is electrically connected to the first clock signal line CK, and the second electrode of the second transistor T2 is electrically connected to the second node N2;

[0171] The gate of the third transistor T3 is electrically connected to the first clock signal line CK, the first electrode of the third transistor T3 is electrically connected to the high voltage line VGH, and the second electrode of the third transistor T3 is electrically connected to the second node N2;

[0172] The first node control circuit includes a fourth transistor T4;

[0173] The gate of the fourth transistor T4 is electrically connected to the first clock signal line CK, the first electrode of the fourth transistor T4 is electrically connected to the input terminal GI, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1-1;

[0174] The first output node control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0175] The gate of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the low voltage line VGL, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3;

[0176] The gate of the sixth transistor T6 is electrically connected to the second clock signal line CB, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first output node N1;

[0177] The first output circuit includes a seventh transistor T7, the second output circuit includes an eighth transistor T8, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0178] The gate of the seventh transistor T7 is electrically connected to the first output node N1, the first electrode of the seventh transistor T7 is electrically connected to the second clock signal line CB, and the second electrode of the seventh transistor T7 is electrically connected to the drive signal output terminal GOUT;

[0179] The gate of the eighth transistor T8 is electrically connected to the second output node, the first electrode of the eighth transistor T8 is electrically connected to the low voltage line VGL, and the second electrode of the eighth transistor T8 is electrically connected to the driving signal output terminal GOUT; the second output node is electrically connected to the second node N2;

[0180] The first plate of the first capacitor C1 is electrically connected to the first output node N1, and the second plate of the first capacitor C1 is electrically connected to the drive signal output terminal GOUT;

[0181] The first plate of the second capacitor C2 is electrically connected to the second output node, and the second plate of the second capacitor C2 is electrically connected to the low voltage line VGL.

[0182] exist Figure 5 In at least one embodiment of the driving circuit shown, all transistors are oxide thin film transistors, and all transistors are n-type transistors, but the present invention is not limited thereto.

[0183] The present invention Figure 5 When at least one embodiment of the driving circuit shown is in operation, T1 is set, and the potential of the first node N1-1 is shunted by T1 to ensure that it is less than the voltage value of the high voltage signal provided by VGH, thereby protecting the threshold voltage drift of T2 caused by excessive gate-source voltage of T2, thereby preventing the driving circuit from failing.

[0184] Figure 6 The present invention Figure 5 FIG. 1 is a timing diagram of the operation of at least one embodiment of the driving circuit shown.

[0185] from Figure 6 It can be seen that when the potential of N1-1 is a high voltage value, the potential of N1-1 is low, so the threshold voltage drift of T2 will not be serious, the threshold voltage drift of T2 will be reduced, and the driving capability of the driving circuit can be increased while meeting the driving requirements.

[0186] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown in the figure, the driving circuit according to at least one embodiment of the present invention further includes a first control circuit, and the first control circuit includes a ninth transistor T9;

[0187] A gate of the ninth transistor T9 is electrically connected to the high voltage line VGH, a first electrode of the ninth transistor T9 is electrically connected to the second node N2, and a second electrode of the ninth transistor T9 is electrically connected to the second output node N4.

[0188] exist Figure 7 In at least one embodiment of the driving circuit shown, T9 is added to include T2, T3 and T5.

[0189] Figure 8 yes Figure 5 A layout diagram of at least one embodiment of a driving circuit is shown.

[0190] exist Figure 8In the figure, GSTV is a starting voltage line, CK is a first clock signal line, CB is a second clock signal line, VGL is a low voltage line, and VGH is a high voltage line.

[0191] like Figure 8 As shown, GSTV, VGL and VGH all extend in the vertical direction.

[0192] Fig. 9 yes Figure 8 The layout diagram of the first metal layer in Fig.10 yes Figure 8 The layout diagram of the first gate metal layer in Fig.11A and Fig. 11B yes Figure 8 The layout of the semiconductor layers in Fig.12 yes Figure 8 The layout diagram of the second gate metal layer in Fig.13 yes Figure 8 Layout diagram of the first source and drain metal layer in, Fig.14 yes Figure 8 Layout diagram of the second source and drain metal layer in .

[0193] In a specific implementation, the display substrate includes a semiconductor layer, a second gate metal layer and a first source-drain metal layer which are sequentially arranged on the base substrate;

[0194] A first voltage line is formed on a first source-drain metal layer, the semiconductor layer includes an active layer pattern of a transistor included in the potential control circuit, and an orthographic projection of the first voltage line on the substrate is located on a side of the orthographic projection of the active layer pattern of the transistor included in the potential control circuit on the substrate close to the display area;

[0195] The gate of the transistor included in the potential control circuit and the first conductive connection portion are both formed in the second gate metal layer, and the gate of the transistor included in the potential control circuit is connected to the first conductive connection portion; the first conductive connection portion is coupled to the first voltage line.

[0196] In at least one embodiment of the present invention, the semiconductor layer, the second gate metal layer and the first source-drain metal layer are sequentially arranged in a direction away from the base substrate.

[0197] In at least one embodiment of the present invention, the first voltage line may be a high voltage line VGH, and the transistor included in the potential control circuit is a first transistor.

[0198] exist Fig.13 In the figure, the line labeled VGH is the high voltage line. Fig.12, the gate of the first transistor is labeled G1, the gate of the first transistor is labeled L1, the first conductive connection portion L1 is connected to the gate G1 of the first transistor, and the first conductive connection portion L1 is coupled to the high voltage line VGH, so that the gate of the first transistor is electrically connected to the high voltage line VGH;

[0199] like Figure 8 As shown, the positive projection of the high voltage line VGH on the substrate is located at the active layer pattern A1 of the first transistor (as shown in FIG. Fig. 11B The orthographic projection of the substrate (as shown) on the substrate is close to the side of the display area.

[0200] In at least one embodiment of the present invention, the high voltage line VGH can be arranged on a side of the first transistor close to the display area to facilitate the connection between the gate of the first transistor and the high voltage line VGH. In a specific implementation, a first output circuit and a second output circuit can be arranged on a side of the high voltage line VGH close to the display area.

[0201] In a specific implementation, the driving circuit further includes a first node control circuit;

[0202] The transistors included in the first node control circuit and the transistors included in the potential control circuit are arranged along a first direction.

[0203] In at least one embodiment of the present invention, the first direction may be a vertical direction.

[0204] In at least one embodiment of the present invention, the transistor included in the potential control circuit can be disposed below the transistor included in the first node control circuit, thereby saving lateral space and facilitating the realization of a narrow frame.

[0205] Optionally, the transistor included in the potential control circuit is a first transistor, the transistor included in the first node control circuit is a fourth transistor, the drive circuit further includes a first output node control circuit; the first output node control circuit includes a fifth transistor and a sixth transistor;

[0206] The fourth transistor, the first transistor, the sixth transistor, and the fifth transistor are arranged along a first direction.

[0207] In at least one embodiment of the present invention, the fourth transistor, the first transistor, the sixth transistor and the fifth transistor may be arranged in a vertical direction, so that four transistors can be disposed in an extremely narrow lateral space, thereby facilitating the realization of a narrow frame.

[0208] In at least one embodiment of the present invention, the driving circuit in the display substrate further includes a first output circuit; the transistor included in the potential control circuit is a first transistor, the driving circuit in the display substrate further includes a second node control circuit and a first output circuit, the second node control circuit includes a second transistor; the first output circuit includes a seventh transistor;

[0209] The display substrate further includes a first gate metal layer disposed between the base substrate and the semiconductor layer;

[0210] like Fig.10 and Fig.12 As shown, the gate G2 of the second transistor is formed on the first gate metal layer, and the gate G7 and the second conductive connection portion L2 of the seventh transistor that are connected to each other are formed on the second gate metal layer;

[0211] The second conductive connection portion L2 is coupled to the gate G2 of the second transistor;

[0212] like Fig.11A As shown, the active layer pattern of the first transistor includes a first electrode S1 of the first transistor, a second electrode D1 of the first transistor, and a first channel portion CH1 disposed between the first electrode S1 of the first transistor and the second electrode D1 of the first transistor;

[0213] like Figure 8-Figure 14 As shown, the first electrode S1 of the first transistor is coupled to the gate G2 of the second transistor through a third conductive connection portion L3 formed in the first source-drain metal layer.

[0214] Optionally, the driving circuit further includes a fifth transistor and a sixth transistor; the second node control circuit further includes a third transistor;

[0215] The semiconductor layer includes an active layer pattern of the fifth transistor and an active layer pattern of the sixth transistor;

[0216] The active layer pattern of the first transistor, the active layer pattern of the sixth transistor and the active layer pattern of the fifth transistor are continuous with each other;

[0217] The active layer pattern of the fifth transistor includes a first electrode of the fifth transistor, a second electrode of the fifth transistor, and a fifth channel portion disposed between the first electrode of the fifth transistor and the second electrode of the fifth transistor;

[0218] The first electrode of the fifth transistor is coupled to the second voltage line; the positive projection of the second voltage line on the substrate is located on a side of the positive projection of the first electrode of the fifth transistor on the substrate away from the display area;

[0219] The second voltage line is formed in the first source-drain metal layer;

[0220] The gate and the fourth conductive connection portion of the fifth transistor which are interconnected are both formed on the first gate metal layer, the fourth conductive connection portion is coupled to the fifth conductive connection portion formed on the first source-drain metal layer; the fifth conductive connection portion is electrically connected to the second electrode of the third transistor;

[0221] A first electrode of the third transistor is coupled to a first voltage line.

[0222] Optionally, the first voltage line and the second voltage line may both extend along a first direction.

[0223] In at least one embodiment of the present invention, the first direction may be a vertical direction, but is not limited thereto.

[0224] like Fig. 11B As shown, the semiconductor layer includes an active layer pattern A5 of the fifth transistor and an active layer pattern A6 of the sixth transistor;

[0225] The active layer pattern A1 of the first transistor, the active layer pattern A6 of the sixth transistor, and the active layer pattern A5 of the fifth transistor are continuous with each other.

[0226] In at least one embodiment of the present invention, VGH, VGL, the clock signal line portion included in the first clock signal line, the clock signal line portion included in the second clock signal line, and GSTV may all extend in a vertical direction, but the present invention is not limited thereto.

[0227] In at least one embodiment of the present invention, GSTV, the clock signal line portion included in the second clock signal line, the clock signal line portion included in the first clock signal line portion, and the low voltage line VGL may be arranged in sequence along a second direction, and the second direction intersects with the first direction. For example, the second direction may be a horizontal direction, but is not limited thereto.

[0228] like Fig.11A As shown, the active layer pattern of the fifth transistor includes a first electrode S5 of the fifth transistor, a second electrode D5 of the fifth transistor, and a fifth channel portion CH5 disposed between the first electrode S5 of the fifth transistor and the second electrode D5 of the fifth transistor;

[0229] like Figure 8 As shown, the first electrode S5 of the fifth transistor is coupled to the low voltage line VGL; the positive projection of the low voltage line VGL on the substrate is located on a side of the positive projection of the first electrode S5 of the fifth transistor on the substrate away from the display area;

[0230] like Fig.13As shown, the low voltage line VGL is formed in the first source-drain metal layer;

[0231] like Fig.12 As shown, the gate G5 and the fourth conductive connection portion L4 of the fifth transistor connected to each other are both formed in the second gate metal layer. Figure 8 As shown, the fourth conductive connection portion L4 is coupled to the fifth conductive connection portion L5 formed on the first source-drain metal layer; the fifth conductive connection portion L5 is electrically connected to the second electrode D3 of the third transistor;

[0232] A first electrode S3 of the third transistor is coupled to a high voltage line VGH.

[0233] exist Fig.11A In the figure, the sixth channel portion of the active layer pattern of the sixth transistor is labeled CH6; the second electrode D1 of the first transistor is multiplexed as the second electrode of the sixth transistor; and the second electrode D5 of the fifth transistor is multiplexed as the first electrode of the sixth transistor.

[0234] In at least one embodiment of the present invention, the driving circuit further includes a first node control circuit, and the first node control circuit includes a fourth transistor;

[0235] The first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the second gate metal layer;

[0236] The first gate of the third transistor is formed on the first gate metal layer, and the second gate of the third transistor is formed on the second gate metal layer;

[0237] The first gate of the fourth transistor is connected to the first gate of the third transistor, and the second gate of the fourth transistor is connected to the second gate of the third transistor;

[0238] The first gate of the fourth transistor and the second gate of the fourth transistor are both coupled to the first clock signal line;

[0239] The semiconductor layer includes an active layer pattern of the second transistor and an active layer pattern of the fourth transistor;

[0240] The active layer pattern of the second transistor includes a first electrode of the second transistor, a second electrode of the second transistor, and a second channel portion disposed between the first electrode of the second transistor and the second electrode of the second transistor;

[0241] The first electrode of the second transistor is electrically connected to the first gate of the third transistor through a connecting conductive portion formed on the first source-drain metal layer; the second electrode of the second transistor is electrically connected to the fifth conductive connecting portion;

[0242] The active layer pattern of the fourth transistor includes a first electrode of the fourth transistor, a second electrode of the fourth transistor, and a fourth channel portion arranged between the first electrode of the fourth transistor and the second electrode of the fourth transistor; the first electrode of the fourth transistor is electrically connected to an input terminal formed in the second gate metal layer through a sixth conductive connection portion formed in the first source-drain metal layer.

[0243] In at least one embodiment of the present invention, the active layer pattern of the first transistor is continuous with the active layer pattern of the sixth transistor;

[0244] The active layer pattern of the first transistor, the active layer pattern of the sixth transistor, the active layer pattern of the fifth transistor and the active layer pattern of the fourth transistor constitute a first active layer pattern, and the first active layer pattern extends along a first direction.

[0245] In at least one embodiment of the present invention, the first direction may be a vertical direction, but is not limited thereto.

[0246] In specific implementation, Fig.11A and Fig. 11B As shown, the active layer pattern A4 of the fourth transistor and the active layer pattern A1 of the first transistor, the active layer pattern A6 of the sixth transistor and the active layer pattern A5 of the fifth transistor are continuous with each other, A4, A1, A6 and A5 are integrally formed to form a first active layer pattern, and the first active layer pattern can extend in a vertical direction to reduce the lateral space, which is conducive to achieving a narrow frame.

[0247] like Figure 8 As shown, T1, T2, T3, T4, T5 and T6 are all arranged between the low voltage line VGL and the high voltage line VGH, and T7 and T8 are located on the side of the high voltage line VGH close to the display area. Since T7 and T8 are electrically connected to the drive signal output terminal GOUT, and GOUT needs to be electrically connected to the pixel circuit located in the display area, T7, T8 and GOUT are arranged close to the display area.

[0248] In a specific implementation, the driving circuit further includes a first node control circuit, and the first node control circuit includes a fourth transistor;

[0249] like Fig.10 and Fig.12 As shown, the first gate G41 of the fourth transistor is formed on the first gate metal layer, and the second gate G42 of the fourth transistor is formed on the second gate metal layer;

[0250] The first gate G31 of the third transistor is formed on the first gate metal layer, and the second gate G32 of the third transistor is formed on the second gate metal layer;

[0251] The first gate G41 of the fourth transistor is connected to the first gate G31 of the third transistor, and the second gate G42 of the fourth transistor is connected to the second gate G32 of the third transistor;

[0252] like Figure 8 As shown, the first gate G41 of the fourth transistor and the second gate G42 of the fourth transistor are both coupled to the first clock signal line CK;

[0253] The semiconductor layer includes an active layer pattern of the second transistor and an active layer pattern of the fourth transistor;

[0254] like Fig.11A As shown, the active layer pattern of the second transistor includes a first electrode S2 of the second transistor, a second electrode D2 of the second transistor, and a second channel portion CH2 disposed between the first electrode S2 of the second transistor and the second electrode D2 of the second transistor;

[0255] like Figures 8 to 14 As shown, the first electrode S2 of the second transistor is electrically connected to the first gate G31 of the third transistor through the connecting conductive portion L0 formed in the first source-drain metal layer; the second electrode D2 of the second transistor is electrically connected to the fifth conductive connecting portion L5;

[0256] The active layer pattern of the fourth transistor includes a first electrode S4 of the fourth transistor, a second electrode D4 of the fourth transistor, and a fourth channel portion CH4 arranged between the first electrode S4 of the fourth transistor and the second electrode D4 of the fourth transistor; the first electrode S4 of the fourth transistor is electrically connected to the input terminal GI formed in the second gate metal layer through a sixth conductive connection portion L6 formed in the first source-drain metal layer.

[0257] In a specific implementation, the gate of the sixth transistor and the seventh conductive connection portion that are connected to each other are formed in the second gate metal layer, and the seventh conductive connection portion is electrically connected to the second clock signal line;

[0258] The first clock signal line and the second clock signal line are located at a side of the second voltage line away from the display area.

[0259] like Fig.12 As shown, the gate G6 and the seventh conductive connection portion L7 of the sixth transistor which are connected to each other are formed in the second gate metal layer, and the seventh conductive connection portion L7 is electrically connected to the second clock signal line CB;

[0260] The first clock signal line CK and the second clock signal line CB are located at a side of the low voltage line VGL away from the display area.

[0261] In at least one embodiment of the present invention, the driving circuit further includes a second output circuit, and the second output circuit includes an eighth transistor;

[0262] The gate of the sixth transistor is connected to the eighth conductive connection portion and is located in the same layer;

[0263] The eighth conductive connection portion is coupled to the first electrode of the seventh transistor;

[0264] The second electrode of the seventh transistor is electrically connected to the drive signal output terminal, and the first electrode of the seventh transistor, the second electrode of the seventh transistor and the drive signal output terminal are all formed in the first source-drain metal layer;

[0265] The gate of the eighth transistor is coupled to the fifth conductive connection portion, the second electrode of the eighth transistor is electrically connected to the drive signal output terminal, the gate of the eighth transistor is formed on the second gate metal layer, and the second electrode of the eighth transistor is formed on the first source-drain metal layer;

[0266] The seventh transistor and the eighth transistor are arranged on a side of the first voltage line close to the display area.

[0267] In a specific implementation, the driving circuit further includes a second output circuit, and the second output circuit includes an eighth transistor;

[0268] like Fig.12 As shown, the gate G6 of the sixth transistor is connected to the eighth conductive connection portion L8 and is located in the same layer;

[0269] like Figure 8-Figure 14 As shown, the eighth conductive connection portion L8 is coupled to the first electrode S7 of the seventh transistor;

[0270] The second electrode D7 of the seventh transistor is electrically connected to the driving signal output terminal GOUT, and the first electrode S7 of the seventh transistor, the second electrode D7 of the seventh transistor and the driving signal output terminal GOUT are all formed in the first source-drain metal layer;

[0271] The gate G8 of the eighth transistor is coupled to the fifth conductive connection portion L5, the second electrode D8 of the eighth transistor is electrically connected to the drive signal output terminal GOUT, the gate G8 of the eighth transistor is formed on the second gate metal layer, and the second electrode D8 of the eighth transistor is formed on the first source-drain metal layer;

[0272] The seventh transistor and the eighth transistor are disposed on a side of the high voltage line VGH close to the display area.

[0273] exist Fig.13As shown, the second electrode of the eighth transistor is labeled D8.

[0274] Optionally, the semiconductor layer includes an active layer pattern of a seventh transistor and an active layer pattern of an eighth transistor; the active layer pattern of the seventh transistor includes A seventh active layer patterns, and the active layer pattern of the eighth transistor includes A eighth active layer patterns; A is a positive integer;

[0275] The ath seventh active layer pattern and the ath eighth active layer pattern are connected to each other.

[0276] like Fig. 11B As shown, the semiconductor layer includes an active layer pattern of a seventh transistor and an active layer pattern of an eighth transistor; the active layer pattern of the seventh transistor includes a first seventh active layer pattern A71, a second seventh active layer pattern A72, and a third seventh active layer pattern A73, and the active layer pattern of the eighth transistor includes a first eighth active layer pattern A81, a second eighth active layer pattern A82, and a third eighth active layer pattern A83;

[0277] A71 and A81 are interconnected, A72 and A82 are interconnected, and A73 and A83 are interconnected.

[0278] In at least one embodiment of the present invention, the driving circuit further includes a first energy storage circuit and a second energy storage circuit; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; the display substrate further includes a first metal layer disposed between the base substrate and the first gate metal layer;

[0279] The first metal layer includes a first plate of a first capacitor and a first plate of a second capacitor, and the first gate metal layer includes a second plate of the first capacitor and a second plate of the second capacitor;

[0280] The first electrode plate of the second capacitor is electrically connected to the fifth conductive connecting portion, and the second electrode plate of the second capacitor is coupled to the second voltage line;

[0281] The first electrode plate of the first capacitor is coupled to the gate of the seventh transistor through a ninth conductive connection portion formed on the first source-drain metal layer;

[0282] The second electrode plate of the first capacitor is connected to the tenth conductive connection portion and is located in the same layer. The tenth conductive connection portion is electrically connected to the driving signal output terminal formed in the first source-drain metal layer.

[0283] In a preferred embodiment, the first plate of the first capacitor and the second plate of the first capacitor both extend along a first direction;

[0284] The orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the seventh transistor on the substrate, and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the seventh transistor on the substrate.

[0285] Optionally, the orthographic projection of the first plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first voltage line on the substrate, and the orthographic projection of the second plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first voltage line on the substrate.

[0286] In a specific implementation, the second capacitor can be disposed under T1, T2, T3, T4, T5 and T6, so as to utilize the space under T1, T2, T3, T4, T5 and T6 to set the second capacitor, which is conducive to achieving a narrow frame.

[0287] In at least one embodiment of the present invention, the first electrode plate of the second capacitor and the second electrode plate of the second capacitor may extend along the second direction, but the present invention is not limited thereto.

[0288] In a specific implementation, the first direction and the second direction may intersect. For example, the second direction may be a horizontal direction, but is not limited thereto.

[0289] like Figure 8-Figure 14 As shown, the orthographic projection of C2a on the substrate partially overlaps with the orthographic projection of the high voltage line VGH on the substrate, and the orthographic projection of C2b on the substrate partially overlaps with the orthographic projection of the high voltage line VGH on the substrate, so as to save lateral space and facilitate the realization of a narrow frame.

[0290] like Fig. 9 As shown, the first metal layer includes a first plate C1a of a first capacitor and a first plate C2a of a second capacitor. Fig.10 As shown, the first gate metal layer includes a second plate C1b of the first capacitor and a second plate C2b of the second capacitor;

[0291] like Figure 8-Figure 14 As shown, the first electrode plate C2a of the second capacitor is electrically connected to the fifth conductive connection portion L5, and the second electrode plate C2b of the second capacitor is coupled to the low voltage line VGL;

[0292] The first electrode plate C1a of the first capacitor is coupled to the gate G7 of the seventh transistor through a ninth conductive connection portion L9 formed on the first source-drain metal layer;

[0293] The second electrode plate C1b of the first capacitor is connected to the tenth conductive connection portion L10 and is located in the same layer. The tenth conductive connection portion L10 is electrically connected to the driving signal output terminal GOUT formed in the first source-drain metal layer.

[0294] like Figure 8-Figure 14 As shown, C1a and C1b both extend in the vertical direction, and the orthographic projection of C1a on the substrate substrate at least partially overlaps with the orthographic projection of the first electrode S7 of the seventh transistor on the substrate substrate, and the orthographic projection of C1b on the substrate substrate at least partially overlaps with the orthographic projection of the first electrode S7 of the seventh transistor on the substrate substrate, so that the first capacitor is set by utilizing the longitudinal space that at least partially overlaps with the first electrode of the seventh transistor, so as to save lateral space and facilitate the realization of a narrow frame.

[0295] Optionally, the display substrate further comprises a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the base substrate;

[0296] The first clock signal line includes a first clock signal line portion and a second clock signal line portion coupled to each other, and the second clock signal line includes a third clock signal line portion and a fourth clock signal line portion coupled to each other;

[0297] The first clock signal line portion and the third clock signal line portion are both formed in a first source-drain metal layer;

[0298] The second clock signal line portion and the fourth clock signal line portion are both formed in a second source-drain metal layer.

[0299] In at least one embodiment of the present invention, the first clock signal line portion, the second clock signal line portion, the third clock signal line portion, and the fourth clock signal line portion may all extend along a first direction.

[0300] exist Fig.13 Among them, the part labeled CK1 is the first clock signal line part, and the part labeled CB1 is the third clock signal line part;

[0301] like Fig.14 As shown, the part labeled CK2 is the second clock signal line part, and the part labeled CB2 is the fourth clock signal line part;

[0302] like Figure 8-Figure 14 As shown, CK1 and CK2 are coupled to each other, and CB1 and CB2 are coupled to each other, so as to reduce the resistance of the first clock signal line and reduce the resistance of the second clock signal line.

[0303] The display device described in the embodiment of the present invention includes the above-mentioned display substrate.

[0304] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0305] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: The invention comprises a driving circuit disposed on a substrate, wherein the driving circuit comprises a potential control circuit; The potential control circuit is electrically connected to the first voltage line, the first node and the first output node respectively, and is used to control the connection or disconnection between the first node and the first output node according to the potential of the first node and / or the potential of the first output node under the control of the first voltage signal provided by the first voltage line; The driving circuit also includes a first node control circuit and a second node control circuit; The first node control circuit is electrically connected to the first clock signal line, the input end and the first node respectively, and is used to control the connection or disconnection between the first node and the input end under the control of the first clock signal provided by the first clock signal line; The second node control circuit is electrically connected to the first node, the first clock signal line and the second node respectively, and is used to control the connection or disconnection between the first clock signal line and the second node under the control of the potential of the first node; The driving circuit also includes a first output node control circuit; The first output node control circuit is electrically connected to the second node, the third node, the first output node, the second clock signal line and the second voltage line respectively, and is used to control the connection or disconnection between the third node and the second voltage line under the control of the potential of the second node, and control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line; The driving circuit further includes a first output circuit; The first output circuit is electrically connected to the first output node, the drive signal output terminal and the second clock signal line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second clock signal line under the control of the potential of the first output node.

2. The display substrate according to claim 1, wherein: The potential control circuit includes a first transistor; A gate of the first transistor is electrically connected to the first voltage line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the first output node.

3. The display substrate according to claim 1, wherein: The second node control circuit is also electrically connected to the first voltage line, and is used to control the connection or disconnection between the second node and the first voltage line under the control of the first clock signal.

4. The display substrate according to claim 3, wherein: The second node is electrically connected to the second output node; or, The driving circuit also includes a first control circuit; the first control circuit is electrically connected to the first voltage line, the second node and the second output node, respectively, and is used to control the connection or disconnection between the second node and the second output node according to the potential of the second node and / or the potential of the second output node under the control of the first voltage signal provided by the first voltage line.

5. The display substrate according to claim 1, wherein: The driving circuit further includes a second output circuit, a first energy storage circuit and a second energy storage circuit; The second output circuit is electrically connected to the second output node, the drive signal output terminal and the second voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node; A first end of the first energy storage circuit is electrically connected to the first output node, a second end of the first energy storage circuit is electrically connected to the drive signal output terminal, and the first energy storage circuit is used to store electrical energy; A first end of the second energy storage circuit is electrically connected to the second output node, a second end of the second energy storage circuit is electrically connected to the second voltage line, and the second energy storage circuit is used to store electrical energy.

6. The display substrate according to claim 3, wherein: The second node control circuit includes a second transistor and a third transistor; The gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal line, and the second electrode of the second transistor is electrically connected to the second node; A gate of the third transistor is electrically connected to the first clock signal line, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the second node.

7. The display substrate according to claim 5, wherein: The first node control circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the first node; The first output node control circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second voltage line, and the second electrode of the fifth transistor is electrically connected to the third node; The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first output node; The first output circuit includes a seventh transistor, the second output circuit includes an eighth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The gate of the seventh transistor is electrically connected to the first output node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the drive signal output terminal; The gate of the eighth transistor is electrically connected to the second output node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the drive signal output terminal; The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal; The first plate of the second capacitor is electrically connected to the second output node, and the second plate of the second capacitor is electrically connected to the second voltage line.

8. The display substrate according to claim 4, wherein: The first control circuit includes a ninth transistor; A gate of the ninth transistor is electrically connected to the first voltage line, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the second output node.

9. The display substrate according to any one of claims 1 to 8, characterized in that: All transistors included in the driving circuit are oxide transistors.

10. The display substrate according to any one of claims 1 to 8, characterized in that: The display substrate comprises a semiconductor layer, a second gate metal layer and a first source-drain metal layer which are sequentially arranged on the base substrate; The first voltage line is formed on the first source-drain metal layer, the semiconductor layer includes an active layer pattern of a transistor included in the potential control circuit, and the positive projection of the first voltage line on the substrate is located on a side of the positive projection of the active layer pattern of the transistor included in the potential control circuit on the substrate close to the display area; The gate of the transistor included in the potential control circuit and the first conductive connection portion are both formed in the second gate metal layer, and the gate of the transistor included in the potential control circuit is connected to the first conductive connection portion; the first conductive connection portion is coupled to the first voltage line.

11. The display substrate according to claim 10, wherein: The driving circuit also includes a first node control circuit; The transistors included in the first node control circuit and the transistors included in the potential control circuit are arranged along a first direction.

12. The display substrate according to claim 11, wherein: The transistor included in the potential control circuit is a first transistor, the transistor included in the first node control circuit is a fourth transistor, the drive circuit further includes a first output node control circuit; the first output node control circuit includes a fifth transistor and a sixth transistor; The fourth transistor, the first transistor, the sixth transistor, and the fifth transistor are arranged along a first direction.

13. The display substrate according to claim 10, wherein: The driving circuit further includes a first output circuit; the transistor included in the potential control circuit is a first transistor, the driving circuit in the display substrate further includes a second node control circuit and a first output circuit, the second node control circuit includes a second transistor; the first output circuit includes a seventh transistor; The display substrate further includes a first gate metal layer disposed between the base substrate and the semiconductor layer; The gate of the second transistor is formed on the first gate metal layer, and the gate of the seventh transistor and the second conductive connection portion connected to each other are formed on the second gate metal layer; The second conductive connection portion is coupled to the gate of the second transistor; The active layer pattern of the first transistor includes a first electrode of the first transistor, a second electrode of the first transistor, and a first channel portion disposed between the first electrode of the first transistor and the second electrode of the first transistor; The first electrode of the first transistor is coupled to the gate of the second transistor through a third conductive connection portion formed on the first source-drain metal layer.

14. The display substrate according to claim 13, wherein: The driving circuit further includes a first output node control circuit, the first output node control circuit includes a fifth transistor and a sixth transistor; the second node control circuit further includes a third transistor; The semiconductor layer includes an active layer pattern of the fifth transistor and an active layer pattern of the sixth transistor; The active layer pattern of the first transistor, the active layer pattern of the sixth transistor and the active layer pattern of the fifth transistor are continuous with each other; The active layer pattern of the fifth transistor includes a first electrode of the fifth transistor, a second electrode of the fifth transistor, and a fifth channel portion disposed between the first electrode of the fifth transistor and the second electrode of the fifth transistor; The first electrode of the fifth transistor is coupled to the second voltage line; The orthographic projection of the second voltage line on the substrate is located on a side of the orthographic projection of the first electrode of the fifth transistor on the substrate away from the display area; The second voltage line is formed in the first source-drain metal layer; The gate and the fourth conductive connection portion of the fifth transistor which are interconnected are both formed on the second gate metal layer, the fourth conductive connection portion is coupled to the fifth conductive connection portion formed on the first source-drain metal layer; the fifth conductive connection portion is electrically connected to the second electrode of the third transistor; The first electrode of the third transistor is coupled to the first voltage line; The first voltage line and the second voltage line both extend along a first direction.

15. The display substrate according to claim 14, wherein: The driving circuit further includes a first node control circuit, the first node control circuit including a fourth transistor; The first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the second gate metal layer; The first gate of the third transistor is formed on the first gate metal layer, and the second gate of the third transistor is formed on the second gate metal layer; The first gate of the fourth transistor is connected to the first gate of the third transistor, and the second gate of the fourth transistor is connected to the second gate of the third transistor; The first gate of the fourth transistor and the second gate of the fourth transistor are both coupled to the first clock signal line; The semiconductor layer includes an active layer pattern of the second transistor and an active layer pattern of the fourth transistor; The active layer pattern of the second transistor includes a first electrode of the second transistor, a second electrode of the second transistor, and a second channel portion disposed between the first electrode of the second transistor and the second electrode of the second transistor; The first electrode of the second transistor is electrically connected to the first gate of the third transistor through a connecting conductive portion formed on the first source-drain metal layer; the second electrode of the second transistor is electrically connected to the fifth conductive connecting portion; The active layer pattern of the fourth transistor includes a first electrode of the fourth transistor, a second electrode of the fourth transistor, and a fourth channel portion arranged between the first electrode of the fourth transistor and the second electrode of the fourth transistor; the first electrode of the fourth transistor is electrically connected to an input terminal formed in the second gate metal layer through a sixth conductive connection portion formed in the first source-drain metal layer.

16. The display substrate according to claim 15, wherein: The active layer pattern of the first transistor is continuous with the active layer pattern of the sixth transistor; The active layer pattern of the first transistor, the active layer pattern of the sixth transistor, the active layer pattern of the fifth transistor and the active layer pattern of the fourth transistor constitute a first active layer pattern, and the first active layer pattern extends along a first direction.

17. The display substrate according to claim 16, wherein: The gate and the seventh conductive connection portion of the sixth transistor which are connected to each other are formed in the second gate metal layer, and the seventh conductive connection portion is electrically connected to the second clock signal line; The first clock signal line and the second clock signal line are located at a side of the second voltage line away from the display area.

18. The display substrate according to claim 17, wherein: The driving circuit further includes a second output circuit, wherein the second output circuit includes an eighth transistor; The gate of the sixth transistor is connected to the eighth conductive connection portion and is located in the same layer; The eighth conductive connection portion is coupled to the first electrode of the seventh transistor; The second electrode of the seventh transistor is electrically connected to the drive signal output terminal, and the first electrode of the seventh transistor, the second electrode of the seventh transistor and the drive signal output terminal are all formed in the first source-drain metal layer; The gate of the eighth transistor is coupled to the fifth conductive connection portion, the second electrode of the eighth transistor is electrically connected to the drive signal output terminal, the gate of the eighth transistor is formed on the second gate metal layer, and the second electrode of the eighth transistor is formed on the first source-drain metal layer; The seventh transistor and the eighth transistor are arranged on a side of the first voltage line close to the display area.

19. The display substrate according to claim 18, wherein: The semiconductor layer includes an active layer pattern of a seventh transistor and an active layer pattern of an eighth transistor; the active layer pattern of the seventh transistor includes A seventh active layer patterns, and the active layer pattern of the eighth transistor includes A eighth active layer patterns; A is a positive integer; The ath seventh active layer pattern and the ath eighth active layer pattern are connected to each other.

20. The display substrate according to claim 18, wherein: The driving circuit further includes a first energy storage circuit and a second energy storage circuit; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; the display substrate further includes a first metal layer disposed between the base substrate and the first gate metal layer; The first metal layer includes a first plate of a first capacitor and a first plate of a second capacitor, and the first gate metal layer includes a second plate of the first capacitor and a second plate of the second capacitor; The first electrode plate of the second capacitor is electrically connected to the fifth conductive connecting portion, and the second electrode plate of the second capacitor is coupled to the second voltage line; The first electrode plate of the first capacitor is coupled to the gate of the seventh transistor through a ninth conductive connection portion formed on the first source-drain metal layer; The second electrode plate of the first capacitor is connected to the tenth conductive connection portion and is located in the same layer. The tenth conductive connection portion is electrically connected to the driving signal output terminal formed in the first source-drain metal layer.

21. The display substrate according to claim 20, wherein: The first plate of the first capacitor and the second plate of the first capacitor both extend along a first direction; The orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the seventh transistor on the substrate, and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode of the seventh transistor on the substrate.

22. The display substrate according to claim 20, wherein: The orthographic projection of the first plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first voltage line on the substrate, and the orthographic projection of the second plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first voltage line on the substrate.

23. The display substrate according to claim 21, wherein: The display substrate further comprises a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the base substrate; The first clock signal line includes a first clock signal line portion and a second clock signal line portion coupled to each other, and the second clock signal line includes a third clock signal line portion and a fourth clock signal line portion coupled to each other; The first clock signal line portion and the third clock signal line portion are both formed in a first source-drain metal layer; The second clock signal line portion and the fourth clock signal line portion are both formed in a second source-drain metal layer; The first clock signal line portion, the second clock signal line portion, the third clock signal line portion, and the fourth clock signal line portion all extend along a first direction.

24. A display device, characterized in that: The display substrate comprises a display substrate as claimed in any one of claims 1 to 23.

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