Pixel circuit, driving method thereof, display substrate and display device

Abstract

The application provides a pixel circuit and a driving method thereof, a display substrate and a display device, and relates to the technical field of display, and aims to solve the short-term residual image and slow response time caused by the hysteresis phenomenon of a display screen and other adverse problems. In the pixel circuit, a data writing circuit is used for controlling the communication between a data line and a second end of a driving circuit under the control of a first scanning signal provided by a first scanning line; a reset circuit is used for controlling the communication between a reset voltage line and the second end of the driving circuit under the control of a third scanning signal provided by a third scanning line; or the reset circuit is coupled with the third scanning line, the reset voltage line and a first end of the driving circuit, and is used for controlling the communication between the reset voltage line and the first end of the driving circuit under the control of the third scanning signal; and the pixel circuit provided by the application is used for driving a light emitting element display.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to application number PCT / CN2021 / 109894, filed on July 30, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, a display substrate, and a display device. Background Technology

[0004] With the increasing popularity of active-matrix organic light-emitting diode (AMOLED) displays in the mid-to-high-end market, the quality requirements for AMOLED displays are becoming increasingly stringent, and more sophisticated design requirements are being placed on them.

[0005] In the pixel circuitry of an AMOLED display, the characteristics of the driving transistors will shift after operating at a certain bias voltage for a period of time, a phenomenon known as hysteresis. This can lead to problems such as short-term image retention and slow response time. Summary of the Invention

[0006] The purpose of this invention is to provide a pixel circuit and its driving method, a display substrate, and a display device to solve problems such as short-term image retention and slow response time caused by hysteresis in the display screen.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A first aspect of the present invention provides a pixel circuit, comprising: a driving circuit, a data writing circuit, and a reset circuit;

[0009] The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the connection between the data line and the second end of the driving circuit under the control of the first scan signal provided by the first scan line.

[0010] The reset circuit is coupled to the third scan line, the reset voltage line and the second terminal of the driving circuit, respectively, and is used to control the connection between the reset voltage line and the second terminal of the driving circuit under the control of the third scan signal provided by the third scan line; or, the reset circuit is coupled to the third scan line, the reset voltage line and the first terminal of the driving circuit, respectively, and is used to control the connection between the reset voltage line and the first terminal of the driving circuit under the control of the third scan signal.

[0011] The driving circuit is used to control the connection between the first terminal and the second terminal of the driving circuit under the control of the potential at its control terminal.

[0012] Optionally, the pixel circuit further includes: a compensation control circuit, a first initialization circuit, a light emission control circuit, an energy storage circuit, and a light emission element;

[0013] The compensation control circuit is electrically connected to the second scan line, the control terminal of the driving circuit, and the first terminal of the driving circuit, respectively, and is used to control the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the second scan signal provided by the second scan line;

[0014] The first initialization circuit is coupled to the initialization control line, the first initialization voltage line and the control terminal of the drive circuit respectively, and is used to control the first initialization voltage line and the control terminal of the drive circuit to connect under the control of the initialization control signal provided by the initialization control line;

[0015] The light-emitting control circuit is coupled to the light-emitting control line, the first end of the driving circuit and the light-emitting element, respectively, and is used to control the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line;

[0016] The energy storage circuit is coupled to the control terminal of the drive circuit and the second terminal of the drive circuit.

[0017] Optionally, the pixel circuit further includes: a second initialization circuit;

[0018] The second initialization circuit is coupled to the third scan line, the second initialization voltage line and the light-emitting element respectively, and is used to control the connection between the second initialization voltage line and the light-emitting element under the control of the third scan signal.

[0019] Optionally, the first initialization voltage line is multiplexed as the reset voltage line.

[0020] Optionally, the light-emitting control circuit is also coupled to the first voltage line and the second terminal of the driving circuit, and is used to control the connection between the first voltage line and the second terminal of the driving circuit under the control of the light-emitting control signal.

[0021] Optionally, the compensation control circuit includes a first transistor, the first initialization circuit includes a second transistor, the driving circuit includes a third transistor, and the light emission control circuit includes a fifth transistor and a sixth transistor.

[0022] The gate of the first transistor is coupled to the second scan line, the first terminal of the first transistor is coupled to the second terminal of the third transistor, and the second terminal of the first transistor is coupled to the gate of the third transistor.

[0023] The gate of the second transistor is coupled to the initialization control line, the first terminal of the second transistor is coupled to the first initialization voltage line, and the second terminal of the second transistor is coupled to the gate of the third transistor.

[0024] The gate of the fifth transistor is coupled to the light-emitting control line, the first terminal of the fifth transistor is coupled to the first voltage line, and the second terminal of the fifth transistor is coupled to the first terminal of the third transistor.

[0025] The gate of the sixth transistor is coupled to the light-emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the light-emitting element.

[0026] Optionally, the first transistor and the second transistor are oxide thin-film transistors.

[0027] Optionally, the second initialization circuit includes a seventh transistor.

[0028] The gate of the seventh transistor is coupled to the third scan line, the first electrode of the seventh transistor is coupled to the second initialization voltage line, and the second electrode of the seventh transistor is coupled to the light-emitting element.

[0029] Optionally, the data writing circuit includes a fourth transistor, and the reset circuit includes an eighth transistor;

[0030] The gate of the fourth transistor is coupled to the first scan line, the first electrode of the fourth transistor is coupled to the data line, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.

[0031] The gate of the eighth transistor is coupled to the third scan line, the first terminal of the eighth transistor is coupled to the reset voltage line, and the second terminal of the eighth transistor is coupled to either the first or second terminal of the third transistor.

[0032] Based on the above-described pixel circuit technical solution, a second aspect of the present invention provides a driving method applied to the above-described pixel circuit, wherein the display cycle includes a write compensation stage and a bias compensation stage, and the driving method includes:

[0033] During the write compensation phase, the data writing circuit, under the control of the first scan signal, controls the connection between the data line and the second terminal of the drive circuit.

[0034] During the bias compensation stage, the reset circuit, under the control of the third scan signal, controls the connection between the reset voltage line and the second terminal of the drive circuit; or, under the control of the third scan signal, the reset circuit controls the connection between the reset voltage line and the first terminal of the drive circuit.

[0035] Optionally, the display cycle may further include an initialization phase and a light-emitting phase;

[0036] During the initialization phase, the first initialization circuit in the pixel circuit, under the control of the initialization control signal, controls the first initialization voltage line to connect with the control terminal of the driving circuit.

[0037] During the write compensation stage, the compensation control circuit in the pixel circuit, under the control of the second scan signal, controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit.

[0038] During the light-emitting stage, the light-emitting control circuit in the pixel circuit controls the connection between the first voltage line and the second terminal of the driving circuit under the control of the light-emitting control signal, and controls the connection between the first terminal of the driving circuit and the light-emitting element, so that the driving circuit drives the light-emitting element to emit light.

[0039] Optionally, the display cycle may further include multiple light-emitting stages and multiple bias compensation stages, with the light-emitting stages and the bias compensation stages being alternately set.

[0040] Based on the above-described pixel circuit technical solution, a third aspect of the present invention provides a display substrate, including a substrate and a plurality of sub-pixels disposed on the substrate, wherein the sub-pixels include the above-described pixel circuit; the sub-pixels further include:

[0041] The data line includes a reset voltage line, a first scan line, and a third scan line; the data line includes at least a portion extending along a first direction, the first scan line includes at least a portion extending along a second direction, and the third scan line includes at least a portion extending along the second direction, the second direction intersecting the first direction.

[0042] The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the connection between the data line and the second end of the driving circuit under the control of the first scan signal provided by the first scan line;

[0043] The reset circuit is coupled to the third scan line and the reset voltage line respectively, and is also coupled to the first or second terminal of the driving circuit. It is used to control the connection between the reset voltage line and the second terminal of the driving circuit under the control of the third scan signal provided by the third scan line; or to control the connection between the reset voltage line and the first terminal of the driving circuit.

[0044] Optionally, the driving circuit includes a third transistor, and the reset circuit includes an eighth transistor;

[0045] The gate of the eighth transistor is coupled to the third scan line, the first terminal of the eighth transistor is coupled to the reset voltage line, and the second terminal of the eighth transistor is coupled to the first terminal of the third transistor.

[0046] The reset voltage line includes at least a portion extending along the first direction, and the reset voltage line and the data line are arranged along the second direction; the orthogonal projection of the reset voltage line on the substrate at least partially overlaps with the orthogonal projection of the gate of the driving transistor on the substrate.

[0047] Optionally, the eighth transistor includes an eighth active layer, the eighth active layer including at least a portion extending along the first direction;

[0048] At least a portion of the orthographic projection of the eighth active layer onto the substrate is located between the orthographic projection of the data line onto the substrate and the orthographic projection of the reset voltage line onto the substrate;

[0049] The orthographic projection of the eighth active layer on the substrate and the orthographic projection of the gate of the driving transistor on the substrate are aligned along the first direction.

[0050] Optionally, the sub-pixel further includes a first conductive connection portion, which is coupled to the second electrode of the eighth transistor and the first electrode of the third transistor, respectively;

[0051] At least a portion of the orthographic projection of the first conductive connection portion onto the substrate is located between the orthographic projection of the data line onto the substrate and the orthographic projection of the reset voltage line onto the substrate.

[0052] Optionally, the driving circuit includes a third transistor, and the reset circuit includes an eighth transistor;

[0053] The gate of the eighth transistor is coupled to the third scan line, the first terminal of the eighth transistor is coupled to the reset voltage line, and the second terminal of the eighth transistor is coupled to the second terminal of the third transistor.

[0054] The reset voltage line includes at least a portion extending along the first direction, and the reset voltage line and the data line are arranged along the second direction; the orthographic projection of the gate of the driving transistor on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the reset voltage line on the substrate.

[0055] Optionally, the eighth transistor includes an eighth active layer, the eighth active layer including at least a portion extending along the first direction;

[0056] The orthographic projection of the eighth active layer on the substrate at least partially overlaps with the orthographic projection of the reset voltage line on the substrate.

[0057] Optionally, the sub-pixel further includes a second conductive connection portion, which is coupled to the second electrode of the eighth transistor and the second electrode of the third transistor, respectively;

[0058] The orthographic projection of the second conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the reset voltage line on the substrate.

[0059] Optionally, the sub-pixel further includes: a first initialization voltage line, the first initialization voltage line including at least a portion extending along a second direction; in two adjacent sub-pixels along the first direction, the first initialization voltage line in one sub-pixel is multiplexed as the reset voltage line in the other sub-pixel.

[0060] Based on the above-described display substrate technical solution, a second aspect of the present invention provides a display device including the above-described display substrate.

[0061] In the technical solution provided by this invention, by setting the reset circuit, a bias voltage with the opposite sign to that of the light-emitting stage can be applied to the driving circuit during the bias compensation stage. This compensates for the characteristic shift of the driving circuit after operating at a certain bias voltage for a period of time, improving problems such as short-term image retention and slow response time. Furthermore, during low-frequency driving, it can compensate for brightness differences caused by the characteristic shift of the driving circuit during a long light-emitting stage, improving flicker phenomena. Additionally, when the technical solution provided by this invention is applied to a display substrate, specific bias voltage compensation can be achieved for the driving circuit in each pixel circuit of the display substrate, resulting in good compensation effects. Moreover, since the reset voltage provided by the reset voltage line can be independently adjusted, a suitable bias voltage can be provided to each pixel circuit in the display substrate as needed. Attached Figure Description

[0062] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0063] Figure 1 This is a first structural schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0064] Figure 2 This is a schematic diagram of the second structure of the pixel circuit provided in an embodiment of the present invention;

[0065] Figure 3 This is a first circuit diagram of a pixel circuit provided in an embodiment of the present invention;

[0066] Figure 4 This is a schematic diagram of characteristic offset provided in an embodiment of the present invention;

[0067] Figure 5 This is a first driving timing diagram of the pixel circuit provided in an embodiment of the present invention;

[0068] Figure 6 This is a second driving timing diagram of the pixel circuit provided in an embodiment of the present invention;

[0069] Figure 7 This is a second circuit diagram of the pixel circuit provided in an embodiment of the present invention;

[0070] Figure 8 A third circuit diagram of the pixel circuit provided in an embodiment of the present invention;

[0071] Figure 9 A fourth circuit diagram of the pixel circuit provided in an embodiment of the present invention;

[0072] Figure 10 This is a schematic diagram of the layout of a display substrate provided in an embodiment of the present invention;

[0073] Figure 11 for Figure 3 Corresponding layout diagram;

[0074] Figure 12 for Figure 11 A schematic diagram of the layout of the poly active layer in the diagram;

[0075] Figure 13 for Figure 11 A schematic diagram of the layout of the first gate metal layer in the middle;

[0076] Figure 14 for Figure 11 A schematic diagram of the layout of the second gate metal layer;

[0077] Figure 15 for Figure 11 A schematic diagram of the layout of the oxide active layer in the image;

[0078] Figure 16 for Figure 11 A schematic diagram of the layout of the third gate metal layer;

[0079] Figure 17 for Figure 11 A schematic diagram of the first connecting hole in the middle;

[0080] Figure 18 forFigure 11 A schematic diagram of the second connecting hole;

[0081] Figure 19 for Figure 11 A schematic diagram of the layout of the first source / drain metal layer in the image;

[0082] Figure 20 for Figure 11 A schematic diagram of the vias formed by the passivation layer in the middle;

[0083] Figure 21 for Figure 11 A schematic diagram of the via formed by the first planarization layer in the middle;

[0084] Figure 22 for Figure 11 A schematic diagram of the layout of the second source / drain metal layer in the image;

[0085] Figure 23 for Figure 8 Corresponding layout diagram;

[0086] Figure 24 for Figure 23 A schematic diagram of the layout of the poly active layer in the diagram;

[0087] Figure 25 for Figure 23 A schematic diagram of the layout of the first gate metal layer in the middle;

[0088] Figure 26 for Figure 23 A schematic diagram of the layout of the first source / drain metal layer in the image;

[0089] Figure 27 for Figure 23 A schematic diagram of the vias formed by the passivation layer in the middle;

[0090] Figure 28 for Figure 23 A schematic diagram of the via formed by the first planarization layer in the middle;

[0091] Figure 29 for Figure 23 A schematic diagram of the layout of the second source / drain metal layer in the image;

[0092] Figure 30 for Figure 9 Corresponding layout diagram;

[0093] Figure 31 for Figure 30 A schematic diagram of the layout of the first source / drain metal layer in the image;

[0094] Figure 32 for Figure 30 A schematic diagram of the layout of the second source / drain metal layer in the image;

[0095] Figure 33 This is a schematic diagram of the stacking of the second gate metal layer to the third gate metal layer provided in an embodiment of the present invention;

[0096] Figure 34 A cross-sectional schematic diagram of the eighth transistor provided in an embodiment of the present invention;

[0097] Figure 35 for Figure 30 A schematic diagram of the layout of the poly active layer in the diagram;

[0098] Figure 36 for Figure 30 A schematic diagram of the layout of the first gate metal layer in the middle;

[0099] Figure 37 for Figure 30 A schematic diagram of the layout of the oxide active layer in the image;

[0100] Figure 38 for Figure 30 A schematic diagram of the first connecting hole in the middle;

[0101] Figure 39 for Figure 30 A schematic diagram of the second connecting hole. Detailed Implementation

[0102] To further illustrate the pixel circuit and its driving method, display substrate, and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0103] Please see Figure 1 , Figure 2 , Figure 3 , Figures 7 to 9 The present invention provides a pixel circuit, including: a driving circuit 11, a data writing circuit 41 and a reset circuit 20;

[0104] The data writing circuit 41 is coupled to the first scan line S1, the data line D1 and the second end of the driving circuit 11 respectively, and is used to control the connection between the data line D1 and the second end of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1.

[0105] The reset circuit 20 is coupled to the third scan line S3, the reset voltage line DR, and the second terminal of the drive circuit 11, respectively, and is used to control the connection between the reset voltage line DR and the second terminal (i.e., the second node N2) of the drive circuit 11 under the control of the third scan signal provided by the third scan line S3; or, the reset circuit 20 is coupled to the third scan line S3, the reset voltage line DR, and the first terminal (i.e., the third node N3) of the drive circuit 11, respectively, and is used to control the connection between the reset voltage line DR and the first terminal of the drive circuit 11 under the control of the third scan signal.

[0106] The driving circuit 11 is used to control the connection between the first terminal and the second terminal of the driving circuit 11 under the control of the potential at its control terminal.

[0107] For example, the first scan line S1 is used to write the first scan signal, and the data line D1 is used to write the data signal. The third scan line S3 is used to write the third scan signal. The reset voltage line DR is used to provide a reset voltage.

[0108] like Figure 5 and Figure 6 As shown, exemplarily, the data signal is used for conventional image display. The reset voltage can change with the data signal. During the bias compensation phase, P2 applies a bias voltage with the opposite sign to that of the driving transistor included in the driving circuit 11, which is opposite to that of the light-emitting phase P4. For example, during the light-emitting phase, the bias voltage Vgs (or Vgd) of the driving transistor P4 is 5V, and during the compensation phase, the reset voltage line DR makes the bias voltage of the driving transistor -5V.

[0109] For example, when the first scan signal is at an active level, the data writing circuit 41 is used to connect the data line D1 to the second terminal of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1. When the first scan signal is at an inactive level, the data writing circuit 41 is used to disconnect the electrical connection between the data line D1 and the second terminal of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1.

[0110] For example, when the third scan signal is at an active level, the reset circuit 20 is configured to, under the control of the third scan signal, connect the reset voltage line DR to either the second terminal or the first terminal of the drive circuit 11. When the third scan signal is at an inactive level, the reset circuit 20 is configured to, under the control of the third scan signal, disconnect the electrical connection between the reset voltage line DR and either the second terminal or the first terminal of the drive circuit 11.

[0111] For example, one display cycle of the pixel circuit operation includes: a write compensation phase P3 and a bias compensation phase P2.

[0112] During the write compensation stage P3, the data writing circuit 41, under the control of the first scan signal, controls the data line D1 to connect with the second end of the drive circuit 11, and writes a data signal to the second end of the drive circuit 11.

[0113] During the bias compensation stage P2, the reset circuit 20, under the control of the third scan signal, controls the reset voltage line DR to connect with the second terminal of the drive circuit 11; or, under the control of the third scan signal, the reset circuit 20 controls the reset voltage line DR to connect with the first terminal of the drive circuit 11; so as to write a reset voltage to the first or second terminal of the drive circuit 11.

[0114] As can be seen from the specific structure of the pixel circuit described above, in the pixel circuit provided by the embodiment of the present invention, by setting the reset circuit 20, a bias voltage with the opposite sign to that of the light emission stage P4 can be applied to the driving circuit 11 during the bias compensation stage P2, thereby compensating for the characteristic shift of the driving circuit 11 after it has been operating at a certain bias voltage for a period of time, and improving problems such as short-term image retention and slow response time. Moreover, during low-frequency driving, it can compensate for the brightness difference caused by the characteristic shift of the driving circuit 11 during the long light emission stage, and improve the flicker phenomenon.

[0115] In addition, when the pixel circuit provided in the embodiments of the present invention is applied to a display substrate, specific bias compensation can be achieved for the driving circuit 11 in each pixel circuit of the display substrate, which has a good compensation effect.

[0116] Furthermore, since the reset voltage provided by the reset voltage line DR can be adjusted independently, a suitable bias voltage can be provided to each pixel circuit in the display substrate as needed.

[0117] like Figure 2 , Figure 3 , Figures 7 to 9 As shown, in some embodiments, the pixel circuit further includes: a compensation control circuit 13, a first initialization circuit 14, a light emission control circuit 31, an energy storage circuit 42, and a light emission element O1;

[0118] The compensation control circuit 13 is electrically connected to the second scan line S2, the control terminal (i.e., the first node N1) of the driving circuit 11, and the first terminal (i.e., the third node N3) of the driving circuit 11, respectively, and is used to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the second scan signal provided by the second scan line S2.

[0119] The first initialization circuit 14 is coupled to the initialization control line R1, the first initialization voltage line Vinit1 and the control terminal of the drive circuit 11 respectively, and is used to control the first initialization voltage line Vinit1 and the control terminal of the drive circuit 11 to connect under the control of the initialization control signal provided by the initialization control line R1.

[0120] The light-emitting control circuit 31 is coupled to the light-emitting control line E1, the first end of the driving circuit 11 and the light-emitting element O1 respectively, and is used to control the first end of the driving circuit 11 and the light-emitting element O1 to communicate under the control of the light-emitting control signal provided by the light-emitting control line E1.

[0121] The energy storage circuit 42 is coupled to the control terminal of the drive circuit 11 and the second terminal of the drive circuit 11.

[0122] For example, each display cycle of the pixel circuit includes: an initialization phase P1, a bias compensation phase P2, a write compensation phase P3, and an emission phase P4.

[0123] More specifically, after the write compensation phase P3, the gate potential of the driving transistor becomes Vdata + Vth, where Vdata is the data voltage corresponding to the data signal, and Vth is the threshold voltage of the driving transistor. Upon entering the light emission phase P4, the stress on the driving transistor is Vgs1 = Vdata + Vth - VDD, where VDD is the power supply voltage received by the driving transistor. Figure 4 As shown, the characteristics of the driving transistors included in the driving circuit 11 will shift, that is, shift from the solid line to the dashed line.

[0124] During the bias compensation phase P2, the reset circuit 20 writes a reset voltage V1 to either the first or second terminal of the drive circuit 11. This reset voltage causes the drive transistor to be biased by Vgs2, where Vgs2 satisfies: Vgs2 = -Vgs1.

[0125] That is: Vgs2=Vdata+Vth-V1=-Vgs1=-(Vdata+Vth-VDD)

[0126] It should be noted that when entering the bias compensation stage P2, the gate voltage Vg of the driving transistor remains unchanged.

[0127] V1 = 2*(Vdata + Vth) - VDD

[0128] Since VDD is a fixed value, and Vth can be obtained through testing, the value relationship between V1 and Vdata can be determined. Setting V1 according to the above relationship will achieve the best compensation effect.

[0129] In the bias compensation stage P2, the driving transistor is subjected to a bias voltage of the same magnitude but opposite direction as that in the light emission stage P4, and thus... Figure 4 As shown, the characteristic curve will return from the dashed line to the solid line, thus completing the bias compensation.

[0130] like Figure 2 , Figure 3 , Figures 7 to 9 As shown, in some embodiments, the pixel circuit further includes a second initialization circuit 32;

[0131] The second initialization circuit 32 is coupled to the third scan line S3, the second initialization voltage line Vinit2 and the light-emitting element O1 respectively, and is used to control the connection between the second initialization voltage line Vinit2 and the light-emitting element O1 under the control of the third scan signal.

[0132] For example, the second initialization voltage line Vinit2 is used to provide a second initialization voltage.

[0133] The second initialization circuit 32 can reset the first electrode of the light-emitting element O1 under the control of the third scanning signal.

[0134] It should be noted that the first electrode of the light-emitting element O1 includes an anode, and the second electrode (i.e., cathode) of the light-emitting element O1 receives a negative power supply signal VSS.

[0135] like Figure 7 and Figure 9 As shown, in some embodiments, the first initialization voltage line Vinit1 is multiplexed as the reset voltage line DR.

[0136] For example, the reset circuit 20 is coupled to the first initialization voltage line Vinit1. The first initialization voltage provided by the first initialization voltage line Vinit1 is adjustable.

[0137] For example, the first initialization voltage provided by the first initialization voltage line Vinit1 is variable. For example, the first initialization voltage can be set to -5V when used for gate reset of the driving transistor, and can be set to 5V when used for bias compensation.

[0138] Setting the first initialization voltage line Vinit1 as the reset voltage line DR can simplify the sub-pixel structure, reduce the layout difficulty of sub-pixels, and improve the resolution of the display substrate.

[0139] like Figure 2 , Figure 3 , Figures 7 to 9As shown, in some embodiments, the light-emitting control circuit 31 is also coupled to the first voltage line (written VDD signal) and the second terminal of the driving circuit 11, for controlling the connection between the first voltage line and the second terminal of the driving circuit 11 under the control of the light-emitting control signal.

[0140] For example, the first voltage line includes a positive power supply line. The light emission control signal controls whether the first voltage provided by the first voltage line is written to the second terminal of the driving circuit 11.

[0141] like Figure 2 , Figure 3 , Figures 7 to 9 As shown, in some embodiments, the compensation control circuit 13 includes a first transistor T1, the first initialization circuit 14 includes a second transistor T2, the driving circuit 11 includes a third transistor T3 (i.e., the driving transistor), and the light emission control circuit 31 includes a fifth transistor T5 and a sixth transistor T6.

[0142] The gate of the first transistor T1 is coupled to the second scan line S2, the first terminal of the first transistor T1 is coupled to the second terminal of the third transistor T3, and the second terminal of the first transistor T1 is coupled to the gate T3-g of the third transistor T3.

[0143] The gate of the second transistor T2 is coupled to the initialization control line R1, the first terminal of the second transistor T2 is coupled to the first initialization voltage line Vinit1, and the second terminal of the second transistor T2 is coupled to the gate T3-g of the third transistor T3.

[0144] The gate of the fifth transistor T5 is coupled to the light-emitting control line E1, the first terminal of the fifth transistor T5 is coupled to the first voltage line, and the second terminal of the fifth transistor T5 is coupled to the first terminal of the third transistor T3.

[0145] The gate of the sixth transistor T6 is coupled to the light-emitting control line E1, the first terminal of the sixth transistor T6 is coupled to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is coupled to the light-emitting element O1.

[0146] In some embodiments, the first transistor T1 and the second transistor T2 are oxide thin-film transistors.

[0147] For example, the first transistor T1 and the second transistor T2 include low temperature polycrystalline oxide transistors (LTPO).

[0148] By setting the first transistor T1 and the second transistor T2 to be oxide thin film transistors, it is beneficial to reduce the gate leakage current of the driving transistor and ensure the stability of the gate potential of the driving transistor.

[0149] like Figure 2 , Figure 3 , Figures 7 to 9 As shown, in some embodiments, the second initialization circuit 32 includes a seventh transistor T7.

[0150] The gate of the seventh transistor T7 is coupled to the third scan line S3, the first electrode of the seventh transistor T7 is coupled to the second initialization voltage line Vinit2, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element O1.

[0151] In some embodiments, the data writing circuit 41 includes a fourth transistor T4, and the reset circuit 20 includes an eighth transistor T8;

[0152] The gate of the fourth transistor T4 is coupled to the first scan line S1, the first electrode of the fourth transistor T4 is coupled to the data line D1, and the second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3.

[0153] The gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, the first terminal of the eighth transistor T8 is coupled to the reset voltage line DR, and the second terminal of the eighth transistor T8 is coupled to the first or second terminal of the third transistor T3.

[0154] For example, such as Figure 2 , Figure 3 , Figures 7 to 9 In the diagram, node N1 is the first node, and node N1 is electrically connected to the gate of T3; node N2 is the second node, and node N3 is the third node; node N2 is electrically connected to the source of T3, and node N3 is electrically connected to the drain of T3.

[0155] For example, in at least one embodiment of the pixel circuit, T1 and T2 can be oxide thin film transistors, T3, T4, T5, T6, T7 and T8 can all be low temperature polycrystalline silicon thin film transistors, T1 and T2 are n-type transistors, and T3, T4, T5, T6, T7 and T8 are p-type transistors, but are not limited thereto.

[0156] For example, T1 and T2 can be single-gate transistors or dual-gate transistors.

[0157] For example, in the channel width-to-length ratio W / L of T1, the value of W ranges from 2 micrometers to 4 micrometers and may include endpoint values, and the value of L ranges from 3 micrometers to 6 micrometers and may include endpoint values.

[0158] For example, T2 and T1 have the same width-to-length ratio.

[0159] For example, in the channel width-to-length ratio W / L of T8, the value of W ranges from 2 micrometers to 3 micrometers and may include endpoint values, and the value of L ranges from 3.2 micrometers to 6 micrometers and may include endpoint values.

[0160] like Figure 5 and Figure 6 As shown, the specific driving process of the pixel circuit with the above structure includes:

[0161] During the initialization phase P1, R1 provides a high voltage signal, and T2 is turned on. S1 provides a high voltage signal, and T4 is turned off. S2 provides a low voltage signal, and T1 is turned off. S3 provides a high voltage signal, and T7 and T8 are turned off. During the initialization phase P1, the gate of T3 is initialized so that T3 can be turned on when the write compensation phase P3 begins.

[0162] During the bias compensation period, R1 provides a low voltage signal, and T2 is off. S1 provides a high voltage signal, and T4 is off. S2 provides a low voltage signal, and T1 is off. S3 provides a low voltage signal, and T7 and T8 are on. During the bias compensation period, the reset voltage provided by DR can be written to the first or second terminal of the third transistor T3, and the second initialization voltage can be written to the anode of O1 to initialize the anode of O1.

[0163] During the write compensation phase P3, transistor T3 is on. R1 provides a low voltage signal, and T2 is off. S1 provides a low voltage signal, and T4 is on. S2 provides a high voltage signal, and T1 is on. S3 provides a high voltage signal, and T7 and T8 are off. The data voltage Vdata on data line D1 is written to the first terminal of the third transistor T3. During the write compensation phase P3, Vdata charges capacitor C through the on-screen transistors T4, T3, and T1 to raise the gate potential of T3 until T3 is off. At this point, the gate potential of T3 is Vdata + Vth.

[0164] During the light-emitting phase P4, E1 provides a low voltage signal, R1 provides a low voltage signal, S1 provides a high voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, T1, T2, T4, T7 and T8 are turned off, T5 and T6 are turned on, and T3 is turned on to drive O1 to emit light.

[0165] Adding T8 to provide bias voltage to the first or second electrode of T3 helps improve the stability of T3; setting T7 to initialize the potential of the anode of O1 facilitates the degree of freedom in switching frequency under low-frequency flicker.

[0166] In some embodiments, the pixel circuit needs to turn on T3 during the threshold compensation stage. Therefore, the voltage difference Vi1-V1 between the first initialization voltage Vi1 provided by the first initialization voltage line Vinit1 and the reset voltage V1 provided by the reset voltage line DR needs to be less than the threshold voltage Vth of the driving transistor T3. Vi1 can be -2 to -6V, for example, -2V, -3V, -4V, -5V, -6V, etc. Vi1-V1 can be less than a*Vth, where a can be 2 to 7, for example, a can be 2, 4, 6, 7; Vth can be -2 to -5V, for example, -2V, -3V, -5V, etc. V1 can be greater than 1.5 times Vth, for example, V1 can be 1.6 times, 1.8 times, 2 times, etc. of Vth.

[0167] For example, V1 is greater than 0. The value of V1 is between 4 and 10V and may include endpoint values.

[0168] In some embodiments, the width-to-length ratio W / L of T8 can be approximately equal to the width-to-length ratio W / L of T7; for example, the width-to-length ratio W / L of T8 can be greater than the width-to-length ratio W / L of T7, that is, the width-to-length ratio W / L of T8 can be slightly larger, so that the N2 node can be quickly reset.

[0169] In some embodiments, the channel width W of T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5, for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of T7 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5, for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0170] In some embodiments, the width-to-length ratio W / L of T8 can be approximately equal to the width-to-length ratio W / L of T2; for example, the width-to-length ratio W / L of T8 can be less than the width-to-length ratio W / L of T2, thus balancing the reset capabilities of nodes N1 and N2.

[0171] In some embodiments, the channel width W of T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5, for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of T2 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5, for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0172] like Figure 1 , Figure 5 and Figure 6 As shown, this embodiment of the invention also provides a driving method applied to the pixel circuit provided in the above embodiment. The display cycle includes a write compensation stage P3 and a bias compensation stage P2. The driving method includes:

[0173] During the write compensation stage P3, the data writing circuit 41, under the control of the first scan signal, controls the data line D1 to connect with the second terminal of the drive circuit 11.

[0174] During the bias compensation stage P2, the reset circuit 20, under the control of the third scan signal, controls the reset voltage line DR to connect with the second terminal of the drive circuit 11; or, under the control of the third scan signal, the reset circuit 20 controls the reset voltage line DR to connect with the first terminal of the drive circuit 11.

[0175] When driving the pixel circuit using the driving method provided in this embodiment of the invention, a bias voltage with the opposite sign to that of the light-emitting stage P4 can be applied to the driving circuit 11 during the bias compensation stage P2. This compensates for the characteristic shift of the driving circuit 11 after operating at a certain bias voltage for a period of time, improving problems such as short-term image retention and slow response time. Furthermore, during low-frequency driving, it can compensate for brightness differences caused by the characteristic shift of the driving circuit 11 during the long light-emitting stage, improving the flicker phenomenon. In addition, it can achieve specific bias compensation for the driving circuit 11 in each pixel circuit of the display substrate, resulting in good compensation effects. Moreover, since the reset voltage provided by the reset voltage line DR can be independently adjusted, a suitable bias voltage can be provided to each pixel circuit in the display substrate as needed.

[0176] like Figure 5 and Figure 6 As shown, in some embodiments, the display cycle further includes an initialization phase P1 and an emission phase P4;

[0177] During the initialization phase P1, the first initialization circuit 14 in the pixel circuit, under the control of the initialization control signal, controls the first initialization voltage line Vinit1 and the control terminal of the driving circuit 11 to connect.

[0178] During the write compensation stage P3, the compensation control circuit 13 in the pixel circuit, under the control of the second scan signal, controls the connection between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11.

[0179] During the light emission stage P4, the light emission control circuit 31 in the pixel circuit controls the first voltage line to connect with the second terminal of the driving circuit 11 under the control of the light emission control signal, and controls the first terminal of the driving circuit 11 to connect with the light emission element O1, so that the driving circuit 11 drives the light emission element O1 to emit light.

[0180] More specifically, in the initialization phase P1, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to connect with the control terminal of the driving circuit 11, initializing the control terminal of the driving circuit 11. In the bias compensation phase P2, the reset circuit 20 controls the reset voltage line DR to connect with the second terminal of the driving circuit 11, or controls the reset voltage line DR to connect with the first terminal of the driving circuit 11. In the write compensation phase P3, the compensation control circuit 13 controls the control terminal of the driving circuit 11 to connect with the first terminal of the driving circuit 11. During at least a portion of the write compensation phase P3, the data write circuit 41 controls the data line D1 to connect with the second terminal of the driving circuit 11. In the light emission phase P4, the light emission control circuit 31 controls the first voltage line to connect with the second terminal of the driving circuit 11, and controls the first terminal of the driving circuit 11 to connect with the light-emitting element O1, causing the driving circuit 11 to drive the light-emitting element O1 to emit light.

[0181] like Figure 5 and Figure 6 As shown, in some embodiments, the display cycle further includes multiple light-emitting stages P4 and multiple bias compensation stages P2, wherein the light-emitting stages P4 and the bias compensation stages P2 are alternately arranged.

[0182] For example, the display cycle includes, in sequence: initialization phase P1, bias compensation phase P2, write compensation phase P3, light emission phase P4, bias compensation phase P2, light emission phase P4, bias compensation phase P2, light emission phase P4, bias compensation phase P2, light emission phase P4, and light emission phase P4.

[0183] It should be noted that the number of light-emitting stages P4 and the number of bias compensation stages P2 can be set according to actual needs.

[0184] The above-mentioned bias compensation is implemented in several fixed stages within a frame, which is more conducive to achieving bias compensation for the driving circuit 11 when the display substrate is in low-frequency display.

[0185] In some embodiments, the unit is the row scan time h, where 1h = 1 second / (refresh rate * total number of rows).

[0186] The width of the light emission control signal provided by the light emission control line E1 at an effective level (such as a high level) is between 30h and 40h, and may include endpoint values.

[0187] The width of the initialization control signal provided by the initialization control line R1 at an effective level (such as a high level) is between 10h and 15h, and may include endpoint values.

[0188] The width of the second scan signal provided by the second scan line S2 at an effective level (such as a high level) is between 10h and 15h, and may include endpoint values.

[0189] The width of the third scan signal provided by the third scan line S3 at an effective level (such as a low level) is between 1h and 3h, and may include endpoint values.

[0190] The width of the first scan signal provided by the first scan line S1 at an effective level (such as a low level) is between 1h and 3h, and may include endpoint values.

[0191] The effective level width of the data signal provided by the data line D1 includes 1h.

[0192] For example, the effective level width of the light emission control signal is 2 to 4 times the effective level width of the initialization control signal.

[0193] For example, the effective level width of the light emission control signal is 2 to 4 times the effective level width of the second scan signal.

[0194] like Figures 1 to 9 , Figure 11 , Figure 23 and Figure 30 As shown, this embodiment of the invention also provides a display substrate, including a substrate and a plurality of sub-pixels disposed on the substrate, wherein the sub-pixels include the pixel circuits provided in the above embodiments; the sub-pixels further include:

[0195] Data line D1, reset voltage line DR, first scan line S1 and third scan line S3; the data line D1 includes at least a portion extending along a first direction, the first scan line S1 includes at least a portion extending along a second direction, the third scan line S3 includes at least a portion extending along the second direction, the second direction intersecting the first direction;

[0196] The data writing circuit 41 is coupled to the first scan line S1, the data line D1 and the second end of the driving circuit 11 respectively, and is used to control the connection between the data line D1 and the second end of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1.

[0197] The reset circuit 20 is coupled to the third scan line S3 and the reset voltage line DR, and is also coupled to the first or second terminal of the drive circuit 11. It is used to control the connection between the reset voltage line DR and the second terminal of the drive circuit 11 under the control of the third scan signal provided by the third scan line S3; or to control the connection between the reset voltage line DR and the first terminal of the drive circuit 11.

[0198] For example, the above-mentioned display substrate includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes a pixel circuit.

[0199] For example, in sub-pixels located in the same column along the first direction, each data line D1 is sequentially coupled to form an integral structure.

[0200] For example, in sub-pixels located in the same column along the first direction, each reset voltage line DR is sequentially coupled to form a single structure. For example, in sub-pixels located in the same row along the second direction, each reset voltage line DR is sequentially coupled to form a single structure.

[0201] For example, in sub-pixels located in the same row along the second direction, each first scan line S1 is sequentially coupled to form a single structure. For example, in sub-pixels located in the same row along the second direction, each third scan line S3 is sequentially coupled to form a single structure.

[0202] For example, the display substrate includes the following layers stacked on the substrate in a direction away from the substrate: a light-shielding layer, an isolation layer, a first buffer layer, a poly active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, an oxide active layer (such as IGZO), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source / drain metal layer, a passivation layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, a pixel defining layer, a spacer layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer.

[0203] For example, the substrate includes a PI substrate. After depositing and forming the second interlayer insulating layer, a CNT drilling process (e.g., CNT-L / EBA and CNT-O / EBB) can be performed, followed by a masking process for the interlayer insulating layer to form vias that penetrate only the second interlayer insulating layer, vias that penetrate the second interlayer insulating layer to the third gate insulating layer, vias that penetrate the second interlayer insulating layer to the first interlayer insulating layer, vias that penetrate the second interlayer insulating layer to the second gate insulating layer, vias that penetrate the second interlayer insulating layer to the first gate insulating layer, and vias that penetrate the second interlayer insulating layer to the isolation layer.

[0204] For example, the data line D1 is fabricated using a second source-drain metal layer. The reset voltage line DR is fabricated using either a second source-drain metal layer or a first source-drain metal layer. The first scan line S1 and the third scan line S3 are both fabricated using a first gate metal layer.

[0205] For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction.

[0206] Because the pixel circuit provided in the above embodiment, by setting the reset circuit 20, can apply a bias voltage with the opposite sign to that of the light-emitting stage P4 to the driving circuit 11 during the bias compensation stage P2, it can compensate for the characteristic shift of the driving circuit 11 after operating at a certain bias voltage for a period of time, thereby improving problems such as short-term image retention and slow response time. Moreover, during low-frequency driving, it can compensate for the brightness difference caused by the characteristic shift of the driving circuit 11 during the long light-emitting stage, thus improving the flicker phenomenon. Therefore, the display substrate provided in the embodiments of the present invention, when including the above-mentioned pixel circuit, also has the above-mentioned beneficial effects, which will not be repeated here.

[0207] Furthermore, when the display substrate provided in this embodiment of the invention includes the aforementioned pixel circuit, it is possible to perform specific bias voltage compensation on the driving circuit 11 in each pixel circuit of the display substrate, resulting in a good compensation effect. In addition, since the reset voltage provided by the reset voltage line DR can be independently adjusted, a suitable bias voltage can be provided to each pixel circuit in the display substrate as needed.

[0208] In some embodiments, the display substrate includes multiple arrayed pixel circuits P and multiple reset voltage lines DR11, DR12, DR21, and DR22, all of which can be used to provide reset voltage.

[0209] like Figure 10As shown, reset voltage lines DR11 and DR12 extend along the column direction, and reset voltage lines DR21 and DR22 extend along the row direction. Adjacent row pixel circuits can be connected to the same row-extending reset voltage line DR. This reset voltage line DR can be located between the aforementioned adjacent row pixel driving circuits 11. The column-extending reset voltage line DR can connect to multiple intersecting row-extending reset voltage lines DR, thus forming a grid structure. The column-extending reset voltage line DR can be located within the area where the red pixel circuit is located. Furthermore, within the same pixel row, two pixel circuits in adjacent columns can be mirrored for easier wiring.

[0210] like Figures 11 to 22 As shown, in some embodiments, the driving circuit 11 includes a third transistor T3, and the reset circuit 20 includes an eighth transistor T8;

[0211] The gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, the first terminal of the eighth transistor T8 is coupled to the reset voltage line DR, and the second terminal of the eighth transistor T8 is coupled to the first terminal of the third transistor T3.

[0212] The reset voltage line DR includes at least a portion extending along the first direction, and the reset voltage line DR and the data line D1 are arranged along the second direction; the orthogonal projection of the reset voltage line DR on the substrate at least partially overlaps with the orthogonal projection of the gate of the driving transistor on the substrate.

[0213] For example, the gate T3-g of the third transistor T3 is fabricated using a first gate metal layer. The gate T8-g of the eighth transistor T8 is formed as an integral structure with the third scan line S3.

[0214] For example, the reset voltage line DR and the data line D1 are disposed in the same layer and made of the same material.

[0215] For example, the orthographic projection of the data line D1 on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate. The orthographic projection of the reset voltage line DR on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate.

[0216] like Figure 34 As shown, for example, the eighth transistor T8 is coupled to the reset voltage line DR via the third conductive connection 63.

[0217] It needs to be explained that, Figure 12The diagram illustrates that T3 includes a third active layer 53, T4 includes a fourth active layer 54, T5 includes a fifth active layer 55, T6 includes a sixth active layer 56, and T7 includes a seventh active layer 57. Figure 15 The diagram illustrates the first active layer 51 included in T1 and the second active layer 52 included in T2. Figure 19 The third conductive connection part 63 is shown. Figure 33 The diagram illustrates the second gate metal layer Gate2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the oxide layer (IGZO), the third gate insulating layer GI3, and the third gate metal layer Gate3.

[0218] It needs to be explained that, Figure 17 The first connection hole is used to connect the first source / drain metal layer and the corresponding structure below it. Figure 17 The depths of the various first connecting holes can be the same or different. Figure 18 The second connection hole is used to connect the first source / drain metal layer and the corresponding structure below it. Figure 18 The depths of the various second connecting holes can be the same or different.

[0219] It needs to be explained that, Figure 23 and Figure 30 In the corresponding embodiments, some single-layer films are not shown; see [link to relevant documentation]. Figure 11 The corresponding single-layer membrane is sufficient.

[0220] The above configuration helps to reduce the layout difficulty of the sub-pixels.

[0221] like Figures 11 to 22 As shown, in some embodiments, the eighth transistor T8 includes an eighth active layer 58, the eighth active layer 58 including at least a portion extending along the first direction;

[0222] At least a portion of the orthographic projection of the eighth active layer 58 onto the substrate is located between the orthographic projection of the data line D1 onto the substrate and the orthographic projection of the reset voltage line DR onto the substrate.

[0223] The orthographic projection of the eighth active layer 58 on the substrate and the orthographic projection of the gate of the driving transistor on the substrate are aligned along the first direction.

[0224] For example, the eighth active layer 58 is made of a poly active layer.

[0225] For example, the orthographic projection of the eighth active layer 58 onto the substrate at least partially overlaps with the orthographic projection of the reset voltage line DR onto the substrate.

[0226] For example, the orthographic projection of the eighth active layer 58 onto the substrate does not overlap with the orthographic projection of the data line D1 onto the substrate.

[0227] For example, at least a portion of the orthographic projection of the eighth active layer 58 onto the substrate is located between the orthographic projection of the light emission control line E1 onto the substrate and the orthographic projection of the second initialization voltage line Vinit2 onto the substrate.

[0228] The above configuration helps to reduce the layout difficulty of the sub-pixels and reduce the parasitic capacitance generated by the eighth transistor T8.

[0229] like Figures 11 to 22 As shown, in some embodiments, the sub-pixel further includes a first conductive connection portion 61, which is coupled to the second electrode of the eighth transistor T8 and the first electrode of the third transistor T3, respectively.

[0230] At least a portion of the orthographic projection of the first conductive connection portion 61 onto the substrate is located between the orthographic projection of the data line D1 onto the substrate and the orthographic projection of the reset voltage line DR onto the substrate.

[0231] For example, the first conductive connection portion 61 is made using the first source / drain metal layer.

[0232] For example, the orthographic projection of the first conductive connection portion 61 on the substrate overlaps with the orthographic projection portion of the data line D1 on the substrate, and overlaps with the orthographic projection portion of the reset voltage line DR on the substrate.

[0233] For example, the orthographic projection of the first conductive connection portion 61 on the substrate does not overlap with the orthographic projection of the data line D1 on the substrate, nor does it overlap with the orthographic projection of the reset voltage line DR on the substrate.

[0234] For example, the orthographic projection of the first conductive connection portion 61 on the substrate overlaps with the orthographic projection portion of the light-emitting control line E1 on the substrate.

[0235] For example, the orthographic projection of the first conductive connection portion 61 on the substrate does not overlap with the orthographic projection of the second plate C2 of the storage capacitor C on the substrate.

[0236] For example, the first conductive connection portion 61 is coupled to the second terminal of the eighth transistor T8 and the first terminal of the third transistor T3 through corresponding vias.

[0237] For example, the first conductive connection portion 61 includes a portion extending along the first direction and a portion extending along a third direction, which intersects both the first direction and the second direction.

[0238] The above configuration helps to reduce the layout difficulty of the sub-pixels.

[0239] like Figures 11 to 22 As shown, in some embodiments, the second initialization voltage line Vinit2 includes a main body, a first protrusion, and a second protrusion. The main body includes at least a portion extending along the second direction, and the first protrusion and the second protrusion are arranged along the second direction. The second initialization circuit 32 includes a seventh transistor T7, the gate of which is coupled to the third scan line S3, and the first electrode of which is coupled to the first protrusion. The first electrode of the eighth transistor T8 is coupled to the second protrusion.

[0240] For example, the seventh transistor T7 includes a seventh active layer, and the eighth active layer 58 is arranged along the second direction with the seventh active layer. The orthographic projection of the eighth active layer 58 on the substrate is located between the orthographic projection of the seventh active layer on the substrate and the orthographic projection of the data line D1 on the substrate.

[0241] like Figures 23 to 29 As shown, in some embodiments, the driving circuit 11 includes a third transistor T3, and the reset circuit 20 includes an eighth transistor T8;

[0242] The gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, the first terminal of the eighth transistor T8 is coupled to the reset voltage line DR, and the second terminal of the eighth transistor T8 is coupled to the second terminal of the third transistor T3.

[0243] The reset voltage line DR includes at least a portion extending along the first direction, and the reset voltage line DR and the data line D1 are arranged along the second direction; the orthogonal projection of the gate of the driving transistor on the substrate is located between the orthogonal projection of the data line D1 on the substrate and the orthogonal projection of the reset voltage line DR on the substrate.

[0244] For example, the orthographic projection of the gate of the driving transistor on the substrate does not overlap with the orthographic projection of the data line D1 on the substrate. Similarly, the orthographic projection of the gate of the driving transistor on the substrate does not overlap with the orthographic projection of the reset voltage line DR on the substrate.

[0245] The above arrangement not only helps to reduce the layout difficulty of the sub-pixel, but also, by placing the data line D1 and the reset voltage line DR on both sides of the sub-pixel, it can effectively avoid mutual interference between the data line D1 and the reset voltage line DR in the same sub-pixel.

[0246] like Figures 23 to 29 As shown, in some embodiments, the eighth transistor T8 includes an eighth active layer 58, the eighth active layer 58 including at least a portion extending along the first direction;

[0247] The orthographic projection of the eighth active layer 58 onto the substrate at least partially overlaps with the orthographic projection of the reset voltage line DR onto the substrate.

[0248] For example, the orthographic projection of the eighth active layer 58 onto the substrate is covered by the orthographic projection of the reset voltage line DR onto the substrate.

[0249] like Figures 23 to 29 As shown, in some embodiments, the sub-pixel further includes a second conductive connection portion 62, which is coupled to the second electrode of the eighth transistor T8 and the second electrode of the third transistor T3, respectively.

[0250] The orthographic projection of the second conductive connection portion 62 on the substrate at least partially overlaps with the orthographic projection of the reset voltage line DR on the substrate.

[0251] For example, the second conductive connection portion 62 is made using the first source / drain metal layer.

[0252] For example, the second conductive connection portion 62 includes a portion extending along the first direction and a portion extending along the third direction.

[0253] For example, the orthographic projection of the second conductive connection portion 62 on the substrate overlaps with the orthographic projection portion of the light-emitting control line E1 on the substrate.

[0254] For example, the second conductive connection portion 62 is coupled to the second electrode of the eighth transistor T8 and the second electrode of the third transistor T3 through vias.

[0255] For example, the orthographic projection of the second conductive connection portion 62 on the substrate overlaps with the orthographic projection of the second plate C2 of the storage capacitor C on the substrate.

[0256] The above configuration helps to reduce the layout difficulty of the sub-pixels.

[0257] like Figures 30 to 32 , Figures 35 to 39As shown, in some embodiments, the sub-pixel further includes: a first initialization voltage line Vinit1, the first initialization voltage line Vinit1 including at least a portion extending along a second direction; in two adjacent sub-pixels along a first direction, the first initialization voltage line Vinit1' in one sub-pixel is multiplexed as the reset voltage line DR in the other sub-pixel.

[0258] For example, the second initialization voltage line Vinit2 is fabricated using the first source-drain metal layer.

[0259] For example, the first initialization voltage line Vinit1 is fabricated using the first gate metal layer.

[0260] It needs to be explained that, Figure 35 The small, independent graphic in the upper right corner is part of the eighth active layer in the previous sub-pixel adjacent to the first direction. Figure 37 The bottommost independent small graphic is the second active layer in the next sub-pixel adjacent to it along the first direction.

[0261] The above setting reuses the first initialization voltage line Vinit1' as the reset voltage line DR, avoiding the need for an additional reset voltage line DR specifically for providing reset voltage. This simplifies the complexity of sub-pixels and reduces the difficulty of sub-pixel layout.

[0262] In some embodiments, the second initialization voltage line Vinit2 includes: a first initial sub-pattern, a second initial sub-pattern, a third initial sub-pattern, and a third protrusion; the first initial sub-pattern and the third initial sub-pattern both extend along the second direction, the first initial sub-pattern and the third initial sub-pattern are offset along the first direction, and the first initial sub-pattern and the third initial sub-pattern are coupled through the second initial sub-pattern; the third protrusion is coupled to the third initial sub-pattern; the second initialization circuit 32 includes a seventh transistor T7, the gate of the seventh transistor T7 is coupled to the third scan line S3, the first electrode of the seventh transistor T7 is coupled to the first initial sub-pattern; the first electrode of the eighth transistor T8 is coupled to the third protrusion.

[0263] For example, the seventh transistor T7 includes a seventh active layer, the orthographic projection of which on the substrate lies between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the reset line on the substrate.

[0264] For example, the orthographic projection of the seventh active layer on the substrate is located between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the eighth active layer 58 on the substrate.

[0265] likeFigure 11 , Figure 14 and Figure 16 As shown, in some embodiments, the sub-pixel further includes a second scan line S2, the second scan line S2 including a first scan sub-pattern S21 and a third scan sub-pattern S22, at least a portion of the first scan sub-pattern S21 and at least a portion of the third scan sub-pattern S22 both extending along the second direction;

[0266] The compensation control circuit 13 includes a first transistor T1, which includes a first oxide active layer; at least a portion of the first oxide active layer is located between the first scan sub-pattern and the third scan sub-pattern in a direction perpendicular to the substrate.

[0267] For example, the first scan sub-pattern is fabricated using a second gate metal layer, and the third scan sub-pattern is fabricated using a third gate metal layer. At least a portion of the first scan sub-pattern is located between the substrate and the third scan sub-pattern.

[0268] like Figure 11 , Figure 14 and Figure 16 As shown, in some embodiments, the sub-pixel further includes an initialization control line R1, which includes a first initialization sub-pattern R11 and a second initialization sub-pattern R12, wherein at least a portion of the first initialization sub-pattern R11 and at least a portion of the second initialization sub-pattern R12 extend along the second direction.

[0269] The first initialization circuit 14 includes a second transistor T2, the second transistor T2 including a second oxide active layer; in a direction perpendicular to the substrate, at least a portion of the second oxide active layer is located between the first initialization sub-pattern and the second initialization sub-pattern.

[0270] For example, the first initialization sub-pattern is fabricated using a second gate metal layer, and the second initialization sub-pattern is fabricated using a third gate metal layer. At least a portion of the first initialization sub-pattern is located between the substrate and the second initialization sub-pattern.

[0271] like Figure 15 As shown, in some embodiments, the first oxide active layer (as indicated by label 51) and the second oxide active layer (as indicated by label 52) are arranged along the first direction;

[0272] The data writing circuit 41 includes a fourth transistor T4, which includes a fourth active layer. The orthographic projection of the fourth active layer on the substrate at least partially overlaps with the orthographic projection of the data line D1 on the substrate. The fourth active layer and the first oxide active layer are arranged along the second direction.

[0273] In some embodiments, the sub-pixel further includes a light emission control line E1, the light emission control line E1 including at least a portion extending along the second direction;

[0274] The light-emitting control circuit 31 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is coupled to the light-emitting control line E1, and the gate of the sixth transistor T6 is coupled to the light-emitting control line E1.

[0275] The fifth transistor T5 includes a fifth active pattern, and the sixth transistor T6 includes a sixth active pattern. The fifth active pattern and the sixth active pattern are arranged along the second direction.

[0276] This invention also provides a display device, including the display substrate provided in the above embodiments.

[0277] Because the display substrate provided in the above embodiments, by providing the reset circuit 20, can apply a bias voltage with the opposite sign to that of the light-emitting stage P4 to the driving circuit 11 during the bias compensation stage P2, thereby compensating for the characteristic shift of the driving circuit 11 after operating at a certain bias voltage for a period of time, and improving problems such as short-term image retention and slow response time. Moreover, during low-frequency driving, it can compensate for the brightness difference caused by the characteristic shift of the driving circuit 11 during the long light-emitting stage, and improve the flicker phenomenon. Therefore, the display device provided in the embodiments of the present invention, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0278] Furthermore, when the display device provided in this embodiment includes the aforementioned display substrate, it can achieve specific bias voltage compensation for the driving circuit 11 in each pixel circuit of the display substrate, resulting in a good compensation effect. In addition, since the reset voltage provided by the reset voltage line DR can be independently adjusted, a suitable bias voltage can be provided to each pixel circuit in the display substrate as needed.

[0279] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0280] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0281] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0282] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0283] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0284] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0285] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0286] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, include: Drive circuit, data writing circuit and reset circuit; The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the connection between the data line and the second end of the driving circuit during the write compensation stage under the control of the first scan signal provided by the first scan line. The reset circuit is coupled to the third scan line, the reset voltage line and the second terminal of the driving circuit, respectively, and is used to control the connection between the reset voltage line and the second terminal of the driving circuit under the control of the third scan signal provided by the third scan line; or, the reset circuit is coupled to the third scan line, the reset voltage line and the first terminal of the driving circuit, respectively, and is used to control the connection between the reset voltage line and the first terminal of the driving circuit under the control of the third scan signal. The driving circuit is used to control the connection between the first terminal and the second terminal of the driving circuit under the control of the potential at its control terminal; The reset voltage line is used to provide an independently adjustable reset voltage that can follow the changes in the data signal transmitted by the data line. During the bias compensation phase, a bias voltage with the opposite sign to that during the light emission phase is applied to the driving transistors included in the driving circuit. The pixel circuit further includes a first initialization circuit, which is coupled to an initialization control line, a first initialization voltage line and the control terminal of the driving circuit, respectively. The first initialization circuit is used to control the first initialization voltage line and the control terminal of the driving circuit to connect during the initialization phase under the control of the initialization control signal provided by the initialization control line. The bias compensation phase is located between the initialization phase and the write compensation phase.

2. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: a compensation control circuit, a light emission control circuit, an energy storage circuit, and a light emission element; The compensation control circuit is electrically connected to the second scan line, the control terminal of the driving circuit, and the first terminal of the driving circuit, respectively, and is used to control the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the second scan signal provided by the second scan line; The light-emitting control circuit is coupled to the light-emitting control line, the first end of the driving circuit and the light-emitting element, respectively, and is used to control the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line; The energy storage circuit is coupled to the control terminal of the drive circuit and the second terminal of the drive circuit.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes: a second initialization circuit; The second initialization circuit is coupled to the third scan line, the second initialization voltage line and the light-emitting element respectively, and is used to control the connection between the second initialization voltage line and the light-emitting element under the control of the third scan signal.

4. The pixel circuit according to claim 2, characterized in that, The first initialization voltage line is reused as the reset voltage line.

5. The pixel circuit according to claim 2, characterized in that, The light-emitting control circuit is also coupled to the first voltage line and the second terminal of the driving circuit, and is used to control the connection between the first voltage line and the second terminal of the driving circuit under the control of the light-emitting control signal.

6. The pixel circuit according to claim 5, characterized in that, The compensation control circuit includes a first transistor, the first initialization circuit includes a second transistor, the driving circuit includes a third transistor, and the light-emitting control circuit includes a fifth transistor and a sixth transistor. The gate of the first transistor is coupled to the second scan line, the first terminal of the first transistor is coupled to the second terminal of the third transistor, and the second terminal of the first transistor is coupled to the gate of the third transistor. The gate of the second transistor is coupled to the initialization control line, the first terminal of the second transistor is coupled to the first initialization voltage line, and the second terminal of the second transistor is coupled to the gate of the third transistor. The gate of the fifth transistor is coupled to the light-emitting control line, the first terminal of the fifth transistor is coupled to the first voltage line, and the second terminal of the fifth transistor is coupled to the first terminal of the third transistor. The gate of the sixth transistor is coupled to the light-emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the light-emitting element.

7. The pixel circuit according to claim 6, characterized in that, The first transistor and the second transistor are oxide thin-film transistors.

8. The pixel circuit according to claim 3, characterized in that, The second initialization circuit includes a seventh transistor. The gate of the seventh transistor is coupled to the third scan line, the first electrode of the seventh transistor is coupled to the second initialization voltage line, and the second electrode of the seventh transistor is coupled to the light-emitting element.

9. The pixel circuit according to claim 1, characterized in that, The driving circuit includes a third transistor; the data writing circuit includes a fourth transistor; and the reset circuit includes an eighth transistor. The gate of the fourth transistor is coupled to the first scan line, the first electrode of the fourth transistor is coupled to the data line, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor. The gate of the eighth transistor is coupled to the third scan line, the first terminal of the eighth transistor is coupled to the reset voltage line, and the second terminal of the eighth transistor is coupled to either the first or second terminal of the third transistor.

10. A driving method, characterized in that, Applied to the pixel circuit as described in any one of claims 1 to 9, the display cycle includes a write compensation phase, a bias compensation phase, and an initialization phase, and the driving method includes: During the write compensation phase, the data writing circuit, under the control of the first scan signal, controls the connection between the data line and the second terminal of the drive circuit. During the bias compensation stage, the reset circuit, under the control of the third scan signal, controls the reset voltage line to connect with the second terminal of the drive circuit; or, under the control of the third scan signal, the reset circuit controls the reset voltage line to connect with the first terminal of the drive circuit. The reset voltage line is used to provide an independently adjustable reset voltage that can follow the changes in the data signal transmitted by the data line. During the bias compensation phase, a bias voltage with the opposite sign to that during the light emission phase is applied to the driving transistors included in the driving circuit. During the initialization phase, the first initialization circuit in the pixel circuit, under the control of the initialization control signal, controls the first initialization voltage line to connect with the control terminal of the driving circuit.

11. The driving method according to claim 10, characterized in that, The display cycle also includes a light-emitting phase; During the write compensation stage, the compensation control circuit in the pixel circuit, under the control of the second scan signal, controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit. During the light-emitting stage, the light-emitting control circuit in the pixel circuit controls the connection between the first voltage line and the second terminal of the driving circuit under the control of the light-emitting control signal, and controls the connection between the first terminal of the driving circuit and the light-emitting element, so that the driving circuit drives the light-emitting element to emit light.

12. The driving method according to claim 10, characterized in that, The display cycle also includes multiple light emission stages and multiple bias compensation stages, which are alternately set.

13. A display substrate, characterized in that, The sub-pixels include a substrate and a plurality of sub-pixels disposed on the substrate, wherein each sub-pixel includes a pixel circuit as described in any one of claims 1 to 9; the sub-pixel further includes: The data line includes a reset voltage line, a first scan line, and a third scan line; the data line includes at least a portion extending along a first direction, the first scan line includes at least a portion extending along a second direction, and the third scan line includes at least a portion extending along the second direction, the second direction intersecting the first direction. The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the connection between the data line and the second end of the driving circuit under the control of the first scan signal provided by the first scan line; The reset circuit is coupled to the third scan line and the reset voltage line respectively, and is also coupled to the first or second terminal of the driving circuit. It is used to control the connection between the reset voltage line and the second terminal of the driving circuit under the control of the third scan signal provided by the third scan line; or to control the connection between the reset voltage line and the first terminal of the driving circuit.

14. The display substrate according to claim 13, characterized in that, The driving circuit includes a third transistor, and the reset circuit includes an eighth transistor; The gate of the eighth transistor is coupled to the third scan line, the first terminal of the eighth transistor is coupled to the reset voltage line, and the second terminal of the eighth transistor is coupled to the first terminal of the third transistor. The reset voltage line includes at least a portion extending along the first direction, and the reset voltage line and the data line are arranged along the second direction; The orthographic projection of the reset voltage line onto the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor onto the substrate.

15. The display substrate according to claim 14, characterized in that, The eighth transistor includes an eighth active layer, the eighth active layer including at least a portion extending along the first direction; At least a portion of the orthographic projection of the eighth active layer onto the substrate is located between the orthographic projection of the data line onto the substrate and the orthographic projection of the reset voltage line onto the substrate; The orthographic projection of the eighth active layer on the substrate and the orthographic projection of the gate of the driving transistor on the substrate are aligned along the first direction.

16. The display substrate according to claim 14, characterized in that, The sub-pixel further includes a first conductive connection portion, which is coupled to the second electrode of the eighth transistor and the first electrode of the third transistor, respectively; At least a portion of the orthographic projection of the first conductive connection portion onto the substrate is located between the orthographic projection of the data line onto the substrate and the orthographic projection of the reset voltage line onto the substrate.

17. The display substrate according to claim 13, characterized in that, The driving circuit includes a third transistor, and the reset circuit includes an eighth transistor; The gate of the eighth transistor is coupled to the third scan line, the first terminal of the eighth transistor is coupled to the reset voltage line, and the second terminal of the eighth transistor is coupled to the second terminal of the third transistor. The reset voltage line includes at least a portion extending along the first direction, and the reset voltage line and the data line are arranged along the second direction; the orthographic projection of the gate of the driving transistor on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the reset voltage line on the substrate.

18. The display substrate according to claim 17, characterized in that, The eighth transistor includes an eighth active layer, the eighth active layer including at least a portion extending along the first direction; The orthographic projection of the eighth active layer on the substrate at least partially overlaps with the orthographic projection of the reset voltage line on the substrate.

19. The display substrate according to claim 17, characterized in that, The sub-pixel further includes a second conductive connection portion, which is coupled to the second electrode of the eighth transistor and the second electrode of the third transistor, respectively; The orthographic projection of the second conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the reset voltage line on the substrate.

20. The display substrate according to claim 13, characterized in that, The sub-pixel further includes: a first initialization voltage line, the first initialization voltage line including at least a portion extending along a second direction; in two adjacent sub-pixels along the first direction, the first initialization voltage line in one sub-pixel is multiplexed as the reset voltage line in the other sub-pixel.

21. A display device, characterized in that, Includes the display substrate as described in any one of claims 13 to 20.

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