Word line driver circuit and memory

Abstract

The embodiment of the present application relates to the field of semiconductors, and provides a word line driver circuit and a memory. The word line driver circuit may at least include: a plurality of word line drivers, each of the word line drivers includes a PMOS transistor and an NMOS transistor, the plurality of word line drivers include a plurality of PMOS transistors and a plurality of NMOS transistors, the plurality of PMOS transistors are arranged side by side, in the arrangement direction of the plurality of PMOS transistors, some of the NMOS transistors are located on one side of the plurality of PMOS transistors, and another part of the NMOS transistors are located on the opposite side of the plurality of PMOS transistors. The embodiment of the present invention is beneficial to improving the electrical performance of the word line driver circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and particularly to a word line driver circuit and a memory. Background Art

[0002] Various circuits in a memory need to use various signals, and signal drivers for applying signals to signal lines are widely used. A word line driver is used to apply a voltage to word lines in a memory cell array, and the word lines can extend from a sub word line driver (SWD) and pass through the entire column of memory cells. The sub word line driver can selectively activate corresponding word lines in response to row addresses corresponding to the word lines received by the storage device, and each memory cell connected to the activated word line can output or input data. Summary of the Invention

[0003] Embodiments of the present application provide a new word line driver circuit and a memory.

[0004] According to some embodiments of the present application, there is provided a word line driver circuit, including: a plurality of word line drivers, each of the word line drivers including a PMOS transistor and an NMOS transistor, the plurality of word line drivers including a plurality of PMOS transistors and a plurality of NMOS transistors, the plurality of PMOS transistors being arranged side by side, and in the arrangement direction of the plurality of PMOS transistors, some of the plurality of NMOS transistors are located on one side of the PMOS transistors, and another part of the NMOS transistors are located on the opposite side of the plurality of PMOS transistors.

[0005] According to some embodiments of the present application, there is also provided a memory including the above word line driver circuit.

[0006] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0007] In the embodiments of the present application, the plurality of PMOS transistors are arranged side by side, and in the arrangement direction of the plurality of PMOS transistors, the plurality of NMOS transistors are located on opposite sides of the plurality of PMOS transistors. In this way, it is beneficial to avoid arranging the PMOS transistors and the NMOS transistors side by side in the direction perpendicular to the above arrangement direction, so that the PMOS transistors and the NMOS transistors have a larger space in the vertical direction, which is beneficial to extending the channel length or gate width of the PMOS transistors and the NMOS transistors, and improving the electrical performance of the word line driver circuit; at the same time, controlling the NMOS transistors to be located on opposite sides of the PMOS transistors is beneficial to making the distance between the PMOS transistors and the NMOS transistors corresponding to different word line drivers shorter, thereby shortening the wiring length, reducing the wire resistance, and reducing the signal delay; in addition, arranging the NMOS transistors on opposite sides of the PMOS transistors is beneficial to improving the symmetry of the word line driver circuit, and thus the electrical performance of the word line driver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0009] Figure 1 Schematic structural diagram of the memory provided by an embodiment of the present application;

[0010] Figure 2 Schematic circuit diagram of the word line driver circuit provided by an embodiment of the present application;

[0011] Figures 3 to 9 Schematic layout diagram of the word line driver circuit provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] The following will elaborate on each embodiment of the present application in conjunction with the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided to help the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0013] Figure 1 Schematic structural diagram of the memory provided by an embodiment of the present application; Figure 2 Schematic circuit diagram of the word line driver circuit provided by an embodiment of the present application; Figures 3 to 9 Schematic layout diagram of the word line driver circuit provided by an embodiment of the present application.

[0014] The word line driver circuit includes: a plurality of word line drivers, each word line driver includes a PMOS transistor and an NMOS transistor. The plurality of word line drivers include a plurality of PMOS transistors and a plurality of NMOS transistors. The plurality of PMOS transistors are arranged side by side. In the arrangement direction of the plurality of PMOS transistors, some NMOS transistors are located on one side of the plurality of PMOS transistors, and some other NMOS transistors are located on the other side of the plurality of PMOS transistors.

[0015] The following will further elaborate on the embodiments of the present application in conjunction with the drawings.

[0016] Refer to Figure 1, according to different connected word lines, the word line driver can be divided into an odd word line driver SWD_ODD and an even word line driver SWD_EVEN. The odd word line driver SWD_ODD is used to connect odd-numbered word lines (such as WL1, WL3, WL5, and WL7), and the even word line driver SWD_EVEN is used to connect even-numbered word lines (such as WL0, WL2, WL4, and WL6). In a storage device, the odd word line driver SWD_ODD and the even word line driver SWD_EVEN are usually arranged at intervals, and the odd-numbered word lines and the even-numbered word lines are usually arranged at intervals.

[0017] Reference Figure 1 and Figure 2 , taking the example that each word line driver circuit includes four word line drivers for illustration. According to the figure, the types of different word line drivers in the same word line driver circuit are the same, that is, they are all odd word line drivers or even word line drivers; each word line driver can include a PMOS transistor and two NMOS transistors, denoted as the zero PMOS transistor, the zero NMOS transistor, and the first NMOS transistor. The gates of the zero PMOS transistor and the zero NMOS transistor are used to receive the first control signal MWLB (such as MWLB <n>) The source of the zero-th PMOS transistor is used to receive the second control signal FX (such as FX0, FX2, FX4, and FX6). The drains of the zero-th PMOS transistor, the zero-th NMOS transistor, and the first NMOS transistor are used to connect to the corresponding word lines (such as WL0, WL2, WL4, and WL6). The sources of the zero-th NMOS transistor and the first NMOS transistor are grounded. The gate of the first NMOS transistor is used to receive the second control complementary signal FXB (such as FXB0, FXB2, FXB4, and FXB6). In some embodiments, the word line driver only includes one PMOS transistor and one NMOS transistor.

[0018] Wherein, the moment when the second control signal FX jumps to the high level is the same as the moment when the second control complementary signal FXB jumps to the low level and the moment when the first control signal MWLB jumps to the low level. The moment when the second control complementary signal FXB jumps to the high level is later than the moment when the second control signal FX jumps to the low level. The moment when the first control signal MWLB jumps to the high level is later than the moment when the second control complementary signal FXB jumps to the high level.

[0019] Exemplarily, the word line driver circuit includes a first word line driver SWD1, a second word line driver SWD2, a third word line driver SWD3, and a fourth word line driver SWD4. The first word line driver SWD1 includes a PMOS transistor P10 and NMOS transistors N10 and N11. The second word line driver SWD2 includes a PMOS transistor P20 and NMOS transistors N20 and N21. The third word line driver SWD3 includes a PMOS transistor P30 and NMOS transistors N30 and N31. The fourth word line driver SWD4 includes a PMOS transistor P40 and NMOS transistors N40 and N41. Among them, P10, P20, P30, and P40 belong to the zero-th PMOS transistor, N10, N20, N30, and N40 belong to the zero-th NMOS transistor, and N11, N21, N31, and N41 belong to the first NMOS transistor.

[0020] In some embodiments, each PMOS transistor is composed of at least two sub-PMOS transistors; in other embodiments, each NMOS transistor is composed of at least two sub-NMOS transistors; in yet another embodiment, each PMOS transistor is composed of at least two sub-PMOS transistors, and each NMOS transistor is composed of at least two sub-NMOS transistors. Exemplarily, the zero-th PMOS transistor is composed of the zero-one PMOS transistor and the zero-two PMOS transistor, the zero-th NMOS transistor is composed of the zero-one NMOS transistor and the zero-two NMOS transistor, and the first NMOS transistor is composed of the one-one NMOS transistor and the one-two NMOS transistor. It should be noted that in the embodiments of the present application, the zero-one PMOS transistor and the zero-two PMOS transistor are NMOS transistors with exactly the same physical characteristics, and the only differences are their own positions and their connection relationships with other components. Similarly, the one-one NMOS transistor and the one-two NMOS transistor, as well as the zero-one NMOS transistor and the zero-two NMOS transistor, are NMOS transistors with exactly the same physical characteristics, and the only differences are their own positions and their connection relationships with other components. Setting the PMOS transistor or the NMOS transistor to be composed of two sub-MOS transistors together is beneficial to adjusting the layout of the layout.

[0021] For the sake of simplicity of illustration, Figures 3 to 9 each transistor or sub-transistor is not labeled in the figure, and those skilled in the art can determine Figure 2 which transistor or sub-transistor is represented by the transistors at different positions in the figure according to Figures 3 to 9 the signals received by the gates, sources, and drains of the different transistors in the figure.

[0022] In some embodiments, referring to Figure 3 , P10 in the first word line driver, P20 in the second word line driver, P30 in the third word line driver, and P40 in the fourth word line driver are arranged side by side along the first direction D1. In the first direction D1, N10 and N11 in the first word line driver and N20 and N21 in the second word line driver are located on one side of the above-mentioned multiple PMOS transistors, and N30 and N31 in the third word line driver and N40 and N41 in the fourth word line driver are located on the opposite side of the above-mentioned multiple PMOS transistors.

[0023] In some embodiments, the distance between the PMOS transistor and the NMOS transistor in the word line driver is recorded as a preset distance, and the preset distances between different word line drivers are the same. Among them, referring to Figure 3 , in the first direction D1, the distances between the zero-th PMOS transistor and the zero-th NMOS transistor and the first NMOS transistor in the word line driver are equal. Specifically, the distances between P10 and N10 and N11 are equal, the distances between P20 and N20 and N21 are equal, the distances between P30 and N30 and N31 are equal, and the distances between P40 and N40 and N41 are equal. Further, the first distance between P10 and N10 is equal to the second distance between P20 and N20, the third distance between P30 and N30, and the fourth distance between P40 and N40. Setting different preset distances to be equal is beneficial to making different word line drivers have the same or similar performance, so that the moments when different word line drivers apply voltage to the corresponding word lines are close, ensuring the stability of the internal timing of the memory.

[0024] In some embodiments, two sub-PMOS transistors share the same source. Taking the first word line driver as an example, the PMOS transistor P10 in the first word line driver is composed of two sub-PMOS transistors P101 and P102. P101 and P102 share the same active region and are used to receive the first control signal FX, specifically FX0.

[0025] In some embodiments, the arrangement direction of multiple PMOS transistors (i.e., the first direction D1) is perpendicular to the channel length direction of the PMOS transistors. Among them, the arrangement direction of two sub-PMOS transistors is parallel to the channel length direction of the PMOS transistors and perpendicular to the first direction D1. Continuing with the first embodiment as an example, the arrangement direction of P101 and P102 is parallel to the channel length direction and perpendicular to the first direction D1.

[0026] In some embodiments, each PMOS transistor includes a first sub-PMOS transistor and a second sub-PMOS transistor. The first sub-PMOS transistors corresponding to different PMOS transistors share the same gate, and the second sub-PMOS transistors corresponding to different PMOS transistors share the same gate. As Figure 3 shown, the PMOS transistor P20 includes P201 and P202, the PMOS transistor P30 includes P301 and P302, the PMOS transistor P40 includes P401 and P402. P101, P201, P301, and P401 are arranged side by side in the first direction D1 and share the same gate, and P102, P202, P302, and P402 are arranged side by side in the first direction D1 and share another gate.

[0027] In some embodiments, the first one NMOS transistor and the first two NMOS transistors are located between the zero one NMOS transistor and the zero two NMOS transistors. Refer to Figure 3 , the internal arrangement of the NMOS transistors of different word line drivers is the same. Taking the first word line driver as an example, the zero-th NMOS transistor N10 in the first word line driver includes a zero-first NMOS transistor N101 and a zero-second NMOS transistor N102. The first NMOS transistor N11 includes a first-first NMOS transistor N111 and a first-second NMOS transistor N112. N111 and N112 are located between N101 and N102.

[0028] In some embodiments, the arrangement directions of the first-first NMOS transistor and the first-second NMOS transistor are parallel to the arrangement directions of the zero-first NMOS transistor and the zero-second NMOS transistor. Similarly, taking the first word line driver as an example, the arrangement direction of N111 and N112 is parallel to the arrangement direction of N101 and N102.

[0029] In some embodiments, the channel length directions of different transistors and their sub-transistors are the same. In this way, it is beneficial to achieve a unique preset spacing between the PMOS transistor and the NMOS transistor in the same word line driver. In this way, it is beneficial to make the word line driver have more stable and balanced performance. Specifically, taking the first word line driver as an example, in the first direction D1, the distance between P101 and N101 is equal to the distance between P102 and N102; wherein, in the first direction D1, the horizontal position of the gate of P101 at least partially coincides with the horizontal position of the gate of N101. The distance between P101 and N101 is the distance between the gate of P101 and the gate of N101. The same applies to P102 and N102, and details will not be elaborated here.

[0030] Correspondingly, in the first direction D1, the distance between P101 and N111 is equal to the distance between P102 and N112; wherein, in the first direction D1, the horizontal position of the gate of P101 at least partially coincides with the horizontal position of the gate of N111. The distance between P101 and N111 is the distance between the gate of P101 and the gate of N111. The same applies to P102 and N112, and details will not be elaborated here.

[0031] In some embodiments, the first NMOS transistor shares the same drain with the second NMOS transistor, the second NMOS transistor shares the same source with the third NMOS transistor, and the third NMOS transistor shares the same drain with the fourth NMOS transistor. Different transistors sharing the same source or drain is beneficial to reducing the overall size of the word line driver, and thus realizing the miniaturization and microminiaturization of the word line driver circuit and the memory. Taking the first word line driver as an example, N101 and N111 share the same active region, and this active region is connected to the first word line WL0 through a contact hole. N111 and N112 share the same active region, and this active region is grounded or connected to a low-level signal. N112 and N102 share the same active region, and this active region is also connected to the first word line WL0 through a contact hole.

[0032] Among them, the second NMOS transistor and the third NMOS transistor share the same gate. Different transistors sharing the same gate is beneficial to reducing the manufacturing difficulty of the gate and ensuring the conductivity of the gate. Specifically, it is beneficial to reducing the complexity of the patterned opening of the mask, avoiding etching defects due to the complex pattern, and ensuring that the gate can be effectively formed. Taking the first word line embodiment as an example, N111 and N112 share the same gate. Or rather, the gates of N111 and N112 are different parts of the same conductive layer, and another conductive layer for connecting the gates of N111 and N112 is located on the isolation structure. The isolation structure is used to isolate adjacent active regions, and the word line can be made of doped polysilicon or metal materials, such as tungsten and molybdenum.

[0033] In some embodiments, the first NMOS transistor and the fourth NMOS transistor are located between the second NMOS transistor and the third NMOS transistor; among them, the first NMOS transistor and the fourth NMOS transistor may share the same gate. Refer to Figure 4 , the internal arrangement of the NMOS transistors of different word line drivers is the same. Taking the first word line driver as an example, N101 and N102 are located between N111 and N112, and N101 and N102 share the same gate.

[0034] Similar to the previous embodiment, the arrangement directions of the first NMOS transistor and the fourth NMOS transistor located in the middle position are parallel to the arrangement directions of the second NMOS transistor and the third NMOS transistor located on both sides. Correspondingly Figure 4 , the arrangement direction of N101 and N102 is parallel to the arrangement direction of N111 and N112.

[0035] Correspondingly, the second NMOS transistor shares the same drain with the first NMOS transistor, the first NMOS transistor shares the same source with the fourth NMOS transistor, and the fourth NMOS transistor shares the same drain with the third NMOS transistor. Correspondingly Figure 4 , N111 and N101 share the same active region, and this active region is connected to the zero-th word line WL0 through a contact hole. N101 and N102 share the same active region, and this active region is grounded or connected to a low-level signal. N102 and N112 share the same active region, and this active region is also connected to the zero-th word line WL0 through a contact hole.

[0036] In some embodiments, referring to Figure 4 , the word line driver includes a first word line driver and a second word line driver. The NMOS transistors N10 in the first word line driver and the NMOS transistor N20 in the second word line driver share the same source and the same gate. Among them, N20 is composed of N201 and N202, N10 is composed of N101 and N102, and N201, N202, N101, and N102 share the same continuous active region and the same continuous conductive layer. It can be understood that the gates of different transistors are different parts of the same conductive layer, and the other parts of the conductive layer connecting the gates of different transistors are located on the isolation structure, and the isolation structure is used to isolate adjacent active regions; in addition, the shared continuous conductive layer can present various shapes according to the arrangement of the transistors. In some embodiments, the shared continuous conductive layer presents a ring shape.

[0037] Correspondingly, the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver share the source. Among them, the first NMOS transistor in the first word line driver is composed of N111 and N112, the first NMOS transistor in the second word line driver is composed of N111 and N112, N111 and N211 share the same source, and N112 and N212 share the same source.

[0038] It can be understood that there are various combinations between different word line drivers. In the embodiments of the present application, the NMOS transistors of the first word line driver and the second word line driver are arranged on the same side of the PMOS transistor as an example, and based on this example, the connection relationship of the NMOS transistors of adjacent word line drivers located on the same side of the PMOS transistor in the word line driver circuit is described. It can be understood that in Figure 4 the shown embodiment, the NMOS transistors of the third word line driver and the fourth word line driver can also apply the above connection relationship; similarly, in other embodiments, if the NMOS transistors of the first word line driver and the third word line driver are located on one side of the PMOS transistor, the above description of the connection relationship is also applicable to the NMOS transistors of the first word line driver and the third word line driver. Subsequently, the first word line driver and the second word line driver are still used as examples for description, and their applicable situations will not be elaborated any further.

[0039] In some embodiments, the arrangement directions of the first NMOS transistor and the second NMOS transistor are parallel to the arrangement directions of the zeroth NMOS transistor and the first NMOS transistor; wherein, the zeroth NMOS transistor and the first NMOS transistor share the same gate, and / or the first NMOS transistor and the second NMOS transistor share the same gate.

[0040] Wherein, in some embodiments, referring to Figure 5 , the word line driver includes a first word line driver and a second word line driver. The first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver are located between the zeroth NMOS transistor included in the first word line driver and the zeroth NMOS transistor included in the second word line driver, that is, N11 and N21 are located between N10 and N20.

[0041] In some other embodiments, referring to Figure 6 , the word line driver includes a first word line driver and a second word line driver. The zeroth NMOS transistor included in the first word line driver and the zeroth NMOS transistor included in the second word line driver are located between the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver, that is, N10 and N20 are located between N11 and N21; in addition, N10 and N20 share the same gate.

[0042] In some embodiments, referring to Figures 3 to 6 , the channel length direction of the NMOS transistors in the word line driver is parallel to the channel length direction of the PMOS transistors, or rather, the channel length direction of the PMOS transistors is the same as the channel length direction of the NMOS transistors; in some other embodiments, referring to Figures 7 to 9 , the channel length direction of the NMOS transistors in the word line driver is perpendicular to the channel length direction of the PMOS transistors. Wherein, Figure 7 the difference between the embodiment shown in Figure 3 and the embodiment shown in Figure 8 lies in the overall adjustment of the channel length direction of the NMOS transistors in the word line driver circuit. Correspondingly, Figure 6 the main difference features between the embodiment shown in Figure 9 and Figure 5 and the embodiment shown in

[0043] Since the extending direction of the word lines connected to the word line driver is generally parallel to the extending direction of the gates of the PMOS transistors in the word line driver, setting the channel length direction of the NMOS transistors perpendicular to the channel length direction of the PMOS transistors is beneficial to avoid arranging a relatively large number of NMOS transistors side by side in the second direction D2 perpendicular to the first direction D1, reserve a larger space for the extension of the drains of the NMOS transistors, make the drains of the NMOS transistors have a larger width, and further facilitate the direct connection of the word lines extending from the drains of the PMOS transistors to the drains of the corresponding NMOS transistors without bending, that is, make the word lines straight, reduce the resistance of the word lines and the RC delay caused by the resistance, and ensure that the word line driver circuit has good electrical performance.

[0044] In this embodiment, a plurality of PMOS transistors are arranged side by side, and in the arrangement direction of the plurality of PMOS transistors, the plurality of NMOS transistors are located on opposite sides of the plurality of PMOS transistors. In this way, it is beneficial to avoid arranging the PMOS transistors and the NMOS transistors side by side in the direction perpendicular to the above arrangement direction, so that the PMOS transistors and the NMOS transistors have a larger space in the vertical direction, which is beneficial to extending the channel length or gate width of the PMOS transistors and the NMOS transistors and improving the electrical performance of the word line driver circuit; at the same time, controlling the NMOS transistors to be located on opposite sides of the PMOS transistors is beneficial to making the distance between the PMOS transistors and the NMOS transistors corresponding to different word line drivers shorter, thereby shortening the wiring length, reducing the wire resistance, and reducing the signal delay; in addition, arranging the NMOS transistors on opposite sides of the PMOS transistors is beneficial to improving the symmetry of the word line driver circuit, and thus the electrical performance of the word line driver circuit.

[0045] The embodiment of the present application also provides a memory, including the word line driver circuit described in any one of the above. In the case where the size of the integrated circuit is increasingly miniaturized, by using the word line driver circuit with the above structure, since its transistors and word lines can have good electrical performance, the word line driver circuit can have good characteristics, thereby improving the overall performance of the memory.

[0046] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.< / n>

Claims

1. A word line driver circuit, characterized in that, it includes: A plurality of word line drivers, each of the word line drivers includes a PMOS transistor and an NMOS transistor. The plurality of word line drivers include a plurality of PMOS transistors and a plurality of NMOS transistors. The plurality of PMOS transistors are arranged side by side and concentratedly. In the arrangement direction of the plurality of PMOS transistors, some of the NMOS transistors are located on one side of the plurality of PMOS transistors, and some of the NMOS transistors are located on the opposite side of the plurality of PMOS transistors.

2. The word line driver circuit according to claim 1, characterized in that, denote the distance between the PMOS transistor and the NMOS transistor in the word line driver as a preset distance, and the preset distances of different word line drivers are the same.

3. The word line driver circuit according to claim 1, characterized in that, each of the PMOS transistors is composed of at least two sub-PMOS transistors; wherein, the at least two sub-PMOS transistors share the same active region; The gate of each of the at least two sub-PMOS transistors receives a first control signal, the at least two sub-PMOS transistors share the same source for receiving a second control signal, and the drain of each of the at least two sub-PMOS transistors is connected to the word line.

4. The word line driver circuit according to claim 1, characterized in that, each of the NMOS transistors is composed of at least two sub-NMOS transistors; wherein, the at least two sub-NMOS transistors share the same active region; The gate of each of the at least two sub-NMOS transistors receives a first control signal or a second control complementary signal, the source of each of the at least two sub-NMOS transistors is grounded, and the drain of each of the at least two sub-NMOS transistors is connected to the word line.

5. The word line driver circuit according to claim 1 or 4, characterized in that, The word line driver includes a zero PMOS transistor, a zero NMOS transistor and a first NMOS transistor. The gate of the zero PMOS transistor receives a first control signal, the source receives a second control signal, and the drain is connected to the word line. The gate of the zero NMOS transistor receives the first control signal, the source is grounded, and the drain is connected to the word line. The gate of the first NMOS transistor receives a second control complementary signal, the source is grounded, and the drain is connected to the word line. The zero NMOS transistor is composed of a zero-one NMOS transistor and a zero-two NMOS transistor, and the first NMOS transistor is composed of a first-one NMOS transistor and a first-two NMOS transistor.

6. The word line driver circuit according to claim 5, characterized in that, the first-one NMOS transistor and the first-two NMOS transistor are located between the zero-one NMOS transistor and the zero-two NMOS transistor.

7. The word line driver circuit according to claim 6, characterized in that, the arrangement direction of the first-one NMOS transistor and the first-two NMOS transistor is parallel to the arrangement direction of the zero-one NMOS transistor and the zero-two NMOS transistor.

8. The word line driver circuit according to claim 6, characterized in that, The first NMOS transistor shares the same drain with the second NMOS transistor, the second NMOS transistor shares the same source with the third NMOS transistor, and the third NMOS transistor shares the same drain with the fourth NMOS transistor.

9. The word line driver circuit according to claim 8, wherein, the second NMOS transistor and the third NMOS transistor share the same gate.

10. The word line driver circuit according to claim 5, wherein, the first NMOS transistor and the fourth NMOS transistor are located between the second NMOS transistor and the third NMOS transistor.

11. The word line driver circuit according to claim 10, wherein, the first NMOS transistor and the fourth NMOS transistor share the same gate.

12. The word line driver circuit according to claim 10, wherein, the word line driver includes a first word line driver and a second word line driver. The first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver share the same source, and the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver share the same gate.

13. The word line driver circuit according to claim 5, wherein, the arrangement direction of the second NMOS transistor and the third NMOS transistor is parallel to the arrangement direction of the first NMOS transistor and the fourth NMOS transistor.

14. The word line driver circuit according to claim 13, wherein, the first NMOS transistor and the fourth NMOS transistor share the same gate, and the second NMOS transistor and the third NMOS transistor share the same gate.

15. The word line driver circuit according to claim 13, wherein, the word line driver includes a first word line driver and a second word line driver. The first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver are located between the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver.

16. The word line driver circuit according to claim 13, wherein, the word line driver includes a first word line driver and a second word line driver. The first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver are located between the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver.

17. The word line driver circuit according to claim 1, wherein, the channel extension direction of the NMOS transistor is perpendicular to the channel extension direction of the PMOS transistor.

18. A memory, wherein, it includes the word line driver circuit according to any one of claims 1 to 17.

Images