Array substrate, preparation method thereof, light emitting device and tiled display device

Abstract

The application provides an array substrate, a preparation method thereof, a light-emitting device and a spliced display device. The array substrate comprises a device area, a peripheral area adjacent to the device area, and the device area and the peripheral area each comprise a substrate and a reflective layer on the substrate; the device area further comprises an interlayer dielectric layer and a plurality of devices, and the interlayer dielectric layer is located at least between the substrate and the reflective layer; the reflective layer has a plurality of hollow areas along a direction perpendicular to the substrate, and the devices are located in the hollow areas; wherein a part of the reflective layer located in the device area is partially overlapped with a part of the interlayer dielectric layer in a normal projection on the substrate, a part of the reflective layer located in the peripheral area covers a part of the substrate located in the peripheral area, and an outer contour of the substrate is consistent with an outer contour of the peripheral area of the array substrate. The peripheral area of the array substrate can reflect light, thereby improving the problem of large optical brightness difference between different areas of the array substrate and improving the display effect of the spliced display device prepared by the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its preparation method, a light-emitting device, and a splicing display device. Background Technology

[0002] With the rapid development of display technology, Mini LED (Mini Light Emitting Diode) and Micro LED (Micro Light Emitting Diode) display products have attracted widespread attention. One of the advantages of Micro / mini LED display products is that they can achieve large-area splicing, that is, splicing multiple array substrates to obtain ultra-large-size display products. Summary of the Invention

[0003] The embodiments of this application provide an array substrate and its preparation method, a light-emitting device, and a splicing display device. The peripheral area of ​​the array substrate can reflect light, thereby improving the problem of large differences in optical brightness in different areas of the array substrate and improving the display effect of the splicing display device prepared by the array substrate.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] On one hand, an array substrate is provided, comprising:

[0006] Device area;

[0007] The peripheral area adjacent to the device area;

[0008] Both the device region and the peripheral region include a substrate and a reflective layer located on the substrate;

[0009] The device region further includes an interlayer dielectric layer and a plurality of devices, wherein the interlayer dielectric layer is located at least between the substrate and the reflective layer; the reflective layer has a plurality of cutout regions along a direction perpendicular to the substrate, and the devices are located within the cutout regions;

[0010] Wherein, the orthographic projection of the reflective layer on the portion of the substrate located in the device region overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, the portion of the reflective layer located in the peripheral region covers the portion of the substrate located in the peripheral region, and the outer contour of the substrate is consistent with the outer contour of the peripheral region of the array substrate; the device includes at least a light-emitting device.

[0011] In some embodiments of this application, the reflective layer includes a first reflective sublayer and a second reflective sublayer, the second reflective sublayer being located on the side of the first reflective sublayer away from the substrate; the orthographic projection of the first reflective sublayer onto the substrate is located in the device region and the peripheral region;

[0012] Wherein, the orthographic projection of the portion of the first reflective sublayer located in the device region on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, and the first reflective sublayer also covers the portion of the substrate located in the peripheral region;

[0013] The orthographic projection of the second reflective sublayer onto the substrate lies within the orthographic projection of the first reflective sublayer onto the substrate.

[0014] In some embodiments of this application, the orthographic projection of the second reflective sublayer onto the substrate is located in the device region;

[0015] The orthographic projection of the second reflective sublayer on the substrate does not overlap with the orthographic projection of the portion of the first reflective sublayer located in the peripheral region on the substrate.

[0016] In some embodiments of this application, the orthographic projection of the second reflective sublayer onto the substrate is located in the peripheral region and the device region;

[0017] The orthographic projection of the portion of the second reflective sublayer located in the peripheral region onto the substrate overlaps with the orthographic projection of the portion of the first reflective sublayer located in the peripheral region onto the substrate.

[0018] In some embodiments of this application, the first reflective sublayer and the second reflective sublayer have the same thickness along a direction perpendicular to the substrate.

[0019] In some embodiments of this application, the array substrate further includes an auxiliary reflective portion; the auxiliary reflective portion is located on the interlayer dielectric layer, and the auxiliary reflective portion is connected to the reflective layer.

[0020] In some embodiments of this application, the auxiliary reflective portion includes a first reflective portion and a second reflective portion, wherein the first reflective portion and the second reflective portion are an integral structure;

[0021] The hollowed-out area exposes a portion of the interlayer dielectric layer, and the first reflective portion

[0022] The orthographic projection on the substrate is located in the cutout area and is in direct contact with the interlayer dielectric layer;

[0023] The second reflective portion is in direct contact with the surface of the reflective layer away from the substrate, and the orthographic projection of the second reflective portion on the substrate overlaps with the orthographic projection of the reflective layer on the substrate.

[0024] In some embodiments of this application, the array substrate further includes a plurality of packaging units corresponding to the device, wherein the orthographic projection of the packaging unit on the substrate covers the orthographic projection of the device on the substrate, and the orthographic projection of the packaging unit on the substrate partially overlaps with the orthographic projection of the reflective layer on the substrate.

[0025] In some embodiments of this application, the device region of the array substrate includes a buffer layer and a first conductive layer disposed sequentially on the substrate, and the interlayer dielectric layer is located on the side of the first conductive layer away from the substrate;

[0026] The interlayer dielectric layer includes a first insulating layer and a first planarization layer, wherein the first planarization layer is located at least between the first insulating layer and the reflective layer.

[0027] In some embodiments of this application, the device region of the array substrate further includes a second conductive layer, a second insulating layer, a second planarization layer and a third insulating layer sequentially stacked on the buffer layer, wherein the third insulating layer is located on the side of the first conductive layer away from the first insulating layer.

[0028] In some embodiments of this application, the first conductive layer includes at least one first pad and at least one second pad, and the interlayer dielectric layer has a plurality of first openings and a plurality of second openings along a direction perpendicular to the substrate, wherein the first openings expose the area where the first pad is located, and the second openings expose the area where the second pad is located.

[0029] The first pad is electrically connected to the first solder pin of the device through the first opening, and the second pad is electrically connected to the second solder pin of the device through the second opening.

[0030] In some embodiments of this application, the array substrate further includes a support pillar located on the side of the reflective layer away from the substrate, and the orthographic projection of the support pillar on the substrate does not overlap with the orthographic projection of the device on the substrate.

[0031] Embodiments of this application also provide a light-emitting device, including the array substrate described above.

[0032] In some embodiments of this application, the light-emitting device further includes a diffuser plate, a quantum dot film, a diffuser sheet, and a composite film stacked sequentially.

[0033] The diffuser plate is located on the light-emitting side of the array substrate.

[0034] Embodiments of this application also provide a splicing display device, including at least two light-emitting devices as described above.

[0035] Embodiments of this application also provide a method for fabricating an array substrate, applied to the fabrication of the array substrate described above, the method comprising:

[0036] A mother substrate is provided; the mother substrate is divided into at least one device region and a dicing region adjacent to the device region;

[0037] An interlayer dielectric layer is formed on the device region of the motherboard substrate;

[0038] A reflective layer is formed on the device region and the cut region of the mother substrate; wherein the reflective layer has a plurality of cutout regions along a direction perpendicular to the mother substrate; the interlayer dielectric layer is located at least between the mother substrate and the reflective layer; the orthographic projection of the portion of the reflective layer located in the device region on the mother substrate overlaps with the orthographic projection portion of the interlayer dielectric layer on the mother substrate, and the portion of the reflective layer located in the cut region covers the cut region of the mother substrate;

[0039] Multiple devices are bonded to the device area of ​​the mother substrate; the devices are located within the cutout area;

[0040] At least one array substrate is obtained by cutting along a cutting line from the back side of the mother substrate; the cutting line is located in the cutting area, and the back side is the surface of the mother substrate away from the device.

[0041] In some embodiments of this application, after the step of cutting along the dicing line from the back side of the mother substrate to obtain at least one of the array substrates, the method further includes:

[0042] The edges of the array substrate are ground using a vertical grinding process.

[0043] In some embodiments of this application, the step of grinding the edge of the array substrate using a vertical grinding process includes:

[0044] The side surfaces of the substrate and the reflective layer of the array substrate are simultaneously ground along a direction perpendicular to the array substrate; wherein the side surfaces of the substrate and the reflective layer are coplanar.

[0045] In some embodiments of this application, the step of forming a reflective layer on the device region and the dicing region of the mother substrate includes:

[0046] A first reflective sublayer is formed; the orthographic projection of the first reflective sublayer onto the mother substrate is located within the device region and the dicing region.

[0047] A second reflective sublayer is formed; the orthogonal projection of the second reflective sublayer onto the mother substrate is located within the device region.

[0048] Alternatively, a first reflective sublayer may be formed; the orthographic projection of the first reflective sublayer onto the mother substrate may lie within the device region and the dicing region.

[0049] A second reflective sublayer is formed; the orthogonal projection of the second reflective sublayer on the mother substrate is located within the device region and the cutting region.

[0050] In some embodiments of this application, after the step of bonding multiple devices to the device region of the mother substrate and before the step of cutting along a dicing line from the back side of the mother substrate to obtain at least one of the array substrates, the method further includes:

[0051] An auxiliary reflective portion is formed on the interlayer dielectric layer; wherein the auxiliary reflective portion is connected to the reflective layer.

[0052] Embodiments of this application provide an array substrate and its fabrication method, a light-emitting device, and a splicing display device. The array substrate includes: a device region; a peripheral region adjacent to the device region; both the device region and the peripheral region include a substrate and a reflective layer located on the substrate; the device region further includes an interlayer dielectric layer and a plurality of devices, the interlayer dielectric layer being located at least between the substrate and the reflective layer; the reflective layer has a plurality of cutout regions along a direction perpendicular to the substrate, and the devices are located within the cutout regions; wherein, the orthographic projection of the reflective layer located in the device region onto the substrate partially overlaps with the orthographic projection of the interlayer dielectric layer onto the substrate, the reflective layer located in the peripheral region covers the substrate located in the peripheral region, and the outer contour of the substrate is consistent with the outer contour of the peripheral region of the array substrate.

[0053] In this way, because a reflective layer is set in the peripheral area, the reflective layer in the peripheral area covers the substrate in the peripheral area, and the outer contour of the substrate is consistent with the outer contour of the peripheral area of ​​the array substrate. This allows the reflective layer to cover the edge of the substrate in the peripheral area. As a result, when the array substrate emits light, the reflective layer in the peripheral area can reflect the light emitted by the array substrate. This greatly improves the problem of the large optical brightness difference between the peripheral area and the device area of ​​the array substrate, and greatly increases the amount of light emitted by the array substrate in the direction perpendicular to the plane of the substrate, thereby improving the light emission efficiency of the array substrate. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figures 1a-5 This is a schematic diagram of the structure of nine array substrates provided in the embodiments of this application;

[0056] Figure 6 This is a schematic diagram of the structure of a light-emitting device provided in an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of the structure of a splicing display device provided in an embodiment of this application;

[0058] Figure 8a Microscopic interferogram of scratches and knife marks on the packaging unit of an array substrate in a related art provided for embodiments of this application;

[0059] Figure 8b A microscope image of the tool marks on the reflective layer of an array substrate in a related art, provided for an embodiment of this application;

[0060] Figure 8c This is a schematic diagram of the structure of a cutting wheel provided in an embodiment of this application;

[0061] Figure 8d A schematic diagram of a front-side cutting process using a cutting wheel provided in an embodiment of this application;

[0062] Figure 9 This is a flowchart illustrating a method for fabricating an array substrate, as provided in an embodiment of this application.

[0063] Figure 10 This is a schematic diagram of the structure of a motherboard for an array substrate provided in an embodiment of this application;

[0064] Figure 11 This is a schematic diagram of the structure of a mother plate for another array substrate provided in an embodiment of this application;

[0065] Figure 12a , Figure 13a and Figure 14 A schematic diagram illustrating three back-side cutting processes provided in the embodiments of this application;

[0066] Figure 12b for Figure 12a A schematic diagram showing the cutting line positions corresponding to the cutting process;

[0067] Figure 13b for Figure 13a A schematic diagram showing the cutting line positions corresponding to the cutting process;

[0068] Figure 15a This is a schematic diagram of a polishing process for an array substrate in a related art, provided as an embodiment of this application.

[0069] Figure 15b and Figure 15c To adopt Figure 15a Two schematic diagrams of the polishing region of the array substrate prepared by the polishing process;

[0070] Figure 16 This is a schematic diagram of a grinding process for an array substrate provided in an embodiment of this application;

[0071] Figure 17a This is a schematic diagram of the structure of a splicing display device in a related art, provided in an embodiment of this application;

[0072] Figure 17b This is a schematic diagram of the structure of a splicing display device provided in an embodiment of this application;

[0073] Figure 18 This is a schematic diagram of the structure of a vacuum suction cup provided in an embodiment of this application. Detailed Implementation

[0074] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0075] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0076] In the embodiments of this application, unless otherwise stated, "a plurality of" means two or more; the orientation or positional relationship indicated by the term "above" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply that the structure or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0077] To facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish the same or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity.

[0078] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0079] Embodiments of this application provide an array substrate, with reference to... Figure 1a or Figure 2a As shown, it includes:

[0080] Device area A; and such Figure 2d The peripheral region B shown is adjacent to the device region A; both device region A and peripheral region B include a substrate 1 and a reflective layer 20 located on the substrate 1.

[0081] Device region A also includes an interlayer dielectric layer 30 and a plurality of devices 12. The interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20. The reflective layer 20 has a plurality of cutout regions L along a direction perpendicular to the substrate 1, and the devices 12 are located within the cutout regions L.

[0082] The orthographic projection of the portion of the reflective layer 20 located in device region A onto the substrate 1 overlaps with the orthographic projection of the interlayer dielectric layer 30 onto the substrate 1. The portion of the reflective layer 20 located in peripheral region B covers the portion of the substrate 1 located in peripheral region B, and the outer contour of the substrate 1 is consistent with the outer contour of peripheral region B of the array substrate.

[0083] The device area A on the array substrate is provided with a variety of devices 12 arranged in an array. The devices 12 include at least light-emitting devices, and may also include any one of sensor devices, micro-driving chips or other types of devices. It can be understood that the number of different types of devices is different, or the array arrangement density of different types of devices is different.

[0084] Peripheral area B is the area between device area A and the boundary of the array substrate. In the actual production process, each array substrate is formed by cutting the mother board, that is, the size of peripheral area B can be determined according to the actual cutting process.

[0085] It should be noted that the width of the peripheral area B is the distance between the boundary of the array substrate and the device area A, and the width of the peripheral area B at various points ranges from 0.2mm to 2mm; for example, it can be 0.2mm, 1mm, 1.2mm, 1.5mm or 2mm.

[0086] In the array substrate, reference Figure 1a or Figure 2a As shown, without considering the bonding area, the area other than the peripheral area B is the device area A.

[0087] The distance between the geometric center of the orthographic projection of any device 12 closest to the boundary of the array substrate and the edge of the array substrate (outer contour of the peripheral region B) along a direction parallel to the plane of the substrate 1 is in the range of 1mm-5mm. For example, the distance can be 1mm, 1.2mm, 1.5mm, 2mm, 3mm, 4mm, or 5mm.

[0088] For example, see reference Figure 2d As shown, the geometric center of the orthographic projection of device 12 located at the upper left corner of the array substrate onto substrate 1 is 4 mm from the edge of the array substrate along the X direction, and the distance between the outer contour of device region A and the outer contour of peripheral region B along the X direction is 0.7 mm; the distance between the geometric center of the orthographic projection of device 12 located at the upper left corner of the array substrate onto substrate 1 and the edge of the array substrate along the Y direction is 2 mm or 3 mm, and the distance between the outer contour of device region A and the outer contour of peripheral region B along the Y direction is 0.7 mm. That is, all devices on the array substrate are located within the area of ​​device region A.

[0089] Substrate 1 can be a rigid substrate. The material of the rigid substrate can be any one of glass, quartz, PET, or plastic. The thickness of the rigid substrate can be 0.2mm-1mm. For example, the thickness of the rigid substrate is 0.2mm, 0.4mm, 0.5mm, 0.7mm, or 1mm.

[0090] The light-emitting device can be a mini LED or a micro LED, and there is no limitation on it.

[0091] For example, the multiple devices 12 can all be sub-millimeter light-emitting diodes or micro light-emitting diodes that emit blue light, or the multiple devices 12 can simultaneously include three types of light-emitting diodes or micro light-emitting diodes that emit red light, green light and blue light.

[0092] Since the light emitted by the light-emitting device is directed in all directions, the reflective layer 20 can reflect the light emitted by the light-emitting device to the light-emitting surface of the array substrate, thereby improving the light utilization rate of the light-emitting device.

[0093] For example, the reflective layer 20 is white to give it a high reflectivity.

[0094] In some embodiments, the reflective layer 20 may be a sheet structure with multiple cutout areas L, or the reflective layer 20 may be fabricated on the array substrate by processes such as sputtering, coating, or plating.

[0095] For example, the material of the reflective layer 20 may include white ink, the components of which include resin (e.g., epoxy resin, polytetrafluoroethylene resin), titanium dioxide (chemical formula TiO2), and organic solvent (e.g., dipropylene glycol methyl ether), etc.

[0096] The material of the reflective layer 20 may also include silicone-based white adhesive. When the material of the reflective layer 20 includes white ink or silicone-based white adhesive, the reflective layer 20 can be formed by screen printing or by spray coating.

[0097] For example, refer to Figure 2b As shown, the distance T1 between the surface of the reflective layer 20 that contacts the interlayer dielectric layer 30 and the surface of the reflective layer 20 that is away from the interlayer dielectric layer 30 can range from 10 μm to 300 μm. For example, the thickness can be 10 μm, 50 μm, 55 μm, 60 μm, 80 μm, 155 μm, 200 μm or 300 μm.

[0098] For example, the reflective layer 20 can be formed by one or more screen printing processes.

[0099] When the reflective layer 20 is produced using a multi-screen printing process, the portion of the reflective layer 20 located at the edge of the cutout area L can be stepped.

[0100] For example, the shape of the orthographic projection of the cutout area L onto the substrate 1 can be a circle, a triangle, or a rectangle, etc.

[0101] The portion of the conductive pattern on the substrate 1 exposed by the cutout area L on the reflective layer 20 is used to connect to the device 12, while the portion of the conductive pattern covered by the reflective layer 20 is used to connect to an external signal source circuit to receive and transmit electrical signals to the device 12.

[0102] The meaning of the interlayer dielectric layer 30 being located at least between the substrate 1 and the reflective layer 20 is: Reference Figure 1a As shown, in the area of ​​the array substrate where no device 12 is disposed, the interlayer dielectric layer 30 is located between the substrate 1 and the reflective layer 20; in the cutout area L, a portion of the interlayer dielectric layer 30 is disposed in a portion of the area between conductive patterns (e.g., between conductive pads 71 ​​and 72), and this portion of the interlayer dielectric layer 30 is located between the substrate 1 and the device 12.

[0103] refer to Figure 1a As shown, the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the substrate 1. The orthogonal projections of the first openings K1 and / or the second openings K2 on the substrate 1 are located within the orthogonal projection range of the cutout region L on the substrate 1.

[0104] The first opening K1 in the interlayer dielectric layer 30 exposes a portion of the conductive pattern disposed on the substrate 1, and the second opening K2 in the interlayer dielectric layer 30 exposes another portion of the conductive pattern disposed on the substrate 1, so that the device 12 is connected to the conductive pattern, and the conductive pattern is connected to an external signal source circuit to receive electrical signals.

[0105] In some embodiments, a reflective layer 20 is provided in both the device region A and the peripheral region B, for example: Reference Figure 1a or Figure 2a As shown, the orthographic projection of the reflective layer 20 on the array substrate does not overlap with the cutout area L.

[0106] For example, the portion of the reflective layer 20 disposed in device region A is located on the side of the interlayer dielectric layer 30 away from the substrate 1, and depending on the material and / or the manufacturing process of the reflective layer 20, the orthographic projection of the reflective layer 20 on the substrate 1 and the orthographic projection of the interlayer dielectric layer 30 on the substrate 1 may have different overlap conditions.

[0107] For example, when the reflective layer 20 is made using a multi-screen printing process, the boundary of the reflective layer 20 in the cutout area L is stepped, and the interlayer dielectric layer 30 in the cutout area L is not covered by the reflective layer 20.

[0108] Figure 3A schematic diagram of an array substrate is shown, in which the reflective layer 20 is not disposed in the peripheral region B of the substrate 1. (Refer to...) Figure 3 As shown, the reflective layer 20 covers almost all areas of the array substrate device region A except for the cutout region L, but does not cover the peripheral region B of the substrate 1. Figure 3 When the array substrate shown emits light, there is no device 12 in the peripheral area B and no reflective layer 20 to reflect light, thus presenting a relatively dark visual effect, that is, the light emission effect is poor.

[0109] The embodiments provided in this application are as follows Figure 1a or Figure 2a In the array substrate shown, since the outer contour of the peripheral region B of the array substrate is the outer contour of the substrate 1, and the portion of the reflective layer 20 located in the peripheral region B covers the peripheral region B of the substrate 1, the portion of the reflective layer 20 located in the peripheral region B can extend to the outer contour of the substrate 1. Thus, when the array substrate emits light, the reflective layer 20 in the peripheral region B can reflect the light emitted from the device region A and incident on its surface, which greatly improves the problem of the large optical brightness difference between the peripheral region B of the array substrate and the device region A. At the same time, it can increase the amount of light emitted by the array substrate in the direction perpendicular to the plane of the substrate 1, thereby improving the light emission efficiency of the array substrate.

[0110] In some embodiments of this application, reference is made to Figure 1a or Figure 2a As shown, the reflective layer 20 includes a first reflective sublayer 10 and a second reflective sublayer 11, with the second reflective sublayer 11 located on the side of the first reflective sublayer 10 away from the substrate 1; the orthographic projection of the first reflective sublayer 10 onto the substrate 1 is located in the device region A and the peripheral region B.

[0111] Wherein, the orthographic projection of the portion of the first reflective sublayer 10 located in device region A on substrate 1 overlaps with the orthographic projection of the interlayer dielectric layer 30 on substrate 1, and the first reflective sublayer 10 also covers the substrate 1 in the peripheral region B.

[0112] The orthographic projection of the second reflective sublayer 11 on the substrate 1 is within the orthographic projection of the first reflective sublayer 10 on the substrate 1.

[0113] In some embodiments, reference Figure 1a As shown, a reflective layer 20 is not required on a portion of the interlayer dielectric layer 30 between the device 12 and the substrate 1. Instead, a reflective layer 20 is provided on the interlayer dielectric layer 30 outside the area where the device 12 is located, such that the orthographic projection of the reflective layer 20 on the substrate 1 overlaps with the orthographic projection of the interlayer dielectric layer 30 on the substrate 1.

[0114] In some embodiments, the orthographic projection of the portion of the first reflective sublayer 10 located in device region A onto the substrate 1 overlaps with the orthographic projection of the interlayer dielectric layer 30 onto the substrate 1. However, in actual fabrication, due to process errors, in a portion of the array substrate, the first reflective sublayer 10 in the reflective layer 20 may extend in the direction pointing from the first reflective sublayer 10 to the device 12, such that the first reflective sublayer 10 covers as shown in the diagram. Figure 1a The portion of the interlayer dielectric layer 30 shown in the diagram, located in the cutout area L, does not overlap with the orthographic projection of device 12 on substrate 1.

[0115] In some embodiments, the orthogonal projection of the second reflective sublayer 11 onto the substrate 1 lies within the orthogonal projection of the first reflective sublayer 10 onto the substrate 1.

[0116] For example, refer to Figure 1a As shown, the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device region A and the peripheral region B. The orthographic projection of the portion of the second reflective sublayer 11 located in the device region A on the substrate 1 is within the orthographic projection of the portion of the first reflective sublayer 10 located in the device region A on the substrate 1. The orthographic projection of the portion of the second reflective sublayer 11 located in the peripheral region B on the substrate 1 overlaps with the orthographic projection of the portion of the first reflective sublayer 10 located in the peripheral region B on the substrate 1.

[0117] Alternatively, the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device region A and the peripheral region B. The orthographic projection of the portion of the second reflective sublayer 11 disposed in the device region A on the substrate 1 is within the orthographic projection of the portion of the first reflective sublayer 10 disposed in the device region A on the substrate 1, and the orthographic projection of the portion of the second reflective sublayer 11 disposed in the peripheral region B on the substrate 1 is within the orthographic projection of the portion of the first reflective sublayer 10 disposed in the peripheral region B on the substrate 1.

[0118] Or, refer to Figure 2a As shown, the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in device region A, and the second reflective sublayer 11 is not provided in the peripheral region B. The orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the portion of the first reflective sublayer 10 provided in device region A on the substrate 1.

[0119] In some embodiments, the orthographic projection of the first reflective sublayer 10 onto the substrate 1 may be located within the orthographic projection of the second reflective sublayer 11 onto the substrate 1. The accompanying drawings of the embodiments of this application illustrate an example where the orthographic projection of the second reflective sublayer 11 onto the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 onto the substrate 1.

[0120] In some embodiments, reference Figure 2aAs shown, the first reflective sublayer 10 covers the edge of the substrate 1, and the second reflective sublayer 11 is recessed into the device region A; such that the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 is controlled within the range of 0.2-2mm.

[0121] For example, the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.5mm, 1.8mm or 2mm. The specific value of the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be determined according to the different designs of the array substrate, the different manufacturing processes or cutting processes of the array substrate.

[0122] In some embodiments, reference Figure 2d A top view of an array substrate is shown, wherein, Figure 2a yes Figure 2d A cross-sectional view along the M1M2 direction. (See diagram below.) Figure 2d As shown, multiple devices 12 are arrayed in device region A. The reflective layer 20 in device region A includes a first reflective sublayer 10 and a second reflective sublayer 11. The reflective layer 20 in peripheral region B includes the first reflective sublayer 10. Figure 2d Only the second reflective sublayer 11 located on the surface of device region A is visible; while the first reflective sublayer 10 covers the edge of the substrate 1 located in the peripheral region B, and the second reflective sublayer 11 is recessed into device region A; so that the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 is controlled within the range of 0.2-2mm. Figure 2d Device 12 shown in the figure is a light-emitting device.

[0123] In some embodiments, the first reflective sublayer 10 and the second reflective sublayer 11 may be made of different materials. For example, the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include silicone-based white glue; or, the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include a reflective sheet.

[0124] Alternatively, the first reflective sublayer 10 and the second reflective sublayer 11 may be made of the same material. For example, both the first reflective sublayer 10 and the second reflective sublayer 11 may be made of white ink. When the materials of the first reflective sublayer 10 and the second reflective sublayer 11 are white ink or silicone-based white glue, screen printing can be used to print the first reflective sublayer 10 and the second reflective sublayer 11, respectively.

[0125] For example, the thickness of the first reflective sublayer 10 along the direction perpendicular to the substrate 1 can be in the range of 25μm-35μm, such as 25μm, 28μm, 30μm, 32μm or 35μm.

[0126] For example, the thickness of the second reflective sublayer 11 in the direction perpendicular to the substrate 1 can be in the range of 25μm-35μm, such as 25μm, 28μm, 30μm, 32μm or 35μm.

[0127] In some embodiments of this application, reference is made to Figure 2a As shown, the second reflective sublayer 11 is located in device region A; the orthographic projection of the second reflective sublayer 11 on substrate 1 does not overlap with peripheral region B. It should be noted that, since peripheral region B refers to the area between device region A and the boundary (cutting line) of array substrate during the fabrication of array substrate, setting the first reflective sublayer 10 on substrate 1 in peripheral region B without setting the second reflective sublayer 11 can, on the one hand, improve the problem of thin film peeling of reflective layer 20 caused by the cutting process when cutting from mother board to array substrate; on the other hand, since the first reflective sublayer 10 is set on substrate 1 in peripheral region B, the first reflective sublayer 10 covers the outer contour of substrate 1, so when the array substrate emits light, the first reflective sublayer 10 in peripheral region B can reflect the light emitted by the array substrate, improving the problem of large optical brightness difference between peripheral region B and device region A of array substrate, greatly increasing the amount of light emitted by array substrate in the direction perpendicular to the plane of substrate 1, thereby improving the light emission efficiency of array substrate.

[0128] In some embodiments, when the materials of both the first reflective sublayer 10 and the second reflective sublayer 11 comprise white ink, and the thicknesses of both the first reflective sublayer 10 and the second reflective sublayer 11 are in the range of 25-35 μm, such as Figure 2a In the array substrate shown, the reflectivity values ​​of the reflective layer 20 in device region A and the reflective layer 20 in peripheral region B differ by less than 5%, which will not cause obvious optical differences between device region A and peripheral region B.

[0129] In some embodiments of this application, reference is made to Figure 1a As shown, the orthographic projections of the first reflective sublayer 10 and the second reflective sublayer 11 on the substrate 1 both extend and cover the peripheral region B. Furthermore, the boundaries of the first reflective sublayer 10 and the second reflective sublayer 11 are basically coincident with the outer contour of the substrate 1. Thus, when the array substrate emits light, the first reflective sublayer 10 and the second reflective sublayer 11 in the peripheral region B can reflect the light emitted by the array substrate. Under the dual action of the first reflective sublayer 10 and the second reflective sublayer 11, the problem of the large optical brightness difference between the peripheral region B and the device region A of the array substrate can be effectively improved. In addition, the amount of light emitted by the array substrate in the direction perpendicular to the plane of the substrate 1 is greatly increased, thereby improving the light emission efficiency of the array substrate.

[0130] In some embodiments, reference Figure 2dAs shown, the array substrate also includes a bonding area D on one side of it. No reflective layer 20 is provided in the bonding area D. The bonding area D includes multiple bonding terminal groups 107. One end of the bonding terminal group 107 is used to connect to the gold finger structure of an external circuit (circuit board or integrated circuit) to receive electrical signals, and the other end is connected to a conductive pattern on the array substrate, such as a signal line, to transmit electrical signals.

[0131] In some embodiments of this application, the first reflective sublayer 10 and the second reflective sublayer 11 have the same thickness along the direction perpendicular to the substrate 1.

[0132] For example, the thickness of the first reflective sublayer 10 and the second reflective sublayer 11 along the direction perpendicular to the substrate 1 is 25 μm, or 30 μm, or 35 μm.

[0133] In some embodiments of this application, reference is made to Figure 1a or Figure 2a As shown, the array substrate also includes an auxiliary reflective portion 13; the auxiliary reflective portion 13 is located on the interlayer dielectric layer 30, and the auxiliary reflective portion 13 is connected to the reflective layer 20.

[0134] When the process stability is sufficiently high, in device region A, the orthographic projection of the reflective layer 20 onto the substrate 1 covers the portion of the interlayer dielectric layer 30 excluding the cutout area L. However, considering process accuracy and manufacturing errors, in actual manufacturing, in some areas of device region A excluding the cutout area L, the orthographic projection of the reflective layer 20 onto the substrate 1 falls within the orthographic projection of the interlayer dielectric layer 30 onto the substrate 1. Therefore, to ensure the reflection effect, an auxiliary reflective part 13 is provided after the reflective layer 30 is set to enhance the reflection effect.

[0135] In some embodiments, when the reflective layer 20 is fabricated using a multiple screen printing process, refer to Figure 1a As shown, the reflective layer 20 at the edge of the cutout area L can be stepped. The reflective layer 20 near the edge of the cutout area L exposes the portion of the interlayer dielectric layer 30 located in the cutout area L. At this time, an auxiliary reflective part 13 can be provided on this portion of the interlayer dielectric layer 30 to cover part of the surface of the interlayer dielectric layer 30 exposed by the reflective layer 20 at the edge of the cutout area L, thereby further increasing the amount of light emitted by the array substrate in the direction perpendicular to the plane of the substrate 1, thereby improving the light emission efficiency of the array substrate.

[0136] In some embodiments, an auxiliary reflective portion 13 is provided on the sidewall of the hollowed-out area L of the reflective layer 20, which can reduce the radial dimension of the hollowed-out area L and improve the dimensional accuracy of the hollowed-out area L. The figures are all labeled with the case where the radial dimension of the hollowed-out area L is not reduced.

[0137] In some embodiments, reference Figure 2bAs shown, the distance T2 between the surface of the auxiliary reflective part 13 that contacts the interlayer dielectric layer 30 and the surface of the auxiliary reflective part 13 that is away from the interlayer dielectric layer 30 is greater than the distance T1 between the surface of the reflective layer 20 that contacts the interlayer dielectric layer 30 and the surface of the reflective layer 20 that is away from the interlayer dielectric layer 30.

[0138] For example, the distance T2 between the surface of the auxiliary reflective portion 13 that contacts the interlayer dielectric layer 30 and the surface of the auxiliary reflective portion 13 that is away from the interlayer dielectric layer 30 can be in the range of 50μm-80μm; the distance T1 between the surface of the reflective layer 20 that contacts the interlayer dielectric layer 30 and the surface of the reflective layer 20 that is away from the interlayer dielectric layer 30 can be in the range of 30μm-50μm.

[0139] It should be noted that the auxiliary reflective part 13 can be set around the edge of the hollow area L by spraying.

[0140] In some embodiments, the material of the auxiliary reflective part 13 includes a silicon-based white adhesive, which is white in color, so that the color of the auxiliary reflective part 13 is approximately the same as the color of the reflective layer 20, thereby ensuring that the reflectivity of the auxiliary reflective part 13 to light is close to that of the reflective layer 20 to light.

[0141] In some embodiments of this application, reference is made to Figure 1a or Figure 2a As shown, the auxiliary reflector 13 includes a first reflector 132 and a second reflector 131, and the first reflector 132 and the second reflector 131 are an integral structure.

[0142] The cutout area L in the reflective layer 20 exposes a portion of the interlayer dielectric layer 30. The orthographic projection of the first reflective part 132 on the substrate 1 is located in the cutout area L, and the first reflective part 132 is in direct contact with the interlayer dielectric layer 30. The second reflective part 131 is in direct contact with the surface of the reflective layer 20 away from the substrate 1, and the orthographic projection of the second reflective part 131 on the substrate 1 overlaps with the orthographic projection of the reflective layer 20 on the substrate 1.

[0143] In some embodiments, reference Figure 2a As shown, the second reflective portion 131 covers a portion of the surface of the first reflective sublayer 10 away from the substrate 1, and a gap Z exists between the second reflective portion 131 and the second reflective sublayer 11 in a direction parallel to the plane of the substrate 1. Alternatively, refer to... Figure 2b As shown, the second reflective portion 131 covers a portion of the surface of the first reflective sublayer 10 away from the substrate 1, and the second reflective portion 131 is connected to the second reflective sublayer 11 in a direction parallel to the plane of the substrate 1. Alternatively, refer to... Figure 2cAs shown, the second reflective portion 131 covers a portion of the surface of the first reflective sublayer 10 away from the substrate 1, and the second reflective portion 131 also covers a portion of the surface of the second reflective sublayer 11 away from the substrate 1.

[0144] In some embodiments of this application, reference is made to Figure 1a or Figure 2a As shown, the array substrate also includes a plurality of packaging units 14 corresponding to the device 12. The orthographic projection of the packaging unit 14 on the substrate 1 covers the orthographic projection of the device 12 on the substrate 1, and the orthographic projection of the packaging unit 14 on the substrate 1 partially overlaps with the orthographic projection of the reflective layer 20 on the substrate 1.

[0145] For example, such as Figure 1a or Figure 2a As shown, each encapsulation unit 14 encapsulates one device 12. While providing encapsulation and protection for the device 12, the encapsulation unit 14 can also be designed with a surface shape away from the substrate 1, such as having a convex lens-like surface, thereby further adjusting the light emission angle of the light-emitting device included in the device 12.

[0146] In some embodiments, the array substrate may further include an encapsulation layer disposed on the side of the device 12 away from the substrate 1 for protecting the device 12.

[0147] For example, the encapsulation layer may be an entire layer covering multiple devices 12.

[0148] Figure 4 This diagram illustrates a structural schematic of device region A on an array substrate. (Refer to...) Figure 4 As shown, the device region A of the array substrate includes a buffer layer 2 and a first conductive layer 7 sequentially disposed on the substrate 1, and an interlayer dielectric layer 30 is located on the side of the first conductive layer 7 away from the substrate 1; wherein, the interlayer dielectric layer 30 includes a first insulating layer 8 and a first planarization layer 9, and the first planarization layer 9 is located at least between the first insulating layer 8 and the reflective layer 20.

[0149] The first conductive layer 7 is used to form a conductive pattern.

[0150] For example, refer to Figure 4 As shown, a first conductive layer 7 is provided in the array substrate. The portion of the first conductive layer 7 covered by the first insulating layer 8 forms the trace 73 in the conductive pattern, which is used to transmit electrical signals. The portion of the first conductive layer 7 not covered by the first insulating layer 8 and far from the surface of the substrate 1 forms a conductive pad, which is used to electrically connect with the device 12 to transmit the electrical signals transmitted in the trace 73 to the device 12.

[0151] For example, if there is sufficient space on substrate 1 to arrange all conductive patterns, the array substrate may include only one conductive layer.

[0152] In some embodiments, the material of the first conductive layer 7 may include any one of copper, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0153] For example, the first conductive layer 7 may include a molybdenum-nickel-titanium alloy (MoNiTi) layer, a copper metal layer, and a molybdenum-niobium alloy (MoNb) layer stacked sequentially. The molybdenum-nickel-titanium alloy layer can increase the nucleation density of copper metal grains during the electroplating process, and the molybdenum-niobium alloy layer serves to prevent copper metal oxidation. The thickness range of the molybdenum-nickel-titanium alloy layer in the first conductive layer 7 may be [missing information]. For example, the thickness can be or

[0154] In some embodiments, the thickness of the first conductive layer 7 can range from 1.5 μm to 7 μm, for example, the thickness can be 1.5 μm, 2 μm, 4 μm, 6.5 μm or 7 μm.

[0155] Figure 5 Another structural schematic diagram of device region A of array substrate is shown. Referring to 5, device region A of array substrate further includes a second conductive layer 3, a second insulating layer 4, a second planarization layer 5 and a third insulating layer 6 stacked sequentially on buffer layer 2. The third insulating layer 6 is located on the side of first conductive layer 7 away from first insulating layer 8.

[0156] In some embodiments, reference Figure 5 As shown, the first conductive layer 7 and the second conductive layer 3 together form a conductive pattern. The first conductive layer 7 is positioned further away from the substrate 1 than the second conductive layer 3. Therefore, the portion of the first conductive layer 7 away from the substrate 1 that is not covered by the interlayer dielectric layer 30 constitutes a conductive pad for electrical connection with the device 12. The portion of the first conductive layer 7 covered by other film layers, along with the second conductive layer 3, constitutes the signal lines and connection lines in the conductive pattern, used to receive and transmit electrical signals from an external signal source circuit to the device 12. In the accompanying drawings provided in the embodiments of this application, the conductive pattern of the second conductive layer 3 is not specifically depicted; its patterned structure can be determined based on the circuit layout design of the array substrate.

[0157] In some embodiments, the material of the second conductive layer 3 may include any one of copper, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0158] In some embodiments, the second conductive layer 3 may include a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer stacked sequentially. The protective layer may include any one of copper-nickel alloy (CuNi), nickel, or indium tin oxide (ITO). The molybdenum-niobium alloy layer enhances the adhesion between the copper metal and the film layer near the substrate, while the protective layer prevents oxidation of the copper metal.

[0159] For example, the thickness of the second conductive layer 3 can be in the range of 0.5-10 μm, for example, the thickness can be 0.5 μm, 1 μm, 1.8 μm, 2.7 μm or 10 μm.

[0160] In some embodiments of this application, reference is made to Figure 1a or Figure 2a As shown, the exposed portion of the surface of the first conductive layer 7 away from the substrate 1 constitutes a conductive pad. The conductive pad includes, for example, at least one first pad 71 and at least one second pad 72. The interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the substrate 1. The first openings K1 expose the area where the first pad 71 is located, and the second openings K2 expose the area where the second pad 72 is located.

[0161] The first pad 71 is electrically connected to the first solder pin 151 of the device 12 through the first opening K1, and the second pad 72 is electrically connected to the second solder pin 152 of the device 12 through the second opening K2.

[0162] In some embodiments, the first pad 71 and the first lead 151 are electrically connected by a soldering material (e.g., solder, not shown) located in the first opening K1, and the second pad 72 and the second lead 152 are electrically connected by a soldering material located in the second opening K2, so as to transmit electrical signals to the device 12 through the first pad 71 and the second pad 72.

[0163] In some embodiments, the soldering material may be pre-printed on the first solder pad 71 and the second solder pad 72, or it may be pre-formed on the first solder foot 151 and the second solder foot 152.

[0164] In some embodiments of this application, the array substrate further includes a plurality of support pillars 102, which are located on the side of the reflective layer 20 away from the substrate 1, and the orthographic projection of the support pillars 102 on the substrate 1 does not overlap with the orthographic projection of the device 12 on the substrate 1.

[0165] It should be noted that the color of the support column 102 can be selected as needed. For example, the support column 102 can be white so that its reflectivity is close to that of the reflective layer 20. Alternatively, the support column 102 can be transparent.

[0166] In some embodiments, reference Figure 1b As shown, the peripheral region B may further include at least one or more of the following film layers: buffer layer 2, second conductive layer 3, second insulating layer 4, second planarization layer 5, third insulating layer 6, first conductive layer 7, first insulating layer 8, and first planarization layer 9. The other film layer structures that the peripheral region B may include besides the reflective layer 20 are determined according to the actual design and are not limited here.

[0167] Embodiments of this application also provide a light-emitting device, see reference. Figure 6 As shown, it includes the array substrate 100 as described above.

[0168] in, Figure 1a The middle substrate 1 and all the film layers between the substrate 1 and the reflective layer 20 constitute Figure 6 The substrate 101 shown herein, exemplarily, includes a substrate 1 and a buffer layer 2, a second conductive layer 3, a second insulating layer 4, a second planarization layer 5, a third insulating layer 6, a first conductive layer 7, a first insulating layer 8, and a first planarization layer 9 stacked on the substrate 1.

[0169] The specific film layers and components included in the array substrate 100 can be referred to the previous description, and will not be repeated here.

[0170] In some embodiments, a light-emitting device is provided, which includes an array substrate provided in the embodiments of this application.

[0171] In some embodiments, the light-emitting device may further include a protective substrate (or cover plate) covering the array substrate.

[0172] The light-emitting device can be used as a backlight device or a display device. Specifically, if all the multiple devices 12 in the light-emitting device are light-emitting devices that emit a single color of light, then the light-emitting device can be used as a backlight device; if the multiple devices 12 in the light-emitting device include light-emitting devices that emit different colors of light, such as three types of light-emitting devices that emit red light, green light, and blue light, then the light-emitting device can be used as a display device.

[0173] In some embodiments, when the array substrate 100 is used in a display device, the support pillars 102 may not be provided in the array substrate 100.

[0174] In some embodiments of this application, reference is made to Figure 6 As shown, the light-emitting device also includes a diffuser plate 103, a quantum dot film 104, a diffuser sheet 105, and a composite film 106 stacked in sequence; wherein, the diffuser plate 103 is located on the light-emitting side of the array substrate 100.

[0175] Multiple support pillars 102 are used to support multiple optical films (including diffuser plate 103, quantum dot film 104, diffuser sheet 105 and composite film 106), so that there is a light mixing distance between the reflective layer 20 in the array substrate 100 and the optical films, which can improve the lamp shadow generated by the array substrate and improve the display quality of the light-emitting device.

[0176] In some embodiments, the material of the diffuser plate 103 may include any one of glass, polystyrene (PS), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polyvinyl chloride (PVC), polyethylene terephthalate (PET), acrylic (PMMA), and acrylic acid (MMA).

[0177] Specifically, quantum dot films (QDEF) are a technology that uses quantum dot phosphors and polymers to form a film. For example, the material of quantum dot film 104 may include perovskite quantum dot material, and its thickness is generally around 100 μm.

[0178] In some embodiments, the material of the diffuser sheet 105 may be the same as the material of the diffuser plate 103.

[0179] In some embodiments, the composite film 106 serves not only to improve light efficiency but also as a protective film for the diffuser plate 103, quantum dot film 104, and diffuser sheet 105, protecting them from scratches or damage.

[0180] In the light-emitting device provided in the embodiments of this application, since the outer contour of the substrate 1 is consistent with the outer contour of the peripheral region B of the array substrate, and the reflective layer 20 located in the peripheral region B covers the substrate 1 located in the peripheral region B, the reflective layer 20 located in the peripheral region B covers the outer contour of the substrate 1, so that there is no non-reflective area on the substrate 1 in the peripheral region B. Therefore, when the light-emitting device emits light, the reflective layer 20 in the peripheral region B can reflect the light emitted by the light-emitting device, which greatly improves the problem of the large optical brightness difference between the peripheral region B and the device region A of the light-emitting device, and greatly increases the amount of light emitted by the light-emitting device in the direction perpendicular to the plane of the substrate 1, thereby improving the light emission efficiency of the light-emitting device.

[0181] Embodiments of this application also provide a splicing display device, see reference. Figure 7 As shown, it includes at least two light-emitting devices as described above.

[0182] It should be noted that the light-emitting devices used in the splicing display device include multiple devices 12 that simultaneously emit red, green and blue light.

[0183] In some embodiments, the splicing display device may further include a multi-port repeater, a power supply, a first frame, and a second frame.

[0184] In this configuration, the light-emitting surface of each light-emitting device is located on the same plane, and each light-emitting device is fixed to the first frame. The first frame is fixed to the second frame, and the second frame is located on the side of the first frame away from the light-emitting device. The multi-port repeater and the power supply equipment are both fixed to the second frame. The multi-port repeater and the power supply equipment are electrically connected, and the binding terminal group 107 of each light-emitting device is electrically connected to the multi-port repeater.

[0185] It should be noted that, Figure 7 The splicing display device shown is composed of Figure 2d The light-emitting device is constructed by splicing together the array substrate shown in the figure.

[0186] In the splicing display device provided in the embodiments of this application, since a reflective layer 20 is also provided in the peripheral area B of the light-emitting device used in the splicing display device (in... Figure 7 In the peripheral area B, a first reflective sub-layer 10 is set, which can reflect the light emitted by the light-emitting device. This greatly improves the problem of the large optical brightness difference between the peripheral area B and the device area A. In the splicing display device formed by splicing the light-emitting devices, when the splicing width is small enough and almost imperceptible to the human eye, there is no optical dark area in the area between two adjacent light-emitting devices, thereby greatly improving the display effect of the splicing display device.

[0187] Regarding the array substrate mentioned above, since a reflective layer 20 is provided on the substrate 1 in the peripheral region B, on the one hand, when using a conventional front-side cutting process to cut the array substrate from the front of the mother board, refer to Figure 8c As shown, since the cutting wheel 302 is fixed on the cutting wheel clamp 301, the cutting wheel clamp 301 will scratch the packaging unit 14 on the array substrate and leave marks on the packaging unit 14 such as Figure 8a The scratches shown are an example. On the other hand, since the cutting wheel 302 cuts directly onto the reflective layer 20, scratches such as those seen are left on the reflective layer 20. Figure 8a He Ru Figure 8b The cutting marks shown cause localized peeling of the reflective layer 20. The peeled-off debris from the reflective layer 20 falls back onto the reflective layer 20, affecting its reflective effect. Furthermore, the front-side cutting process using a cutting wheel will cut into the reflective layer 20. Due to the influence of the reflective layer 20, the cutting wheel 302 has difficulty directly cutting onto the surface of the substrate 1, leading to cutting failure.

[0188] Figure 8dA schematic diagram of a front-side cutting process using a cutting wheel is shown. The substrate to be cut is located on the cutting machine 305. To ensure successful cutting using this front-side cutting process, the following conditions must be met: First, the distance d1 between the reflective layer 20 and the axis of the cutting wheel 302 (where the cutting line is located) must be greater than or equal to 0.7 mm to allow the cutting wheel 302 to directly cut the surface of the substrate 1. Second, the distance d2 between the clamping jig 301 of the cutting wheel and the packaging unit 104 must be greater than 0 mm to ensure that the clamping jig 301 does not scratch the packaging unit 104. In practical applications, the distance between the axis of the cutting wheel and one edge of the clamping jig 301 is approximately 3 mm. With a radius r of 1.25 mm for the packaging unit 14 and a cutting process fluctuation range of 0.25 mm, the distance d3 between the axis of the cutting wheel 302 and the geometric center of the orthographic projection of the packaging unit 14 onto the mother substrate 400 satisfies d3 ≥ 3 mm + 1.25 mm + 0.25 = 4.5 mm. However, the array substrate obtained by using the front-side cutting process of the blade wheel has a problem that the reflective layer 20 does not extend to the peripheral area B, so the peripheral area B has a large difference in optical brightness compared with the device area A.

[0189] Therefore, embodiments of this application provide a method for fabricating an array substrate, applicable to the fabrication of the array substrate described above, with reference to... Figure 9 As shown, the method includes:

[0190] S901, providing such Figure 10 Or such as Figure 11 The mother substrate 400 shown is divided into at least one device region A and a cutting region C adjacent to the device region A.

[0191] It should be noted that by removing the area C1 outside the cutting line in the cutting area C, the surrounding area B can be obtained.

[0192] For example, as Figure 10 The mother substrate 400 shown is cut along the cutting line. After removing the C1 region of the mother substrate 400, at least one substrate 1 can be obtained.

[0193] S902. An interlayer dielectric layer 30 is formed on the device region A of the mother substrate 400;

[0194] S903. A reflective layer 20 is formed on the device area A and the dicing area C of the mother substrate 400;

[0195] The reflective layer 20 has multiple cutout areas L along a direction perpendicular to the mother substrate 400; the interlayer dielectric layer 30 is located at least between the mother substrate 400 and the reflective layer 20; the orthographic projection of the portion of the reflective layer 20 located in device region A on the mother substrate 400 overlaps with the orthographic projection of the interlayer dielectric layer 30 on the mother substrate 400; and the portion of the reflective layer 20 located in cutting region C covers the cutting region C of the mother substrate 400.

[0196] S904. Multiple devices 12 are bonded in device area A of mother substrate 400; device 12 is located in cutout area L;

[0197] Device area A is provided with an array of various devices 12, including light-emitting devices, as well as any one of sensor devices, micro-driver chips or other types of devices.

[0198] The meaning of the interlayer dielectric layer 30 being located at least between the substrate 1 and the reflective layer 20 is: Reference Figure 1a As shown, in the area of ​​the array substrate where no device 12 is disposed, the interlayer dielectric layer 30 is located between the substrate 1 and the reflective layer 20; in the cutout area L, a portion of the interlayer dielectric layer 30 is disposed in a portion of the area between the conductive patterns (between conductive pads 71 ​​and 72), and this portion of the interlayer dielectric layer 30 is located between the substrate 1 and the device 12.

[0199] Combination Figure 10 and Figure 1a As shown, the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the mother substrate 400. The orthogonal projections of the first openings K1 and / or the second openings K2 on the substrate 1 are located within the orthogonal projection range of the cutout region L on the substrate 1.

[0200] The first opening K1 in the interlayer dielectric layer 30 exposes the conductive pattern 71 disposed on the substrate 1, and the second opening K2 in the interlayer dielectric layer 30 exposes the conductive pattern 72 disposed on the substrate 1, so that the device 12 is connected to the conductive pattern 71 and the conductive pattern 72 respectively, and the conductive pattern is connected to an external signal source circuit to receive electrical signals.

[0201] A reflective layer 20 is provided in both device area A and cutting area C. Example: Reference Figure 10 or Figure 11 As shown, a reflective layer 20 is provided in all areas of the mother plate of the array substrate except for the cutout area L where the device 12 is set.

[0202] In some embodiments, at least one of the buffer layer 2, the second conductive layer 3, the second insulating layer 4, the second planarization layer 5, the third insulating layer 6, the first conductive layer 7, the first insulating layer 8, and the first planarization layer 9 may extend to the cutting area C, depending on the actual design, and is not limited here.

[0203] S905. Cut along the cutting line from the back side of the mother substrate 400 to obtain at least one array substrate; the cutting line is located in the cutting area C, and the back side is the surface of the mother substrate 400 away from the device 12.

[0204] Figure 12a A schematic diagram of a back-side cutting process is shown.

[0205] In some embodiments, reference Figure 12a As shown, when cutting along the cutting line from the back side of the mother substrate 400, the mother substrate of the array substrate is located on the cutting machine 305, and the cutting wheel 302 is disposed on the back side of the mother substrate 400. In addition, since the mother substrate 400 is not supported by the cutting machine 305 near the cutting area and is in a suspended state, a roller 306 is also provided on the other side of the mother substrate of the array substrate opposite to the cutting wheel 302 to counteract the cutting pressure generated by the cutting wheel 302 when cutting from the back side of the mother substrate 400.

[0206] Since the back of the mother substrate 400 does not have a reflective layer 20, it can be cut at any position in the cutting area according to the cutting requirements. In this way, when cutting, there is no need to consider the distance between the axis of the cutting wheel 302 and the edge of the reflective layer 20, nor is there any need to consider the possible scratches and wear of the clamps 301 of the cutting wheel 302 on the packaging unit 14. Moreover, when cutting from the back, the cutting wheel 302 can directly contact the back of the mother substrate 400, and there is no problem of cutting failure caused by the influence of the reflective layer 20.

[0207] It should be noted that, Figure 12a and Figure 13a In the diagram, a reflective layer 20, a device 12, and a packaging unit 14 are drawn on the mother substrate 400. Other structures included in the mother substrate of the array substrate are not shown. The other structures included in the mother substrate of the array substrate are similar to those included in the array substrate. For details, please refer to the previous description of the structure of the array substrate. They will not be repeated here.

[0208] Figure 12b It shows Figure 12a A schematic diagram showing the cutting line positions of the motherboard of the array substrate. Figure 12b In the diagram, the position marked by the dashed line is the location of the cutting line. After cutting away the area C1 outside the cutting line along the cutting line, the array substrate can be obtained. The area C1 outside the cutting line of the array substrate mother board also has a reflective layer 20. However, since a back-side cutting process is used, the reflective layer 20 does not affect the cutting process.

[0209] In some embodiments, such as Figure 13a As shown, a schematic diagram of another back-side cutting process is illustrated. Figure 13aIn the middle, the cutting line is located in the middle of the mother plate of the two array substrates. The middle position of the cutting machine table 305 is hollowed out to leave space for the cutting blade 302 to be installed here. Figure 13b It shows Figure 13a A schematic diagram showing the cutting line positions of the motherboard of the array substrate. The area between the two cutting lines is the C1 region that needs to be cut off.

[0210] In some embodiments, such as Figure 14 As shown, to improve the cutting efficiency of the cutting wheel 302 on the back side, a multi-wheel simultaneous cutting method can be used. Figure 14 In each array substrate motherboard corresponding to the position of the cutting wheel 302, a roller 306 is provided on the side of the reflective layer 20 away from the motherboard substrate 400 to balance the cutting pressure generated by the cutting wheel 302 during cutting.

[0211] The embodiments of this application provide a method such as Figure 18 The vacuum chuck 500 shown is a soft-nozzle chuck, which has a good adsorption effect on array substrates with non-flat surfaces and is used to transport and move the mother plate or array substrate during cutting.

[0212] refer to Figure 15a As shown, after cutting, the edges of the array substrate can be ground to reduce the probability of damage caused by possible protrusions, notches or microcracks, thereby improving the reliability of the array substrate.

[0213] In the bevel grinding process, the array substrate is placed on the grinding machine 307, and the grinding wheel 308 rotates counterclockwise so that the grinding wheel 308 grinds the reflective layer 20 first, and then grinds the substrate 1. This avoids localized peeling of the reflective layer 20 caused by pulling when grinding the substrate 1 first. Specifically, during the bevel grinding process, the initial grinding point between the grinding wheel 308 and the array substrate is as follows: Figure 15a At the junction of the surface of the reflective layer 20 and the side surface of the substrate 1, after polishing, the array substrate will produce a surface like... Figure 15c The grinding area shown (the area where the bevel is located) can be examined under a microscope. The width of grinding area G1 is as follows: Figure 15b As shown in the figure, there is no reflective layer 20 in the area of ​​approximately 150 μm, which severely affects the optical performance of the array substrate.

[0214] Therefore, in some embodiments of this application, after the step of cutting along the dicing line from the back side of the mother substrate 400 to obtain at least one array substrate, the fabrication method further includes:

[0215] S906. The edges of the array substrate are ground using a vertical grinding process.

[0216] In some embodiments of this application, step S906, grinding the edge of the array substrate using a vertical grinding process, includes:

[0217] S9061, Reference Figure 16 As shown, the side surface of the substrate 1 and the side surface of the reflective layer 20 of the array substrate are simultaneously ground along a direction perpendicular to the array substrate 100; wherein the side surface of the substrate 1 and the side surface of the reflective layer 20 are coplanar.

[0218] It should be noted that, in Figure 16 In the diagram, the other films between substrate 1 and reflective layer 20 are not shown. Please refer to the previous description for details.

[0219] In some embodiments, a process reference for grinding the array substrate using a vertical grinding process is provided. Figure 16 As shown, the initial grinding point of the grinding wheel 308 is the side of the array substrate. Specifically, the grinding wheel 308 rotates counterclockwise and grinds the side of the substrate 1 and the side of the reflective layer 20 simultaneously. This can greatly reduce the difference between the wear degree of the reflective layer 20 at the edge of the array substrate and the wear degree of the substrate 1, thereby reducing the grinding width of the grinding area G2. The grinding width of the grinding area G2 of the array substrate ground by the vertical grinding process is about 100um. The vertical grinding process greatly improves the optical performance at the edge of the array substrate.

[0220] In some embodiments of this application, step S903, forming the reflective layer 20 on the device region A and the dicing region C of the mother substrate 400, includes:

[0221] S9031. A first reflective sublayer 10 is formed, and the orthogonal projection of the first reflective sublayer 10 on the mother substrate 400 is located within the device region A and the dicing region C.

[0222] S9032, Form a second reflective sublayer 11, the orthogonal projection of the second reflective sublayer 11 on the mother substrate 400 is located in device region A;

[0223] Alternatively, a first reflective sublayer 10 is formed, the orthogonal projection of the first reflective sublayer 10 on the mother substrate 400 is located within the device region A and the dicing region C;

[0224] A second reflective sublayer 11 is formed in device region A and dicing region C. The orthogonal projection of the second reflective sublayer 11 on the mother substrate 400 is located within device region A and dicing region C.

[0225] In some embodiments, references Figure 10As shown, the first reflective sublayer 10 covers the edge of the substrate 1, and the second reflective sublayer 11 is recessed into the device region A; such that the distance H1 between the edge of the second reflective sublayer 11 and the edge (cut line) of the substrate 1 is controlled within the range of 0.2-2mm.

[0226] For example, the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.5mm, 1.8mm or 2mm. The specific value of the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be determined according to the different designs of the array substrate, the different manufacturing processes or cutting processes of the array substrate, and is not limited here.

[0227] In some embodiments, the first reflective sublayer 10 and the second reflective sublayer 11 may comprise different materials. For example, the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include silicone-based white adhesive. Alternatively, the materials of the first reflective sublayer 10 and the second reflective sublayer 11 may be the same. For example, both the first reflective sublayer 10 and the second reflective sublayer 11 may comprise white ink. When the materials of the first reflective sublayer 10 and the second reflective sublayer 11 comprise white ink or silicone-based white adhesive, screen printing can be used to print the first reflective sublayer 10 and the second reflective sublayer 11, respectively.

[0228] For example, the thickness of the first reflective sublayer 10 can be in the range of 25μm-35μm, such as 25μm, 28μm, 30μm, 32μm or 35μm.

[0229] For example, the thickness of the second reflective sublayer 11 can be in the range of 25μm-35μm, such as 25μm, 28μm, 30μm, 32μm or 35μm.

[0230] In some embodiments of this application, after the step of bonding a plurality of devices 12 in device region A of the mother substrate 400, and before the step of cutting along a dicing line from the back side of the mother substrate 400 to obtain at least one array substrate, the method further includes:

[0231] An auxiliary reflective portion 13 is formed on the interlayer dielectric layer 30; wherein the auxiliary reflective portion 13 is connected to the reflective layer 20.

[0232] In some embodiments, when the reflective layer 20 is fabricated using a multiple screen printing process, the reflective layer 20 at the edge of the cutout area L can be stepped, exposing a portion of the interlayer dielectric layer 30. In this case, an auxiliary reflective portion 13 can be provided on the interlayer dielectric layer 30 to cover the portion of the interlayer dielectric layer 30 exposed by the reflective layer 20 at the edge of the cutout area L. This compensates for the problem that the reflective layer 20 is not covered on part of the interlayer dielectric layer 30, thereby further increasing the amount of light emitted by the array substrate in the direction perpendicular to the plane of the substrate 1, thereby improving the light emission efficiency of the array substrate.

[0233] In some embodiments, providing an auxiliary reflective portion 13 on the sidewall of the hollowed-out area L of the reflective layer 20 can reduce the radial dimension of the hollowed-out area L and improve the dimensional accuracy of the hollowed-out area L.

[0234] It should be noted that the auxiliary reflective part 13 can be prepared by spraying around the edge of the hollowed-out area, and reference is made to... Figure 2b As shown, the distance T2 between the surface of the auxiliary reflective part 13 that contacts the interlayer dielectric layer 30 and the surface of the auxiliary reflective part 13 that is away from the interlayer dielectric layer 30 is greater than the distance T1 between the surface of the reflective layer 20 that contacts the interlayer dielectric layer 30 and the surface of the reflective layer 20 that is away from the interlayer dielectric layer 30.

[0235] In some embodiments, the material of the auxiliary reflective part 13 includes a silicon-based white adhesive, which is white in color, so that the color of the auxiliary reflective part 13 is approximately the same as the color of the reflective layer 20, thereby ensuring that the reflectivity of the auxiliary reflective part 13 to light is close to that of the reflective layer 20 to light.

[0236] The embodiments of this application provide schematic diagrams of the structure of a splicing display device formed by array substrates cut using both front-cutting and back-cutting processes. Figure 17a A schematic diagram of a splicing display device is shown, which is formed by cutting an array substrate using a tangential process. Figure 17b A schematic diagram of a splicing display device is shown, which is formed by cutting an array substrate using a back-cutting process.

[0237] exist Figure 17aIn the splicing display device shown, the array substrate forming the light-emitting devices is obtained using a tangential process. The area in the light-emitting device without a reflective layer is marked as 20N. The splicing display device includes two light-emitting devices. In each light-emitting device, the distance from the edge of the reflective layer 20 to the edge of the light-emitting device is 0.7mm. The splicing width d5 ​​of the splicing display device is 0.9mm. Therefore, the width d6 of the area without a reflective layer between two adjacent light-emitting devices is d5 + 0.7mm * 2 = 2.3mm. That is, the distance between the display areas of two adjacent light-emitting devices in the splicing display device is 2.3mm. When the splicing display device displays an image, there will be a 2.3mm wide area that does not display an image (non-display area), which seriously reduces the display effect of the splicing display device.

[0238] exist Figure 17b In the splicing display device shown, the array substrate forming the light-emitting devices is obtained using a back-cutting process. The splicing display device includes two light-emitting devices. In each light-emitting device, there is no area without a reflective layer in each light-emitting device used for splicing. Therefore, the width of the area without a reflective layer between two adjacent light-emitting devices is d6 = d5 = 0.9 mm. Compared with the splicing display device obtained by the orthogonal cutting process, the splicing display device obtained by the back-cutting process has a smaller non-display area between two adjacent light-emitting devices, thereby greatly improving the display effect of the splicing display device.

[0239] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Device area; The peripheral area adjacent to the device area; Both the device region and the peripheral region include a substrate and a reflective layer located on the substrate; The device region further includes an interlayer dielectric layer and a plurality of devices, wherein the interlayer dielectric layer is located at least between the substrate and the reflective layer; the reflective layer has a plurality of cutout regions along a direction perpendicular to the substrate, and the devices are located within the cutout regions; Wherein, the orthographic projection of the portion of the reflective layer located in the device region on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate; the portion of the reflective layer located in the peripheral region covers the portion of the substrate located in the peripheral region; and the outer contour of the substrate is consistent with the outer contour of the peripheral region; the device includes at least a light-emitting device; The array substrate further includes an auxiliary reflective portion; the auxiliary reflective portion is located on the interlayer dielectric layer, and the auxiliary reflective portion is connected to the reflective layer; The auxiliary reflective part includes a first reflective part and a second reflective part, and the first reflective part and the second reflective part are an integral structure; The cutout area exposes a portion of the interlayer dielectric layer, the orthographic projection of the first reflective part on the substrate is located in the cutout area, and the first reflective part is in direct contact with the interlayer dielectric layer; The second reflective portion is in direct contact with the surface of the reflective layer away from the substrate, and the orthographic projection of the second reflective portion on the substrate overlaps with the orthographic projection of the reflective layer on the substrate; The array substrate further includes a plurality of packaging units corresponding to the device. The orthographic projection of the packaging unit on the substrate covers the orthographic projection of the device on the substrate, and the orthographic projection of the packaging unit on the substrate partially overlaps with the orthographic projection of the reflective layer on the substrate.

2. The array substrate according to claim 1, characterized in that, The reflective layer includes a first reflective sublayer and a second reflective sublayer, the second reflective sublayer being located on the side of the first reflective sublayer away from the substrate; the orthographic projection of the first reflective sublayer onto the substrate is located in the device region and the peripheral region; Wherein, the orthographic projection of the portion of the first reflective sublayer located in the device region on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, and the first reflective sublayer also covers the portion of the substrate located in the peripheral region; The orthographic projection of the second reflective sublayer onto the substrate lies within the orthographic projection of the first reflective sublayer onto the substrate.

3. The array substrate according to claim 2, characterized in that, The orthographic projection of the second reflective sublayer onto the substrate is located in the device region; The orthographic projection of the second reflective sublayer on the substrate does not overlap with the orthographic projection of the portion of the first reflective sublayer located in the peripheral region on the substrate.

4. The array substrate according to claim 2, characterized in that, The orthographic projection of the second reflective sublayer onto the substrate lies between the peripheral region and the device region; The orthographic projection of the portion of the second reflective sublayer located in the peripheral region onto the substrate overlaps with the orthographic projection of the portion of the first reflective sublayer located in the peripheral region onto the substrate.

5. The array substrate according to claim 2, characterized in that, The first reflective sublayer and the second reflective sublayer have the same thickness along the direction perpendicular to the substrate.

6. The array substrate according to claim 1, characterized in that, The device region of the array substrate further includes a buffer layer and a first conductive layer disposed sequentially on the substrate, wherein the interlayer dielectric layer is located on the side of the first conductive layer away from the substrate; The interlayer dielectric layer includes a first insulating layer and a first planarization layer, wherein the first planarization layer is located at least between the first insulating layer and the reflective layer.

7. The array substrate according to claim 6, characterized in that, The device region of the array substrate further includes a second conductive layer, a second insulating layer, a second planarization layer and a third insulating layer stacked sequentially on the buffer layer, wherein the third insulating layer is located on the side of the first conductive layer away from the first insulating layer.

8. The array substrate according to claim 6, characterized in that, The first conductive layer includes at least one first pad and at least one second pad, and the interlayer dielectric layer has a plurality of first openings and a plurality of second openings along a direction perpendicular to the substrate, wherein the first openings expose the area where the first pad is located, and the second openings expose the area where the second pad is located. The first pad is electrically connected to the first solder pin of the device through the first opening, and the second pad is electrically connected to the second solder pin of the device through the second opening.

9. The array substrate according to claim 8, characterized in that, The array substrate also includes a plurality of support pillars, which are located on the side of the reflective layer away from the substrate, and the orthographic projection of the support pillars on the substrate does not overlap with the orthographic projection of the device on the substrate.

10. A light-emitting device, characterized in that, Includes the array substrate as described in any one of claims 1-9.

11. The light-emitting device according to claim 10, characterized in that, The light-emitting device also includes a diffuser plate, a quantum dot film, a diffuser sheet, and a composite film stacked in sequence; The diffuser plate is located on the light-emitting side of the array substrate.

12. A splicing display device, characterized in that, It includes at least two light-emitting devices as described in claim 10 or 11.

13. A method for fabricating an array substrate, characterized in that, The method is applied to the fabrication of an array substrate as described in any one of claims 1-9, the method comprising: A mother substrate is provided; the mother substrate is divided into at least one device region and a dicing region adjacent to the device region; An interlayer dielectric layer is formed on the device region of the motherboard substrate; A reflective layer is formed on the device region and the cut region of the mother substrate; wherein the reflective layer has a plurality of cutout regions along a direction perpendicular to the mother substrate; the interlayer dielectric layer is located at least between the mother substrate and the reflective layer; the orthographic projection of the portion of the reflective layer located in the device region on the mother substrate overlaps with the orthographic projection portion of the interlayer dielectric layer on the mother substrate, and the portion of the reflective layer located in the cut region covers the cut region of the mother substrate; Multiple devices are bonded to the device area of ​​the mother substrate; the devices are located within the cutout area; At least one array substrate is obtained by cutting along a cutting line from the back side of the mother substrate; the cutting line is located in the cutting area, and the back side is the surface of the mother substrate away from the device; After the step of bonding multiple devices to the device region on the mother substrate, and before the step of cutting along a dicing line from the back side of the mother substrate to obtain at least one of the array substrates, the method further includes: An auxiliary reflective portion is formed on the interlayer dielectric layer; wherein the auxiliary reflective portion is connected to the reflective layer; The cutout area exposes a portion of the interlayer dielectric layer, the orthographic projection of the first reflective part on the substrate is located in the cutout area, and the first reflective part is in direct contact with the interlayer dielectric layer; The second reflective portion is in direct contact with the surface of the reflective layer away from the substrate, and the orthographic projection of the second reflective portion on the substrate overlaps with the orthographic projection of the reflective layer on the substrate; The array substrate further includes a plurality of packaging units corresponding to the device. The orthographic projection of the packaging unit on the substrate covers the orthographic projection of the device on the substrate, and the orthographic projection of the packaging unit on the substrate partially overlaps with the orthographic projection of the reflective layer on the substrate.

14. The method for fabricating an array substrate according to claim 13, characterized in that, After the step of cutting along the dicing line from the back side of the mother substrate to obtain at least one of the array substrates, the method further includes: The edges of the array substrate are ground using a vertical grinding process.

15. The method for fabricating an array substrate according to claim 14, characterized in that, The step of grinding the edge of the array substrate using a vertical grinding process includes: The side surfaces of the substrate and the reflective layer of the array substrate are simultaneously ground along a direction perpendicular to the array substrate; wherein the side surfaces of the substrate and the reflective layer are coplanar.

16. The method for fabricating an array substrate according to claim 13, characterized in that, The step of forming a reflective layer on the device region and the dicing region of the mother substrate includes: A first reflective sublayer is formed; the orthographic projection of the first reflective sublayer onto the mother substrate is located within the device region and the dicing region. A second reflective sublayer is formed; the orthogonal projection of the second reflective sublayer onto the mother substrate is located within the device region. Alternatively, a first reflective sublayer may be formed; the orthographic projection of the first reflective sublayer onto the mother substrate may lie within the device region and the dicing region. A second reflective sublayer is formed; the orthogonal projection of the second reflective sublayer on the mother substrate is located within the device region and the cutting region.

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