Protection of transformations by intermediate randomization in cryptographic operations

Abstract

Aspects of the present disclosure relate to a method and system of performing a cryptographic operation involving a number theoretic transform of a first vector to a second vector, the steps of which include: performing a plurality of iterations by obtaining components of the first vector, wherein each iteration includes determining a plurality of output values, wherein each of the plurality of output values is a linear combination of two or more input values, the input values in the first iteration being the components of the first vector, the output values of the last iteration representing components of the second vector, and wherein one or more of the output values of at least one iteration are randomized by multiplying at least one input value by a random number, and determining the components of the second vector based on the output values of the last iteration of the plurality of iterations.

Description

Technical Field

[0001] This disclosure relates to cryptographic computation applications, and more specifically, to the protection of cryptographic operations (such as computations involving transformations containing secret information) from side-channel attacks. Attached Figure Description

[0002] This disclosure will be more fully understood through the detailed description given below and the accompanying drawings of various implementations of this disclosure.

[0003] Figure 1 This is a block diagram illustrating an example system architecture capable of protecting transformations performed therein as part of an cryptographic operation using intermediate randomization, according to one or more aspects of this disclosure.

[0004] Figure 2 This is an exemplary illustration of a number-theoretic transformation (or digital Fourier transform) process that uses intermediate randomization to protect secure information from side-channel attacks, according to one or more aspects of this disclosure.

[0005] Figure 3 This is another exemplary illustration of a number-theoretic transformation (or digital Fourier transform) process that uses intermediate randomization to protect secure information from side-channel attacks, according to one or more aspects of this disclosure.

[0006] Figure 4 A flowchart depicts an illustrative example of a method for protecting secure information from side-channel attacks during number-theoretic transformation (or digital Fourier transform) computation by intermediate randomization according to one or more aspects of this disclosure.

[0007] Figure 5 A block diagram depicts an example computer system operating according to one or more aspects of this disclosure. Detailed Implementation

[0008] Various aspects of this disclosure relate to protecting cryptographic operations employing linear transformations from side-channel attacks by using randomization of data and / or data streams.

[0009] In public-key cryptosystems, processing devices can have various components / modules for performing cryptographic operations on input messages. The input messages used in such operations are typically large positive integers. Examples of cryptographic operations include, but are not limited to, operations involving Rivest Shamir Adelman (RSA) and elliptic curve Diffie-Hellman (ECDH) keys, digital signature algorithms (DSA), and elliptic curve digital signature algorithms (ECDSA) used to authenticate messages transmitted between nodes in a public-key cryptosystem. Cryptographic algorithms typically involve modular arithmetic operations of modulus p, where the set of all integers Z is enclosed in a circle of length p (the set Z). pAround p, any two numbers differing by p (or any other integer multiple of p) are considered the same number. Pre-quantum cryptography applications often take advantage of the fact that extracting the private key multiplier from the public key product (mod p) involving the private key multiplier is an operation that would be extremely difficult on a classical computer. The development of quantum computers has put some conventional algorithms (RSA, DSA, ECDH, EDCDSA) at risk and has spurred the development of many post-quantum cryptography algorithms, such as hash-based algorithms, code-based algorithms, multivariate algorithms, lattice-based algorithms, key-based algorithms, symmetric-key algorithms, and others. Some post-quantum algorithms are based on the shortest vector problem, i.e., the difficulty of determining the shortest (non-zero) vector in a vector space given a known set of conditions. For example, the Kyber and NewHope key encapsulation algorithms are based on the difficulty of solving the error-laden learning problem on a modular lattice.

[0010] Cryptographic applications employ various schemes and algorithms to protect data using keys. Using keys and other secret information in computational operations can expose this secret information to side-channel attacks. Side-channel attacks can be performed by monitoring the emissions (signals) generated by the electronic circuitry of a target's (the victim's) computer. These signals can be acoustic, electrical, magnetic, optical, thermal, etc. By recording these emissions, hardware Trojans and / or malware may be able to correlate specific processor (and / or memory) activity with the operations performed by the processor. Simple power analysis (SPA) side-channel attacks may involve examining the power consumed by the device as a function of time. More sophisticated differential power analysis (DPA) attacks may involve statistically analyzing power measurements performed on multiple cryptographic operations (or multiple iterations of a single cryptographic operation) because the presence of noise masks the processor's signals. Attackers employing DPA may be able to filter out the noise components of the power signal (taking advantage of the fact that noise components may be uncorrelated between different operations or iterations) to extract the signal components representing the actual processor operation and infer the value of the private key from that signal.

[0011] As part of an initiative by the National Institute of Standards and Technology (NIST), several post-quantum cryptographic schemes have been developed for key encapsulation algorithms (e.g., Kyber, NewHope) and digital signatures (e.g., Dilithium). This cryptographic application utilizes efficient multiplication in a polynomial ring and employs number-theoretic transforms (NTTs). NTT is a simulation of the discrete Fourier transform (DFT) applied to an N-component input vector x(m), m = 0, 1, 2, ..., N-1, using the Nth unit root. The number W N The polynomial transforms the input vector into an output vector X(k), k = 0, 1, 2, ... N-1:

[0012]

[0013] In the case of DFT, the digital W N It can be a complex number on a complex ring with a radius of 1, for example, W N =exp(-2πi / N). In the case of NTT, the number W N It can be ring Z p The modulo p operation of natural numbers in the range whose Nth power is 1: For example, if the transformation is applied to an 8-component vector (N=8) and p=17 is chosen, then the Nth root of unity can be chosen as W. N =2, thus making In fact, the Z-ring 17 On It equals unit (256 - 17 × 15 = 1).

[0014] In secure cryptographic applications, the number of components N is typically large. Directly calculating NTT according to the above definition results in N... 2 Multiplication (4N in the case of DFT) 2 (Real number multiplication). The Fast Fourier Transform (FFT) technique reduces the number of operations required for N log N and is based on certain symmetries of the roots of the unit, such as... And so on. The FFT technique is also applicable to NTT, referred to in this paper as Fast NTT. Fast NTT (similar to FFT) is equivalent to first calculating the N / 2 2-point transform (first iteration), then calculating the N / 4 4-point transform (second iteration), and so on, until the final N-point transform is obtained in the last iteration (log₂ N iterations), as shown in the reference below. Figure 2 and Figure 3 In more detail, Cooley-Tukey butterfly operations can be used to perform fast NTT and FFT, where the two input values ​​to a specific iteration A and B can be transformed into output values ​​according to the following formula: A,B→A+B·W N AB·W N In an alternative implementation using Gentleman-Sande butterfly operations, the input values ​​can be determined according to A, B → A + B, (AB)·W. N Transform into output values. In some implementations, to enhance cryptographic protection, at least some fast NTT iterations may involve double (2N) order W. 2N The unit root.

[0015] The secret information contained in the input vector x(m) and output vector X(k) may be vulnerable to side-channel attacks, where an attacker can use a single tracking emission operation by measuring the emission (emission) from the processor (and / or memory device) performing the transformation. Various countermeasures can be developed to randomize computational operations and reduce deterministic emission from the processor / memory device. For example, the linearity of NTT can be used to mask the transformation (throughout this disclosure, whenever NTT is referenced, it should be understood that similar techniques apply to the DFT). The masking process can mask the input x(m) using a random vector y(m). For example, a first transformation can be applied to the sum of the input vectors x(m) + y(m), and a second transformation can be applied to the random input vector y(m). Subsequently, the output vector of the second transformation Y(k) can be subtracted from the output vector of the first transformation X(k) + Y(k) to determine the target transformation X(k). Since the correlation between the inputs to the first and second transformations can still be tracked by a side-channel attacker, this masking provides additional, but still suboptimal, protection. For each iteration of the fast NTT algorithm, a similar remasking could be performed separately (e.g., using different random vectors y generated for various iterations), but this could result in significant costs in terms of memory and processor computation. Other safeguards could include performing NTT computations in a randomized order, but such randomization can be difficult to implement.

[0016] This disclosure addresses this and other drawbacks of conventional NTT implementations by describing intermediate randomization performed during various iterations of a fast NTT process. Successive fast NTT iterations may include performing one or more multiplication operations involving multiplying the output value of a previous iteration by the unit root A·W. N In one implementation, such operations can be protected by additional multiplication using a random number α: W N →A·W N • α. In another implementation, it can be achieved by using another randomly selected order of the same order. The unit root or a randomly selected bi(2N) order The unit root is replaced to protect this operation. This randomization can be performed in some or all of the fast NTT iterations. At the end (or beginning) of the fast NTT, the output value of the last iteration (or the input value of the first iteration) can be adjusted to compensate for the randomization introduced during the fast NTT iterations. As a result, the correct (target) output vector can still be computed while reducing deterministic emissions from the system hardware and shielding computation from potential side-channel attacks. Introducing randomization increases computational entropy and makes it more difficult for an attacker to gather a set of statistics sufficient to discover secret information. The disclosed implementation can be used with NTT as well as with DFT (real or complex).

[0017] Figure 1 This is a block diagram illustrating an example system architecture 100 capable of protecting transformations performed therein as part of an cryptographic operation using intermediate randomization, according to one or more aspects of this disclosure. Example system architecture 100 may be a desktop computer, tablet computer, smartphone, server (local or remote), thin / thin client, etc. Example system architecture 100 may be a smart card reader, wireless sensor node, embedded system dedicated to one or more specific applications (e.g., cryptographic application 110), etc. System architecture 100 may include, but is not limited to, a computer system 102 having one or more processors 120 (e.g., central processing unit (CPU)) and one or more memory devices 130 capable of executing binary instructions. A “processor” refers to a device capable of executing instructions encoded as arithmetic, logic, or I / O operations. In an illustrative example, the processor may follow the von Neumann architecture model and may include an arithmetic logic unit (ALU), a control unit, and multiple registers. A “processing device” refers to a device capable of executing instructions encoded as arithmetic, logic, or I / O operations. In one illustrative example, the processing device may follow the von Neumann architecture model and may include an arithmetic logic unit (ALU), a control unit, and multiple registers. Alternatively, the processing device may be a single-core processor typically capable of executing one instruction at a time (or processing a single instruction pipeline), or a multi-core processor capable of executing multiple instructions simultaneously. Furthermore, the processing device may be implemented as a single integrated circuit, two or more integrated circuits, or may be a component of a multi-chip module.

[0018] System architecture 100 may include an input / output (I / O) interface 104 to connect computer system 102 to peripheral hardware devices 106, such as card readers, terminals, printers, scanners, and IoT devices. System architecture 100 may also include an internet interface 108 to facilitate connectivity to various networks (internet, wireless LAN, personal area network (PAN), public network, private network, etc.) and may include a radio front-end module and other devices (amplifiers, digital-to-analog and analog-to-digital converters, dedicated logic units, etc.) to enable data transmission to / from computer system 102. Various hardware components of computer system 102 may be connected via a bus 112, which may have its own logic circuitry, such as a bus interface logic unit.

[0019] Computer system 102 may support one or more cryptographic applications 110, such as embedded cryptographic application 110-1 and / or external cryptographic application 110-2. Cryptographic application 110 may be a security authentication application, public key signing application, key encapsulation application, key decapsulation application, encryption application, decryption application, secure storage application, etc. External cryptographic application 110-2 may be instantiated on the same computer system 102, for example, by an operating system executed by processor 120 and residing in memory device 130. Alternatively, external cryptographic application 110-2 may be instantiated by a guest operating system supported by a virtual machine monitor (hypervisor) executed by processor 120. In some implementations, external cryptographic application 110-2 may reside on a remote access client device or a remote server (not shown), for which computer system 102 provides cryptographic support.

[0020] Processor 120 may include one or more processor cores 122 with access to cache 124 (single-level or multi-level cache) and one or more hardware registers 126. In various implementations, each processor core 122 may execute instructions to run multiple hardware threads, also referred to as a logical processor. Various logical processors (or processor cores) may be assigned to one or more cryptographic applications 110, although more than one processor may be assigned to a single cryptographic application for parallel processing. A multi-core processor 120 can execute multiple instructions simultaneously. A single-core processor 120 typically executes one instruction at a time (or processes a single instruction pipeline). Processor 120 may be implemented as a single integrated circuit, two or more integrated circuits, or may be a component of a multi-chip module.

[0021] Memory device 130 may refer to volatile or non-volatile memory and may include read-only memory (ROM) 132, random access memory (RAM) 134, and (not shown) electrically erasable programmable read-only memory (EEPROM), flash memory, trigger memory, or any other device capable of storing data. RAM 134 may be dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static memory (such as static random access memory), etc.

[0022] Memory device 130 may include one or more registers, such as one or more input registers 136 storing the input vector x(m), one or more output registers 138 storing the output vector X(k), and one or more working registers 140 storing intermediate values ​​generated during various fast NTT iterations. Memory device 130 may also include one or more control registers 142 for storing information about the operating node, selecting a key encapsulation / digital signature algorithm (e.g., Kyber, NewHope, Dilithium), initializing the NTT program, and selecting the implementation of the initialized NTT program (e.g., Cooley-Tukey butterfly or Gentleman-Sander butterfly). Control register 142 may communicate with one or more processor cores 122 and a clock 128 that can track the ongoing iterations. Registers 136-142 may be implemented as part of RAM 134. In some implementations, some or all of registers 136-142 may be implemented separately from RAM 134. Some or all of registers 136-142 may be implemented as part of processor 120 (e.g., as part of hardware register 126). In some implementations, processor 120 and memory device 130 may be implemented as a single field-programmable gate array (FPGA).

[0023] According to an implementation of this disclosure, computer system 102 may include a randomization module 150 to provide instructions to processor 120 to perform DPA-resistant cryptographic operations. The randomization module 150 may be implemented in software, hardware (e.g., as part of processor 120), firmware, or any combination thereof. The randomization module 150 may include an output adjustment module 152 to compensate for randomization operations and ensure the correct target vector is determined. In some implementations, the randomization module 150 may access the contents of registers 136-142 to retrieve and store data during fast NTT iterations.

[0024] Figure 2This is an exemplary illustration of an NTT (or DFT) process 200 that uses intermediate randomization to protect secure information from side-channel attacks according to one or more aspects of this disclosure. An exemplary implementation (decimation-time FFT) based on grouping the even components of input vectors 202x(0), x(2), ... x(N-2) and the odd components of input vectors 202x(1), x(3), ... x(N-1) into separate N / 2-point NTTs and continuing similar grouping until N / 2 of a 2-point NTT (radix-2 implementation) is reached is shown. Thus, the NTT is implemented as a log2N-stage process with increasing range until the output vector 204X(k) is obtained. An exemplary implementation for N=8 is shown, but if W8 is used with a general W... N The substitution method can perform a similar operation on any N that is a power of 2.

[0025] In the depicted N=8 implementation, the 2-point transform iteration 210 involves four CT butterfly operations to compute two intermediate values ​​from each pair of input values ​​grouped as x(m), x(m+N / 2). Lines indicate which input values ​​are used when computing the corresponding intermediate values, and numbers and letters indicate the weights (rotation factors) associated with each line. For example, the first CT butterfly operation computes...

[0026]

[0027] Perform similar operations for other iterations. For example, the intermediate values ​​of F1(1) and F1(3) for the 4-point transformation iteration 220 can be calculated according to the following formula:

[0028]

[0029] Furthermore, the output values ​​of X(3) and X(7) of the 8-point transformation (final) iteration 230 can be calculated according to the following formulas:

[0030]

[0031] To protect the NTT process 200 from side-channel attacks, some or all intermediate stages (iterations) may include a randomization operation 206. In some implementations, the randomization operation may include multiplying a unit root by a random number. In some implementations, the same random number may be used to randomize all operations of the same iteration, but the random numbers for different iterations may be different from each other. For example, all 2-point transform iterations 210 It can be multiplied by the first random number α1, and all 4-point transformations iterate 220 times. and It can be multiplied by the second random number α2, and all 8-point transformations iterate 230 times. and It can be multiplied by a third random number α3. Therefore, the exemplary operations using randomization listed above can be performed as follows:

[0032]

[0033]

[0034]

[0035] random number α j The existence of this modifies the output value X(m) and makes it different from the correct (target) output value (the output value that would be obtained if the randomization operation were not performed). For example, the output component X(5) of NTT procedure 200 could be:

[0036]

[0037] To compensate for the randomization factor in the final expression, the input vector 202 components x(m) can be adjusted according to the following schedule (e.g., before the first iteration 210). For the first input pair x(0), x(4) can be adjusted as x(0) → x(0), x(4) → x(4) ÷ α1. For the second input pair x(2), x(6) can be adjusted by dividing by α2, etc., as shown below (the divisor is shown):

[0038]

[0039] The adjustment for odd pairs differs from that for even pairs by an additional divisor of the random value of the last iteration (e.g., α3 in the case of N=8).

[0040] In another implementation, this can be achieved by using the same order. Randomization is performed by replacing the Nth unit root with another unit root. For example, replacing the root... This will result in the following remapping of the root:

[0041]

[0042] And fixed by symmetry and This remains unchanged. Any such random remapping that maps each root to another root can be used. Specifically, there may be N / 2 acceptable remapping schemes (remapping schemes) This is unacceptable because it maps even and odd order roots to even order roots. One of the remapping schemes can be chosen for the entire NTT process and maintained for all iterations of the process. After the NTT process is complete, the correct components of the output vector 204 can be retrieved using the reverse remapping. In the example above, the final readout can be performed as follows:

[0043]

[0044] X(0) and X(4) are read directly from their respective outputs. In some implementations, for additional protection, two randomization methods can be combined: a global remapping scheme can be randomly selected for the entire NTT process, and an additional log2N random number α can be selected for the multiplication randomization within each log2N iteration. j In some implementations, the selected root of unity can be of order 2N. Randomly select from the units of unity, such that

[0045] Figure 3 This is another exemplary illustration of an NTT (or DFT) process 300 that uses intermediate randomization to protect security information from side-channel attacks according to one or more aspects of this disclosure. A Gentleman-Sande butterfly implementation (frequency decimation FFT) is shown, based on grouping the first half-components of the input vectors 202x(0), x(1), ... x(N / 2-1) and the second half-components of the input vectors 202x(N / 2-1), x(N / 2-2), ... x(N-1) into separate N / 2-point NTTs and continuing this grouping until N / 2 of a 2-point NTT (radix-2 implementation) is reached. Thus, the NTT is implemented as a log2N-stage process with an increasing range until the output vector 304X(k) is obtained. An exemplary implementation of N=8 is shown, but a more general W is used in W8. N In the case of substitution, a similar operation can be performed on any N that is an integer power of 2.

[0046] In the depicted N=8 implementation, the 2-point transform iteration 310 (executed last) involves four GS butterfly operations to compute the components of the output vector 304X(k), which are grouped into X(m) and X(m+N / 2) according to a corresponding pair of intermediate values ​​(G and H). Lines indicate which input values ​​are used when computing the corresponding intermediate values, and numbers and letters indicate the weights (rotation factors) associated with each line. For example, the third GS butterfly operation of the 2-point transform iteration 310 includes computing...

[0047]

[0048] Perform similar operations for other iterations. For example, the intermediate values ​​of G1(1) and G2(1) for the 4-point transformation iteration 320 can be calculated according to the following formula:

[0049]

[0050] Furthermore, the intermediate values ​​of F1(3) and F2(3) of the 8-point transformation iteration 330 (executed first) can be calculated from the components x(3) and x(7) of the input vector 302 according to the following formula:

[0051]

[0052] To protect the NTT process 200 from side-channel attacks, some or all intermediate stages may include a randomization operation 306. In some implementations, the randomization operation may include multiplying a unit root by a random number. In some implementations, the same random number may be used to randomize all operations of the same iteration, but the random numbers for different iterations may be different from each other. For example, all 2-point transform iterations 310 It can be multiplied by the first random number α1, and all 4-point transformations iterate 320 times. and It can be multiplied by the second random number α2, and all 8-point transformations iterate 310 times. and It can be multiplied by a third random number α3. Therefore, the exemplary operations using randomization listed above can be performed as follows:

[0053]

[0054]

[0055]

[0056] random number α j The existence of this modifies the output value X(m) and makes it different from the (target) correct output value (as determined without randomization). For example, the output component X(6) of NTT process 300 could be:

[0057]

[0058] To compensate for the randomization factor in the final expression, the output vector 304 components X(k) can be adjusted according to the following schedule (e.g., after the 2-point transformation iteration 310). The first outputs for X(0) and X(4) can be adjusted as X(0) → X(0), X(4) → X(4) ÷ α1. The second outputs for X(2) and X(6) can be adjusted by dividing by α2, etc., as shown below (the divisor is shown):

[0059]

[0060] The adjustment for odd pairs differs from that for even pairs by an additional divisor of the random value of the 2-point transformation iteration (e.g., α3 in the case of N=8).

[0061] In another implementation, this can be achieved by using the same order. Another unit root replaces the Nth unit root and then with respect to... Figure 2 Randomization is performed by remapping the output in the same manner as described in the CT butterfly iteration. In some implementations, for additional protection, two randomization methods can be combined (e.g., randomization of the GS butterfly operation and root remapping): a global remapping scheme can be randomly selected for the NTT process, and a log2N random number α can be additionally selected for the multiplication randomization within each log2N iteration. j .

[0062] Figure 2 and Figure 3 A radix-2 implementation is described, where the output value of each iteration is determined as a linear combination of the two input values. In some implementations, radix-4 (radix-6, radix-8, etc.) can be similarly randomized. For example, in a radix-4 implementation, the output value of each iteration is determined as a linear combination of the four input values. Similarly, more general radix-R transformations can be randomized. In some implementations, different radix values ​​can be used in different iterations. For example, the first iteration could be a radix-4 iteration, while subsequent iterations could be radix-2 iterations.

[0063] Figure 4 A flowchart depicts an illustrative example of a method 400 for protecting security information from side-channel attacks during NTT (or FFT) computation via intermediate randomization according to one or more aspects of this disclosure. Each of method 400 and / or its various functions, routines, subroutines, or operations can be executed by one or more processing units of a computer system implementing the method. In some implementations, method 400 can be executed by a single processing thread. Alternatively, method 400 can be executed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In one illustrative example, the processing threads implementing method 400 can be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Optionally, the processing threads implementing method 400 can execute asynchronously with each other. Figure 4 Compared to the order shown, the boxes of method 400 can be executed in a different order. Some boxes can be executed simultaneously with other boxes. Some boxes can be optional.

[0064] Method 400 can be generated by the processor / ALU (e.g., Figure 1The processor 120 performs cryptographic operations to implement this, which may involve public and private key numbers, two private key numbers, digital signatures, etc. The cryptographic operations may be part of a larger computational operation involving multiple private key numbers and / or multiple public key numbers. The cryptographic operations may involve post-quantum key encapsulation algorithms (e.g., Kyber, NewHope) and / or post-quantum digital signatures (e.g., Dilithium). The cryptographic operations may include transforming a first vector (e.g., input vector 202 or 302) into a second vector. The transformation from the first vector to the second vector may represent the components in the second vector as a polynomial of numbers with units (taking the modulus of a number in the case of NTT, or the modulus of the complex plane in the case of DFT). The coefficients of the polynomial may be determined by the components of the first vector. In some implementations, the transformation is an NTT transformation from a first vector with N components x(m) to a second vector with N components X(k). In some implementations, the transformation is a DFT transformation. The transformation may be a direct transformation (NTT or DFT) or an inverse transformation (NTT or DFT).

[0065] At box 410, the processing device executing method 400 (e.g., Figure 1 The processor 120 can obtain the components of the first vector. For example, the processing device can obtain an identifier (e.g., an address) of the input register 136 storing the components of the first vector. At block 420, method 400 can continue to obtain one or more random numbers. In some implementations, the one or more random numbers can be generated by a random number generator of randomization module 152. In some implementations, the random numbers can be stored in input register 136 or working register 140 before obtaining the first vector. In some implementations, random numbers are generated one by one as needed, for example, before performing the corresponding iteration of an NTT (or DFT) that will use the random numbers.

[0066] At box 430, method 400 can continue to perform multiple iterations to process the components of the first vector. As part of box 440, the first iteration can use the components of the first vector as input values ​​and produce output values ​​that are linear combinations of the input values, for example, where each output value is a combination of two input values ​​(radix-2 calculation), a combination of four input values ​​(radix-4 calculation), or some other combination of any other number of input values. The second iteration can use the output value of the first iteration as input values ​​and can perform similar calculations. Such iterative processes can continue until all iterations are performed using the output values ​​of previous iterations as input values ​​for subsequent iterations. The output value of the last iteration can represent the components of the second vector. In some implementations, the output value of the last iteration may still be different from the components of the second vector and may undergo additional adjustments to make it equal to the components of the second vector.

[0067] In some implementations, all iterations can be iterations with the same radix; for example, all iterations can be radix-2 (or radix-4, etc.) iterations. In such implementations, the number of iterations can be log₂N (or log₄N, etc.). In some implementations, some iterations can be radix-m iterations, while others can be radix-n iterations, where m ≠ n. In some implementations, each iteration of multiple iterations can include a Cooley-Tukey butterfly transformation (see...). Figure 2 (See also Gentleman-Sande butterfly transformation) Figure 3 In some implementations, each iteration of multiple iterations may include addition and multiplication operations modulo prime numbers (e.g., in instances of NTT). In some implementations, each iteration of multiple iterations may include operations involving complex numbers (e.g., in instances of DFT).

[0068] As part of box 450, the processing device performing method 400 may perform a first randomization operation in conjunction with one of the iterations (“first randomization iteration”). The randomization operation may be performed by the randomization module 150 of computer system 102. In some implementations, the first randomization iteration may be the same as the first iteration. In some implementations, the first randomization iteration may be the r-th iteration (the first r-1 iterations are not randomized). The first randomization operation may include multiplying at least one input value in the first randomization iteration by one or more random numbers (α1, α2...α...). N The first random number (α1) in the process. For example, in the CT butterfly iteration example, the two input values ​​input to the first randomization operation A and B can be transformed into the output value of the first randomization operation according to the following formula: A, B → A + B · α1 · W N Similarly, in the example of the GS butterfly iteration, the two input values ​​to the first randomization operations A and B can be transformed into the output values ​​of the first randomization operations according to the following formula: A, B → A+B, (AB)·α1·W N In both the CT butterfly implementation and the GS butterfly implementation, the first randomization operation includes multiplying at least one input value (A or B, or both A and B) by a first unit root W. N .

[0069] In some implementations, the first random number used in the first randomization iteration is a randomly selected root of unity (e.g., a root of unity of order N or 2N). For example, in the CT butterfly iteration instance, the two input values ​​input to the first randomization operations A and B can be transformed according to the following formula: In the example of the GS butterfly iteration, the input values ​​can be transformed according to the following formula: A, B → A + B. random unit root You can choose from multiple roots of unity, which can be a subset of all roots of unity of order N (e.g., odd-numbered roots of unity W). N , ... (a subset of ...) or a subset of the 2Nth order unit root.

[0070] As part of box 460, the processing device performing method 400 can perform a second randomization operation in conjunction with one of the iterations (“second randomization iteration”). This is done by multiplying at least one input value of the second randomization iteration by one or more random numbers (α1, α2...α...). N The second random number (α2) in the equation is multiplied by the second root of unity (e.g., ...), the second root of unit can be different from the first root of unit used in the first randomized iteration (but it can also be the same as the first root of unit, for example, W). N In some implementations, the second randomization iteration can immediately follow the first randomization iteration. However, in some implementations, the second randomization iteration can be the last iteration (such that there are s non-randomization iterations between the first and second randomization iterations). In some implementations, multiple random numbers (α3, α4...α) are used. N The corresponding random number in the formula is used to randomize all subsequent iterations (e.g., the third, fourth, etc.). In some implementations, only some iterations are randomized. In some implementations, only the first iteration is randomized. For example, a random unit root is selected during (or before) the first randomized iteration. Used for the first randomization iteration, and then the same (once chosen) unit root is used in all subsequent iterations (without undergoing any additional randomization). In some implementations, a random unit root is selected during (or before) the first randomization iteration. And one or more random numbers (α1, α2...α) N It is still used in some (or all) iterations (including those that have been passed). The first randomization iteration of randomization is randomly selected to increase data security and protection.

[0071] At block 460, the processing device executing method 400 can determine the components of the second vector based on the output value of the last iteration. Due to the randomization performed at blocks 450 and 460, the output value of the last iteration may differ from the (target) components of the second vector. Therefore, the processing device can perform multiple adjustment operations to compensate for the first (second, third, etc.) randomization operation. The adjustment operations can be performed by the output adjustment module 152 of the randomization module 150 of the computer system 102. For example, the adjustment operation may involve a division operation (in modulo p operations, this can be performed via multiplication using a properly determined multiplier, such as Montgomery multiplication). The division operation may depend on the specific output value being adjusted and may involve (in the case of GS implementation) dividing the output value of the last iteration by one or more random numbers (α1, α2...α). N ), such as regarding Figure 3 In more detail, this division transforms the output value of the last iteration into the actual components of the second vector.

[0072] In some implementations, a random unit root is selected. In some implementations, multiple adjustment operations may include remapping (recombining) the output of the last iteration to obtain the correct sequence of the components of the second vector. In some implementations, two sets of adjustment operations may be performed. For example, if a random unit root is chosen before the first randomization iteration. Then use random numbers α1, α2...α N Randomized multiplication allows the adjustment operations to be performed in reverse order. First, division is performed by one or more random numbers α1, α2...α N The adjusted division is then remapped (recombined) to obtain the output value, thus obtaining the components of the second vector.

[0073] In some implementations (e.g., in the case of CT iterations), the adjustment operation can adjust the values ​​of the corresponding components of the first (i.e., input) vector, rather than the output values ​​of the last iteration. For example, the adjustment operation could involve dividing the components of the input vector by one or more random numbers (α1, α2...α...). N ), such as regarding Figure 2 More detailed description. In this case, an adjustment operation is performed before the first iteration, and the output value of the last iteration is the actual component of the second vector. In some implementations, a random unit root is chosen. In an example, multiple adjustment operations may include remapping (recombining) the output of the last iteration to obtain the correct sequence of the components of the second vector. In such an implementation, the components of the first vector are divided by one or more random numbers α1, α2...α before the first iteration. NAfter the last iteration, the output values ​​are remapped (recombined) to obtain the components of the second vector.

[0074] Figure 5 A block diagram depicts an example computer system 500 operating according to one or more aspects of this disclosure. In various illustrative examples, the computer system 500 may represent... Figure 1 The computer system 102 shown.

[0075] Example computer system 500 can be connected to other computer systems in a LAN, intranet, extranet, and / or the Internet. Computer system 500 can operate with server capabilities in a client-server network environment. Computer system 500 can be a personal computer (PC), set-top box (STB), server, network router, switch, or bridge, or any device capable of executing a set of instructions (sequential or otherwise) specifying the actions to be taken by that device. Furthermore, although only a single example computer system is illustrated, the term "computer" should also be considered as encompassing any collection of computers that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0076] Example computer system 500 may include processing device 502 (also called processor or CPU), main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), etc.), static memory 506 (e.g., flash memory, static random access memory (SDRAM), etc.), and secondary memory, which can communicate with each other via bus 530.

[0077] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 502 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. According to one or more aspects of this disclosure, processing device 502 may be configured to execute instructions implementing method 400 for protecting security information from side-channel attacks during NTT (or FFT) computation through intermediate randomization.

[0078] Example computer system 500 may also include a network interface device 508 that can be communicatively coupled to network 520. Example computer system 500 may also include a video display 510 (e.g., a liquid crystal display (LCD), a touch screen, or a cathode ray tube (CRT)), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), and a sound signal generation device 516 (e.g., a speaker).

[0079] Data storage device 518 may include a computer-readable storage medium (or more specifically, a non-transitory computer-readable storage medium) 528 thereon storing one or more sets of executable instructions 522. According to one or more aspects of this disclosure, the executable instructions 522 may include executable instructions for implementing a method 400 for protecting security information from side-channel attacks by intermediate randomization during NTT (or FFT) computation.

[0080] The executable instructions 522 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by the example computer system 500, which also constitute computer-readable storage media. The executable instructions 522 may further be transmitted or received over a network via network interface device 508.

[0081] Although computer-readable storage medium 528 is Figure 5 While referred to as a single medium, the term "computer-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of operational instructions. The term "computer-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution that causes the machine to perform any or more of the methods described herein. Therefore, the term "computer-readable storage medium" should be considered to include, but is not limited to, solid-state storage, optical, and magnetic media.

[0082] Some of the detailed descriptions above are presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms here are generally considered to be self-consistent sequences of steps that lead to desired results. These steps are steps that require the physical manipulation of physical quantities. Typically, though not always, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has proven convenient, primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0083] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specified, as is apparent from the following discussion, the discussion using terms such as “identify,” “determine,” “store,” “adjust,” “cause,” “return,” “compare,” “create,” “stop,” “load,” “copy,” “throw,” “replace,” and “execute” refers to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities within the registers and memory of the computer system and transform them into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage, transmission, or display devices.

[0084] Examples of this disclosure also relate to apparatus for performing the methods described herein. This apparatus may be specifically constructed for the desired purpose, or it may be a general-purpose computer system selectively programmed by a computer program stored in a computer system. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic disk storage media, optical storage media, flash memory devices, other types of machine-accessible storage media, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0085] The methods and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it may be convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will be described below. Furthermore, the scope of this disclosure is not limited to any particular programming language. It should be understood that the teachings of this disclosure can be implemented using various programming languages.

[0086] It should be understood that the above description is intended to be illustrative and not restrictive. Many other implementation examples will become apparent to those skilled in the art upon reading and understanding the above description. Although specific examples are described herein, it should be recognized that the systems and methods of this disclosure are not limited to the examples described herein but can be practiced with modifications within the scope of the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive. Consequently, the scope of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for performing a cryptographic operation including a number-theoretic transformation (NTT) from a first vector to a second vector, the method comprising: The components of the first vector are obtained by the processing device; One or more random numbers are obtained by the processing device; The processing device performs multiple iterations, wherein each iteration includes: Determine a plurality of output values, wherein each of the plurality of output values ​​is a linear combination of two or more input values; Wherein, (1) the input value to the first iteration in the multiple iterations is the component of the first vector, (2) the input value to each subsequent iteration in the multiple iterations is the output value of the previous iteration in the multiple iterations, (3) the output value of the last iteration in the multiple iterations represents the component of the second vector, and one or more output values ​​of the first randomized iteration in the multiple iterations are randomized using a first randomization operation, the first randomization operation comprising multiplying at least one input value to the first randomized iteration by a first random number among the one or more random numbers; and The processing device determines the components of the second vector based on the output value of the last iteration in the multiple iterations.

2. The method according to claim 1, further comprising: Perform multiple adjustment operations, wherein each of the multiple adjustment operations adjusts the corresponding output value of the last iteration in the multiple iterations to compensate for the first randomization operation, and makes the output value of the last iteration in the multiple iterations equal to the component of the second vector.

3. The method according to claim 1, further comprising: Perform multiple adjustment operations, wherein each of the multiple adjustment operations adjusts the value of a corresponding component of the first vector to compensate for the first randomization operation, and makes the output value of the last iteration of the multiple iterations equal to the component of the second vector.

4. The method of claim 1, wherein the number of iterations of the multiple iterations is equal to the logarithm of the number of components of the first vector divided by the base 2, and wherein the number of components of the first vector is equal to the number of components of the second vector.

5. The method of claim 1, wherein each iteration in the multiple iterations comprises multiple parallel instances of the Cooley-Tukey butterfly transform or multiple parallel instances of the Gentleman-Sande butterfly transform.

6. The method of claim 1, wherein the first randomization operation further comprises multiplying the at least one input value in the first randomization iteration by a first unit root.

7. The method of claim 6, wherein one or more output values ​​of the second randomized iteration in the plurality of iterations are randomized using a second randomization operation, the second randomization operation comprising multiplying at least one input value to the second randomized iteration by a second random number of the one or more random numbers and by a second number which is a second unit root.

8. The method of claim 1, wherein the first random number is a first unit root randomly selected from a plurality of N-order unit roots or from a plurality of 2N-order unit roots, wherein N is the number of the components of the first vector.

9. The method of claim 1, wherein each output value in each of the multiple iterations is determined based on two output values ​​from the previous iteration.

10. A non-transitory computer-readable medium storing instructions, wherein the instructions, when executed by a processing device performing a cryptographic operation including a number-theoretical transformation (NTT) from a first vector to a second vector, cause the processing device to: Obtain the components of the first vector; Get one or more random numbers; Performing multiple iterations, wherein in each of the multiple iterations, the processing device is used to: Determine a plurality of output values, wherein each of the plurality of output values ​​is a linear combination of two or more input values; in, (1) The input value to the first iteration in the multiple iterations is the component of the first vector, (2) The input value to each subsequent iteration in the multiple iterations is the output value of the previous iteration in the multiple iterations, (3) The output value of the last iteration in the multiple iterations represents the component of the second vector, and one or more output values ​​of the first randomized iteration in the multiple iterations are randomized using a first randomization operation, the first randomization operation comprising multiplying at least one input value to the first randomized iteration by a first random number among the one or more random numbers; as well as The components of the second vector are determined based on the output value of the last iteration in the multiple iterations.

11. The computer-readable medium of claim 10, wherein the instructions are further configured to cause the processing device to: Perform multiple adjustment operations, wherein each of the multiple adjustment operations adjusts the corresponding output value of the last iteration in the multiple iterations to compensate for the first randomization operation, and makes the output value of the last iteration in the multiple iterations equal to the component of the second vector.

12. The computer-readable medium of claim 10, wherein the instructions are further configured to cause the processing device to: Perform multiple adjustment operations, wherein each of the multiple adjustment operations adjusts the value of a corresponding component of the first vector to compensate for the first randomization operation, and makes the output value of the last iteration of the multiple iterations equal to the component of the second vector.

13. The computer-readable medium of claim 10, wherein the number of iterations of the multiple iterations is equal to the logarithm of the number of components of the first vector divided by the base 2, and wherein the number of components of the first vector is equal to the number of components of the second vector.

14. The computer-readable medium of claim 10, wherein each of the multiple iterations comprises multiple parallel instances of the Cooley-Tukey butterfly transform or multiple parallel instances of the Gentleman-Sande butterfly transform.

15. The computer-readable medium of claim 10, wherein the first randomization operation further comprises multiplying the at least one input value in the first randomization iteration by a first unit root.

16. The computer-readable medium of claim 15, wherein one or more output values ​​of the second randomized iteration in the plurality of iterations are randomized using a second randomization operation, the second randomization operation comprising multiplying at least one input value to the second randomized iteration by a second random number of the one or more random numbers and by a second number that is a second unit root.

17. The computer-readable medium of claim 10, wherein the first random number is a first unit root randomly selected from a plurality of N-order units or from a plurality of 2N-order units, wherein N is the number of the components of the first vector.

18. The computer-readable medium of claim 10, wherein each of the output values ​​in each of the plurality of iterations is determined based on two output values ​​from the previous iteration.

19. A system for performing a cryptographic operation including a number-theoretic transformation (NTT) from a first vector to a second vector, the system comprising: A memory device for storing the first vector and the second vector; as well as A processing device, coupled to the memory device, is used for: Obtain the components of the first vector; Get one or more random numbers; Performing multiple iterations, wherein in each of the multiple iterations, the processing device is to be used for: Determine a plurality of output values, wherein each of the plurality of output values ​​is a linear combination of two or more input values; Wherein, (1) the input value to the first iteration in the multiple iterations is the component of the first vector, (2) the input value to each subsequent iteration in the multiple iterations is the output value of the previous iteration in the multiple iterations, (3) the output value of the last iteration in the multiple iterations represents the component of the second vector, and one or more output values ​​of the first randomized iteration in the multiple iterations are randomized using a first randomization operation, the first randomization operation comprising multiplying at least one input value to the first randomized iteration by a first random number among the one or more random numbers; as well as The components of the second vector are determined based on the output value of the last iteration in the multiple iterations.

20. The system of claim 19, wherein the processing device is further configured to: Perform multiple adjustment operations, wherein each of the multiple adjustment operations adjusts the corresponding output value of the last iteration in the multiple iterations to compensate for the first randomization operation, and makes the output value of the last iteration in the multiple iterations equal to the component of the second vector.

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