Data drive integrated circuit, display device and pixel compensation method

Abstract

The present disclosure provides a data driving integrated circuit, comprising: a digital-to-analog converter, which is configured to receive a corresponding digital data signal from a timing controller and convert the corresponding digital data signal into a corresponding analog data signal, and the corresponding analog data signal is output to a display panel through a corresponding data line; an analog-to-digital converter, which is configured to receive a corresponding analog sensing signal from a corresponding sensing line in the display panel and convert the corresponding analog sensing signal into a corresponding digital sensing signal, and the corresponding digital sensing signal is output to the timing controller; a first sensing switch, which is configured to control the connection between a first reference voltage line and the corresponding sensing line; a second sensing switch, which is configured to control the connection between a second reference voltage line and the corresponding sensing line; and a third sensing switch, which is configured to control the connection between the analog-to-digital converter and the corresponding sensing line.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a data drive integrated circuit, a display device and a pixel compensation method. Background Art

[0002] In an organic light emitting diode (OLED) display device, the pixel driving circuit includes a driving transistor for controlling the driving current flowing through the organic light emitting diode. Due to the instability of the manufacturing process, device parameter drift and transistor aging, the driving current may vary from transistor to transistor and drift over time, resulting in non-uniformity problems on the sub-pixels in the display device. Pixel compensation can be used to compensate for voltage signals or current signals. Summary of the invention

[0003] In one aspect, the present disclosure provides a data driver integrated circuit, comprising: a digital-to-analog converter, configured to receive a corresponding digital data signal from a timing controller and convert the corresponding digital data signal into a corresponding analog data signal, and the corresponding analog data signal is output to a display panel through a corresponding data line; an analog-to-digital converter, configured to receive a corresponding analog sensing signal from a corresponding sensing line in the display panel and convert the corresponding analog sensing signal into a corresponding digital sensing signal, and the corresponding digital sensing signal is output to the timing controller; a first sensing switch, configured to control a connection between a first reference voltage line and the corresponding sensing line; a second sensing switch, configured to control a connection between a second reference voltage line and the corresponding sensing line; and a third sensing switch, configured to control a connection between the analog-to-digital converter and the corresponding sensing line.

[0004] In one aspect, the present disclosure provides a display device, comprising: the data driver integrated circuit described herein; a plurality of data lines, which are respectively coupled to the data driver integrated circuit; a plurality of sensing lines, which are respectively coupled to the data driver integrated circuit; the first reference voltage line, which is configured to provide a first reference voltage signal; and the second reference voltage line, which is configured to provide a second reference voltage signal.

[0005] In some embodiments, corresponding sensing lines are coupled to multiple columns of pixel driving circuits.

[0006] In some embodiments, the corresponding sensing line is coupled to n columns of pixel driving circuits, and n pixel driving circuits in a corresponding row of the n columns of pixel driving circuits are respectively connected to n light emitting elements in n sub-pixels respectively.

[0007] In some embodiments, the corresponding sensing line is coupled to 2n columns of pixel driving circuits, and 2n pixel driving circuits in corresponding rows of the 2n columns of pixel driving circuits are respectively connected to 2n light emitting elements in the 2n sub-pixels.

[0008] In some embodiments, the display device also includes multiple pixel driving circuits and multiple light-emitting diodes; each pixel driving circuit includes: a storage capacitor having a first capacitor electrode coupled to a first node and a second capacitor coupled to a second node; a driving transistor having a first electrode coupled to a corresponding voltage supply line, a second electrode coupled to the second node, and a gate coupled to the first node; a switching transistor having a first electrode coupled to a corresponding data line, a second electrode coupled to the first node, and a gate coupled to a corresponding first gate line; and a sensing transistor having a first electrode coupled to the corresponding sensing line, a second electrode coupled to the second node, and a gate coupled to a corresponding second gate line.

[0009] In one aspect, the present disclosure provides a pixel compensation method, comprising: in a sensing voltage writing phase, providing a turn-on voltage signal to a corresponding first gate line to turn on a switching transistor in a corresponding pixel driving circuit; providing a turn-on voltage signal to a corresponding second gate line to turn on a sensing transistor in the corresponding pixel driving circuit; controlling a first sensing switch of a data driving integrated circuit to be in a conductive state to electrically connect a first reference voltage line to a corresponding sensing line, while keeping a second sensing switch and a third sensing switch of the data driving integrated circuit in a non-conductive state; providing a first reference voltage signal to the corresponding sensing line through the first reference voltage line; and providing a sensing voltage signal to a first electrode of the switching transistor through a corresponding data line, the sensing voltage signal reaching a first node through the switching transistor, the first node being coupled to a gate of the driving transistor, a drain of the switching transistor, and a first capacitor electrode of a storage capacitor.

[0010] In some embodiments, the second sensing switch is configured to control a connection between a second reference voltage line and the corresponding sensing line; and the third sensing switch is configured to control a connection between an analog-to-digital converter of the data driving integrated circuit and the corresponding sensing line.

[0011] In some embodiments, the pixel compensation method also includes: in a charging stage, controlling the first sensing switch, the second sensing switch and the third sensing switch of the data driver integrated circuit to be in a non-conductive state respectively; providing a cut-off voltage signal to the corresponding first gate line to turn off the switching transistor in the corresponding pixel driving circuit; providing a turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; and providing a voltage signal to a corresponding voltage supply line coupled to a first electrode of the driving transistor, allowing a charging current to flow through the driving transistor, thereby charging the corresponding sensing line.

[0012] In some embodiments, the corresponding sensing line is charged from a voltage level of the first reference voltage signal to a voltage level within a conversion voltage range of an analog-to-digital converter of the data driving integrated circuit.

[0013] In some embodiments, during the charging phase, the pixel compensation method further includes interrupting the data voltage signal to any data line.

[0014] In some embodiments, the pixel compensation method further includes: in a sensing stage after the charging stage, controlling the third sensing switch of the data driver integrated circuit to be in a conductive state to electrically connect the corresponding sensing line to an analog-to-digital converter, while keeping the first sensing switch and the second sensing switch of the data driver integrated circuit in a non-conductive state.

[0015] In some embodiments, the pixel compensation method further includes: in a conversion phase, converting a corresponding analog sensing signal from a corresponding sensing line into a corresponding digital sensing signal; and outputting the corresponding digital sensing signal to a timing controller.

[0016] In some embodiments, the pixel compensation method further includes: in a data write-back phase after a charging phase and a conversion phase, controlling the second sensing switch of the data driver integrated circuit to be in a conductive state to electrically connect a second reference voltage line to the corresponding sensing line, while keeping the first sensing switch and the third sensing switch of the data driver integrated circuit in a non-conductive state; providing a second reference voltage signal to the corresponding sensing line through the second reference voltage line; providing the turn-on voltage signal to the corresponding first gate line to turn on the switching transistor in the corresponding pixel driving circuit; providing the turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; and providing a corresponding data signal to the first electrode of the switching transistor through the corresponding data line, and the corresponding data signal passes through the switching transistor to the first node; wherein a voltage level of the second reference voltage signal is higher than a voltage level of the first reference voltage signal.

[0017] In some embodiments, the pixel compensation method also includes: in an idle stage after the data write back stage, controlling the first sensing switch, the second sensing switch and the third sensing switch of the data driver integrated circuit to be in the non-conductive state respectively; providing a cut-off voltage signal to the corresponding first gate line to turn off the switching transistor in the corresponding pixel driving circuit; and providing a turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit.

[0018] In some embodiments, during the idle phase, the pixel compensation method further includes interrupting the data voltage signal to any data line.

[0019] In some embodiments, the pixel compensation method also includes: in an image display period after a sensing period, controlling the second sensing switch of the data driver integrated circuit to be in a conductive state to electrically connect a second reference voltage line to the corresponding sensing line, while keeping the first sensing switch and the third sensing switch of the data driver integrated circuit in a non-conductive state; providing a second reference voltage signal to the corresponding sensing line through the second reference voltage line; providing the turn-on voltage signal to the corresponding first gate line to turn on a switching transistor in a corresponding pixel driving circuit; providing the turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; and providing a corresponding data signal to the first electrode of the switching transistor through the corresponding data line, and the corresponding data signal passes through the switching transistor to the first node; wherein a voltage level of the second reference voltage signal is higher than a voltage level of the first reference voltage signal.

[0020] In some embodiments, the sensing voltage signal continuously includes a first low voltage level, a first high voltage level, a second high voltage level, and a second low voltage level; wherein the first high voltage level is higher than the second high voltage level; and the second high voltage level is higher than the voltage level of the threshold voltage of the driving transistor.

[0021] In some embodiments, the pixel compensation method further includes: calibrating a plurality of analog-to-digital converters in one or more data driver integrated circuits in a display device relative to each other; wherein calibrating the plurality of analog-to-digital converters includes: in a first calibration phase, controlling a second sensing switch of a corresponding data driver integrated circuit to be in a conductive state to electrically connect a second reference voltage line to the corresponding sensing line while keeping the first sensing switch and the third sensing switch of the corresponding data driver integrated circuit in a non-conductive state; and providing a second reference voltage signal to the corresponding sensing line through the second reference voltage line; wherein calibrating the plurality of analog-to-digital converters further includes: in a second calibration phase, controlling the third sensing switch of the corresponding data driver integrated circuit to be in a conductive state to electrically connect the corresponding sensing line to the corresponding analog-to-digital converter while keeping the first sensing switch and the second sensing switch of the corresponding data driver integrated circuit in a non-conductive state; converting a corresponding analog sensing signal into a corresponding digital sensing signal through the corresponding analog-to-digital converter; and outputting the corresponding digital sensing signal to a timing controller; wherein the values ​​of the plurality of analog sensing signals respectively converted by the plurality of analog-to-digital converters are used to calibrate the plurality of analog-to-digital converters relative to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0023] Figure 1 is a schematic diagram showing the structure of a data driving integrated circuit according to some embodiments of the present disclosure.

[0024] Figure 2 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0025] Figure 3 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0026] Figure 4 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0027] Figure 5 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0028] Figure 6 is a circuit diagram showing the structure of each pixel driving circuit in some embodiments according to the present disclosure.

[0029] Fig. 7A is a timing diagram for operating a display device according to some embodiments of the present disclosure.

[0030] Figure 7B is a timing diagram for operating a display device according to some embodiments of the present disclosure.

[0031] Figure 8 is a schematic diagram of a waveform of a sensing voltage signal according to some embodiments of the present disclosure.

[0032] Fig. 9 A process of calibrating multiple analog-to-digital converters in some embodiments according to the present disclosure is shown. DETAILED DESCRIPTION

[0033] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0034] The present disclosure particularly provides a data driver integrated circuit, a display device, and a pixel compensation method, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a data driver integrated circuit. In some embodiments, the data driver integrated circuit includes a digital-to-analog converter, which is configured to receive a corresponding digital data signal from a timing controller and convert the corresponding digital data signal into a corresponding analog data signal, and the corresponding analog data signal is output to a display panel through a corresponding data line; an analog-to-digital converter, which is configured to receive a corresponding analog sensing signal from a corresponding sensing line in the display panel, and convert the corresponding analog sensing signal into a corresponding digital sensing signal, and the corresponding digital sensing signal is output to the timing controller; a first sensing switch, which is configured to control the connection between a first reference voltage line and the corresponding sensing line; a second sensing switch, which is configured to control the connection between a second reference voltage line and the corresponding sensing line; and a third sensing switch, which is configured to control the connection between the analog-to-digital converter and the corresponding sensing line.

[0035] Figure 1 is a schematic diagram showing the structure of a data driver integrated circuit according to some embodiments of the present disclosure. Figure 1 In some embodiments, the data driving integrated circuit includes a digital-to-analog converter DAC, an analog-to-digital converter ADC, a first sensing switch SW1, a second sensing switch SW2, and a third sensing switch SW3. Figure 1 As shown, the digital-to-analog converter DAC is configured to receive a corresponding digital data signal rdds from a timing controller, and convert the corresponding digital data signal rdds into a corresponding analog data signal rads, and the analog data signal rads is output to the display panel through the corresponding data line RDL. The analog-to-digital converter ADC is configured to receive a corresponding analog sensing signal rass from a corresponding sensing line RSL in the display panel, and convert the corresponding analog sensing signal rass into a corresponding digital sensing signal rdss, and the corresponding digital sensing signal rdss is output to the timing controller. The first sensing switch SW1 is configured to control the connection between the first reference voltage line Vref1 and the corresponding sensing line RSL. The second sensing switch SW2 is configured to control the connection between the second reference voltage line Vref2 and the corresponding sensing line RSL. The third sensing switch SW3 is configured to control the connection between the analog-to-digital converter ADC and the corresponding sensing line RSL.

[0036] Optionally, the first reference voltage line Vref1 is configured to provide a first reference voltage signal. Optionally, the second reference voltage line Vref2 is configured to provide a second reference voltage signal. Optionally, the voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal.

[0037] In another aspect, the present disclosure provides a display device having the data driver integrated circuit described herein. In some embodiments, the display device further includes a plurality of data lines, respectively coupled to the data driver integrated circuit; a plurality of sensing lines, respectively coupled to the data driver integrated circuit; a first reference voltage line, configured to provide a first reference voltage signal; and a second reference voltage line, configured to provide a second reference voltage signal.

[0038] Figure 2 Schematic diagram showing the structure of a display device in some embodiments of the present disclosure. Figure 2 In some embodiments, the display device includes a display panel DP having an array of sub-pixels sp; one or more gate drive circuits GDC, which are electrically connected to a plurality of first gate lines GL1 and a plurality of second gate lines GL2; a data drive circuit DDC, which is electrically connected to a plurality of data lines DL and a plurality of sensing lines SL; and a timing controller TC. The timing controller TC is configured to receive image data ("RGB") and timing data ("Timing") from an external device such as a host. The image data RGB includes a plurality of input pixel data for a plurality of pixels, respectively. Each of the input pixel data may include red grayscale data R, green grayscale data G, and blue grayscale data B for a corresponding one of the plurality of pixels. The timing controller TC is configured to control the operation of the one or more gate drive circuits GDC and the data drive circuit DDC. In one example, the timing controller TC is configured to output a plurality of digital data signals ("Data") to the data drive circuit DDC.

[0039] In another example, the plurality of digital data signals ("Data") are compensation data signals. In another example, the timing controller TC is configured to receive a plurality of digital sensing signals ("Sdata") from the data driving circuit DDC. In another example, the timing controller TC is configured to output a plurality of source control signals ("SCS") to the data driving circuit DDC. In another example, the timing controller TC is configured to output a plurality of gate control signals ("GCS") to one or more gate driving circuits GDC.

[0040] In some embodiments, the display device further includes a plurality of voltage supply lines EL. In one example, the plurality of voltage supply lines EL include one or more high voltage supply lines (e.g., a Vdd signal line configured to provide a VDD signal). In another example, the plurality of voltage supply lines EL include one or more low voltage supply lines (e.g., a Vss signal line configured to provide a VSS signal).

[0041] In some embodiments, the display device further comprises a first reference voltage line Vref1 and a second reference voltage line Vref2. Optionally, the first reference voltage line Vref1 is configured to provide a first reference voltage signal. Optionally, the second reference voltage line Vref2 is configured to provide a second reference voltage signal. Optionally, the voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal.

[0042] Figure 3 is a plan view of a display device according to some embodiments of the present disclosure. Figure 3 In some embodiments, the display device includes an array of sub-pixels sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The display device includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of sensing lines SL, and a plurality of voltage supply lines Vdd. The light emission of each sub-pixel sp is driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of the light-emitting element through a high voltage supply line; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light emission of the light-emitting element. Figure 3 In one example shown, the total number of the plurality of data lines DL is the same as the total number of the plurality of sensing lines SL. A large number of signal lines in a display device requires additional integrated circuits and also results in a lower aperture ratio.

[0043] Figure 4 Schematic diagram showing the structure of a display device in some embodiments of the present disclosure. Figure 4 In some embodiments, each sensing line RSL is coupled to a plurality of columns of pixel driving circuits. Figure 4 , a display device having an RGB format is depicted. Each pixel in the display device includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. A plurality of data lines include a data line ("DL_R") connected to the red sub-pixel, a data line ("DL_G") connected to the green sub-pixel, and a data line ("DL_B") connected to the blue sub-pixel.

[0044] In some embodiments, each sensing line RSL is coupled to an n-column pixel driving circuit, and the n pixel driving circuits in each row of the n-column pixel driving circuit are respectively connected to n light-emitting elements in n sub-pixels. Optionally, n represents the number of sub-pixels of different colors in each pixel. In one example, each pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and n=3.

[0045] Figure 5 Schematic diagram showing the structure of a display device in some embodiments of the present disclosure. Figure 5 In some embodiments, each sensing line RSL is coupled to a 2n column pixel driving circuit, and the 2n pixel driving circuits in each row of the 2n column pixel driving circuit are respectively connected to 2n light-emitting elements in each of the 2n sub-pixels. Optionally, n represents the number of sub-pixels of different colors in each pixel. In one example, each pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and n=3.

[0046] Figure 6 is a circuit diagram showing the structure of each pixel driving circuit in some embodiments of the present disclosure. Figure 6 , each pixel driving circuit RPDC is connected to each light emitting element RLE. In some embodiments, each pixel driving circuit RPDC includes a corresponding storage capacitor RCst having a first capacitor electrode coupled to a first node N1 and a second capacitor electrode coupled to a second node N2; a driving transistor T1 having a first electrode coupled to a corresponding voltage supply line Vdd, a second electrode coupled to a second node N2, and a gate coupled to the first node N1; a switching transistor T2 having a first electrode coupled to a corresponding data line RDL, a second electrode coupled to a first node N1, and a gate coupled to a corresponding first gate line RGL1; and a sensing transistor T3 having a first electrode coupled to a corresponding sensing line RSL, a second electrode coupled to a second node N2, and a gate coupled to a corresponding second gate line RGL2. The first node N1 is coupled to the gate of the driving transistor T1, the second electrode of the switching transistor T2, and the first capacitor electrode of the corresponding storage capacitor RCst. The second node N2 is coupled to the second electrode of the driving transistor T1, the second electrode of the sensing transistor T3, the second capacitor electrode of the corresponding storage capacitor RCst, and the anode of the corresponding light emitting element LE. Various suitable light emitting elements may be used in the array substrate. Examples of suitable light emitting elements include organic light emitting diodes, quantum dot light emitting diodes and micro light emitting diodes. Optionally, the light emitting element is a micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.

[0047] As used herein, in the case of a transistor, in some embodiments, the first electrode refers to a source, and in some embodiments, the second electrode refers to a drain.

[0048] On the other hand, the present disclosure also provides a pixel compensation method. In some embodiments, the pixel compensation method includes, in the sensing voltage writing phase, providing a turn-on voltage signal to the corresponding first gate line to turn on the switch transistor in the corresponding pixel driving circuit; providing a turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; controlling the first sensing switch of the data driving integrated circuit to be in a conductive state to electrically connect the first reference voltage line to the corresponding sensing line, while keeping the second sensing switch and the third sensing switch of the data driving integrated circuit in a non-conductive state; providing a first reference voltage signal to the corresponding sensing line through the first reference voltage line; and providing a sensing voltage signal to the first electrode of the switching transistor through the corresponding data line, the sensing voltage signal reaches a first node through the switching transistor, and the first node is coupled to the gate of the driving transistor, the drain of the switching transistor and the first capacitor electrode of the storage capacitor.

[0049] Fig. 7A is a timing diagram for operating a display device according to some embodiments of the present disclosure. Figure 7B is a timing diagram for operating a display device according to some embodiments of the present disclosure. Fig. 7A and Figure 7B Shown with Figure 4 The operation of the display device in the format shown. This operation description is generally also applicable to Figure 5 The operation of the display device in the format shown. Fig. 7A and Figure 7B , the operation of the display device includes an image display period P1 and a sensing period P2 after the image display period P1. Fig. 7A and Figure 7B , the current frame image Fn and the next adjacent frame image F(n+1) are shown.

[0050] In the image display period P1, refer to Fig. 7A , Figure 7B , Figure 4 and Figure 6 , providing a turn-on voltage signal to the corresponding first gate line RGL1 (for example, row by row) to turn on the switch transistor T2 in the corresponding pixel driving circuit RPDC; providing a turn-on voltage signal to the corresponding second gate line RGL2 to turn on the sensing transistor T3 in the corresponding pixel driving circuit RPDC; providing a corresponding data signal through the corresponding data line RDL (for example, Fig. 7A and Figure 7B1 to DL_R1 to DL_Rn, DL_G1 to DL_Gn, and DL_B1 to DL_Bn (depicted in FIG. 1 ) to the first electrode of the switching transistor T2, and the corresponding data signal is transmitted to the first node N1 through the switching transistor T2. The data driving voltage (e.g., Vdata) is written to the gate of the driving transistor T1 (and the first capacitor electrode of the corresponding storage capacitor RCst) through the corresponding data line RDL. As a result, the data driving voltage is stored in the corresponding storage capacitor RCst.

[0051] During the image display period P1, the second sensing switch SW2 of the data driver integrated circuit is controlled in a conductive state to electrically connect the second reference voltage line Vref2 to the corresponding sensing line RSL, while the first sensing switch SW1 and the third sensing switch SW3 of the data driver integrated circuit are maintained in a non-conductive state. A second reference voltage signal (e.g., 1V) is provided to the corresponding sensing line RSL through the second reference voltage line Vref2 and then transferred to the second capacitor electrode of the corresponding storage capacitor RCst. The second reference voltage signal is a relatively high voltage signal (compared to the first reference voltage signal). The voltage level at the anode of the corresponding light emitting element RLE is reset by the sensing line SL (e.g., reset to the voltage level of the second reference voltage signal).

[0052] Subsequently, in the image display period P1, a cut-off voltage signal is provided to the corresponding first gate line RGL1 (for example, row by row) to turn off the switch transistor T2 in the corresponding pixel driving circuit RPDC; a cut-off voltage signal is provided to the corresponding second gate line RGL2 to turn off the sensing transistor T3 in the corresponding pixel driving circuit RPDC. The driving transistor T1 is turned on by the data driving voltage and operates in the saturation region. A voltage supply signal (for example, a VDD signal) is provided to the first electrode of the driving transistor T1, and the driving transistor T1 generates a driving current. The driving current flows through the corresponding light-emitting element RLE, driving the corresponding light-emitting element RLE to emit light.

[0053] Reference again Fig. 7A and Figure 7B In some embodiments, the sensing period P2 includes one or more of a sensing voltage writing phase S1, a charging phase S2, a sensing phase S3, a conversion phase S4, a data writing back phase S5, and an idle phase S6. Fig. 7A and Figure 7B In the above, for the purpose of illustration only, pixel compensation for one sub-pixel (e.g., a red sub-pixel in the current frame image Fn, or a green sub-pixel in the next adjacent frame image F(n+1)) is described. However, it can be understood that the operation in the sensing period P2 is repeated for multiple sub-pixels in the display device (e.g., all sub-pixels one by one).

[0054] refer to Fig. 7A , Figure 7B , Figure 4 and Figure 6 In the sensing voltage writing stage S1, in some embodiments, the pixel compensation method includes providing a turn-on voltage signal to the corresponding first gate line RGL1 to turn on the switch transistor T2 in the corresponding pixel driving circuit RPDC; providing a turn-on voltage signal to the corresponding second gate line RGL2 to turn on the sensing transistor T3 in the corresponding pixel driving circuit RPDC; controlling the first sensing switch SW1 of the data driving integrated circuit to be in a conductive state to electrically connect the first reference voltage line Vref1 to the corresponding sensing line RSL, while keeping the second sensing switch SW2 and the third sensing switch SW3 of the data driving integrated circuit in a non-conductive state; providing a first reference voltage signal (e.g., 0V) to the corresponding sensing line through the first reference voltage line Vref1; and providing the sensing voltage signal to the first electrode of the switching transistor through the corresponding data line, and the sensing voltage signal reaches the first node coupled to the gate of the driving transistor, the drain of the switching transistor and the first capacitor electrode of the storage capacitor through the switching transistor. Optionally, the first reference voltage signal is a low voltage signal (e.g., a ground voltage signal) to ensure that the initial states of multiple sensing lines are the same. Optionally, the duration of the sensing voltage writing stage S1 is about 100μs.

[0055] Fig. 7A and Figure 7B Shows that there is Figure 4 1 and 2. The operation of the display device of the format shown in FIG. 1 is performed, wherein each sensing line RSL is coupled to three columns of pixel driving circuits. Therefore, the corresponding sensing line RSL is shared between three sub-pixels in the same row. For example, the corresponding sensing line RSL is shared between a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Fig. 7A and Figure 7BAs shown, when sensing is performed in the red sub-pixel in the current frame image Fn, a sensing voltage signal (e.g., DL_R_Sense) with a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the red sub-pixel through the corresponding data line (e.g., DL_R). Because the corresponding sensing line RSL is shared between the red sub-pixel, the green sub-pixel, and the blue sub-pixel, the sensing performance in the blue sub-pixel and the green sub-pixel must be prevented to avoid interference. Therefore, when a sensing voltage signal (e.g., DL_R_Sense) with a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the red sub-pixel through the corresponding data line (e.g., DL_R), a low voltage signal (e.g., 0V) is provided to the first electrode of the switching transistor T2 in the sub-pixels of other colors (e.g., blue sub-pixel and green sub-pixel) through other corresponding data lines (e.g., DL_G and DL_B), respectively. This ensures that the charging current in the subsequent charging stage does not flow through the driving transistors in the blue sub-pixel and the green sub-pixel. Interference between adjacent sub-pixels can be avoided.

[0056] Similarly, in the next adjacent frame image F(n+1), sensing is performed in the green sub-pixel in the next adjacent frame image F(n+1), and a sensing voltage signal (e.g., DL_G_Sense) having a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the green sub-pixel through the corresponding data line (e.g., DL_G), while a low voltage signal (e.g., 0V) is provided to the first electrodes of the switching transistors T2 in the sub-pixels of other colors (e.g., red sub-pixel and blue sub-pixel) through other corresponding data lines (e.g., DL_R and DL_B). This ensures that the charging current in the subsequent charging phase does not flow through the driving transistors in the red sub-pixel and the green sub-pixel. Interference between adjacent sub-pixels can be avoided.

[0057] Reference Fig. 7A , Figure 7B , Figure 4 and Figure 6 In the charging stage S2, the pixel compensation method further includes controlling the first sensing switch SW1, the second sensing switch SW2 and the third sensing switch SW3 of the data driving integrated circuit to be in a non-conductive state respectively; providing a cut-off voltage signal to the corresponding first gate line RGL1 to turn off the switch transistor T2 in the corresponding pixel driving circuit; providing a turn-on voltage signal to the corresponding second gate line RGL2 to turn on the sensing transistor T3 in the corresponding pixel driving circuit; and providing a voltage signal to the corresponding voltage supply line RVdd coupled to the first electrode of the driving transistor T1, allowing the charging current to flow through the driving transistor T1, thereby charging the corresponding sensing line RSL. Optionally, the duration of the charging stage S2 is about 120μs.

[0058] As discussed in the case of the sensing voltage writing phase S1, in the sensing voltage writing phase S1 in the current frame image Fn, a sensing voltage signal (e.g., DL_R_Sense) having a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the red sub-pixel through the corresponding data line (e.g., DL_R), and a low voltage signal (e.g., 0V) is provided to the first electrode of the switching transistor T2 in the sub-pixels of other colors (e.g., blue sub-pixel and green sub-pixel) through the corresponding data lines (e.g., DL_G and DL_B), respectively. In the charging phase S2 of the current frame image Fn, the charging current flows through the driving transistor T1 in the red sub-pixel, while the charging current does not flow through the driving transistors in the blue sub-pixel and the green sub-pixel. Interference between adjacent sub-pixels can be avoided.

[0059] Similarly, as discussed in the case of the sensing voltage writing phase S1, in the sensing voltage writing phase S1 in the next adjacent frame image F(n+1), sensing is performed in the green sub-pixel in the next adjacent frame image F(n+1), and a sensing voltage signal (e.g., DL_G_Sense) having a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the green sub-pixel through the corresponding data line (e.g., DL_G), while a low voltage signal (e.g., 0V) is provided to the first electrode of the switching transistor T2 in the sub-pixels of other colors (e.g., the red sub-pixel and the blue sub-pixel) through other corresponding data lines (e.g., DL_R and DL_B), respectively. In the charging phase S2 of the current frame image Fn, the charging current flows through the driving transistor T1 in the green sub-pixel, while the charging current does not flow through the driving transistors in the red sub-pixel and the blue sub-pixel. Interference between adjacent sub-pixels can be avoided.

[0060] The description of the operation of the sensing voltage writing phase S1 and the charging phase S2 is also generally applicable to the Figure 5 The display device operates in the format shown. Figure 5In the format shown, the corresponding sensing line RSL is shared between two red sub-pixels, two green sub-pixels and two blue sub-pixels. When sensing is performed in the first red sub-pixel in the current frame image Fn, a sensing voltage signal with a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the red sub-pixel through the corresponding data line (e.g., DL_R), and a low voltage signal (e.g., 0V) is provided to the first electrode of the switching transistor T2 in the two blue sub-pixels, the two green sub-pixels and the other red sub-pixel. In the charging phase S2 of the current frame image Fn, the charging current flows through the driving transistor T1 in the first red sub-pixel, while the charging current does not flow through the driving transistors in the two blue sub-pixels, the two green sub-pixels and the other red sub-pixel. Interference between adjacent sub-pixels can be avoided. Similarly, when sensing is performed in the green sub-pixel in the next adjacent frame image F(n+1), a sensing voltage signal with a relatively high voltage level is provided to the first electrode of the switching transistor T2 in the first green sub-pixel through the corresponding data line (e.g., DL_G), and a low voltage signal (e.g., 0V) is provided to the first electrode of the switching transistor T2 in the two red sub-pixels, the two blue sub-pixels, and the other green sub-pixel. Interference between adjacent sub-pixels can be avoided. In the charging phase S2 of the next adjacent frame image F(n+1), the charging current flows through the driving transistor T1 in the first green sub-pixel, while the charging current does not flow through the driving transistors in the two red sub-pixels, the two blue sub-pixels, and the other green sub-pixel. Interference between adjacent sub-pixels can be avoided.

[0061] In some embodiments, the corresponding sensing line RSL is charged from the voltage level of the first reference voltage signal to a voltage level within the conversion voltage range of the analog-to-digital converter of the data driver integrated circuit. In one example, the conversion voltage range of the analog-to-digital converter is, for example, 1V to 4V. In another example, the corresponding sensing line RSL is charged from the voltage level of the first reference voltage signal to, for example, 1V (e.g., Fig. 7A ).

[0062] Optionally, the corresponding sensing line RSL is charged from the voltage level of the first reference voltage signal to a middle voltage level (e.g., 2.5V) of the conversion voltage range of the analog-to-digital converter. In another example, the corresponding sensing line RSL is charged from the voltage level of the first reference voltage signal to, for example, 2.5V (e.g., Figure 7B By charging the voltage level of the corresponding sensing line RSL to a middle voltage level approximately in the conversion voltage range, the conversion accuracy can be significantly improved.

[0063] In some embodiments, in the charging stage S2, the pixel compensation method further includes interrupting the data voltage signal to any data line (eg, Fig. 7A and Figure 7BIn one example, the data line is provided with a voltage signal of 0V (eg, Fig. 7A and Figure 7B DL_RL, DL_GL, DL_BL in .

[0064] refer to Fig. 7A , Figure 7B , Figure 4 and Figure 6 In the sensing stage S3 after the charging stage S2, the pixel compensation method further includes controlling the third sensing switch SW3 of the data driver integrated circuit to be in a conductive state to electrically connect the corresponding sensing line RSL to the analog-to-digital converter, while keeping the first sensing switch SW1 and the second sensing switch SW2 of the data driver integrated circuit in a non-conductive state. In the sensing stage S3, the pixel compensation method further includes providing a cutoff voltage signal to the corresponding first gate line RGL1 to turn off the switching transistor T2 in the corresponding pixel driving circuit; providing a cutoff voltage signal to the corresponding second gate line RGL2 to turn off the sensing transistor T3 in the corresponding pixel driving circuit. Optionally, the duration of the sensing stage S3 is about 40μs.

[0065] In some embodiments, in the sensing phase S3, the pixel compensation method further includes interrupting the data voltage signal to any data line (eg, Fig. 7A and Figure 7B In one example, the data line is provided with a voltage signal of 0V (eg, Fig. 7A and Figure 7B DL_RL, DL_GL, DL_BL in .

[0066] Reference Fig. 7A , Figure 7B , Figure 4 and Figure 6 , in the conversion stage S4, the pixel compensation method also includes converting the corresponding analog sensing signal from the corresponding sensing line RSL into a corresponding digital sensing signal; and outputting the corresponding digital sensing signal to the timing controller. In the conversion stage S4, the pixel compensation method also includes providing a cut-off voltage signal to the corresponding first gate line RGL1 to turn off the switching transistor T2 in the corresponding pixel driving circuit; providing a cut-off voltage signal to the corresponding second gate line RGL2 to turn off the sensing transistor T3 in the corresponding pixel driving circuit; and controlling the first sensing switch SW1, the second sensing switch SW2 and the third sensing switch SW3 of the data driver integrated circuit to be in a non-conductive state. The conversion occurs in the analog-to-digital converter of the data integrated circuit. Optionally, the duration of the conversion stage S4 is about 10μs to 100μs. The duration of the conversion stage S4 is at least partially related to the display resolution and the conversion rate.

[0067] In some embodiments, in the conversion phase S4, the pixel compensation method further includes interrupting the data voltage signal to any data line (eg, Fig. 7A and Figure 7B In one example, the data line is provided with a voltage signal of 0V (eg, Fig. 7A and Figure 7B DL_RL, DL_GL, DL_BL in .

[0068] refer to Fig. 7A , Figure 7B , Figure 4 and Figure 6 , in the data write-back phase S5 after the charging phase S3 and the conversion phase S4, the pixel compensation method further includes controlling the second sensing switch SW2 of the data driving integrated circuit to be in a conductive state to electrically connect the second reference voltage line Vref2 to the corresponding sensing line RSL, while keeping the first sensing switch SW1 and the third sensing switch SW3 of the data driving integrated circuit in a non-conductive state; providing a second reference voltage signal (for example, 1V) to the corresponding sensing line through the second reference voltage line Vref2; providing the turn-on voltage signal to the corresponding first gate line RGL1 to turn on the switch transistor T2 in the corresponding pixel driving circuit RPDC; providing the turn-on voltage signal to the corresponding second gate line RGL2 to turn on the sensing transistor T2 in the corresponding pixel driving circuit RPDC; and providing the corresponding data signal (for example, Fig. 7A and Figure 7B DL_R1, DL_G1, DL_B1) depicted in FIG. 1 to the first electrode of the switch transistor T2, and the corresponding data signal passes through the switch transistor T2 to the first node N1. Optionally, the voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal. Optionally, the duration of the data write-back phase S5 is approximately the display duration of 1 to 3 rows of sub-pixels.

[0069] In the charging phase S2, the sensing phase S3, and the conversion phase S4, the data line (eg Fig. 7A and Figure 7B DL_R, DL_G, DL_B) in are provided with a 0V voltage signal (e.g. Fig. 7A and Figure 7B DL_RL, DL_GL, DL_BL in the image frame F(n+1), and the voltage level at the first node N1 is reduced to 0 V. Before the image display period P1 in the next adjacent frame image F(n+1), the voltage level at the first node N1 is increased to the corresponding data signal (for example, Fig. 7A and Figure 7BThe voltage level of the first node N1 is increased to the voltage level of the corresponding data signal by having the data write-back phase S5.

[0070] refer to Fig. 7A , Figure 7B , Figure 4 and Figure 6 , in the idle stage S6 after the data write back stage S5, the pixel compensation method further includes controlling the first sensing switch SW1, the second sensing switch SW2 and the third sensing switch SW3 of the data driving integrated circuit to be in a non-conductive state respectively; providing a cut-off voltage signal to the corresponding first gate line RGL1 to turn off the switching transistor T2 in the corresponding pixel driving circuit RPDC; and providing a turn-on voltage signal to the corresponding second gate line RGL2 to turn on the sensing transistor T3 in the corresponding pixel driving circuit RPDC.

[0071] In some embodiments, in the idle phase S6, the pixel compensation method further includes interrupting the data voltage signal to any data line (eg, Fig. 7A and Figure 7B In one example, the data line is provided with a voltage signal of 0V (eg, Fig. 7A and Figure 7B Since the switch transistor T2 is turned off in the idle phase S6, the voltage level of the first node N1 is maintained at the voltage level of the corresponding data signal.

[0072] refer to Fig. 7A , Figure 7B , Figure 4 and Figure 6, in the image display period after the sensing period P2 in the current frame image Fn (for example, P1 in the next adjacent frame image F(n+1)), the pixel compensation method further includes controlling the second sensing switch SW2 of the data driver integrated circuit to be in a conductive state to electrically connect the second reference voltage line Vref2 to the corresponding sensing line RSL, while keeping the first sensing switch SW1 and the third sensing switch SW3 of the data driver integrated circuit in a non-conductive state; providing a second reference voltage signal (for example, 1V) to the corresponding sensing line RSL through the second reference voltage line Vref2; providing a turn-on voltage signal to the corresponding first gate line RGL1 to turn on the switch transistor T2 in the corresponding pixel driving circuit RPDC; providing the turn-on voltage signal to the corresponding second gate line RGL2 to turn on the sensing transistor T2 in the corresponding pixel driving circuit RPDC; and providing a corresponding data signal to the first electrode of the switch transistor T2 through the corresponding data line RDL, and the corresponding data signal passes through the switch transistor T2 to the first node N1. Optionally, the voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal.

[0073] As discussed above, in some embodiments, in the sensing voltage writing phase S1, the sensing voltage signal (eg, Fig. 7A and Figure 7B The sensing voltage signal DL_R_Sense and DL_G_Sense depicted in FIG. 1 is provided to the first electrode of the switching transistor through the corresponding data line RDL, and the sensing voltage signal reaches the first node N1 through the switching transistor. Figure 8 is a schematic diagram of the waveform of the sensing voltage signal according to some embodiments of the present disclosure. Figure 8 In some embodiments, the sensing voltage signal continuously includes a first low voltage level LV1, a first high voltage level HV1, a second high voltage level HV2, and a second low voltage level LV2. Optionally, the first high voltage level HV1 is higher than the second high voltage level HV2. Optionally, the second high voltage level HV2 is higher than the voltage level of the threshold voltage Vth of the driving transistor.

[0074] In some embodiments, the display device may include one or more data driver integrated circuits, and each data driver integrated circuit may include one or more analog-to-digital converters. Multiple analog-to-digital converters in the display device may output digital signals with different values ​​when receiving the same analog signal. Therefore, it is desirable to calibrate multiple analog-to-digital converters in the display device. Fig. 9 The process of calibrating multiple analog-to-digital converters according to some embodiments of the present disclosure is shown. Fig. 9 and Figure 1In some embodiments, calibrating multiple analog-to-digital converters includes, in a first calibration phase CP1, controlling the second sensing switch SW2 of the corresponding data driver integrated circuit to be in a conductive state to electrically connect the second reference voltage line Vref2 to the corresponding sensing line RSL, while maintaining the first sensing switch SW1 and the third sensing switch SW3 of the corresponding data driver integrated circuit in a non-conductive state; and providing a second reference voltage signal (e.g., 1V) to the corresponding sensing line through the second reference voltage line Vref2.

[0075] In some embodiments, calibrating the plurality of analog-to-digital converters further comprises, in a second calibration phase CP2, controlling the third sensing switch SW3 of the corresponding data driver integrated circuit to be in a conductive state to electrically connect the corresponding sensing line RSL to the corresponding analog-to-digital converter ADC, while maintaining the first sensing switch SW1 and the second sensing switch SW2 of the corresponding data driver integrated circuit in a non-conductive state; converting the corresponding analog sensing signal into a corresponding digital sensing signal through the corresponding analog-to-digital converter; and outputting the corresponding digital sensing signal to the timing controller. The values ​​of the plurality of analog sensing signals respectively converted by the plurality of analog-to-digital converters are used to calibrate the plurality of analog-to-digital converters relative to each other.

[0076] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A display device, comprising: Data driver integrated circuit; a plurality of data lines, which are respectively coupled to the data driving integrated circuit; A plurality of sensing lines, which are respectively coupled to the data driving integrated circuit; A first reference voltage line configured to provide a first reference voltage signal; a second reference voltage line configured to provide a second reference voltage signal, and configured to transmit the second reference voltage signal to a corresponding sensing line during a data write-back phase after a charging phase and a conversion phase; as well as a plurality of pixel driving circuits and a plurality of light emitting diodes; The data driving integrated circuit comprises: a digital-to-analog converter configured to receive a corresponding digital data signal from the timing controller and convert the corresponding digital data signal into a corresponding analog data signal, and the corresponding analog data signal is output to the display panel through a corresponding data line; an analog-to-digital converter configured to receive a corresponding analog sensing signal from a corresponding sensing line in the display panel and convert the corresponding analog sensing signal into a corresponding digital sensing signal, wherein the corresponding digital sensing signal is output to the timing controller; a first sensing switch configured to control a connection between the first reference voltage line and the corresponding sensing line, and configured to be in a non-conductive state during the data write-back phase; a second sensing switch configured to control connection between the second reference voltage line and the corresponding sensing line, and configured to be in a conductive state during the data write-back phase to electrically connect the second reference voltage line to the corresponding sensing line; and a third sensing switch configured to control a connection between the analog-to-digital converter and the corresponding sensing line, and configured to be in a non-conductive state during the data write-back phase; Each pixel driving circuit includes: a storage capacitor having a first capacitor electrode coupled to the first node and a second capacitor electrode coupled to the second node; a driving transistor having a first electrode coupled to a corresponding voltage supply line, a second electrode coupled to the second node, and a gate coupled to the first node; a switch transistor having a first electrode coupled to a corresponding data line, a second electrode coupled to the first node, and a gate coupled to a corresponding first gate line; and a sensing transistor having a first electrode coupled to the corresponding sensing line, a second electrode coupled to the second node, and a gate coupled to the corresponding second gate line, Wherein, the corresponding first gate line is configured to receive a turn-on voltage signal in the data write-back phase to turn on the switch transistor in the corresponding pixel driving circuit; Wherein, the corresponding second gate line is configured to receive a turn-on voltage signal in the data write-back phase to turn on the sensing transistor in the corresponding pixel driving circuit; Wherein, the first electrode of the switch transistor is configured to receive a corresponding data signal through the corresponding data line during the data write-back phase, and the corresponding data signal passes through the switch transistor to the first node; The voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal.

2. The display device according to claim 1, wherein: The corresponding sensing lines are coupled to a plurality of columns of pixel driving circuits.

3. The display device according to claim 1, wherein: The corresponding sensing lines are coupled to n columns of pixel driving circuits, and the n pixel driving circuits in corresponding rows of the n columns of pixel driving circuits are respectively connected to n light emitting elements in the n sub-pixels.

4. The display device according to claim 1, wherein: The corresponding sensing lines are coupled to 2n columns of pixel driving circuits, and 2n pixel driving circuits in corresponding rows of the 2n columns of pixel driving circuits are respectively connected to 2n light emitting elements in the 2n sub-pixels.

5. The display device according to any one of claims 1 to 4, further comprising the timing controller; wherein: The timing controller is configured to control the second sensing switch of the data driver integrated circuit to be in a conductive state in a data write-back phase after a charging phase and a conversion phase, so as to electrically connect the second reference voltage line to the corresponding sensing line, while keeping the first sensing switch and the third sensing switch of the data driver integrated circuit in a non-conductive state; and provide the second reference voltage signal to the corresponding sensing line through the second reference voltage line; Providing the on-voltage signal to the corresponding first gate line to turn on the switch transistor in the corresponding pixel driving circuit; The on-voltage signal is provided to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; and a corresponding data signal is provided to the first electrode of the switching transistor through the corresponding data line, and the corresponding data signal passes through the switching transistor to the first node.

6. A pixel compensation method, comprising: In the sensing voltage writing phase, Providing a turn-on voltage signal to the corresponding first gate line to turn on a switch transistor in the corresponding pixel driving circuit; Providing a turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; Controlling a first sensing switch of the data driving integrated circuit to be in a conductive state to electrically connect the first reference voltage line to the corresponding sensing line, while keeping the second sensing switch and the third sensing switch of the data driving integrated circuit in a non-conductive state; providing a first reference voltage signal to the corresponding sensing line through the first reference voltage line; as well as providing a sensing voltage signal to a first electrode of the switch transistor through a corresponding data line, the sensing voltage signal passing through the switch transistor to a first node, the first node being coupled to a gate of a drive transistor, a drain of the switch transistor and a first capacitor electrode of a storage capacitor; The method further comprises: In the data write-back phase after the charging phase and the conversion phase, controlling the second sensing switch of the data driving integrated circuit to be in a conductive state to electrically connect the second reference voltage line to the corresponding sensing line while keeping the first sensing switch and the third sensing switch of the data driving integrated circuit in a non-conductive state; providing a second reference voltage signal to the corresponding sensing line through the second reference voltage line; Providing the on-voltage signal to the corresponding first gate line to turn on the switch transistor in the corresponding pixel driving circuit; providing the on-voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; and Provide a corresponding data signal to the first electrode of the switch transistor through the corresponding data line, and the corresponding data signal passes through the switch transistor to the first node; The voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal.

7. The pixel compensation method according to claim 6, wherein: The second sensing switch is configured to control a connection between a second reference voltage line and the corresponding sensing line; and The third sensing switch is configured to control a connection between an analog-to-digital converter of the data driving integrated circuit and the corresponding sensing line.

8. The pixel compensation method according to claim 6 or 7, further comprising: During the charging phase, Controlling the first sensing switch, the second sensing switch and the third sensing switch of the data driving integrated circuit to be in a non-conductive state respectively; Providing a cutoff voltage signal to the corresponding first gate line to turn off the switch transistor in the corresponding pixel driving circuit; Providing a turn-on voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; as well as A voltage signal is provided to a corresponding voltage supply line coupled to the first electrode of the drive transistor, allowing a charging current to flow through the drive transistor, thereby charging the corresponding sense line.

9. The pixel compensation method according to claim 8, wherein: The corresponding sensing line is charged from a voltage level of the first reference voltage signal to a voltage level within a conversion voltage range of an analog-to-digital converter of the data driving integrated circuit. 10 . The pixel compensation method according to claim 8 , further comprising interrupting a data voltage signal to any data line during the charging phase.

11. The pixel compensation method according to claim 6 or 7, further comprising: In the sensing phase following the charging phase, The third sensing switch of the data driving integrated circuit is controlled to be in a conductive state to electrically connect the corresponding sensing line to an analog-to-digital converter, while keeping the first and second sensing switches of the data driving integrated circuit in a non-conductive state.

12. The pixel compensation method according to claim 11, further comprising: During the conversion phase, converting corresponding analog sensing signals from corresponding sensing lines into corresponding digital sensing signals; as well as The corresponding digital sensing signal is output to a timing controller.

13. The pixel compensation method according to claim 6, further comprising: In the idle phase after the data write-back phase, Controlling the first sensing switch, the second sensing switch and the third sensing switch of the data driving integrated circuit to be in the non-conductive state respectively; Providing a cutoff voltage signal to the corresponding first gate line to turn off the switch transistor in the corresponding pixel driving circuit; as well as A turn-on voltage signal is provided to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit. 14 . The pixel compensation method according to claim 13 , further comprising interrupting a data voltage signal to any data line during the idle phase.

15. The pixel compensation method according to claim 6 or 7, further comprising: In the image display period after the sensing period, controlling the second sensing switch of the data driving integrated circuit to be in a conductive state to electrically connect the second reference voltage line to the corresponding sensing line while keeping the first sensing switch and the third sensing switch of the data driving integrated circuit in a non-conductive state; providing a second reference voltage signal to the corresponding sensing line through the second reference voltage line; Providing the on-voltage signal to the corresponding first gate line to turn on the switch transistor in the corresponding pixel driving circuit; Providing the on-voltage signal to the corresponding second gate line to turn on the sensing transistor in the corresponding pixel driving circuit; as well as Provide a corresponding data signal to the first electrode of the switch transistor through the corresponding data line, and the corresponding data signal passes through the switch transistor to the first node; The voltage level of the second reference voltage signal is higher than the voltage level of the first reference voltage signal.

16. The pixel compensation method according to claim 6 or 7, wherein: The sensing voltage signal successively includes a first low voltage level, a first high voltage level, a second high voltage level, and a second low voltage level; wherein the first high voltage level is higher than the second high voltage level; and The second high voltage level is a voltage level higher than a threshold voltage of the driving transistor.

17. The pixel compensation method according to claim 6 or 7, further comprising: calibrating a plurality of analog-to-digital converters in one or more data driver integrated circuits in a display device relative to each other; Wherein, calibrating the plurality of analog-to-digital converters comprises: In the first calibration phase, controlling the second sensing switch of the corresponding data driver integrated circuit to be in a conductive state to electrically connect the second reference voltage line to the corresponding sensing line while keeping the first sensing switch and the third sensing switch of the corresponding data driver integrated circuit in a non-conductive state; and providing a second reference voltage signal to the corresponding sensing line through the second reference voltage line; Wherein, calibrating the plurality of analog-to-digital converters further comprises: In the second calibration phase, controlling the third sensing switch of the corresponding data driver integrated circuit to be in a conductive state to electrically connect the corresponding sensing line to a corresponding analog-to-digital converter, while keeping the first sensing switch and the second sensing switch of the corresponding data driver integrated circuit in a non-conductive state; Converting the corresponding analog sensing signal into a corresponding digital sensing signal through the corresponding analog-to-digital converter; and Outputting the corresponding digital sensing signal to a timing controller; The values ​​of the multiple analog sensing signals respectively converted by the multiple analog-to-digital converters are used to calibrate the multiple analog-to-digital converters relative to each other.

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