Display device and method for manufacturing the same

Abstract

A display device and a method of manufacturing the same are provided. A display device according to an embodiment includes: a substrate including a first emission region; and a first light-emitting element disposed in the first emission region, wherein the substrate includes a first hole passing through the substrate in the first emission region, and at least a portion of the first light-emitting element is disposed in the first hole.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] In recent years, interest in information display has increased. Accordingly, research and development of display devices have been continuously carried out. Summary of the Invention

[0003] Technical Problem

[0004] An object to be achieved by the present disclosure is to provide a display device and a method of manufacturing the display device that can align and fix a light-emitting element in a vertical direction according to a pressure difference of a substrate including a through hole.

[0005] The object of the present disclosure is not limited to the above object, and other technical objects not described will be clearly understood by those skilled in the art from the following description.

[0006] Technical Solution

[0007] According to an embodiment of the present disclosure for achieving the above object, a display device may include a substrate and a first light-emitting element, wherein the substrate includes a first emission region, the first light-emitting element is disposed in the first emission region, the substrate may include a first hole passing through the substrate in the first emission region, and at least a part of the first light-emitting element may be disposed in the first hole.

[0008] The first light-emitting element may include a first surface and a second surface opposite to each other, the first surface may be disposed on the lower surface side of the substrate, the second surface may be disposed on the upper surface side of the substrate, and the aspect ratio of the first light-emitting element may be greater than 1.

[0009] In a plan view, the diameter of the second surface may be greater than the diameter of the first surface, and the first light-emitting element may further include a side surface disposed between the first surface and the second surface.

[0010] The side surface of the first light-emitting element may be in contact with the inner circumferential surface of the first hole.

[0011] The first hole may include a side wall perpendicular to the lower surface of the substrate, the diameter of the first hole may be greater than the diameter of the first surface and may be less than the diameter of the second surface, and a part of the first light-emitting element may protrude to the outside of the substrate.

[0012] The display device may further include a filling member filled between the side wall of the first hole and the first light-emitting element.

[0013] The first hole may include a vertical surface perpendicular to the lower surface of the substrate and an inclined surface having a predetermined angle with respect to the lower surface of the substrate, and a side surface of the first light-emitting element may contact the inclined surface and not contact the vertical surface.

[0014] In a plan view, the diameter of the first surface and the diameter of the second surface may be the same.

[0015] The first hole may include a side wall having a predetermined angle with respect to the lower surface of the substrate, the diameter of the first light-emitting element may be greater than the diameter of the lower through-hole surface of the first hole and may be less than the diameter of the upper through-hole surface of the first hole, and a part of the first light-emitting element may protrude to the outside of the substrate.

[0016] The display device may further include a filling member filled between the side wall of the first hole and the first light-emitting element.

[0017] The first hole may include a side wall perpendicular to the lower surface of the substrate, the substrate may further include a protrusion protruding from the side wall of the first hole and integrated with the substrate, the protrusion may contact a part of the first surface, and the protrusion may expose another part of the first surface.

[0018] The thickness of the substrate may be less than the length of the first light-emitting element, and a part of the first light-emitting element may protrude to the outside of the substrate.

[0019] The thickness of the substrate may be greater than the length of the first light-emitting element, and the first light-emitting element may be disposed within the substrate.

[0020] The display device may further include a common electrode and a pixel electrode, wherein the common electrode is disposed on the lower surface of the substrate and electrically connected to the first surface of the first light-emitting element, and the pixel electrode is disposed on the upper surface of the substrate and electrically connected to the second surface of the first light-emitting element.

[0021] The display device may further include a transistor disposed on the upper surface of the substrate in a first circuit region adjacent to the first emission region, and the transistor may be electrically connected to the pixel electrode.

[0022] The display device may further include a second light-emitting element whose emitted light has a color different from the color of the light emitted by the first light-emitting element, the substrate may further include a second hole passing through the substrate in a second emission region adjacent to the first emission region, in a plan view, the diameter of the second hole may be less than the diameter of the first hole, and at least a part of the second light-emitting element may be disposed in the second hole.

[0023] The diameter of the second light-emitting element may be less than the diameter of the first light-emitting element.

[0024] The display device may further include a common electrode, a first pixel electrode, and a second pixel electrode. The common electrode is disposed on the lower surface of the substrate and electrically connected to the first surfaces of the first light-emitting element and the second light-emitting element. The first pixel electrode is disposed on the upper surface of the substrate and electrically connected to the second surface of the first light-emitting element. The second pixel electrode is disposed on the upper surface of the substrate and electrically connected to the second surface of the second light-emitting element that is opposite to the first surface of the second light-emitting element.

[0025] The display device may further include a plurality of channel walls disposed under the substrate, and the plurality of channel walls may not overlap with the first hole.

[0026] According to an embodiment of the present disclosure for achieving the above object, a method of manufacturing a display device may include: preparing a substrate including a first hole; providing a first mixture including a first light-emitting element on the substrate; and vertically aligning the first light-emitting element in the first hole by setting a first pressure in an upper portion of the substrate to be higher than a second pressure in a lower portion of the substrate, and the first hole passes through the substrate.

[0027] The first light-emitting element may include a first surface and a second surface opposite to each other, and an aspect ratio of the first light-emitting element may be greater than 1.

[0028] A diameter of the first surface may be smaller than a diameter of the second surface, and when vertically aligning the first light-emitting element, the first surface may be disposed on the lower surface side of the substrate and the second surface may be disposed on the upper surface side of the substrate.

[0029] The substrate may further include a second hole passing through the substrate. The method may further include: providing a second mixture including a second light-emitting element on the substrate, and a color of light emitted by the second light-emitting element is different from a color of light emitted by the first light-emitting element; and vertically aligning the second light-emitting element in the second hole by setting the first pressure to be higher than the second pressure. A diameter of the second hole may be smaller than a diameter of the first hole, and a diameter of the second light-emitting element may be smaller than a diameter of the first light-emitting element.

[0030] The substrate may further include a third hole passing through the substrate. The method may further include: providing a third mixture including a third light-emitting element on the substrate, and a color of light emitted by the third light-emitting element is different from colors of light emitted by the first light-emitting element and the second light-emitting element; and vertically aligning the third light-emitting element in the third hole by setting the first pressure to be higher than the second pressure. A diameter of the third hole may be smaller than diameters of the first hole and the second hole, and a diameter of the third light-emitting element may be smaller than diameters of the first light-emitting element and the second light-emitting element.

[0031] The method may further include: providing a common electrode on a lower surface of the substrate and electrically connected to a first surface of the first light-emitting element and a first surface of the second light-emitting element; providing a first pixel electrode on an upper surface of the substrate and electrically connected to a second surface of the first light-emitting element; and providing a second pixel electrode on the upper surface of the substrate and electrically connected to a second surface of the second light-emitting element.

[0032] Details of other embodiments are included in the detailed description and the drawings.

[0033] Advantageous Effects

[0034] According to the display device and the method of manufacturing the display device according to embodiments of the present disclosure, the light-emitting elements can be aligned and fixed in the vertical direction according to the pressure difference of the substrate including the through holes. Therefore, the area where the light-emitting elements are provided can be widely ensured, and a high-resolution display device can be realized.

[0035] In addition, since the light-emitting elements are arranged in the vertical direction, and the light emitted from the light-emitting elements is directly emitted upward, the light output efficiency of the display device can be improved, and a separate reflection partition wall for reflecting the light in the horizontal direction in the vertical direction can be omitted.

[0036] In addition, since the light-emitting elements are physically fixed in the holes of the substrate according to the pressure difference between the upper part and the lower part of the substrate, a separate fixing layer for fixing the light-emitting elements can be omitted, and the alignment accuracy of the light-emitting elements in the display device can be improved.

[0037] In addition, by adjusting the size of the light-emitting elements and the size of the holes in the substrate, the light-emitting elements of a desired color can be provided at desired positions.

[0038] The effects according to the embodiments are not limited by the above content, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 and Figure 2 are a perspective view and a cross-sectional view showing a light-emitting element according to an embodiment.

[0040] Figure 3 is a perspective view showing a light-emitting element according to another embodiment.

[0041] Figure 4 is a cross-sectional view showing a light-emitting element according to still another embodiment.

[0042] Figure 5 is a perspective view showing a light-emitting element according to still another embodiment.

[0043] Figure 6 and Figure 7is a perspective view showing a light-emitting element according to still another embodiment.

[0044] Figure 8 is a plan view schematically showing a display device according to an embodiment.

[0045] Figures 9a to 9c is a circuit diagram showing pixels according to an embodiment, respectively.

[0046] Figure 10 is a circuit diagram showing pixels according to another embodiment.

[0047] Figure 11 is Figure 8 a schematic exploded perspective view of the display device of

[0048] Figure 12 is Figure 11 a plan view of the display device of

[0049] Figure 13 is a cross-sectional view of the display device taken along line A-A' of Figure 12

[0050] Figure 14 is Figure 12 a cross-sectional view of the display device taken along line B-B' of

[0051] Figures 15 to 20 is a cross-sectional view of the display device according to various embodiments, and specifically, is a cross-sectional view corresponding to line B-B' of Figure 12

[0052] Figures 21 to 27 is a perspective view and a cross-sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure. Detailed Description

[0053] With reference to the embodiments described in detail below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving them will become apparent. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various different forms. The present embodiments are provided so that the present disclosure will be thorough and complete, and those skilled in the art to which the present disclosure pertains can fully understand the scope of the present disclosure. The present disclosure is defined only by the scope of the claims.

[0054] ​​In a case where an element or a layer is referred to as being "on" another element or layer, it includes a case where the other layer or the other element is directly disposed on the other element or directly disposed between other layers. The shapes, dimensions, ratios, angles, quantities, etc. disclosed in the drawings for describing the embodiments are exemplary, and thus, the present disclosure is not limited thereto. Throughout the specification, the same reference numerals denote the same components. In addition, portions irrelevant to the present disclosure in the drawings may be omitted or simply expressed to clarify the description of the present disclosure.

[0055] Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Thus, within the technical scope of the present disclosure, the first component mentioned below may be the second component. Unless the context clearly indicates otherwise, the singular expression includes the plural expression.

[0056] Each of the features of the various embodiments of the present disclosure may be partially or wholly coupled or combined with each other, and various interlocks and drives are possible technically. Each embodiment may be implemented independently of each other and their associations may be implemented together.

[0057] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0058] Figure 1 and Figure 2 are a perspective view and a cross-sectional view showing a light-emitting element according to an embodiment. Although a rod-shaped light-emitting element LD having a cylindrical shape is shown in Figure 1 and Figure 2 , the type and / or shape of the light-emitting element LD according to the present disclosure is not limited thereto.

[0059] Referring to Figure 1 and Figure 2 , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be formed as a stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked in one direction.

[0060] According to an embodiment, the light-emitting element LD may be a rod-shaped light-emitting diode manufactured in a rod shape. Here, the rod shape may include a rod shape or a bar shape that is longer in the longitudinal direction than in the width direction, such as a cylinder or a polygonal column, but the shape of its cross section is not particularly limited. For example, the length L of the light-emitting element LD may be greater than the diameter D (or the width of the cross section) of the light-emitting element LD. That is, the aspect ratio of the light-emitting element LD may be greater than 1.

[0061] The light-emitting element LD may include a first surface LDa and a second surface LDb that face each other in one direction. The first surface LDa and the second surface LDb may be surfaces exposed to the outside. For example, the first semiconductor layer 11 may be disposed on the first surface LDa of the light-emitting element LD, and the second semiconductor layer 13 may be disposed on the second surface LDb of the light-emitting element LD, but the reverse may also be the case.

[0062] According to an embodiment, the light-emitting element LD may have a size as small as the nanometer scale to the micrometer scale. For example, the diameter D and / or the length L may be in the range of 100 nm to 10 μm. However, the size of the light-emitting element LD is not limited thereto. For example, the size of the light-emitting element LD may be variously changed according to the design conditions of various devices (such as display devices, etc.) using the light-emitting element LD as a light source.

[0063] The first semiconductor layer 11 may include at least one n-type semiconductor material. For example, the first semiconductor layer 11 may include a semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, or InN, and may include an n-type semiconductor material doped with a first conductive dopant such as Si, Ge, Se, or Sn. However, the material configuring the first semiconductor layer 11 is not limited thereto, and various other materials may also configure the first semiconductor layer 11.

[0064] The active layer 12 may be formed on the first semiconductor layer 11 and may include a single quantum well structure or a multi-quantum well structure. In the case where the material of the active layer 12 includes a multi-quantum well structure, the active layer 12 may include a structure in which quantum layers and well layers are alternately stacked.

[0065] In the case where an electric field of a predetermined voltage or a higher voltage is applied to both ends (or the first surface LDa and the second surface LDb) of the light-emitting element LD, as electron-hole pairs are coupled in the active layer 12, the light-emitting element LD may emit light. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD may be used as a light source for various light-emitting devices (including pixels of a display device).

[0066] The active layer 12 may emit light having a wavelength of 400 nm to 900 nm. For example, in the case where the active layer 12 emits light in the blue or green wavelength band, the active layer 12 may include a nitrogen-containing inorganic material such as AlGaN or InAlGaN. Specifically, in the case where the active layer 12 is a structure in which quantum layers and well layers are alternately stacked in a multi-quantum well structure, the quantum layer may include an inorganic material such as AlGaN or InAlGaN, and the well layer may include an inorganic material such as GaN or AlInN. In an embodiment, the active layer 12 may include InAlGaN as the quantum layer and AlInN as the well layer.

[0067] However, the materials and structure of the light-emitting element LD are not limited thereto, and the active layer 12 may include a structure in which a semiconductor material having a large band gap and a semiconductor material having a small band gap are alternately stacked. In addition, the active layer 12 may include a group III to group V semiconductor material according to the wavelength band of the emitted light. The light emitted from the active layer 12 is not limited to light in the blue or green wavelength band, and may be light in the red wavelength band depending on the materials included.

[0068] Meanwhile, the light emitted from the active layer 12 may be emitted to the first surface LDa and the second surface LDb of the light-emitting element LD in the longitudinal direction of the light-emitting element LD. In addition, some of the light emitted from the active layer 12 may be emitted to the side surface (or outer circumferential surface) of the active layer 12. That is, the directivity of the light emitted from the active layer 12 is not limited to one direction.

[0069] The second semiconductor layer 13 may be provided on the active layer 12 and may include a semiconductor material of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, or InN, and may include a p-type semiconductor material doped with a second conductive dopant such as Mg, Zn, Ca, or Ba. However, the materials configuring the second semiconductor layer 13 are not limited thereto, and various other materials may configure the second semiconductor layer 13.

[0070] Meanwhile, in the drawings, the first semiconductor layer 11 and the second semiconductor layer 13 are configured as one layer, but the present disclosure is not limited thereto. For example, depending on the material of the active layer 12, the first semiconductor layer 11 and the second semiconductor layer 13 may include a greater number of layers. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may further include a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0071] According to an embodiment, a first length L1 of the first semiconductor layer 11 may be greater than a second length L2 of the second semiconductor layer 13.

[0072] According to an embodiment, a side surface of the light-emitting element LD (e.g., an outer circumferential surface of the light-emitting element LD) may be parallel to the longitudinal direction of the light-emitting element LD. That is, the side surface of the light-emitting element LD may extend in a direction perpendicular to the first surface LDa and the second surface LDb.

[0073] According to an embodiment, the light-emitting element LD may further include an insulating film INF provided on the surface. The insulating film INF may be formed on the surface of the light-emitting element LD to surround the outer circumferential surface of the active layer 12, and may also surround the outer circumferential surfaces of the first semiconductor layer 11 and the second semiconductor layer 13.

[0074] According to an embodiment, the insulating film INF may expose the first surface LDa and the second surface LDb of the light-emitting element LD. For example, the insulating film INF may not cover and may expose the outer surfaces of each of the first semiconductor layer 11 and the second semiconductor layer 13 positioned at both ends of the light-emitting element LD in the longitudinal direction, for example, two flat surfaces of a cylinder (i.e., the first surface LDa and the second surface LDb).

[0075] According to an embodiment, the insulating film INF may include a transparent insulating material. For example, the insulating film INF may include one or more inorganic insulating materials such as SiO2, Si3N4, Al2O3, or TiO2, but the material of the insulating film INF is not particularly limited and may include various currently known insulating materials.

[0076] In an embodiment, the insulating film INF may include a single-layer structure. In the case where the insulating film INF includes a single-layer structure, the insulating film INF may be formed of one of the above inorganic insulating materials. In another embodiment, the insulating film INF may include a multi-layer structure. In the case where the insulating film INF includes a multi-layer structure, each of the layers of the insulating film INF may be formed of one of the above inorganic insulating materials.

[0077] The insulating film INF may prevent an electrical short circuit that may occur when the active layer 12 comes into contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, by forming the insulating film INF, surface defects of the light-emitting element LD may be minimized to improve the lifespan and efficiency.

[0078] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may further include additional components provided on and / or below each layer. For example, the light-emitting element LD may further include one or more phosphor layers, active layers, semiconductor material layers, and / or electrode layers provided on one side of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0079] Figure 3 is a perspective view showing a light-emitting element according to another embodiment. In Figure 3 order to facilitate description, a part of the insulating film INF is omitted.

[0080] Combined additionally Figure 1 andFigure 2 Reference Figure 3 The light-emitting element LD may further include an electrode layer 14 disposed on the second semiconductor layer 13.

[0081] The electrode layer 14 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto. According to an embodiment, the electrode layer 14 may be a Schottky contact electrode. The electrode layer 14 may include a metal or a metal oxide. For example, the electrode layer 14 may include Cr, Ti, Al, Au, Ni, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc.

[0082] According to an embodiment, the electrode layer 14 may be substantially transparent or semi-transparent. Thus, the light generated in the active layer 12 of the light-emitting element LD may pass through the electrode layer 14 and may be emitted to the outside of the light-emitting element LD.

[0083] Figure 4 is a cross-sectional view showing a light-emitting element according to still another embodiment.

[0084] Additionally combined with Figure 3 Reference Figure 4 the insulating film INF' may have at least a partially curved shape in a corner region adjacent to the electrode layer 14. According to an embodiment, when manufacturing the light-emitting element LD, the curved shape may be formed due to an etching process.

[0085] Meanwhile, even if Figure 1 and Figure 2 the electrode layer 14 is not included in the light-emitting element LD, the insulating film INF' may have at least a partially curved shape in the corner region.

[0086] Figure 5 is a perspective view showing a light-emitting element according to still another embodiment. In Figure 5 for ease of description, a portion of the insulating film INF is omitted.

[0087] Additionally combined with Figure 1 and Figure 2 Reference Figure 5 the light-emitting element LD may further include a third semiconductor layer 15 disposed between the first semiconductor layer 11 and the active layer 12, and a fourth semiconductor layer 16 and a fifth semiconductor layer 17 disposed between the active layer 12 and the second semiconductor layer 13. In addition, the light-emitting element LD may further include a first electrode layer 14a formed on the upper surface of the second semiconductor layer 13 and a second electrode layer 14b formed on the lower surface of the first semiconductor layer 11.

[0088] Figure 5 The light-emitting element LD of Figure 1The embodiment is different in that a plurality of semiconductor layers 15, 16, and 17 and electrode layers 14a and 14b are further provided, and the active layer 12 includes another element. In addition, the arrangement and structure of the insulating film INF are the same as those of Figure 1 in terms of arrangement and structure.

[0089] As described above, in the Figure 1 light-emitting element LD, the active layer 12 can emit blue or green light by including nitrogen (N). Figure 5 The light-emitting element LD of Figure 5 can be a semiconductor in which each of the active layer 12 and other semiconductor layers 11, 13, 15, 16, and 17 includes phosphorus (P). That is, according to the

[0090] embodiment, the light-emitting element LD can emit red light having a central wavelength range of 620 nm to 750 nm. However, it should be understood that the central wavelength band of the red light is not limited to the above range and can include all wavelength ranges that can be considered red in the present technical field. Figure 5 Specifically, in the light-emitting element LD according to the

[0091] embodiment, the first semiconductor layer 11 can include an n-type semiconductor material. For example, the first semiconductor layer 11 can include a semiconductor material such as InAlGaP, GaP, AlGaP, InGaP, AlP, or InP, and can include an n-type semiconductor material doped with a first conductive dopant such as Si, Ge, Se, or Sn. In an embodiment, the first semiconductor layer 11 can be n-InAlGaP doped with n-type Si.

[0092] The active layer 12 can be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. The same as the Figure 2 active layer 12 of Figure 5The active layer 12 can also emit light in a specific wavelength band by including a single quantum well structure material or a multi - quantum well structure material. For example, the active layer 12 can include materials such as AlGaP, InAlGaP, etc. Specifically, in the case where the active layer 12 has a structure in which quantum layers and well layers are alternately stacked in a multi - quantum well structure, the quantum layers can include materials such as AlGaP or InAlGaP, and the well layers can include materials such as GaP or AlInP. In an embodiment, by including InAlGaP as the quantum layer and AlInP as the well layer, the active layer 12 can emit red light having a central wavelength band of 620 nm to 750 nm.

[0093] Figure 5 The light - emitting element LD can include a cladding layer disposed adjacent to the active layer 12. For example, the third semiconductor layer 15 below the active layer 12 and the fourth semiconductor layer 16 above the active layer 12, which are disposed between the first semiconductor layer 11 and the second semiconductor layer 13, can be cladding layers.

[0094] The third semiconductor layer 15 can be disposed between the first semiconductor layer 11 and the active layer 12. The third semiconductor layer 15 can include an n - type semiconductor material similar to the first semiconductor layer 11. In an embodiment, the third semiconductor layer 15 can include n - AlInP, but the present disclosure is not limited thereto.

[0095] The fourth semiconductor layer 16 can be disposed between the active layer 12 and the second semiconductor layer 13. The fourth semiconductor layer 16 can include a p - type semiconductor material similar to the second semiconductor layer 13. In an embodiment, the fourth semiconductor layer 16 can include p - AlInP.

[0096] The fifth semiconductor layer 17 can be disposed between the fourth semiconductor layer 16 and the second semiconductor layer 13. The fifth semiconductor layer 17 can include a p - type semiconductor material similar to the second semiconductor layer 13 and the fourth semiconductor layer 16. According to an embodiment, the fifth semiconductor layer 17 can function to reduce the lattice constant difference between the fourth semiconductor layer 16 and the second semiconductor layer 13. For example, the fifth semiconductor layer 17 can be a tensile - strain barrier reduction (TSBR) layer. In an embodiment, the fifth semiconductor layer 17 can include p - GaInP, p - AlInP, p - InAlGaP, etc., but the present disclosure is not limited thereto.

[0097] The first electrode layer 14a and the second electrode layer 14b may be respectively disposed on the first semiconductor layer 11 and the second semiconductor layer 13. The first electrode layer 14a may be disposed on the upper surface of the second semiconductor layer 13, and the second electrode layer 14b may be disposed on the lower surface of the first semiconductor layer 11. According to an embodiment, at least one of the first electrode layer 14a and the second electrode layer 14b may be omitted. Each of the first electrode layer 14a and the second electrode layer 14b may include at least one of the materials in the electrode layer 14 that can be used for Figure 3 at least one of the materials in the electrode layer 14.

[0098] Figure 6 and Figure 7 FIG. is a perspective view showing a light-emitting element according to still another embodiment. In Figure 6 and Figure 7 , for ease of description, a part of the insulating film INF is omitted.

[0099] Referring to Figure 1 , Figure 2 , Figure 6 and Figure 7 , different from the light-emitting element LD of Figure 1 and Figure 2 , the light-emitting element LD of Figure 6 may be arranged in a vertically asymmetric shape in which the area of the first surface LDa of the first semiconductor layer 11 is different from the area of the second surface LDb of the second semiconductor layer 13. For example, the light-emitting element LD may be arranged in a truncated shape such as a truncated cone shape or a truncated polygon shape. That is, the light-emitting element LD may include a first surface LDa and a second surface LDb that are parallel to each other and have different areas, and may have an isosceles trapezoid shape in a cross-sectional view.

[0100] For example, as shown in Figure 6 , the first diameter Da of the first surface LDa of the light-emitting element LD may be smaller than the second diameter Db of the second surface LDb. Therefore, the side surface (e.g., the outer circumferential surface of the light-emitting element LD) between the first surface LDa and the second surface LDb of the light-emitting element LD may have a predetermined angle (e.g., an obtuse angle) with respect to the first surface LDa.

[0101] In another embodiment, as shown in Figure 7 , the first diameter Da of the first surface LDa of the light-emitting element LD may be larger than the second diameter Db of the second surface LDb. Therefore, the side surface (or the outer circumferential surface of the light-emitting element LD) of the light-emitting element LD may have a predetermined angle (e.g., an acute angle) with respect to the first surface LDa.

[0102] Meanwhile, Figure 6 and Figure 7The aspect ratio of the light-emitting element LD can be 1 or greater. That is, the length L of the light-emitting element LD can be greater than the first diameter Da of the first surface LDa and the second diameter Db of the second surface LDb.

[0103] In the following embodiments, the light-emitting element LD included in the display device can be at least one of the above-described Figures 1 to 7 light-emitting elements LD. In some embodiments, the display device can include Figures 1 to 5 the rod-shaped light-emitting element shown in Figure 6 and Figure 7 the truncated light-emitting element shown in. This will be described in detail later.

[0104] Figure 8 is a plan view schematically showing a display device according to an embodiment.

[0105] Referring to Figure 8 , the display device 1000 can include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. In addition, the substrate SUB can include a display area DA in which a plurality of pixels PXL are disposed to display an image, and a non-display area NDA other than the display area DA.

[0106] The substrate SUB can be formed of glass, quartz, ceramic, plastic, etc. In the case where the substrate SUB includes plastic, the substrate SUB can be a flexible substrate, but the present disclosure is not limited thereto. For example, the substrate SUB can include an organic material such as polyimide (PI).

[0107] The display area DA can be an area in which the pixels PXL are disposed. The non-display area NDA can be an area in which drivers SDV, DDV, and EDV for driving the pixels PXL and various lines connecting the pixels PXL to the drivers SDV, DDV, and EDV are disposed.

[0108] The display area DA can have various shapes. For example, the display area DA can be set to various shapes such as a closed polygon including sides formed by straight lines, a circle, an ellipse, etc. including sides formed by curves, and a semi-circle, a semi-ellipse, etc. including sides formed by straight lines and curves.

[0109] In the case where the display area DA includes a plurality of areas, each area can also be set to the above various shapes. In addition, the areas of the plurality of areas can be the same as or different from each other. In an embodiment of the present disclosure, a case where the display area DA is set to a quadrilateral shape having sides including straight lines is described as an embodiment.

[0110] The non-display area NDA can be provided on at least one side of the display area DA. In an embodiment, the non-display area NDA can surround the display area DA.

[0111] Pixels PXL can be provided in the display area DA of the substrate SUB. Each of the pixels PXL can include at least one light-emitting element LD connected to a scan line and a data line to be driven by corresponding scan signals and data signals.

[0112] Each of the pixels PXL can emit light of any one of red, green, and blue, but the present disclosure is not limited thereto. For example, each of the pixels PXL can emit light of one of cyan, magenta, yellow, and white.

[0113] Specifically, the pixel PXL can include a first pixel PXL1 (or first sub-pixel) that emits light of a first color, a second pixel PXL2 (or second sub-pixel) that emits light of a second color different from the first color, and a third pixel PXL3 (or third sub-pixel) that emits light of a third color different from the first and second colors. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 arranged adjacent to each other can configure one pixel unit PXU capable of emitting various colors of light.

[0114] According to an embodiment, the first pixel PXL1 can be a red pixel that emits red light, the second pixel PXL2 can be a green pixel that emits green light, and the third pixel PXL3 can be a blue pixel that emits blue light.

[0115] Pixels PXL can be provided in multiple numbers and can be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the arrangement of the pixels PXL is not particularly limited and can be arranged in various forms.

[0116] Drivers SDV, DDV, and EDV can provide signals to each of the pixels PXL through each line unit (not shown), and thus can control the driving of each of the pixels PXL. In Figure 8 For ease of description, the line unit is omitted.

[0117] Drivers SDV, DDV, and EDV can include a scan driver SDV that provides scan signals to the pixels PXL through scan lines, a data driver DDV that provides data signals to the pixels PXL through data lines, an emission control driver EDV that provides emission control signals to the pixels PXL through emission control lines, and a timing controller (not shown). The timing controller can control the scan driver SDV, the data driver DDV, and the emission control driver EDV.

[0118] According to an embodiment, the emission control driver EDV may be omitted. In addition, according to an embodiment, the timing controller may be integrated into the data driver DDV and may be set to one configuration.

[0119] The scan driver SDV may be disposed on one side of the substrate SUB and may be disposed in one direction (e.g., the second direction DR2). The scan driver SDV may be mounted on the substrate SUB as a separate part, but the present disclosure is not limited thereto. For example, the scan driver SDV may be directly formed on the substrate SUB. In addition, the scan driver SDV may be positioned outside the substrate SUB and may also be connected to each of the pixels PXL through a connection member.

[0120] The data driver DDV may be disposed on one side of the substrate SUB and may be disposed in a direction (e.g., the first direction DR1) intersecting the scan driver SDV. The data driver DDV may be mounted on the substrate SUB as a separate part, or may be positioned outside the substrate SUB and may be connected to each of the pixels PXL through a connection member.

[0121] The emission control driver EDV may be disposed on one side of the substrate SUB and may be disposed in the same direction (e.g., the second direction DR2) as the scan driver SDV. As Figure 8 shown, the emission control driver EDV may be disposed on the same side as the scan driver SDV, but the present disclosure is not limited thereto. For example, the emission control driver EDV may be disposed on a side different from the side where the scan driver SDV is disposed. The emission control driver EDV may be mounted on the substrate SUB as a separate part, but the present disclosure is not limited thereto. For example, the emission control driver EDV may be directly formed on the substrate SUB, or may be positioned outside the substrate SUB and may be connected to each of the pixels PXL through a connection member.

[0122] In an embodiment, each of the pixels PXL may be configured as an active pixel. However, the type, structure, and / or driving method of the pixel PXL applicable to the present disclosure are not particularly limited.

[0123] Figures 9a to 9c are circuit diagrams respectively showing pixels according to an embodiment. Specifically, Figures 9a to 9c shows an embodiment of a pixel configuring an active light-emitting display panel.

[0124] Referring to Figure 1 、 Figure 2 and Figure 9a ,the pixel PXL may include at least one light-emitting element LD and a driving circuit DC connected to the light-emitting element LD to drive the light-emitting element LD.

[0125] The first electrode (e.g., anode) of the light-emitting element LD can be connected to the first driving power supply VDD through the driving circuit DC, and the second electrode (e.g., cathode) of the light-emitting element LD can be connected to the second driving power supply VSS. The light-emitting element LD can emit light with a brightness corresponding to the amount of driving current controlled by the driving circuit DC.

[0126] Although only one light-emitting element LD is shown in Figure 9a , only one configuration is shown, and according to an embodiment, one pixel PXL may include a plurality of light-emitting elements LD. The plurality of light-emitting elements LD included in the pixel PXL can be connected in parallel and / or in series with each other. Figure 9a

[0127] The first driving power supply VDD and the second driving power supply VSS can have different potentials. For example, the difference between the potential of the first driving power supply VDD and the potential of the second driving power supply VSS can be equal to or greater than the threshold voltage of the light-emitting element LD or a larger voltage. That is, the voltage applied through the first driving power supply VDD can be greater than the voltage applied through the second driving power supply VSS.

[0128] According to an embodiment of the present disclosure, the driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0129] The first electrode of the first transistor M1 (driving transistor) can be connected to the first driving power supply VDD, and the second electrode of the first transistor M1 can be electrically connected to the first electrode (e.g., anode) of the light-emitting element LD. The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0130] The first electrode of the second transistor M2 (switching transistor) can be connected to the data line DL, and the second electrode of the second transistor M2 can be connected to the first node N1. Here, the first electrode and the second electrode of the second transistor M2 can be different electrodes. For example, when the first electrode is the source electrode, the second electrode can be the drain electrode. The gate electrode of the second transistor M2 can be connected to the scan line SL.

[0131] In the case of providing a scan signal with a voltage (e.g., gate turn-on voltage) through which the first transistor M1 can be turned on from the scan line SL, the second transistor M2 can be turned on to electrically connect the data line DL and the first node N1 to each other. At this time, the data signal of the corresponding frame can be provided to the data line DL, and thus the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0132] ​One electrode of the storage capacitor Cst may be connected to the first driving power supply VDD, and the other electrode of the storage capacitor Cst may be connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to the data signal supplied to the first node N1, and may hold the charging voltage until the data signal of the next frame is supplied.

[0133] For ease of description, Figure 9a a driving circuit DC having a relatively simple structure is shown, which includes a second transistor M2 for transmitting a data signal to each of the pixels PXL, a storage capacitor Cst for storing the data signal, and a first transistor M1 for supplying a driving current corresponding to the data signal to the light-emitting element LD.

[0134] However, the present disclosure is not limited thereto, and the structure of the driving circuit DC may be variously changed and implemented. For example, the driving circuit DC may further include other circuit elements, such as a compensation transistor for compensating the threshold voltage of the first transistor M1, an initialization transistor for initializing the first node N1, and / or an emission control transistor for controlling the emission time of the light-emitting element LD.

[0135] In addition, in Figure 9a both the first transistor M1 and the second transistor M2 included in the driving circuit DC are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor M1 and the second transistor M2 included in the driving circuit DC may be changed to an N-type transistor.

[0136] For example, as Figure 9b shown in, the first transistor M1 and the second transistor M2 of the driving circuit DC may be implemented as N-type transistors. Except for the change in the connection positions of some components (e.g., the storage capacitor Cst) due to the change in the transistor type, Figure 9b the configuration or operation of the driving circuit DC shown in Figure 9a may be similar to the configuration or operation of the driving circuit DC of

[0137] In addition, as another example, referring to Figure 9c , the pixel PXL may further include a third transistor M3 (sensing transistor).

[0138] The gate electrode of the third transistor M3 may be connected to the sense signal line SSL. One electrode of the third transistor M3 may be connected to the sense line SENL, and the other electrode of the third transistor M3 may be connected to the first electrode (e.g., anode) of the light-emitting element LD. During the sensing period, according to the sense signal provided to the sense signal line SSL, the third transistor M3 may transfer the voltage value of the first electrode of the light-emitting element LD to the sense line SENL. The voltage value transferred through the sense line SENL may be provided to an external circuit (e.g., a timing controller), and the external circuit may extract characteristic information (e.g., the threshold voltage of the first transistor M1, etc.) of the pixel PXL based on the provided voltage value. The extracted characteristic information may be used to convert image data so as to compensate for the characteristic deviation of the pixel PXL.

[0139] Figure 10 is a circuit diagram showing a pixel according to another embodiment.

[0140] Reference Figure 10 , a pixel PXL according to another embodiment of the present disclosure may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0141] The first electrode (e.g., anode) of the light-emitting element LD may be connected to the first transistor T1 via the sixth transistor T6, and the second electrode (e.g., cathode) of the light-emitting element LD may be connected to the second driving power supply VSS. The light-emitting element LD may emit light having a predetermined brightness corresponding to the amount of driving current provided from the first transistor T1.

[0142] One electrode of the first transistor T1 (driving transistor) may be connected to the first driving power supply VDD via the fifth transistor T5, and the other electrode of the first transistor T1 may be connected to the first electrode of the light-emitting element LD via the sixth transistor T6. In response to the voltage of the first node N1 as its gate electrode, the first transistor T1 may control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD.

[0143] The second transistor T2 (switching transistor) may be connected between the data line DL and one electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the scan line SL. When a scan signal having a gate-on voltage is provided to the scan line SL, the second transistor T2 may be turned on to electrically connect the data line DL and the said one electrode of the first transistor T1 to each other.

[0144] The third transistor T3 may be connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the scan line SL. When a scan signal with a gate-on voltage is provided to the scan line SL, the third transistor T3 may be turned on to electrically connect the other electrode of the first transistor T1 and the first node N1 to each other.

[0145] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be connected to the scan line SL-1. When a scan signal with a gate-on voltage is provided to the scan line SL-1, the fourth transistor T4 may be turned on to supply the voltage of the initialization power supply Vint to the first node N1. Here, the initialization power supply Vint may be set to a voltage lower than the voltage of the data signal.

[0146] The fifth transistor T5 may be connected between the first driving power supply VDD and the one electrode of the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the emission control line EL. When an emission control signal with a gate-on voltage is provided to the emission control line EL, the fifth transistor T5 may be turned on and may be turned off in other cases.

[0147] The sixth transistor T6 may be connected between the other electrode of the first transistor T1 and the first electrode of the light-emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the emission control line EL. When an emission control signal with a gate-on voltage is provided to the emission control line EL, the sixth transistor T6 may be turned on and may be turned off in other cases.

[0148] The seventh transistor T7 may be connected between the initialization power supply Vint and the first electrode (e.g., anode) of the light-emitting element LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SL+1. When a scan signal with a gate-on voltage is provided to the scan line SL+1, the seventh transistor T7 may be turned on to supply the voltage of the initialization power supply Vint to the first electrode of the light-emitting element LD.

[0149] Figure 10 The case where the gate electrode of the seventh transistor T7 is connected to the scan line SL+1 is shown. However, the technical scope of the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the gate electrode of the seventh transistor T7 may be connected to the scan line SL or the scan line SL-1. In this case, when a scan signal with a gate-on voltage is provided to the scan line SL or the scan line SL-1, the voltage of the initialization power supply Vint may be supplied to the anode of the light-emitting element LD via the seventh transistor T7.

[0150] The storage capacitor Cst may be connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to a data signal and a threshold voltage of the first transistor T1.

[0151] Meanwhile, in Figure 10 , all the transistors included in the driving circuit DC, for example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be changed to an N-type transistor.

[0152] Figure 11 is Figure 8 a schematic exploded perspective view of a display device. Figure 12 is Figure 11 a plan view of a display device. Figure 13 is a cross-sectional view of a display device taken along line A-A’ of Figure 12 . Figure 14 is a cross-sectional view of a display device taken along line B-B’ of Figure 12 . For ease of description, Figures 11 to 14 may be Figure 8 an enlarged and simplified view of a part of the display device 1000. Hereinafter, descriptions of content overlapping with that described with reference to Figure 8 are omitted.

[0153] Referring to Figures 11 to 14 , the display device 1000 may include a substrate SUB and a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 disposed on the substrate SUB. According to an embodiment, the display device 1000 may further include a channel wall CW.

[0154] The substrate SUB may include an upper surface SUBa and a lower surface SUBb. The upper surface SUBa and the lower surface SUBb of the substrate SUB may face each other and may be substantially parallel to each other. As an embodiment, the upper surface SUBa and the lower surface SUBb of the substrate SUB may have the same rectangular shape, and as a whole, the substrate SUB may have a rectangular parallelepiped shape. Hereinafter, “disposed on the upper surface SUBa of the substrate SUB” may mean disposed in the third direction DR3 with respect to the upper surface SUBa of the substrate SUB, and “disposed on the lower surface SUBb of the substrate SUB” may mean disposed in a direction opposite to the third direction DR3 with respect to the lower surface SUBb of the substrate SUB.

[0155] A first hole HL1, a second hole HL2, and a third hole HL3 passing through the substrate SUB may be formed in the substrate SUB. A first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3, which will be described later, may be disposed in the first hole HL1, the second hole HL2, and the third hole HL3.

[0156] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may respectively include the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, and may respectively emit light of different colors. As described above, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may configure one pixel unit PXU capable of expressing various colors. In the present embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be Figure 6 the light-emitting element LD, but the present disclosure is not limited thereto.

[0157] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be sequentially arranged on the substrate SUB. For example, in the case where the display device 1000 has a stripe-type pixel arrangement, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be sequentially arranged in a first direction DR1, and the same pixels may be arranged in a second direction DR2. The arrangement of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is not limited thereto, and the pixels may be arranged in various methods such as the PenTile method.

[0158] Since the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures, the first pixel PXL1 is specifically described, and regarding the second pixel PXL2 and the third pixel PXL3, the points different from the first pixel PXL1 are mainly described.

[0159] The first pixel PXL1 may include a first emission region LA1 and a first circuit region CA1 defined on the substrate SUB. The first emission region LA1 may be a region where the first light-emitting element LD1 is disposed, and the first circuit region CA1 may be a region where lines and circuit elements for providing drive signals to the first light-emitting element LD1 are disposed. The shapes and areas of the first emission region LA1 and the first circuit region CA1 may be variously changed as needed.

[0160] In the first emission region LA1, the substrate SUB may include a first hole HL1 in which a first light-emitting element LD1 is disposed. As described above, the first hole HL1 may completely penetrate the substrate SUB. A plurality of first holes HL1 may be formed in the first emission region LA1. According to an embodiment, the first hole HL1 may be formed in substantially the same shape as the first light-emitting element LD1, but the present disclosure is not limited thereto.

[0161] The first light-emitting element LD1 may be disposed in the first hole HL1, and at least a part of the first light-emitting element LD1 may be inserted into the substrate SUB through the first hole HL1. For example, the first light-emitting element LD1 may be inserted and fixed into the first hole HL1 according to a pressure difference between the upper part and the lower part of the substrate SUB.

[0162] The second pixel PXL2 may include a second emission region LA2 and a second circuit region CA2. In the second emission region LA2, the substrate SUB may include a second hole HL2 in which a second light-emitting element LD2 is disposed. According to an embodiment, the diameter of the second hole HL2 may be smaller than the diameter of the first hole HL1. In addition, the second hole HL2 may be formed in substantially the same shape as the second light-emitting element LD2.

[0163] The second light-emitting element LD2 may be disposed in the second hole HL2. According to an embodiment, the size (or diameter) of the second light-emitting element LD2 may be smaller than the size (or diameter) of the first light-emitting element LD1, and may be inserted into the substrate SUB after the first light-emitting element LD1 is disposed.

[0164] The third pixel PXL3 may include a third emission region LA3 and a third circuit region CA3. In the third emission region LA3, the substrate SUB may include a third hole HL3 in which a third light-emitting element LD3 is disposed. According to an embodiment, the diameter of the third hole HL3 may be smaller than the diameters of the first hole HL1 and the second hole HL2. In addition, the third hole HL3 may be formed in substantially the same shape as the third light-emitting element LD3.

[0165] The third light-emitting element LD3 may be disposed in the third hole HL3. According to an embodiment, the size (or diameter) of the third light-emitting element LD3 may be smaller than the sizes (or diameters) of the first light-emitting element LD1 and the second light-emitting element LD2, and may be inserted into the substrate SUB after the first light-emitting element LD1 and the second light-emitting element LD2 are disposed.

[0166] Figures 11 to 14A structure is shown in which one of the light-emitting elements LD1, LD2, and LD3 is disposed in each of the emission regions LA1, LA2, and LA3, but the present disclosure is not limited thereto. For example, at least two of the light-emitting elements LD1, LD2, and LD3 may be respectively disposed in each of the emission regions LA1, LA2, and LA3. In addition, the number of the light-emitting elements LD1, LD2, and LD3 disposed in each of the emission regions LA1, LA2, and LA3 may be different from each other. In an embodiment, the number of the third light-emitting element LD3 disposed in the third emission region LA3 may be greater than the number of the first light-emitting element LD1 disposed in the first emission region LA1, but the present disclosure is not limited thereto.

[0167] As Figure 13 shown, in the first emission region LA1, the first pixel electrode AE1 may be disposed on the upper surface SUBa of the substrate SUB, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB. The first pixel electrode AE1 may be disposed on the first light-emitting element LD1 and may be electrically connected to the second surface LD1b of the first light-emitting element LD1. In addition, a portion of the common electrode CE may be disposed on the first light-emitting element LD1 and may be electrically connected to the first surface LD1a of the first light-emitting element LD1. According to an embodiment, the first pixel electrode AE1 may contact the second surface LD1b of the first light-emitting element LD1, and the common electrode CE may contact the first surface LD1a of the first light-emitting element LD1. One of the first pixel electrode AE1 and the common electrode CE may be an anode, and the other may be a cathode.

[0168] The first pixel electrode AE1 and the common electrode CE may provide a driving signal to the first light-emitting element LD1 in response to a scan signal and a data signal, and the first light-emitting element LD1 may emit light having a luminance corresponding to the provided driving signal.

[0169] When further combined with Figure 9a the description, each of the first pixel electrode AE1 and the common electrode CE may be electrically connected to any one of the driving circuit DC and the second driving power supply VSS through a separate connection line or connection member. For example, the first pixel electrode AE1 may be electrically connected to the driving circuit DC, and the common electrode CE may be electrically connected to the second driving power supply VSS. Accordingly, the first pixel electrode AE1 and the common electrode CE may provide a driving signal to the light-emitting element LD.

[0170] The first pixel electrode AE1 and the common electrode CE may be formed of a conductive material. In an embodiment, each of the first pixel electrode AE1 and the common electrode CE may include a metal such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof. In another embodiment, each of the first pixel electrode AE1 and the common electrode CE may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In an embodiment, the first pixel electrode AE1 may include a transparent conductive material, and the common electrode CE may include a conductive material having a constant reflectance.

[0171] The light emitted from the first light-emitting element LD1 may be emitted in the third direction DR3 and in the direction opposite to the third direction DR3. In the case where the first pixel electrode AE1 includes a transparent conductive material, the light emitted from the first light-emitting element LD1 in the third direction DR3 may pass through the first pixel electrode AE1 and travel. Further, in the case where the common electrode CE includes a conductive material having a constant reflectance, the light emitted from the first light-emitting element LD1 in the direction opposite to the third direction DR3 may be reflected by the common electrode CE and may travel in the third direction DR3, and the light output efficiency of the display device 1000 may be improved.

[0172] The plurality of circuit elements configuring the driving circuit (e.g., Figure 9a the DC) of the first pixel PXL1 may be provided in the first circuit region CA1. For example, at least one transistor T may be provided in the first circuit region CA1. Here, the transistor T may be Figure 9a the first transistor M1, but the present disclosure is not limited thereto.

[0173] The first insulating layer INS1 may be provided on the upper surface SUBa of the substrate SUB. For example, the first insulating layer INS1 may be a buffer layer. The first insulating layer INS1 may be completely formed on the substrate SUB and may cover the first pixel electrode AE1. The first insulating layer INS1 may provide a space in the first circuit region CA1 where the transistor T is to be provided. The first insulating layer INS1 may prevent impurities from diffusing into the circuit elements provided on the substrate SUB. The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material, but the present disclosure is not limited thereto. The first insulating layer INS1 may be provided as a single layer, or may include a multilayer structure according to an embodiment. In the case where the first insulating layer INS1 includes a multilayer structure, the first insulating layer INS1 may include an organic insulating layer and an inorganic insulating layer stacked alternately.

[0174] In a first circuit region CA1, a transistor T may be disposed on a first insulating layer INS1. The transistor T may include an active layer ACT, a gate electrode GE, a first transistor electrode TET1, and a second transistor electrode TET2.

[0175] The active layer ACT may be disposed on the first insulating layer INS1. The active layer ACT may include a first region connected to the first transistor electrode TET1, a second region connected to the second transistor electrode TET2, and a channel region positioned between the first region and the second region. One of the first region and the second region may be a source region, and the other may be a drain region.

[0176] The active layer ACT may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the active layer ACT may include an intrinsic semiconductor that is a semiconductor pattern without doped impurities, and each of the first region and the second region of the active layer ACT may be a semiconductor pattern doped with a predetermined impurity.

[0177] A second insulating layer INS2 may be disposed on the active layer ACT. For example, the second insulating layer INS2 may be a gate insulating layer. The second insulating layer INS2 may completely cover the active layer ACT. That is, the active layer ACT may be disposed between the first insulating layer INS1 and the second insulating layer INS2. The second insulating layer INS2 may be an inorganic insulating layer including an inorganic material, but the present disclosure is not limited thereto.

[0178] The gate electrode GE may be disposed on the second insulating layer INS2. The gate electrode GE may overlap at least a part of the active layer ACT. The gate electrode GE may be insulated from the active layer ACT through the second insulating layer INS2.

[0179] A third insulating layer INS3 may be disposed on the gate electrode GE. For example, the third insulating layer INS3 may be an interlayer insulating layer. The third insulating layer INS3 may completely cover the gate electrode GE. That is, the gate electrode GE may be disposed between the second insulating layer INS2 and the third insulating layer INS3. The third insulating layer INS3 may be an inorganic insulating layer including an inorganic material, but the present disclosure is not limited thereto.

[0180] The first transistor electrode TET1 and the second transistor electrode TET2 may be disposed on the third insulating layer INS3. The first transistor electrode TET1 and the second transistor electrode TET2 may be electrically connected to the active layer ACT. For example, the first transistor electrode TET1 and the second transistor electrode TET2 may contact the first region and the second region of the active layer ACT through contact holes penetrating the second insulating layer INS2 and the third insulating layer INS3, respectively. According to an embodiment, the first transistor electrode TET1 or the second transistor electrode TET2 may be omitted, or may be integrally formed with the first region or the second region of the active layer ACT.

[0181] Any one of the first transistor electrode TET1 and the second transistor electrode TET2 may be electrically connected to the first pixel electrode AE1. For example, at least a portion of the first transistor electrode TET1 may extend toward the first emission region LA1, and may be electrically connected to the first pixel electrode AE1 through a contact hole CNT or a connection member penetrating the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. Accordingly, the transistor T disposed in the first circuit region CA1 may be electrically connected to the first light-emitting element LD1, and a driving signal for driving the first light-emitting element LD1 to emit light may be provided.

[0182] Similarly, as Figure 14 shown, in the second emission region LA2, the second pixel electrode AE2 may be disposed on the upper surface SUBa of the substrate SUB, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB. The second pixel electrode AE2 may be disposed on the second light-emitting element LD2, and may be electrically connected to the second surface LD2b of the second light-emitting element LD2. In addition, the common electrode CE may be disposed on the second light-emitting element LD2, and may be electrically connected to the first surface LD2a of the second light-emitting element LD2. According to an embodiment, the second pixel electrode AE2 may contact the second surface LD2b of the second light-emitting element LD2, and the common electrode CE may contact the first surface LD2a of the second light-emitting element LD2.

[0183] In addition, in the third emission region LA3, the third pixel electrode AE3 may be disposed on the upper surface SUBa of the substrate SUB, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB. The third pixel electrode AE3 may be disposed on the third light-emitting element LD3 and may be electrically connected to the second surface LD3b of the third light-emitting element LD3. In addition, the common electrode CE may be disposed on the third light-emitting element LD3 and may be electrically connected to the first surface LD3a of the third light-emitting element LD3. According to an embodiment, the third pixel electrode AE3 may contact the second surface LD3b of the third light-emitting element LD3, and the common electrode CE may contact the first surface LD3a of the third light-emitting element LD3.

[0184] According to an embodiment, the common electrode CE may be continuously disposed on the lower surface SUBb of the substrate SUB in the first direction DR1 and may be electrically connected to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. That is, the common electrode CE may provide the same signal (or voltage) to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0185] Meanwhile, for ease of description, in Figure 14 the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 that are sequentially stacked on the upper surface SUBa of the substrate SUB are omitted.

[0186] As Figure 14 shown, the first light-emitting element LD1 of the first pixel PXL1 may include a first surface LD1a and a second surface LD1b that face each other, and may include a side surface (or outer circumferential surface) between the first surface LD1a and the second surface LD1b. The diameter Da1 of the first surface LD1a may be smaller than the diameter Db1 of the second surface LD1b. Therefore, the side surface of the first light-emitting element LD1 may form a predetermined angle with the first surface LD1a, and the angle may be an obtuse angle.

[0187] The first hole HL1 may include a first sidewall SW1 (or inner circumferential surface), and the first sidewall SW1 may form a predetermined angle with respect to the lower surface SUBb (or through surface) of the substrate SUB. The angle formed by the first sidewall SW1 and the lower surface SUBb of the substrate SUB may be the same as the angle formed by the side surface of the first light-emitting element LD1 and the first surface LD1a. Therefore, the shape of the first hole HL1 may be substantially the same as the shape of the first light-emitting element LD1, and at least a part of the side surface of the first light-emitting element LD1 may contact the first sidewall SW1 of the first hole HL1.

[0188] In addition, the second light-emitting element LD2 of the second pixel PXL2 may include a first surface LD2a and a second surface LD2b that face each other, and may include a side surface (or outer circumferential surface) between the first surface LD2a and the second surface LD2b. The diameter Da2 of the first surface LD2a may be smaller than the diameter Db2 of the second surface LD2b. Accordingly, the side surface of the second light-emitting element LD2 may form a predetermined angle with the first surface LD2a, and the angle may be an obtuse angle.

[0189] The diameter Da2 of the first surface LD2a of the second light-emitting element LD2 may be smaller than the diameter Da1 of the first surface LD1a of the first light-emitting element LD1. In addition, the diameter Db2 of the second surface LD2b of the second light-emitting element LD2 may be smaller than the diameter Db1 of the second surface LD1b of the first light-emitting element LD1. According to an embodiment, the diameter Db2 of the second surface LD2b of the second light-emitting element LD2 may be smaller than the diameter Da1 of the first surface LD1a of the first light-emitting element LD1.

[0190] The second hole HL2 may include a second sidewall SW2, and the second sidewall SW2 may form a predetermined angle with the lower surface SUBb (or through surface) of the substrate SUB. The angle formed by the second sidewall SW2 and the lower surface SUBb of the substrate SUB may be the same as the angle formed by the side surface of the second light-emitting element LD2 and the first surface LD2a. Accordingly, the shape of the second hole HL2 may be substantially the same as the shape of the second light-emitting element LD2, and at least a portion of the side surface of the second light-emitting element LD2 may contact the second sidewall SW2 of the second hole HL2.

[0191] In addition, the third light-emitting element LD3 of the third pixel PXL3 may include a first surface LD3a and a second surface LD3b that face each other, and may include a side surface (or outer circumferential surface) between the first surface LD3a and the second surface LD3b. The diameter Da3 of the first surface LD3a may be smaller than the diameter Db3 of the second surface LD3b. Accordingly, the side surface of the third light-emitting element LD3 may form a predetermined angle with the first surface LD3a, and the angle may be an obtuse angle.

[0192] The diameter Da3 of the first surface LD3a of the third light-emitting element LD3 may be smaller than the diameter Da2 of the first surface LD2a of the second light-emitting element LD2. In addition, the diameter Db3 of the second surface LD3b of the third light-emitting element LD3 may be smaller than the diameter Db2 of the second surface LD2b of the second light-emitting element LD2. According to an embodiment, the diameter Db3 of the second surface LD3b of the third light-emitting element LD3 may be smaller than the diameter Da2 of the first surface LD2a of the second light-emitting element LD2.

[0193] The third hole HL3 may include a third sidewall SW3, and the third sidewall SW3 may form a predetermined angle with respect to the lower surface SUBb (or the through surface) of the substrate SUB. The angle formed by the third sidewall SW3 and the lower surface SUBb of the substrate SUB may be the same as the angle formed by the side surface and the first surface LD3a of the third light-emitting element LD3. Accordingly, the shape of the third hole HL3 may be substantially the same as the shape of the third light-emitting element LD3, and at least a portion of the side surface of the third light-emitting element LD3 may contact the third sidewall SW3 of the third hole HL3.

[0194] In an embodiment, the first sidewall SW1 of the first hole HL1, the second sidewall SW2 of the second hole HL2, and the third sidewall SW3 of the third hole HL3 may form the same angle with respect to the lower surface SUBb of the substrate SUB, but the present disclosure is not limited thereto. In another embodiment, at least two of the first sidewall SW1, the second sidewall SW2, and the third sidewall SW3 may form different angles with respect to the lower surface SUBb of the substrate SUB.

[0195] Meanwhile, as Figure 11 and Figure 13 shown, a channel wall CW may be formed on the lower surface SUBb of the substrate SUB. The channel wall CW may be formed to extend in a first direction DR1. In addition, a plurality of channel walls CW may be formed. In this case, the plurality of channel walls CW may be arranged in a second direction DR2.

[0196] The channel wall CW may not overlap with the first emission region LA1, the second emission region LA2, and the third emission region LA3 in a third direction DR3. Specifically, the channel wall CW may not overlap with the first hole HL1, the second hole HL2, and the third hole HL3 of the substrate SUB. According to an embodiment, at least a portion of the channel wall CW may overlap with the first circuit region CA1, the second circuit region CA2, and the third circuit region CA3.

[0197] A microchannel MC may be formed between the plurality of channel walls CW. In the manufacturing process of the display device 1000, a fluid may flow through the microchannel MC. The pressure difference between the upper and lower portions of the substrate SUB may be adjusted according to the state (e.g., rate, etc.) of the fluid flowing through the microchannel MC, and the pressure on the lower side of the substrate SUB may be adjusted to be lower than the pressure on the upper side of the substrate SUB so as to dispose the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 on the substrate SUB. A method of disposing the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 on the substrate SUB will be described later with reference to Figures 21 to 27 describe a method of disposing the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 on the substrate SUB.

[0198] As described above, the light-emitting elements LD1, LD2, and LD3 of each of the pixels PXL1, PXL2, and PXL3 can be respectively disposed in the holes HL1, HL2, and HL3 of the substrate SUB. Since the light-emitting elements LD1, LD2, and LD3 are disposed in the vertical direction on the substrate SUB, an area in which the light-emitting elements LD1, LD2, and LD3 are disposed can be widely ensured, and thus it can be advantageous in realizing a high-resolution display device. In addition, since the light emitted from the light-emitting elements LD1, LD2, and LD3 can be directly emitted in the third direction DR3, the light output efficiency of the display device 1000 can be improved.

[0199] Hereinafter, other embodiments of the display device are described. In the following embodiments, components identical to those of the foregoing embodiments are denoted by the same reference numerals, and their descriptions are omitted or simplified, and different points are mainly described.

[0200] Figures 15 to 20 is a cross-sectional view of a display device according to various embodiments, and specifically, is a cross-sectional view corresponding to the line B-B' of Figure 12

[0201] Referring to Figure 15 , the display device 1000_1 may include a substrate SUB_1 and first pixel PXL1, second pixel PXL2, and third pixel PXL3 disposed on the substrate SUB_1.

[0202] First hole HL1_1, second hole HL2_1, and third hole HL3_1 passing through the substrate SUB_1 may be formed in the substrate SUB_1. The first hole HL1_1 may include a first sidewall SW1 (or inner circumferential surface), and the first sidewall SW1 may be perpendicular to the lower surface SUBb of the substrate SUB_1. Similar to the first hole HL1_1, the second hole HL2_1 and the third hole HL3_1 may also include a second sidewall SW2 and a third sidewall SW3 perpendicular to the lower surface SUBb of the substrate SUB_1, respectively.

[0203] The first light-emitting element LD1 may be disposed in the first hole HL1_1. Here, the diameter of the second surface LD1b of the first light-emitting element LD1 may be larger than the diameter of the first hole HL1_1. Therefore, the first light-emitting element LD1 may not be completely inserted into the first hole HL1_1, and only a part of the first light-emitting element LD1 may be disposed in the first hole HL1_1. Another part of the first light-emitting element LD1 not disposed in the first hole HL1_1 may be exposed to the outside of the substrate SUB_1 (or protrude toward the outside of the substrate SUB_1).

[0204] Similarly, the diameter of the second surface LD2b of the second light-emitting element LD2 may be greater than the diameter of the second hole HL2_1. Therefore, only a part of the second light-emitting element LD2 may be disposed in the second hole HL2_1, and another part of the second light-emitting element LD2 that is not disposed in the second hole HL2_1 may be exposed to the outside of the substrate SUB_1 (or protrude toward the outside of the substrate SUB_1).

[0205] In addition, the diameter of the second surface LD3b of the third light-emitting element LD3 may be greater than the diameter of the third hole HL3_1. Therefore, only a part of the third light-emitting element LD3 may be disposed in the third hole HL3_1, and another part of the third light-emitting element LD3 that is not disposed in the third hole HL3_1 may be exposed to the outside of the substrate SUB_1 (or protrude toward the outside of the substrate SUB_1).

[0206] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the upper surface SUBa of the substrate SUB_1, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB_1.

[0207] Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may cover a part of the light-emitting element LD that protrudes toward the outside of the substrate SUB_1, and may be formed with a substantially uniform thickness along the surfaces of the substrate SUB_1 and the light-emitting element LD.

[0208] The common electrode CE may contact the first surfaces LD1a, LD2a, and LD3a of the corresponding first light-emitting element LD1, second light-emitting element LD2, and third light-emitting element LD3. Since the light-emitting element LD is not completely inserted into the holes HL1_1, HL2_1, and HL3_1, the common electrode CE may fill a part of the holes HL1_1, HL2_1, and HL3_1.

[0209] According to an embodiment, a filler FL for filling the empty space between the light-emitting element LD and the side walls SW1, SW2, and SW3 of the holes HL1_1, HL2_1, and HL3_1 may also be provided, but the present disclosure is not limited thereto. For example, an air layer may exist between the light-emitting element LD and the holes HL1_1, HL2_1, and HL3_1. The filler FL may be formed by including an organic material, but the material of the filler FL is not limited thereto.

[0210] Reference Figure 16 , the display device 1000_2 may include a substrate SUB_2 and first pixels PXL1, second pixels PXL2, and third pixels PXL3 disposed on the substrate SUB_2.

[0211] The first hole HL1_2, the second hole HL2_2, and the third hole HL3_2 passing through the substrate SUB_2 may be formed in the substrate SUB_2. The first hole HL1_2 may include a first sidewall SW1_2 (or an inner circumferential surface). Here, the first sidewall SW1_2 may include an inclined surface SW1a having a predetermined angle with respect to the lower surface SUBb of the substrate SUB_2 and a vertical surface SW1b perpendicular to the lower surface SUBb of the substrate SUB_2.

[0212] Similar to the first hole HL1_2, the second hole HL2_2 may include a second sidewall SW2_2 including an inclined surface SW2a and a vertical surface SW2b, and the third hole HL3_2 may include a third sidewall SW3_2 including an inclined surface SW3a and a vertical surface SW3b.

[0213] The first light-emitting element LD1 may be disposed in the first hole HL1_2. According to an embodiment, a side surface of the first light-emitting element LD1 may contact the inclined surface SW1a, but may not contact the vertical surface SW1b.

[0214] Similarly, the second light-emitting element LD2 may be disposed in the second hole HL2_2, and a side surface of the second light-emitting element LD2 may contact the inclined surface SW2a, but may not contact the vertical surface SW2b. In addition, the third light-emitting element LD3 may be disposed in the third hole HL3_2, and a side surface of the third light-emitting element LD3 may contact the inclined surface SW3a, but may not contact the vertical surface SW3b.

[0215] Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the upper surface SUBa of the substrate SUB_2, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB_2.

[0216] According to an embodiment, a filler FL for filling the blank spaces between the light-emitting elements LD and the sidewalls SW1_2, SW2_2, and SW3_2 of the holes HL1_2, HL2_2, and HL3_2 may also be provided. In this case, the filler FL may be disposed between the light-emitting element LD and the vertical surfaces SW1b, SW2b, and SW3b.

[0217] As described above, the light-emitting element LD is not limited to Figure 6 the truncated light-emitting element LD. In Figure 17 and Figure 18 the embodiments, the light-emitting element LD_3 may be Figure 1 the rod-shaped light-emitting element LD.

[0218] Refer to Figure 17, the display device 1000_3 may include a substrate SUB and a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 disposed on the substrate SUB.

[0219] Each of the pixels PXL1, PXL2, and PXL3 may include a rod-shaped light-emitting element LD_3. The first pixel PXL1 may include a first light-emitting element LD1_3, the second pixel PXL2 may include a second light-emitting element LD2_3, and the third pixel PXL3 may include a third light-emitting element LD3_3.

[0220] A first hole HL1, a second hole HL2, and a third hole HL3 passing through the substrate SUB may be formed in the substrate SUB. The holes HL1, HL2, and HL3 may include sidewalls SW1, SW2, and SW3 having a predetermined angle with respect to the lower surface SUBb of the substrate SUB, respectively.

[0221] The first light-emitting element LD1_3 may be disposed in the first hole HL1. The diameter of the first surface LD1a of the first light-emitting element LD1_3 may be larger than the diameter of the lower through surface of the first hole HL1. In addition, the diameter of the second surface LD1b of the first light-emitting element LD1_3 may be smaller than the diameter of the upper through surface of the first hole HL1. Accordingly, a part of the first light-emitting element LD1_3 may be disposed in the first hole HL1, and another part of the first light-emitting element LD1_3 may protrude to the outside of the substrate SUB.

[0222] Similarly, the second light-emitting element LD2_3 may be disposed in the second hole HL2, and the third light-emitting element LD3_3 may be disposed in the third hole HL3. A part of the second light-emitting element LD2_3 may be disposed in the second hole HL2, and another part of the second light-emitting element LD2_3 may protrude to the outside of the substrate SUB. In addition, a part of the third light-emitting element LD3_3 may be disposed in the third hole HL3, and another part of the third light-emitting element LD3_3 may protrude to the outside of the substrate SUB.

[0223] A first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3 may be disposed on the upper surface SUBa of the substrate SUB, and a common electrode CE may be disposed on the lower surface SUBb of the substrate SUB.

[0224] Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may cover the part of the light-emitting element LD_3 protruding to the outside of the substrate SUB_3, and may be formed with a substantially uniform thickness along the surfaces of the substrate SUB_3 and the light-emitting element LD_3.

[0225] The common electrode CE can be electrically connected to the first surfaces LD1a, LD2a, and LD3a of the corresponding first light-emitting element LD1_3, second light-emitting element LD2_3, and third light-emitting element LD3_3. According to an embodiment, the common electrode CE can contact the first surfaces LD1a, LD2a, and LD3a. Since the light-emitting element LD_3 is not fully inserted into the holes HL1, HL2, and HL3, the common electrode CE can fill a part of the holes HL1, HL2, and HL3.

[0226] According to an embodiment, a filler FL for filling the blank space between the light-emitting element LD_3 and the side walls SW1, SW2, and SW3 of the holes HL1, HL2, and HL3 can also be provided.

[0227] Reference Figure 18 , the display device 1000_4 can include a substrate SUB_4 and a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 provided on the substrate SUB_4.

[0228] Each of the pixels PXL1, PXL2, and PXL3 can include a rod-shaped light-emitting element LD_4. The first pixel PXL1 can include a first light-emitting element LD1_4, the second pixel PXL2 can include a second light-emitting element LD2_4, and the third pixel PXL3 can include a third light-emitting element LD3_4.

[0229] First holes HL1_4, second holes HL2_4, and third holes HL3_4 passing through the substrate SUB_4 can be formed in the substrate SUB_4. The holes HL1_4, HL2_4, and HL3_4 can respectively include side walls SW1, SW2, and SW3 perpendicular to the lower surface SUBb of the substrate SUB_4. In addition, the substrate SUB_4 can further include protrusions PT1, PT2, and PT3 formed in the corresponding holes HL1_4, HL2_4, and HL3_4. The protrusions PT1, PT2, and PT3 can be formed on one side of the lower surface SUBb of the substrate SUB_4 and can protrude from the corresponding side walls SW1, SW2, and SW3.

[0230] As an embodiment, the protrusions PT1, PT2, and PT3 can be configured to be integrally formed with the substrate SUB_4. For example, in the process of forming the holes HL1_4, HL2_4, and HL3_4 in the substrate SUB_4, the protrusions PT1, PT2, and PT3 can be the parts that are retained and not removed from the substrate SUB_4. However, the present disclosure is not limited thereto, and in another embodiment, the protrusions PT1, PT2, and PT3 can be formed separately from the substrate SUB_4.

[0231] The first light-emitting element LD1_4 can be disposed in the first hole HL1_4. The first protrusion PT1 can contact a portion of the first surface LD1a of the first light-emitting element LD1_4. Another portion of the first surface LD1a of the first light-emitting element LD1_4 that does not contact the first protrusion PT1 can be exposed to the outside. A portion of the first light-emitting element LD1_4 including the second surface LD1b can be exposed to the outside of the substrate SUB_4.

[0232] During the process of disposing the first light-emitting element LD1_4 in the first hole HL1_4, the first protrusion PT1 can prevent the first light-emitting element LD1_4 from separating toward the lower surface SUBb of the substrate SUB_4.

[0233] Similarly, the second light-emitting element LD2_4 can be disposed in the second hole HL2_4, and the third light-emitting element LD3_4 can be disposed in the third hole HL3_4. A second protrusion PT2 of the second hole HL2_4 can contact a portion of the first surface LD2a of the second light-emitting element LD2_4, and a third protrusion PT3 of the third hole HL3_4 can contact a portion of the first surface LD3a of the third light-emitting element LD3_4.

[0234] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be disposed on the upper surface SUBa of the substrate SUB_4, and the common electrode CE can be disposed on the lower surface SUBb of the substrate SUB_4.

[0235] Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can cover a portion of the light-emitting element LD_4 protruding to the outside of the substrate SUB_4, and can be formed with a substantially uniform thickness along the surfaces of the substrate SUB_4 and the light-emitting element LD_4.

[0236] The common electrode CE can be electrically connected to the first surfaces LD1a, LD2a, and LD3a of the corresponding first light-emitting element LD1_4, second light-emitting element LD2_4, and third light-emitting element LD3_4. According to an embodiment, the common electrode CE can contact the first surfaces LD1a, LD2a, and LD3a. Since the light-emitting element LD_4 is not completely inserted into the holes HL1_4, HL2_4, and HL3_4, the common electrode CE can fill a portion of the holes HL1_4, HL2_4, and HL3_4.

[0237] The above-described embodiment shows a structure in which the thickness of the substrate is the same as the length of the light-emitting element. However, the thickness of the substrate and the length of the light-emitting element are not limited to the above case.

[0238] As an embodiment, as Figure 19As shown in the figure, the display device 1000_5 may include a substrate SUB_5 and a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 disposed on the substrate SUB_5. Here, the thickness Ha of the substrate SUB_5 may be less than the length L of the light-emitting element LD of each of the pixels PXL1, PXL2, and PXL3.

[0239] Accordingly, a portion of each of the light-emitting elements LD may protrude outside the substrate SUB_5. For example, a portion of the first light-emitting element LD1 including the first surface LD1a and a portion of the first light-emitting element LD1 including the second surface LD1b may protrude outside the substrate SUB_5.

[0240] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the upper surface SUBa of the substrate SUB_5, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB_5. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed along the upper surface SUBa of the substrate SUB_5 and the surfaces of the second surfaces LD1b, LD2b, and LD3b of the light-emitting elements LD, and the common electrode CE may be continuously disposed along the lower surface SUBb of the substrate SUB_5 and the surfaces of the first surfaces LD1a, LD2a, and LD3a of the light-emitting elements LD.

[0241] In another embodiment, as Figure 20 shown in the figure, the display device 1000_6 may include a substrate SUB_6 and a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 disposed on the substrate SUB_6. Here, the thickness Hb of the substrate SUB_6 may be greater than the length L of the light-emitting element LD of each of the pixels PXL1, PXL2, and PXL3.

[0242] Accordingly, each of the light-emitting elements LD may be disposed within the substrate SUB_6. For example, compared to the lower surface SUBb of the substrate SUB_6, the first surface LD1a of the first light-emitting element LD1 may be positioned in the upward direction (e.g., in the third direction DR3), and compared to the upper surface SUBa of the substrate SUB_6, the second surface LD1b of the first light-emitting element LD1 may be positioned in the downward direction (e.g., in the direction opposite to the third direction DR3).

[0243] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the upper surface SUBa of the substrate SUB_6, and the common electrode CE may be disposed on the lower surface SUBb of the substrate SUB_6. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed along the upper surface SUBa of the substrate SUB_6 and the surfaces among the second surfaces LD1b, LD2b, and LD3b of the light-emitting element LD, and may fill part of each of the holes HL1, HL2, and HL3. In addition, the common electrode CE may be continuously disposed along the lower surface SUBb of the substrate SUB_6 and the surfaces among the first surfaces LD1a, LD2a, and LD3a of the light-emitting element LD, and may fill part of the holes HL1, HL2, and HL3.

[0244] Figures 21 to 27 are a perspective view and a cross-sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure. Specifically, Figures 21 to 27 may be a view showing a method of manufacturing Figures 11 to 14 the display device shown in

[0245] Combined with Figures 11 to 14 the embodiments described Figures 21 to 27 to sequentially describe a method of manufacturing a display device according to an embodiment.

[0246] First, as shown in Figure 21 and Figure 22 a first mixed solution MX1 including a first light-emitting element LD1 may be provided on a substrate SUB.

[0247] The substrate SUB may include a first hole HL1 formed in a first emission region LA1, a second hole HL2 formed in a second emission region LA2, and a third hole HL3 formed in a third emission region LA3. Here, the first hole HL1, the second hole HL2, and the third hole HL3 may penetrate the substrate SUB.

[0248] The first mixed solution MX1 may be completely dispersed on the upper surface SUBa of the substrate SUB. The shape of the first hole HL1 formed in the substrate SUB may be the same as the shape of the first light-emitting element LD1. That is, the diameter of the first hole HL1 may be substantially the same as the diameter of the first light-emitting element LD1. The sizes of the second hole HL2 and the third hole HL3 formed in the substrate SUB may be smaller than the size of the first light-emitting element LD1.

[0249] After the first mixture MX1 is dispersed on the substrate SUB, in order to set and fix the first light-emitting element LD1 in the first hole HL1, the upper-side pressure and the lower-side pressure of the substrate SUB can be adjusted. Specifically, the upper-side pressure (or the first pressure) of the substrate SUB can be adjusted to be greater than the lower-side pressure (or the second pressure) of the substrate SUB.

[0250] In order to adjust the lower-side pressure of the substrate SUB to be low, the channel wall CW formed under the substrate SUB and the microchannel MC formed between the channel walls CW can be used. For example, by flowing a fluid through the microchannel MC at a high rate, the lower-side pressure of the substrate SUB can be adjusted to be low. Thus, a pressure difference F can be generated between the upper part and the lower part of the substrate SUB, and the first light-emitting element LD1 can be inserted into the first hole HL1 of the substrate SUB through the pressure difference F and can be vertically aligned.

[0251] As described above, the size (or diameter) of the first light-emitting element LD1 can be larger than the size (or diameter) of the second hole HL2 and the size (or diameter) of the third hole HL3 formed in the substrate SUB, and the first light-emitting element LD1 cannot be inserted into the second hole HL2 and the third hole HL3. Thus, the first light-emitting element LD1 can be set at a desired position (e.g., the first hole HL1).

[0252] In addition, the areas (or diameters) of the first surface LD1a and the second surface LD1b of the first light-emitting element LD1 can be different from each other. For example, the diameter of the first surface LD1a of the first light-emitting element LD1 can be smaller than the diameter of the second surface LD1b of the first light-emitting element LD1. Thus, in the process in which the first light-emitting element LD1 is inserted into the first hole HL1, when the first light-emitting element LD1 is inserted from the second surface LD1b, the diameter of the first hole HL1 can gradually decrease from the upper surface SUBa to the lower surface SUBb of the substrate SUB, and the first light-emitting element LD1 cannot be normally inserted into the first hole HL1. That is, since the shapes of the first light-emitting element LD1 and the first hole HL1 are formed to be vertically asymmetric, the direction in which the first light-emitting element LD1 is set and fixed can be determined. For example, the first surface LD1a of the first light-emitting element LD1 can be set on one side (i.e., the lower surface side) of the lower surface SUBb of the substrate SUB, and the second surface LD1b of the first light-emitting element LD1 can be set on one side (i.e., the upper surface side) of the upper surface SUBa of the substrate SUB.

[0253] After the first light-emitting element LD1 is disposed in the first hole HL1, the first mixture MX1 can be removed from the substrate SUB. In the process of removing the first mixture MX1, the first light-emitting elements LD1 that are not disposed in the first hole HL1 or are incorrectly disposed in the second hole HL2 or the third hole HL3 can be recovered. The recovered first light-emitting elements LD1 can be reused in the process of manufacturing another display device, and the manufacturing cost of the display device can be reduced.

[0254] Next, as Figure 23 and Figure 24 shown, a second mixture MX2 including the second light-emitting element LD2 can be provided on the substrate SUB.

[0255] The second mixture MX2 can be completely dispersed on the upper surface SUBa of the substrate SUB. The shape of the second hole HL2 formed in the substrate SUB can be the same as the shape of the second light-emitting element LD2. That is, the diameter of the second hole HL2 can be substantially the same as the diameter of the second light-emitting element LD2. The size of the third hole HL3 formed in the substrate SUB can be smaller than the size of the second light-emitting element LD2.

[0256] After the second mixture MX2 is dispersed on the substrate SUB, the upper-side pressure and the lower-side pressure of the substrate SUB can be adjusted, and the upper-side pressure (or the first pressure) of the substrate SUB can be adjusted to be greater than the lower-side pressure (or the second pressure) of the substrate SUB to dispose and fix the second light-emitting element LD2 in the second hole HL2. The second light-emitting element LD2 can be inserted into the second hole HL2 of the substrate SUB through the pressure difference F between the upper part and the lower part of the substrate SUB and can be vertically aligned.

[0257] As described above, since the first light-emitting element LD1 is disposed in the first hole HL1, the second light-emitting element LD2 can not be disposed in the first hole HL1. In addition, the size (or diameter) of the second light-emitting element LD2 can be greater than the size (or diameter) of the third hole HL3 formed in the substrate SUB, and the second light-emitting element LD2 can not be inserted into the third hole HL3. Therefore, the second light-emitting element LD2 can be disposed at a desired position (e.g., the second hole HL2).

[0258] In addition, similar to the first light-emitting element LD1, the diameter of the first surface LD2a of the second light-emitting element LD2 can be smaller than the diameter of the second surface LD2b of the second light-emitting element LD2. Since the shapes of the second light-emitting element LD2 and the second hole HL2 are vertically asymmetric, the direction in which the second light-emitting element LD2 is disposed and fixed can be determined. For example, the first surface LD2a of the second light-emitting element LD2 can be disposed on one side of the lower surface SUBb of the substrate SUB, and the second surface LD2b of the second light-emitting element LD2 can be disposed on one side of the upper surface SUBa of the substrate SUB.

[0259] After the second light-emitting element LD2 is disposed in the second hole HL2, the second mixture MX2 can be removed from the substrate SUB. In the process of removing the second mixture MX2, the second light-emitting element LD2 that is not disposed in the second hole HL2 or is incorrectly disposed in the third hole HL3 can be recovered. The recovered second light-emitting element LD2 can be reused in the process of manufacturing another display device.

[0260] Next, as Figure 25 and Figure 26 shown, a third mixture MX3 including a third light-emitting element LD3 can be provided on the substrate SUB.

[0261] The third mixture MX3 can be completely dispersed on the upper surface SUBa of the substrate SUB. The shape of the third hole HL3 formed in the substrate SUB can be the same as the shape of the third light-emitting element LD3. That is, the diameter of the third hole HL3 can be substantially the same as the diameter of the third light-emitting element LD3.

[0262] After the third mixture MX3 is dispersed on the substrate SUB, the upper-side pressure and the lower-side pressure of the substrate SUB can be adjusted, and the upper-side pressure (or the first pressure) of the substrate SUB can be adjusted to be greater than the lower-side pressure (or the second pressure) of the substrate SUB to dispose and fix the third light-emitting element LD3 in the third hole HL3. The third light-emitting element LD3 can be inserted into the third hole HL3 of the substrate SUB through the pressure difference F between the upper and lower parts of the substrate SUB and can be vertically aligned.

[0263] As described above, since the first light-emitting element LD1 is disposed in the first hole HL1 and the second light-emitting element LD2 is disposed in the second hole HL2, the third light-emitting element LD3 can be not disposed in the first hole HL1 and the second hole HL2. Therefore, the third light-emitting element LD3 can be disposed at a desired position (e.g., the third hole HL3).

[0264] In addition, similar to the first light-emitting element LD1 and the second light-emitting element LD2, the diameter of the first surface LD3a of the third light-emitting element LD3 may be smaller than the diameter of the second surface LD3b of the third light-emitting element LD3. Since the shapes of the third light-emitting element LD3 and the third hole HL3 are vertically asymmetric, the direction in which the third light-emitting element LD3 is disposed and fixed can be determined. For example, the first surface LD3a of the third light-emitting element LD3 may be disposed on one side of the lower surface SUBb of the substrate SUB, and the second surface LD3b of the third light-emitting element LD3 may be disposed on one side of the upper surface SUBa of the substrate SUB.

[0265] After the third light-emitting element LD3 is disposed in the third hole HL3, the third mixture MX3 can be removed from the substrate SUB. In the process of removing the third mixture MX3, the third light-emitting element LD3 that is not disposed in the third hole HL3 can be recovered. The recovered third light-emitting element LD3 can be reused in the process of manufacturing another display device.

[0266] Thereafter, as Figure 27 shown, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be respectively disposed and fixed in the first hole HL1, the second hole HL2, and the third hole HL3 formed in the substrate SUB.

[0267] Similar to Figure 13 and Figure 14 the display device 1000, a first pixel electrode AE1 electrically connected to the first light-emitting element LD1, a second pixel electrode AE2 electrically connected to the second light-emitting element LD2, and a third pixel electrode AE3 electrically connected to the third light-emitting element LD3 can be formed on the upper surface SUBa of the substrate SUB, and a common electrode CE commonly electrically connected to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be formed on the lower surface SUBb of the substrate SUB. The pixel electrodes AE1, AE2, and AE3 and the common electrode CE can provide drive signals to each of the light-emitting elements LD1, LD2, and LD3, and the light-emitting elements LD1, LD2, and LD3 can emit light with a brightness corresponding to the provided drive signals.

[0268] As described above, the pixel electrodes AE1, AE2, and AE3 may include a transparent conductive material and may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. Therefore, among the light emitted from the light-emitting elements LD1, LD2, and LD3, the light traveling in the third direction DR3 can pass through the pixel electrodes AE1, AE2, and AE3 and can be emitted to the outside.

[0269] In addition, the common electrode CE may include a conductive material having a constant reflectivity, and may include, for example, metals such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof. Therefore, among the light emitted from the light-emitting elements LD1, LD2, and LD3, the light traveling in the direction opposite to the third direction DR3 may be reflected by the common electrode CE in the third direction DR3 and may be emitted to the outside.

[0270] According to the method of manufacturing a display device according to an embodiment, since the light-emitting elements LD1, LD2, and LD3 can be aligned and fixed in the first hole HL1, the second hole HL2, and the third hole HL3 formed in the substrate SUB in the vertical direction, an area in which the light-emitting elements LD1, LD2, and LD3 can be disposed can be widely ensured, and a high-resolution display device can be realized.

[0271] In addition, since the light-emitting elements LD1, LD2, and LD3 are fixed to the substrate SUB according to the pressure difference F between the upper part and the lower part of the substrate SUB, the light-emitting elements LD1, LD2, and LD3 can be firmly fixed as compared with fixing by electricity, and a separate fixing member for fixing the light-emitting elements LD1, LD2, and LD3 can be omitted. Therefore, the alignment accuracy of the light-emitting elements LD1, LD2, and LD3 and the reliability of the display device can be improved.

[0272] In addition, since the sizes of the light-emitting elements LD1, LD2, and LD3 and the sizes of the holes HL1, HL2, and HL3 are adjusted to be different from each other, the light-emitting elements LD1, LD2, and LD3 can be disposed at desired positions. In addition, since the light-emitting elements LD1, LD2, and LD3 are formed in a vertically asymmetric shape, the directions in which the light-emitting elements LD1, LD2, and LD3 are aligned can be controlled.

[0273] As described above, since the misaligned light-emitting elements LD1, LD2, and LD3 can be recovered and reused in the process of aligning the light-emitting elements LD1, LD2, and LD3, the manufacturing cost of the display device can be reduced.

[0274] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art to which the present disclosure pertains will understand that the embodiments can be implemented in other specific forms without changing the technical scope and basic features of the present disclosure. Therefore, it should be understood that the above-described embodiments are illustrative and not restrictive in all respects.

Claims

1. A display device, comprising: a substrate including a first emission region; and a first light-emitting element disposed in the first emission region, wherein the substrate includes a first hole passing through the substrate in the first emission region, at least a part of the first light-emitting element is disposed in the first hole, and the display device further includes: a plurality of channel walls disposed under the substrate; and a microchannel formed between the plurality of channel walls and overlapping with the first hole, wherein the first light-emitting element is disposed in the first hole by flowing a fluid through the microchannel.

2. The display device according to claim 1, wherein The first light-emitting element includes a first surface and a second surface opposite to each other, the first surface is disposed on the lower surface side of the substrate, the second surface is disposed on the upper surface side of the substrate, and the aspect ratio of the first light-emitting element is greater than 1.

3. The display device according to claim 2, wherein, In a plan view, the diameter of the second surface is greater than the diameter of the first surface, and the first light-emitting element further includes a side surface disposed between the first surface and the second surface.

4. The display device according to claim 3, wherein, The side surface of the first light-emitting element contacts the inner circumferential surface of the first hole.

5. The display device according to claim 3, wherein, The first hole includes a side wall perpendicular to the lower surface of the substrate, the diameter of the first hole is greater than the diameter of the first surface and less than the diameter of the second surface, and a part of the first light-emitting element protrudes to the outside of the substrate.

6. The display device according to claim 5, further comprising: a filler filled between the side wall of the first hole and the first light-emitting element.

7. The display device according to claim 3, wherein The first hole includes a vertical surface perpendicular to the lower surface of the substrate and an inclined surface having a predetermined angle with respect to the lower surface of the substrate, and the side surface of the first light-emitting element contacts the inclined surface and does not contact the vertical surface.

8. The display device according to claim 2, wherein, In a plan view, the diameters of the first surface and the second surface are the same.

9. The display device according to claim 8, wherein, The first hole includes a side wall having a predetermined angle with respect to the lower surface of the substrate, the diameter of the first light-emitting element is greater than the diameter of the lower through surface of the first hole and less than the diameter of the upper through surface of the first hole, and a part of the first light-emitting element protrudes to the outside of the substrate.

10. The display device according to claim 9, further comprising: a filler filled between the side wall of the first hole and the first light-emitting element.

11. The display device according to claim 8, wherein, The first hole includes a side wall perpendicular to the lower surface of the substrate, the substrate further includes a protrusion protruding from the side wall of the first hole and integrated with the substrate, the protrusion contacts a part of the first surface, and the protrusion exposes another part of the first surface.

12. The display device according to claim 2, wherein, The thickness of the substrate is less than the length of the first light-emitting element, and a part of the first light-emitting element protrudes to the outside of the substrate.

13. The display device according to claim 2, wherein, The thickness of the substrate is greater than the length of the first light-emitting element, and the first light-emitting element is disposed within the substrate.

14. The display device according to claim 2, further comprising: a common electrode disposed on the lower surface of the substrate and electrically connected to the first surface of the first light-emitting element; and A pixel electrode is disposed on an upper surface of the substrate and electrically connected to the second surface of the first light-emitting element.

15. The display device according to claim 14, further comprising: A transistor is disposed on the upper surface of the substrate in a first circuit region adjacent to the first emission region, wherein the transistor is electrically connected to the pixel electrode.

16. The display device according to claim 2, further comprising: A second light-emitting element, wherein a color of light emitted by the second light-emitting element is different from a color of light emitted by the first light-emitting element, wherein The substrate further includes a second hole passing through the substrate in a second emission region adjacent to the first emission region, In a plan view, a diameter of the second hole is smaller than a diameter of the first hole, and At least a part of the second light-emitting element is disposed in the second hole.

17. The display device according to claim 16, wherein, A diameter of the second light-emitting element is smaller than a diameter of the first light-emitting element.

18. The display device according to claim 16, further comprising: A common electrode is disposed on a lower surface of the substrate and electrically connected to the first surface of the first light-emitting element and the first surface of the second light-emitting element; A first pixel electrode is disposed on the upper surface of the substrate and electrically connected to the second surface of the first light-emitting element; And A second pixel electrode is disposed on the upper surface of the substrate and electrically connected to a second surface of the second light-emitting element opposite to the first surface of the second light-emitting element.

19. The display device according to claim 1, Among them, The plurality of channel walls do not overlap with the first hole.

20. A method of manufacturing a display device, comprising: Preparing a substrate including a first hole; Providing a first mixture including a first light-emitting element on the substrate; And Vertically aligning the first light-emitting element in the first hole by setting a first pressure of an upper portion of the substrate to be higher than a second pressure of a lower portion of the substrate, wherein the first hole passes through the substrate, and The method further includes: adjusting the second pressure to be lower than the first pressure by flowing a fluid through a microchannel formed between channel walls at a lower portion of the substrate and extending in one direction.

21. The method according to claim 20, wherein, The first light-emitting element includes a first surface and a second surface opposite to each other, and An aspect ratio of the first light-emitting element is greater than 1.

22. The method according to claim 21, wherein A diameter of the first surface is smaller than a diameter of the second surface, and When vertically aligning the first light-emitting element, the first surface is disposed on a lower surface side of the substrate and the second surface is disposed on an upper surface side of the substrate.

23. The method according to claim 20, wherein The substrate further includes a second hole passing through the substrate, The method further includes: Providing a second mixture including a second light-emitting element on the substrate, wherein a color of light emitted by the second light-emitting element is different from a color of light emitted by the first light-emitting element; and Vertically aligning the second light-emitting element in the second hole by setting the first pressure to be higher than the second pressure, wherein a diameter of the second hole is smaller than a diameter of the first hole, and The diameter of the second light-emitting element is smaller than the diameter of the first light-emitting element.

24. The method according to claim 23, wherein, The substrate further includes a third hole passing through the substrate. The method further includes: providing a third mixture including a third light-emitting element on the substrate, the color of the light emitted by the third light-emitting element being different from the color of the light emitted by the first light-emitting element and the second light-emitting element; and vertically aligning the third light-emitting element in the third hole by setting the first pressure to be higher than the second pressure. wherein the diameter of the third hole is smaller than the diameter of the first hole and the diameter of the second hole, and the diameter of the third light-emitting element is smaller than the diameter of the first light-emitting element and the diameter of the second light-emitting element.

25. The method according to claim 23, further comprising: providing a common electrode on the lower surface of the substrate and electrically connected to the first surface of the first light-emitting element and the first surface of the second light-emitting element; providing a first pixel electrode on the upper surface of the substrate and electrically connected to the second surface of the first light-emitting element; and providing a second pixel electrode on the upper surface of the substrate and electrically connected to the second surface of the second light-emitting element.

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