Display substrate and display device

Abstract

The present invention provides a display substrate and a display device. The display substrate includes a substrate and a shift register unit disposed on the substrate; the shift register unit includes a first first voltage line, an on-off control circuit, a first energy storage circuit, and a fourth node control circuit; the substrate includes an edge region and a display region, and the shift register unit is disposed in the edge region; the on-off control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor; at least a part of the first first voltage line extends along a first direction; the fourth node control circuit includes a second transistor; the first capacitor, the first transistor, the first first voltage line, and the second transistor are arranged along a second direction; the second transistor, the first first voltage line, the first transistor, and the first capacitor are arranged in sequence along the direction close to the display region; the first direction intersects with the second direction. The present invention can ensure the stability of the output signal of the shift register unit.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display substrate and a display device. Background Art

[0002] The existing display substrate cannot ensure the stability of the output signal of the shift register unit while maintaining the original PPI (Pixels Per Inch). Summary of the Invention

[0003] The main object of the present invention is to provide a display substrate and a display device, so as to solve the problem in the prior art that the stability of the output signal of the shift register unit cannot be ensured while maintaining the original PPI (Pixels Per Inch).

[0004] To achieve the above object, an embodiment of the present invention provides a display substrate, including a substrate and a shift register unit disposed on the substrate; the shift register unit includes a first first voltage line, a turn-on and turn-off control circuit, a first energy storage circuit, and a fourth node control circuit; the substrate includes an edge region and a display region, and the shift register unit is disposed in the edge region; the turn-on and turn-off control circuit includes a first transistor, the first energy storage circuit includes a first capacitor; the fourth node control circuit includes a second transistor;

[0005] At least a part of the first first voltage line extends along a first direction;

[0006] The first capacitor, the first transistor, the first first voltage line, and the second transistor are arranged along a second direction; the second transistor, the first first voltage line, the first transistor, and the first capacitor are arranged in sequence along the direction close to the display region;

[0007] The first direction intersects with the second direction.

[0008] Optionally, the first transistor includes a first active pattern, and at least a part of the first active pattern extends along the first direction;

[0009] The gate of the first transistor and the first first voltage line are in different layers; the gate of the first transistor is coupled to a first conductive connection portion, and the first conductive connection portion is coupled to the first first voltage line through a via.

[0010] Optionally, the shift register unit further includes a first clock signal line, a second clock signal line, a second energy storage circuit, and a fourth node control circuit, and the second energy storage circuit includes a second capacitor;

[0011] The second capacitor is located on a side of the first first voltage line away from the display area;

[0012] The first clock signal line and the second clock signal line are located on a side of the second capacitor away from the first first voltage line.

[0013] Optionally, a first electrode plate of the second capacitor is coupled to a second conductive connection portion, a first electrode of the first transistor is electrically connected to a third conductive connection portion through a via, and the third conductive connection portion is coupled to the second conductive connection portion through a via, so that the first electrode of the first transistor is coupled to the first electrode plate of the second capacitor;

[0014] A second electrode plate of the second capacitor is coupled to a first connection conductive portion, and the first connection conductive portion is coupled to the first clock signal line through a via, so that the second electrode plate of the second capacitor is coupled to the first clock signal line.

[0015] Optionally, a positive projection of the second electrode plate of the second capacitor on the substrate does not overlap with a positive projection of the first first voltage line on the substrate.

[0016] Optionally, a gate of the second transistor is coupled to a fourth conductive connection portion;

[0017] A second electrode of the first transistor is coupled to a fifth conductive connection portion through a via;

[0018] The fourth conductive connection portion is coupled to the fifth conductive connection portion through a via, so that the second electrode of the first transistor is coupled to the gate of the second transistor.

[0019] Optionally, the fourth node control circuit further includes a third transistor; the third transistor is disposed between the first clock signal line and the first first voltage line;

[0020] A first electrode of the third transistor is coupled to the first first voltage line, and a second electrode of the third transistor is coupled to a sixth conductive connection portion through a via; the sixth conductive connection portion is coupled to a second electrode of the second transistor through a via, so that the second electrode of the third transistor is coupled to the second electrode of the second transistor;

[0021] A gate of the third transistor is coupled to a seventh conductive connection portion and an eighth conductive connection portion respectively, and the seventh conductive connection portion is coupled to the second clock signal line through a via;

[0022] The first electrode of the second transistor is coupled to the ninth conductive connection portion through a via, and the ninth conductive connection portion is coupled to the eighth conductive connection portion through a via, so that the first electrode of the second transistor is coupled to the gate of the third transistor.

[0023] Optionally, the shift register unit further includes a second voltage line and a first node control circuit; the second voltage line is located on a side of the first first voltage line close to the display area; the first node control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; the fourth transistor, the fifth transistor, and the sixth transistor are disposed between the first first voltage line and the second voltage line;

[0024] The fourth transistor includes a fourth active pattern, the fifth transistor includes a fifth active pattern, and the sixth transistor includes a sixth active pattern; the fourth active pattern, the fifth active pattern, and the sixth active pattern are integrally formed;

[0025] A first end of the sixth active pattern is coupled to the second voltage line; a second end of the fourth active pattern is coupled to a fifth conductive connection portion through a via.

[0026] Optionally, the fourth node control circuit further includes a third transistor; the fourth transistor is located on a side of the first first voltage line away from the third transistor; the gate of the third transistor is respectively coupled to a seventh conductive connection portion and an eighth conductive connection portion, the seventh conductive connection portion is coupled to the second clock signal line through a via, and the eighth conductive connection portion is coupled to the gate of the fourth transistor, so that the gate of the fourth transistor is coupled to the second clock signal line;

[0027] The gate of the fifth transistor is coupled to a tenth conductive connection portion, and the tenth conductive connection portion is coupled to the first clock signal line through a via, so that the gate of the fifth transistor is coupled to the first clock signal line;

[0028] A second electrode of the third transistor is coupled to a sixth conductive connection portion through a via, the gate of the sixth transistor is coupled to an eleventh conductive connection portion, and the eleventh conductive connection portion is coupled to the sixth conductive connection portion through a via, so that the gate of the sixth transistor is coupled to the second electrode of the third transistor.

[0029] Optionally, the shift register unit further includes a third node control circuit; the first energy storage circuit includes a first capacitor; the third node control circuit includes a seventh transistor and an eighth transistor; the eighth transistor and the seventh transistor are disposed between the first first voltage line and the second voltage line;

[0030] The seventh transistor includes a seventh active pattern, and the eighth transistor includes an eighth active pattern; the seventh active pattern and the eighth active pattern are integrally formed;

[0031] A first end of the eighth active pattern is coupled to a twelfth conductive connection portion through a via, and the twelfth conductive connection portion is coupled to the second voltage line, so that the first end of the eighth active pattern is coupled to the second voltage line;

[0032] A first end of the seventh active pattern is coupled to a thirteenth conductive connection portion through a via, and the thirteenth conductive connection portion is coupled to a second electrode plate of the first capacitor through a via, so that the first end of the seventh active pattern is coupled to the second electrode plate of the first capacitor;

[0033] A first electrode plate of the first capacitor is coupled to a gate of the sixth transistor;

[0034] A gate of the eighth transistor is coupled to a fourteenth conductive connection portion, the fourteenth conductive connection portion is coupled to a fifth conductive connection portion through a via, and the fifth conductive connection portion is coupled to a second electrode of the first transistor through a via, so that the gate of the eighth transistor is coupled to the second electrode of the first transistor;

[0035] A gate of the seventh transistor is coupled to a gate of the fifth transistor.

[0036] Optionally, the shift register unit further includes a fifth node control circuit;

[0037] The fifth node control circuit includes a ninth transistor;

[0038] The ninth transistor includes a ninth active pattern, at least a part of the ninth active pattern extends along a first direction, and the ninth transistor is located between the first capacitor and the second voltage line;

[0039] A gate of the ninth transistor is coupled to a first electrode plate of the first capacitor;

[0040] A first end of the ninth active pattern is coupled to a fifteenth conductive connection portion through a via, a gate of the seventh transistor is coupled to a sixteenth conductive connection portion, and the fifteenth conductive connection portion is coupled to the sixteenth conductive connection portion through a via, so that the first end of the ninth active pattern is coupled to the gate of the seventh transistor; a second end of the ninth active pattern is coupled to the thirteenth conductive connection portion through a via, so that the second end of the ninth active pattern is coupled to the second electrode plate of the first capacitor.

[0041] Optionally, the shift register unit further includes a third energy storage circuit, and the third energy storage circuit includes a third capacitor;

[0042] The positive projection of the first electrode plate of the third capacitor on the substrate, the positive projection of the second electrode plate of the third capacitor on the substrate, and the positive projection of the second voltage line on the substrate at least partially overlap;

[0043] The first electrode plate of the third capacitor is coupled to the seventeenth conductive connection portion through a via, and the seventeenth conductive connection portion is coupled to the second end of the eighth active pattern through a via, so that the first electrode plate of the third capacitor is coupled to the second end of the eighth active pattern;

[0044] The second electrode plate of the third capacitor is coupled to the second voltage line through a via.

[0045] Optionally, the shift register unit further includes a first output circuit, a second output circuit, and a second first voltage line; the first output circuit includes a first output transistor, and the second output circuit includes a second output transistor; the first output transistor and the second output transistor are located between the second voltage line and the second first voltage line, and the second first voltage line is located on the side of the second voltage line close to the display area.

[0046] Optionally, the shift register unit further includes a signal output line, a second energy storage circuit, and a third energy storage circuit; the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor; the first electrode plate of the second capacitor is coupled to the second conductive connection portion;

[0047] The active layers of the first output transistor and the second output transistor are formed by a continuous semiconductor layer, and the semiconductor layer extends along the first direction;

[0048] The first electrode of the first output transistor is coupled to the second electrode of the second output transistor, the first electrode of the first output transistor is coupled to the eighteenth conductive connection portion, and the eighteenth conductive connection portion is coupled to the signal output line through a via;

[0049] The second electrode of the first output transistor is coupled to the second first voltage line;

[0050] The first electrode of the second output transistor is coupled to the second voltage line;

[0051] The gate of the first output transistor is coupled to the second conductive connection portion, and the gate of the second output transistor is coupled to the first electrode plate of the third capacitor.

[0052] Optionally, the shift register unit includes a first first voltage line, a second first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a signal output line, a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first output transistor, and a second output transistor;

[0053] The gate of the first transistor is coupled to the first first voltage line, the first electrode of the first transistor is coupled to the first plate of the second capacitor, and the second electrode of the first transistor is coupled to the gate of the second transistor;

[0054] The gate of the second transistor is coupled to the second electrode of the first transistor;

[0055] The second plate of the second capacitor is coupled to the first clock signal line;

[0056] The first electrode of the third transistor is coupled to the first first voltage line, and the second electrode of the third transistor is coupled to the second electrode of the second transistor;

[0057] The gate of the third transistor is coupled to the first electrode of the second transistor;

[0058] The gate of the fourth transistor is coupled to the second clock signal line; the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor; the first electrode of the fifth transistor is coupled to the second electrode of the sixth transistor; the first electrode of the sixth transistor is coupled to the second voltage line;

[0059] The gate of the fifth transistor is coupled to the first clock signal line, and the second electrode of the third transistor is coupled to the gate of the sixth transistor;

[0060] The first electrode of the eighth transistor is coupled to the second voltage line, the first electrode of the seventh transistor is coupled to the second plate of the first capacitor, and the first plate of the first capacitor is coupled to the gate of the sixth transistor; the second electrode of the seventh transistor is coupled to the second electrode of the eighth transistor;

[0061] The gate of the eighth transistor is coupled to the second electrode of the first transistor, and the gate of the seventh transistor is coupled to the gate of the fifth transistor;

[0062] The first electrode of the ninth transistor is coupled to the gate of the seventh transistor, and the second electrode of the ninth transistor is coupled to the second plate of the first capacitor; the gate of the ninth transistor is coupled to the first plate of the first capacitor;

[0063] The first electrode of the third capacitor is coupled to the second electrode of the eighth transistor, and the second electrode of the third capacitor is coupled to the second voltage line;

[0064] The first electrode of the first output transistor is coupled to the second electrode of the second output transistor. The second electrode of the second output transistor is coupled to the signal output line. The second electrode of the first output transistor is coupled to the second first voltage line. The first electrode of the second output transistor is coupled to the second voltage line. The gate of the first output transistor is coupled to the first electrode of the first transistor. The gate of the second output transistor is coupled to the first electrode of the third capacitor;

[0065] The positive projection of the first electrode of the third capacitor on the substrate, the positive projection of the second electrode of the third capacitor on the substrate, and the positive projection of the second voltage line on the substrate overlap at least partially.

[0066] Optionally, the first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the first capacitor are disposed between the first first voltage line and the second voltage line. The second transistor, the third transistor, and the second capacitor are disposed between the first second voltage line and the first clock signal line;

[0067] The first clock signal line and the second clock signal line are disposed on a side of the first first voltage line away from the second voltage line;

[0068] The first output transistor and the second output transistor are disposed between the second voltage line and the second first voltage line. The second first voltage line is disposed on a side of the second voltage line away from the first first voltage line.

[0069] Optionally, the fourth transistor, the fifth transistor, and the sixth transistor are arranged in sequence along a first direction;

[0070] The eighth transistor, the seventh transistor, and the first capacitor are arranged in sequence along the first direction;

[0071] The eighth transistor, the fourth transistor, and the third transistor are arranged in sequence along a second direction;

[0072] The first capacitor, the first transistor, and the second transistor are arranged in sequence along the second direction;

[0073] At least a part of the first clock signal line, at least a part of the second clock signal line, at least a part of the first of the first voltage lines, at least a part of the second of the first voltage lines, and at least a part of the second voltage line extend in a first direction.

[0074] Optionally, the display substrate further includes a plurality of rows of pixel circuits disposed on the display area of the substrate, and the pixel circuits include a light emission control terminal;

[0075] The shift register unit corresponds to at least one row of the pixel circuits;

[0076] The shift register unit includes a signal output line, and the signal output line of the shift register unit is coupled to the light emission control terminals of the at least one row of pixel circuits for providing a light emission control signal to the light emission control terminals of the at least one row of pixel circuits.

[0077] An embodiment of the present invention further provides a display device including the above-mentioned display substrate.

[0078] In the display substrate and the display device according to the embodiment of the present invention, the first transistor is disposed between the first of the first voltage lines and the first capacitor, and the first capacitor, the first transistor, the first of the first voltage lines, and the second transistor are arranged in a second direction, so as to utilize the lateral space to dispose the first transistor, thereby not increasing the longitudinal dimension occupied by the shift register unit, and thus being able to ensure the stability of the output signal of the shift register unit without changing the original PPI (Pixels Per Inch), so as to achieve the purpose of improving the display performance. Description of the Drawings

[0079] Figure 1 is a circuit diagram of at least one embodiment of a shift register unit included in the display substrate according to the embodiment of the present invention;

[0080] Figure 2 is Figure 1 a working timing diagram of the embodiment of the shift register unit shown;

[0081] Figure 3 is a circuit diagram of at least one embodiment of a shift register unit included in the display substrate according to the embodiment of the present invention;

[0082] Figure 4 is a schematic diagram of area division of the display substrate according to at least one embodiment of the present invention;

[0083] Figure 5 is a schematic diagram of the connection relationship between the shift register unit and the pixel circuits included in the display substrate according to at least one embodiment of the present invention;

[0084] Figure 6 It is a layout schematic diagram of a shift register unit provided by at least one embodiment of the present invention;

[0085] Figure 7 is Figure 6 a layout schematic diagram of the active layer in

[0086] Figure 8 is Figure 6 a layout schematic diagram of the first gate metal layer in

[0087] Figure 9 is Figure 6 a layout schematic diagram of the second gate metal layer in

[0088] Figure 10 is Figure 6 a via schematic diagram adopted in

[0089] Figure 11 is Figure 6 a schematic diagram of the source-drain metal layer in Detailed implementation manners

[0090] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0091] The transistors adopted in all embodiments of the present invention can be triodes, thin-film transistors, field-effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two poles of the transistor other than the gate, one pole is called the first electrode and the other pole is called the second electrode.

[0092] During actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain electrode and the second electrode can be the source electrode; or, the first electrode can be the source electrode and the second electrode can be the drain electrode.

[0093] As Figure 1 shown, at least one embodiment of the present invention provides a display substrate, and the display substrate includes a shift register unit located in the edge region of the substrate; at least one embodiment of the shift register unit includes an on-off control circuit, a first energy storage circuit, a second energy storage circuit, a third energy storage circuit, a first output circuit, a second output circuit, a first node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit 110; the first energy storage circuit includes a first capacitor; the on-off control circuit includes a first transistor.

[0094] The on-off control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, and the third energy storage circuit includes a third capacitor C3; the first output circuit includes a first output transistor T10, the second output circuit includes a second output transistor T11, and the fourth-node control circuit includes a second transistor T2 and a third transistor T3; the first-node control circuit includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; the third-node control circuit includes a seventh transistor T7 and an eighth transistor T8; the fifth-node control circuit includes a ninth transistor T9;

[0095] The gate G1 of the first transistor T1 is coupled to a first voltage line V1, the first electrode S1 of the first transistor T1 is coupled to a second node N2, and the second electrode D1 of the first transistor T1 is coupled to a first node N1;

[0096] The gate G2 of the second transistor T2 is coupled to the second electrode D1 of the first transistor T1;

[0097] The second plate C2b of the second capacitor C2 is coupled to the first clock signal line CB;

[0098] The first electrode S3 of the third transistor T3 is coupled to the first voltage line V1, and the second electrode D3 of the third transistor T3 is coupled to the second electrode D2 of the second transistor T2;

[0099] The gate G3 of the third transistor T3 and the first electrode S2 of the second transistor T2 are both coupled to a second clock signal line CK;

[0100] The first electrode S4 of the fourth transistor T4 is coupled to an input terminal E1;

[0101] The gate G4 of the fourth transistor T4 is coupled to the second clock signal line CK; the second electrode D4 of the fourth transistor T4 is coupled to the second electrode D5 of the fifth transistor T5; the first electrode S5 of the fifth transistor T5 is coupled to the second electrode D6 of the sixth transistor T6; the first electrode S6 of the sixth transistor T6 is coupled to a second voltage line V2;

[0102] The gate G5 of the fifth transistor T5 is coupled to the first clock signal line CB, and the second electrode D3 of the third transistor T3 is coupled to the gate G6 of the sixth transistor T6;

[0103] The first electrode S8 of the eighth transistor T8 is coupled to the second voltage line V2, the first electrode S7 of the seventh transistor T7 is coupled to the second plate C1b of the first capacitor C1, and the first plate C1a of the first capacitor C1 is coupled to the gate G6 of the sixth transistor T6; the second electrode D7 of the seventh transistor T7 is coupled to the second electrode D8 of the eighth transistor T8;

[0104] The gate G8 of the eighth transistor T8 is coupled to the second electrode D1 of the first transistor T1, and the gate G7 of the seventh transistor T7 is coupled to the gate G5 of the fifth transistor T5;

[0105] The first electrode S9 of the ninth transistor T9 is coupled to the first clock signal line CB, and the second electrode D9 of the ninth transistor T9 is coupled to the second plate C1b of the first capacitor C1; the gate G9 of the ninth transistor T9 is coupled to the first plate C1a of the first capacitor C1;

[0106] The first plate C3a of the third capacitor C3 is coupled to the second electrode D8 of the eighth transistor T8, and the second plate C3b of the third capacitor C3 is coupled to the second voltage line V2;

[0107] The first electrode S10 of the first output transistor T10 is coupled to the second electrode D11 of the second output transistor T11, the second electrode D11 of the second output transistor T11 is coupled to the signal output line E1, the second electrode D10 of the first output transistor T10 is coupled to the first voltage line V1, the first electrode S11 of the second output transistor T11 is coupled to the second voltage line V2, and the gate G10 of the first output transistor T10 is coupled to the first electrode S1 of T1; the gate G11 of the second output transistor T11 is coupled to the first plate C3a of the third capacitor C3.

[0108] In at least one embodiment of the shift register unit as Figure 1 shown in the present invention, the gate signal of T10 is unstable due to interference from other signals, causing the signal output from E1 to have glitches and resulting in abnormal display; T1 is used to isolate T10 from the interfering signals affecting it, making the signal output from E1 stable and improving the display performance.

[0109] In at least one embodiment of the present invention, the first voltage line may be a low voltage line and the second voltage line may be a high voltage line, but this is not limiting.

[0110] In Figure 1 at least one embodiment of the shift register unit as shown, all the transistors are p-type transistors, but this is not limiting.

[0111] In an embodiment of the present invention, Figure 1 At least one embodiment of the shift register unit shown may be a light emission control driving circuit, but is not limited thereto.

[0112] In at least one embodiment of the present invention, the first electrode of the transistor may be the source electrode, and the second electrode of the transistor may be the drain electrode; alternatively, the first electrode of the transistor may be the drain electrode, and the second electrode of the transistor may be the source electrode.

[0113] In Figure 1 Among them, the one labeled N1 is the first node, the one labeled N2 is the second node, the one labeled N3 is the third node, and the one labeled N4 is the fourth node.

[0114] As Figure 2 shown, when at least one embodiment of the shift register unit of the present invention as Figure 1 shown operates,

[0115] In the first time period P1, E1 provides a high level, CK provides a low level, T4, T3, and T1 are turned on, the potential of N1 is high, T2 is turned off, the potential of N2 is low, T5, T8, and T10 are turned off, and T6 and T9 are turned on; at this time, the potential of the first electrode of T7 is high, CB provides a high level, and T7 is turned off; since the voltage across the capacitor does not change suddenly, the potential of N4 remains at the high level of the previous frame, T11 is turned off, and the potential of the light emission control signal output by E1 remains at the low level of the previous frame;

[0116] In the second time period P2, E1 and CK provide high levels, CB provides a low level, T4, T2, and T3 are turned off, the potential of N2 remains low, T5, T6, and T9 are turned on, the potential of N1 is high, the potential of the first electrode of T7 changes from high to low, T7 is turned on, T8 is turned off, the potential of N4 is low, T11 is turned on, and E1 outputs a high level; T1 is turned on, and T10 is turned off;

[0117] In the third time period P3, both E1 and CB provide high levels, CK provides a low level, T4 and T3 are turned on, the potential of N1 is high, the potential of N2 is low, T2 and T5 are turned off, T6 and T9 are turned on, the potential of the first electrode of T7 changes from the low level of the previous time period to high, T7 is turned off, the potential of N4 is maintained at low due to the discharge of C3, T11 is turned on, and E1 outputs a high level; T1 is turned on, and T8 and T10 are turned off;

[0118] In the fourth time period P4, both E1 and CB provide low levels, CK provides a high level, T4 and T3 are cut off, the potential of N1 is high, T2 is cut off, the potential of N2 remains low, T5, T6, and T9 are turned on, the potential of the first electrode of T7 jumps to low, T7 is turned on, the potential of N4 is low, T11 is turned on, E1 outputs a high level, T1 is turned on, and T8 and T10 are cut off;

[0119] In the fifth time period P5, both E1 and CK provide low levels, CB provides a high level, T4, T2, T3, and T1 are all turned on, the potentials of N1 and N2 are both low, T5 is cut off, T6 and T9 are turned on, the potential of the first electrode of T7 becomes high, T7 is cut off, T8 is turned on, the potential of N4 becomes high, T11 is cut off, T10 is turned on, and E1 outputs a low level;

[0120] In the sixth time period P6, both E1 and CB provide low levels, CK provides a high level, T4 and T3 are cut off, the potential of N1 remains low, T2 is turned on, the potential of N2 is high, T1, T5, and T6 are turned on, T9 is cut off, the potential of the first electrode of T7 is high, T7 and T8 are turned on, the potential of N4 is high, T11 is cut off, T10 is turned on, and E1 outputs a low level;

[0121] In the seventh time period P7, both E1 and CK provide low levels, CB provides a high level, T4, T2, T3, T1, and T6 are all turned on, the potentials of N1 and N2 are low, T9 is cut off, T6 and T9 are turned on, the potential of the first electrode of T7 is high, T7 is cut off, T8 is turned on, the potential of N4 is high, T11 is cut off, T10 is turned on, and the output of E1 is low;

[0122] In the eighth time period P8, both E1 and CB provide low levels, CK provides a high level, T4 and T3 are cut off, the potential of N1 remains low, T2 is turned on, the potential of N2 is high, T5 is turned on, T6 and T9 are cut off, the potential of the first electrode of T7 remains high, T1, T7, and T8 are turned on, the potential of N4 is high, T11 is cut off, T10 is turned on, and E1 outputs a low level;

[0123] After the seventh time period P7, T8 remains on, T11 is cut off, T1 periodically charges C2, the potential of N1 remains low, T10 remains on, so that E1 outputs a low level until the next frame of input signal pulse enters.

[0124] Figure 3 It is Figure 1 On the basis of removing the labels of the electrodes of each transistor and the plates of the capacitors, and showing the labels of each circuit.

[0125] Such asFigure 3 As shown, at least one embodiment of the shift register unit includes a turn-on / off control circuit 11, a first energy storage circuit 12, a second energy storage circuit 13, a third energy storage circuit 14, a first output circuit 15, a second output circuit 16, a first node control circuit 17, a third node control circuit 18, a fourth node control circuit 19, and a fifth node control circuit 110.

[0126] As Figure 4 shown, the one labeled J1 is the display substrate, the one labeled A0 is the display area, the one labeled B1 is the first edge area, and the one labeled B2 is the second edge area.

[0127] In the display area A0 of the display substrate J1, multiple light emission control lines, multiple gate lines, and multiple data lines can be provided, as well as multiple sub-pixels defined by the intersection of the multiple gate lines and the multiple data lines;

[0128] In the first edge area B1 and / or the second edge area B2, a driving module can be provided, and the driving module includes multiple shift register units;

[0129] The signal output lines of each of the multiple shift register units included in the driving module can be respectively coupled to A light emission control lines, for providing light emission control signals for the corresponding light emission control lines.

[0130] Wherein, A can be a positive integer. During actual operation, A can be equal to 1, 2, 3, 4, or other positive integers, and the value of A can be selected according to actual situations.

[0131] During specific implementation, the light emission control line is coupled to the light emission control end of the corresponding row of pixel circuits.

[0132] Optionally, the display substrate further includes multiple rows of pixel circuits provided on the substrate; the pixel circuits include light emission control ends;

[0133] The shift register unit included in the driving module corresponds to at least one row of the pixel circuits;

[0134] The signal output line of the shift register unit is coupled to the light emission control ends of the at least one row of pixel circuits, for providing light emission control signals for the light emission control ends of the at least one row of pixel circuits.

[0135] In at least one embodiment of the present invention, the pixel circuits can be provided in the effective display area of the display substrate, and the driving module can be provided in the edge area of the display substrate.

[0136] As Figure 5As shown, the component labeled Y1 is the driving module. The component labeled S31 is the first-stage shift register unit included in the driving module Y1. The component labeled S32 is the second-stage shift register unit included in the driving module Y1. The component labeled S3N-1 is the (N-1)-th stage shift register unit included in the driving module Y1. The component labeled S3N is the N-th stage shift register unit included in the driving module Y1, where N is an integer greater than 3.

[0137] In Figure 5 the component labeled R1 is the first row pixel circuit, the component labeled R2 is the second row pixel circuit, the component labeled R3 is the third row pixel circuit, the component labeled R4 is the fourth row pixel circuit, the component labeled R2N-3 is the (2N-3)-th row pixel circuit, the component labeled R2N-2 is the (2N-2)-th row pixel circuit, the component labeled R2N-1 is the (2N-1)-th row pixel circuit, and the component labeled R2N is the 2N-th row pixel circuit.

[0138] S31 provides the light emission control signal for R1 and R2, S32 provides the light emission control signal for R3 and R4, S3N-1 provides the light emission control signal for R2N-3 and R2N-2, and S3N provides the light emission control signal for R2N-1 and R2N.

[0139] As Figure 5 shown, in the edge region, the display substrate may further include a gate driving circuit. The gate driving circuit includes multiple stages of gate driving units, and the gate driving units can correspond to the pixel rows one by one, for providing the corresponding gate driving signals for the pixels in the corresponding rows.

[0140] In Figure 5 the component labeled Y2 is the gate driving circuit. The component labeled S21 is the first row gate driving unit included in the gate driving circuit. The component labeled S22 is the second row gate driving unit included in the gate driving circuit. The component labeled S23 is the third row gate driving unit included in the gate driving circuit. The component labeled S24 is the fourth row gate driving unit included in the gate driving circuit. The component labeled S2N-3 is the (2N-3)-th row gate driving unit included in the gate driving circuit. The component labeled S2N-2 is the (2N-2)-th row gate driving unit included in the gate driving circuit. The component labeled S2N-1 is the (2N-1)-th row gate driving unit included in the gate driving circuit. The component labeled S2N is the 2N-th row gate driving unit included in the gate driving circuit.

[0141] In Figure 6 shown, at least one embodiment of the shift register unit includes a first voltage line, a second voltage line, a first clock signal line CB, and a second clock signal line CK. The first voltage line includes a first first voltage line V11 and a second first voltage line V12.

[0142] V12, V2, V11, CB, and CK are arranged in a direction away from the display area, and V11, V2, V11, CB, and CK extend along a first direction.

[0143] As Figure 1 and Figure 6 shown, at least one embodiment of the shift register unit includes a turn-on / off control circuit, a first energy storage circuit, and a fourth node control circuit; the turn-on / off control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1;

[0144] At least a part of the first first voltage line V11 extends along the first direction;

[0145] The fourth node control circuit includes a second transistor T2;

[0146] The first capacitor C1, the first transistor T1, the first first voltage line V11, and the second transistor T2 are arranged along a second direction; the second transistor T2, the first first voltage line V11, the first transistor T1, and the first capacitor C1 are arranged in sequence along a direction close to the display area;

[0147] The first direction intersects the second direction.

[0148] In at least one embodiment of the present invention, the first direction may be a vertical direction, and the second direction may be a horizontal direction, but not limited thereto.

[0149] In at least one embodiment of the shift register unit, the first transistor T1 is disposed between the first first voltage line V11 and the first capacitor C1, and the first capacitor C1, the first transistor T1, the first first voltage line V11, and the second transistor T2 are arranged along the second direction, so as to utilize the lateral space to dispose the first transistor T1, thereby not increasing the longitudinal dimension occupied by the shift register unit, so that T1 can be added without changing the original PPI (Pixel per inch), so as to ensure the stability of the output signal of the shift register unit and achieve the purpose of improving the display performance.

[0150] In at least one embodiment of the present invention, as long as the longitudinal dimension occupied by the shift register unit remains unchanged, the size of the pixel circuit in the display area can be ensured to remain unchanged, thereby ensuring the original PPI.

[0151] As Figure 7As shown, the active pattern of T1 is labeled as A1, and A1 extends along the first direction; A1 includes a first first conductive part A11, a first channel part A13, and a second first conductive part A12 arranged in sequence from bottom to top; A11 serves as the first electrode of T1, and A12 serves as the second electrode of T1.

[0152] In Figure 8 , the gate of T1 is labeled as G1, and the first plate of C1 is labeled as C1a. In Figure 9 , the second plate of C1 is labeled as C1b, and in Figure 11 , the first first voltage line is labeled as V11; V11 extends along the first direction.

[0153] From Figures 6 - 11 shown, the orthographic projection of the first plate C1a of C1 on the substrate, the orthographic projection of A11 on the substrate, and the orthographic projection of V11 on the substrate are arranged along the first direction, and the first direction can be the horizontal direction; the orthographic projection of C1a on the substrate and the orthographic projection of C1b on the substrate at least partially overlap.

[0154] From Figure 6 it can be seen that above T1, no transistor is provided, so on the basis of adding T1, the longitudinal dimension will not be increased, ensuring that the original PPI remains unchanged.

[0155] Optionally, at least one of a transistor, a capacitor, and a signal line is not provided between the first transistor and the first first voltage line, so that the first transistor and the first first voltage line are adjacent, facilitating the coupling of the gate of the first transistor and the first first voltage line.

[0156] In at least one embodiment of the present invention, as Figure 6 shown, the first transistor T1 and the first first voltage line V11 are adjacent to facilitate the coupling of the gate of T1 and V11.

[0157] As Figure 7 , the first transistor T1 includes a first active pattern A1, and at least a part of the first active pattern A1 extends along the first direction;

[0158] As Figures 6 - 11 shown, the gate G1 of the first transistor T1 and the first first voltage line V11 are located in different layers; as Figure 8 shown, the gate G1 of the first transistor T1 is coupled to the first conductive connection part L1, and the first conductive connection part L1 is coupled to the first first voltage line V11 through the first via H1.

[0159] Optionally, as Figure 1 , Figures 6 - 11As shown, the shift register unit further includes a first clock signal line CB, a second clock signal line CK, and a second energy storage circuit. The second energy storage circuit includes a second capacitor C2, and the fourth node control circuit includes a second transistor T2;

[0160] The second capacitor C2 and the second transistor T2 are located on a side of the first first voltage line V11 away from the display area;

[0161] The first clock signal line CB and the second clock signal line CK are located on a side of the second capacitor C2 away from the first first voltage line V11.

[0162] In at least one embodiment of the present invention, the fact that the second capacitor C2 and the second transistor T2 are located on a side of the first first voltage line V11 away from the display area may mean that: the orthographic projection of the second capacitor C2 on the substrate and the orthographic projection of the second transistor T2 on the substrate are located on a side of the orthographic projection of the first first voltage line V11 on the substrate away from the display area;

[0163] The fact that the first clock signal line CB and the second clock signal line CK are located on a side of the second capacitor C2 away from the first first voltage line V11 may mean that: the orthographic projection of the first clock signal line CB on the substrate and the orthographic projection of the second clock signal line CK on the substrate are located on a side of the orthographic projection of the second capacitor C2 on the substrate away from the orthographic projection of the first first voltage line V11 on the substrate.

[0164] As Figure 11 shown, both CB and CK extend along a first direction (the first direction may be a vertical direction). As Figures 6 - 11 shown, in at least one embodiment of the present invention, V11 is shifted to the right so that T2 and C2 are disposed between V11 and CB.

[0165] In Figures 6 - 11 the at least one embodiment shown, V11 may be shifted to the right by about 8um, and the lateral length of at least one embodiment of the shift register unit may be increased by 25um, and T1 is disposed through the extra lateral space.

[0166] In Figures 6 - 11 the at least one embodiment shown, CB is disposed between CK and C2 to facilitate the coupling of the second electrode plate of C2 and CB; however, in actual operation, the positions of CB and CK may also be interchanged.

[0167] As Figures 6 - 11, T2 can be a double-gate transistor. The one labeled G21 is the first gate included in T2, and the one labeled G22 is the second gate included in T2. G21 and G22 are coupled.

[0168] In Figure 8 , the one labeled C2a is the first electrode plate of C2, and the one labeled C2b is the second electrode plate of C2. The orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of C2b on the substrate.

[0169] As Figure 8 shown, the first electrode plate C2a of the second capacitor is coupled to the second conductive connection part L2. As Figures 6 - 11 shown, A11 (A11 serves as the first electrode of the first transistor) is electrically connected to the third conductive connection part L3 through the second via hole H2, and the third conductive connection part L3 is coupled to the second conductive connection part L2 through the third via hole H3, so that A11 (A11 serves as the first electrode of the first transistor) is coupled to the first electrode plate C2a of the second capacitor C2;

[0170] As Figures 6 - 11 shown, the second electrode plate C2b of the second capacitor C2 is coupled to the first connection conductive part L01, and the first connection conductive part L01 is coupled to the first clock signal line CB through the fourth via hole H4, so that the second electrode plate C2b of the second capacitor C2 is coupled to the first clock signal line CB.

[0171] In at least one embodiment of the present invention, "coupled" may include: integrally formed; or, electrically connected to each other through vias or conductive connection parts; but not limited thereto.

[0172] In Figure 8 at least one embodiment shown, the first electrode plate C2a of the second capacitor is integrally formed with the second conductive connection part L2.

[0173] Optionally, the orthographic projection of the second electrode plate of the second capacitor on the substrate does not overlap with the orthographic projection of the first first voltage line on the substrate. In at least one embodiment of the present invention, the first first voltage line is moved from a position overlapping with the second capacitor to a position adjacent to the first transistor, and the lateral dimension of at least one embodiment of the shift register unit is increased, and the first transistor is arranged through the extra space.

[0174] As Figure 8 shown, the first gate G21 of the second transistor T2 and the second gate G22 of the second transistor T2 are both coupled to the fourth conductive connection part L4;

[0175] As Figures 6 - 11As shown, A12 (A12 serves as the second electrode of the first transistor T1) is coupled to the fifth conductive connection portion L5 through the fifth via hole H5; the fourth conductive connection portion L4 is coupled to the fifth conductive connection portion L5 through the sixth via hole H6, so that the second electrode of the first transistor is coupled to G21 and G22.

[0176] In Figure 8 At least one embodiment shown, G21 and G22 are integrally formed.

[0177] Optionally, as Figure 1 and Figure 6 shown, the fourth node control circuit further includes a third transistor; the third transistor T3 is disposed between the first clock signal line CB and the first first voltage line V11;

[0178] As Figure 7 shown, T3 includes a third active pattern A3, and the third active pattern A3 includes a first third conductive portion A31, a third channel portion A33, and a second third conductive portion A32 arranged in sequence from top to bottom;

[0179] A31 serves as the first electrode of the third transistor T3, and A32 serves as the second electrode of the third transistor T3.

[0180] As Figure 7 shown, the second transistor T2 has a second active pattern A2, and A2 includes a first channel portion A231, a second channel portion A232, a first second conductive portion A21, and a second second conductive portion A22;

[0181] The orthographic projection of A231 on the substrate overlaps with the orthographic projection of G21 on the substrate, and the orthographic projection of A232 on the substrate overlaps with the orthographic projection of G22 on the substrate;

[0182] A21 serves as the first electrode of T2, and A22 serves as the second electrode of T2.

[0183] As Figures 6 - 11 shown, A31 (A31 serves as the first electrode of T3) is coupled to the second connection conductive portion L02 through the first connection via hole Hc1, and the second connection conductive portion L02 is coupled to the first first voltage line V11, so that the first electrode of T3 is coupled to V11; A32 (A32 serves as the second electrode of T3) is coupled to the sixth conductive connection portion L6 through the seventh via hole H7; the sixth conductive connection portion L6 is coupled to A22 (serving as the second electrode of the second transistor T2) through the eighth via hole H8, so that the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2;

[0184] AsFigures 6 - 11 As shown, the gate G3 of the third transistor T3 is coupled to the seventh conductive connection portion L7 and the eighth conductive connection portion L8 respectively. The seventh conductive connection portion L7 is coupled to the second clock signal line CK through the ninth via H9, so that the gate G3 of the third transistor T3 is coupled to CK;

[0185] As Figures 6 - 11 shown, A21 (serving as the first electrode of the second transistor) is coupled to the ninth conductive connection portion L9 through the tenth via H10, and the ninth conductive connection portion L9 is coupled to the eighth conductive connection portion L8 through the eleventh via H11, so that the first electrode of the second transistor T2 is coupled to the gate G3 of the third transistor T3.

[0186] In Figure 8 at least one embodiment shown, G3, L7 and L8 are integrally formed.

[0187] In at least one embodiment of the present invention, as Figures 6 - 11 shown, T3 and T2 are arranged along the first direction. The third active pattern A3 included in T3 extends along the first direction. The second active pattern A2 included in T2 is U-shaped, and the plate included in C2 is L-shaped. T2, T3 and C2 are arranged between CK and V11.

[0188] Optionally, the shift register unit further includes a second voltage line and a first node control circuit; the second voltage line V2 is located on the side of the first first voltage line V11 close to the display area; as Figure 1 and Figure 6 shown, the first node control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are arranged between the first first voltage line V11 and the second voltage line V2;

[0189] As Figure 7 shown, the fourth transistor T4 includes a fourth active pattern, the fifth transistor T5 includes a fifth active pattern, and the sixth transistor T6 includes a sixth active pattern; the fourth active pattern, the fifth active pattern and the sixth active pattern are integrally formed;

[0190] The fourth active pattern includes a first fourth conductive portion A41, a fourth channel portion A43 and a second fourth conductive portion A42 arranged in sequence along the first direction; the first fourth conductive portion A41 is the first end of the fourth active pattern; the second fourth conductive portion A42 is the second end of the fourth active pattern;

[0191] The fifth active pattern includes a second fifth conductive part, a fifth channel part A53, and a first fifth conductive part arranged in sequence in a first direction; the second fifth conductive part is the first end of the fifth active pattern; the second fifth conductive part is the second end of the fifth active pattern;

[0192] The sixth active pattern includes a second sixth conductive part A62, a sixth channel part A63, and a first sixth conductive part A61 arranged in sequence in a first direction; the second sixth conductive part A62 is the second end of the sixth active pattern, and the first sixth conductive part A61 is the first end of the sixth active pattern;

[0193] The second fourth conductive part A42 is multiplexed as the second fifth conductive part, and the first fifth conductive part is multiplexed as the second sixth conductive part A62; the first fourth conductive part A41 serves as the first electrode of the fourth transistor T4, the second fourth conductive part A42 serves as the second electrode of the fourth transistor T4, the first fifth conductive part A51 serves as the first electrode of the fifth transistor T5, and the second fifth conductive part A52 serves as the second electrode of the fifth transistor T5; the first sixth conductive part A61 serves as the first electrode of the sixth transistor T6, and the second sixth conductive part A62 serves as the second electrode of the sixth transistor T6.

[0194] A42 is coupled to the fifth conductive connection part L5 through a second connection via Hc2, so that A42 is coupled to A12, thereby coupling the second electrode of the fourth transistor T4 to the second electrode of the first transistor T1;

[0195] The first sixth conductive part A61 is coupled to the third connection conductive part L03 through a third connection via Hc3, and the third connection conductive part L03 is coupled to the second voltage line V2, so that A61 is coupled to V2, thereby coupling the first electrode of the sixth transistor T6 to V2.

[0196] In Figure 11 In at least one of the illustrated embodiments, V2 and L03 are integrally formed.

[0197] In Figures 6 - 11 In at least one of the illustrated embodiments, A41 can be coupled to the signal output line of the adjacent upper-stage shift register unit through a via.

[0198] In Figures 6 - 11 In, the one labeled ESTV is the start signal line, and the first electrode of the fourth transistor in the first-stage shift register unit of the shift register unit is coupled to the start signal line ESTV.

[0199] In at least one embodiment of the present invention, the statement that the second voltage line V2 is located on the side of the first first voltage line V11 closer to the display area may mean that: the orthographic projection of the second voltage line V2 on the substrate is located on the side of the orthographic projection of the first first voltage line V11 on the substrate closer to the display area;

[0200] The statement that the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are disposed between the first first voltage line V11 and the second voltage line V2 may mean that: the orthographic projection of the fourth transistor T4 on the substrate, the orthographic projection of the fifth transistor T5 on the substrate, and the orthographic projection of the sixth transistor T6 on the substrate are disposed between the orthographic projection of the first first voltage line V11 on the substrate and the orthographic projection of the second voltage line V2 on the substrate.

[0201] As Figure 7 shown, A4, A5, and A6 are formed of a continuous semiconductor layer, at least a part of A4 extends along a first direction (the first direction may be a vertical direction), at least a part of A5 extends along the first direction, at least a part of A6 extends along the first direction, the orthographic projections of A4, A5, and A6 on the substrate are located above the orthographic projection of the first electrode plate of C1 on the substrate, and there are no orthographic projections of A4, A5, and A6 on the substrate above the orthographic projection of A1 on the substrate, so as to ensure that the longitudinal dimension occupied by at least one embodiment of the shift register unit will not be increased due to the addition of T1.

[0202] As Figure 1 、 Figures 6 - 11 shown, the fourth node control circuit further includes a third transistor T3; the fourth transistor T4 is located on the side of the first first voltage line V11 away from the third transistor T3; the gate of the third transistor T3 is respectively coupled to a seventh conductive connection portion L7 and an eighth conductive connection portion L8, the seventh conductive connection portion L7 is coupled to the second clock signal line CK through a via, and the eighth conductive connection portion L8 is coupled to the gate G4 of the fourth transistor T4, so that the gate G4 of the fourth transistor T4 is coupled to the second clock signal line CK;

[0203] As Figures 6 - 11 shown, the gate G5 of the fifth transistor T5 is coupled to a tenth conductive connection portion L10, and the tenth conductive connection portion L10 is coupled to the first clock signal line CB through a twelfth via H12, so that the gate G5 of the fifth transistor T5 is coupled to the first clock signal line CB;

[0204] A32 (A32 serves as the second electrode of the third transistor T2) is coupled to the sixth conductive connection portion L6 through the seventh via hole H7. The gate G6 of the sixth transistor T6 is coupled to the eleventh conductive connection portion L11. The eleventh conductive connection portion L11 is coupled to the sixth conductive connection portion L6 through the thirteenth via hole H13, so that the gate G6 of the sixth transistor T6 is coupled to A32 (A32 serves as the second electrode of the third transistor).

[0205] In Figure 8 In at least one of the illustrated embodiments, L8 and G4 are integrally formed, G5 and L10 are integrally formed, and G6 and L11 are integrally formed.

[0206] In at least one embodiment of the present invention, that the fourth transistor T4 is located on a side of the first first voltage line V11 away from the third transistor T3 may mean that: the orthographic projection of the fourth transistor T4 on the substrate is located on a side of the orthographic projection of the first first voltage line V11 on the substrate away from the orthographic projection of the third transistor T3 on the substrate.

[0207] As Figure 1 、 Figures 6 - 11 As shown, the shift register unit further includes a third node control circuit; the first energy storage circuit includes a first capacitor C1; the third node control circuit includes a seventh transistor T7 and an eighth transistor T8; the eighth transistor T8 and the seventh transistor T7 are disposed between the first first voltage line V11 and the second voltage line V2;

[0208] As Figure 7 As shown, the seventh transistor T7 includes a seventh active pattern A7, and the eighth transistor T8 includes an eighth active pattern A8; the seventh active pattern A7 and the eighth active pattern A8 are integrally formed;

[0209] The eighth active pattern A8 includes a first eighth conductive portion A81, an eighth channel portion A83, and a second eighth conductive portion A82 arranged in sequence along a first direction; the first eighth conductive portion A81 is the first end of the eighth active pattern A8, and the second eighth conductive portion A82 is the second end of the eighth active pattern A8;

[0210] The seventh active pattern A7 includes a second seventh conductive portion, a seventh channel portion A73, and a first seventh conductive portion A71 arranged in sequence along the first direction; the second seventh conductive portion is the second end of the seventh active pattern A7, and the first seventh conductive portion A71 is the first end of the seventh active pattern A7;

[0211] The second seventh conductive part is multiplexed as the second eighth conductive part A82;

[0212] The first eighth conductive part A81 serves as the first electrode of the eighth transistor T8, and the second eighth conductive part A82 serves as the second electrode of the eighth transistor T8; the first seventh conductive part A71 serves as the first electrode of the seventh transistor T7, and the second seventh conductive part A72 serves as the second electrode of the seventh transistor T7;

[0213] As Figures 6 - 11 shown, the first eighth conductive part A81 is coupled to the twelfth conductive connection part L12 through the fourteenth via H14, and the twelfth conductive connection part L12 is coupled to the second voltage line V2, so that the first eighth conductive part A81 is coupled to the second voltage line V2;

[0214] The first seventh conductive part A71 is coupled to the thirteenth conductive connection part L13 through the fifteenth via H15, and the thirteenth conductive connection part L13 is coupled to the second plate C1b of the first capacitor C1 through the sixteenth via H16, so that the first seventh conductive part A71 is coupled to the second plate C1b of the first capacitor C1;

[0215] The first plate C1a of the first capacitor C1 is coupled to the gate G6 of the sixth transistor T6;

[0216] The gate G8 of the eighth transistor T8 is coupled to the fourteenth conductive connection part L14, the fourteenth conductive connection part L14 is coupled to the fifth conductive connection part L5 through the seventeenth via H17, and the fifth conductive connection part L5 is coupled to the second electrode of the first transistor T1 through the fifth via H5, so that the gate G8 of the eighth transistor T8 is coupled to the second electrode of the first transistor T1;

[0217] As Figure 8 shown, the gate G7 of the seventh transistor T7 is coupled to the gate G5 of the fifth transistor T5.

[0218] In Figures 6 - 11 at least one embodiment shown, V2 and L12 are integrally formed, C1a and G6 and G9 are integrally formed, G8 and L14 are integrally formed, and G7 and G5 are integrally formed.

[0219] In at least one embodiment of the present invention, A7 and A8 are formed by continuous semiconductor layers, at least a part of A7 extends along a first direction (the first direction may be a vertical direction), at least a part of A8 extends along the first direction, the orthographic projection of A7 on the substrate and the orthographic projection of A8 on the substrate are located above the orthographic projection of the first electrode plate of C1 on the substrate, and there is no orthographic projection of A7 on the substrate and orthographic projection of A8 on the substrate above the orthographic projection of A1 on the substrate, so as to ensure that the longitudinal dimension occupied by at least one embodiment of the shift register unit will not be increased due to the addition of T1.

[0220] In at least one embodiment of the present invention, the arrangement of the eighth transistor T8 and the seventh transistor T7 between the first first voltage line V11 and the second voltage line V2 may be: the orthographic projection of the eighth transistor T8 on the substrate and the orthographic projection of the seventh transistor T7 on the substrate are arranged between the orthographic projection of the first first voltage line V11 on the substrate and the orthographic projection of the second voltage line V2 on the substrate.

[0221] Optionally, as Figure 1 , Figures 6 - 11 shown, the shift register unit further includes a fifth node control circuit; the fifth node control circuit includes a ninth transistor T9;

[0222] As Figure 7 shown, the ninth transistor T9 includes a ninth active pattern A9, and at least a part of the ninth active pattern A9 extends along the first direction;

[0223] As Figures 6 - 11 shown, the ninth transistor T9 is located between the first capacitor C1 and the second voltage line V2;

[0224] The gate G9 of the ninth transistor T9 is coupled to the first electrode plate C1a of the first capacitor C1;

[0225] The ninth active pattern A9 includes a first ninth conductive part A91, a ninth channel part A93, and a second ninth conductive part A92 arranged in sequence along the first direction; the first ninth conductive part A91 is the first end of the ninth active pattern A9, and the second ninth conductive part A92 is the second end of the ninth active pattern A9;

[0226] The first ninth conductive part A91 serves as the first electrode of the ninth transistor T9, and the second ninth conductive part A92 serves as the second electrode of the ninth transistor T9;

[0227] The first ninth conductive part A91 is coupled to the fifteenth conductive connection part L15 through the eighteenth via hole H18. The gate G7 of the seventh transistor T7 is coupled to the sixteenth conductive connection part L16. The fifteenth conductive connection part L15 is coupled to the sixteenth conductive connection part L16 through the nineteenth via hole H19, so that the first ninth conductive part A91 is coupled to the gate G7 of the seventh transistor T7. The second ninth conductive part A92 is coupled to the thirteenth conductive connection part L13 through the twentieth via hole H20, so that the second ninth conductive part A92 is coupled to the second electrode plate C1b of the first capacitor C1.

[0228] In Figures 6 - 11 In at least one of the illustrated embodiments, G9 and C1a are integrally formed, and G7 and L16 are integrally formed.

[0229] In at least one embodiment of the present invention, T9 can be disposed between C1 and V2.

[0230] In at least one embodiment of the present invention, the fact that the ninth transistor T9 is located between the first capacitor C1 and the second voltage line V2 may mean that the orthographic projection of the ninth transistor T9 on the substrate is located between the orthographic projection of the first capacitor C1 on the substrate and the orthographic projection of the second voltage line V2 on the substrate.

[0231] Optionally, as Figure 1 , Figures 6 - 11 shown, the shift register unit further includes a third energy storage circuit, and the third energy storage circuit includes a third capacitor C3;

[0232] The orthographic projection of the first electrode plate C3a of the third capacitor C3 on the substrate, the orthographic projection of the second electrode plate C3b of the third capacitor C3 on the substrate and the orthographic projection of the second voltage line V2 on the substrate at least partially overlap;

[0233] The first electrode plate C3a of the third capacitor C3 is coupled to the seventeenth conductive connection part L17 through the twenty-first via hole H21, and the seventeenth conductive connection part L17 is coupled to the second eighth conductive part A82 through the twenty-second via hole H22, so that the first electrode plate C3a of the third capacitor C3 is coupled to the second eighth conductive part A82;

[0234] The second electrode plate C3b of the third capacitor C3 is coupled to the second voltage line V2 through the twenty-third via hole H23.

[0235] In specific implementation, the orthographic projection of the electrode plate of the third capacitor C3 on the substrate and the orthographic projection of the second voltage line V2 on the substrate at least partially overlap to save the occupied lateral space.

[0236] In at least one embodiment of the present invention, as Figure 1 , Figures 6 - 11 shown, the shift register unit further includes a first output circuit, a second output circuit, and a second first voltage line V12; the first output circuit includes a first output transistor T10, and the second output circuit includes a second output transistor T11; the first output transistor T10 and the second output transistor T11 are located between the second voltage line V2 and the second first voltage line V12, and the second first voltage line V12 is located on the side of the second voltage line V2 close to the display area.

[0237] In specific implementation, the first output transistor and the second output transistor are arranged between the second voltage line V2 and the second first voltage line V12, and V12 is arranged on the side of V2 close to the display area.

[0238] In at least one embodiment of the present invention, that the first output transistor T10 and the second output transistor T11 are located between the second voltage line V2 and the second first voltage line V12 may mean that: the orthographic projection of the first output transistor T10 on the substrate and the orthographic projection of the second output transistor T11 on the substrate are located between the orthographic projection of the second voltage line V2 on the substrate and the orthographic projection of the second first voltage line V12 on the substrate;

[0239] That the second first voltage line V12 is located on the side of the second voltage line V2 close to the display area may mean that: the orthographic projection of the second first voltage line V12 on the substrate is located on the side of the orthographic projection of the second voltage line V2 on the substrate close to the display area.

[0240] Optionally, as Figure 1 , Figures 6 - 11 shown, the shift register unit further includes a signal output line E1, a second energy storage circuit, and a third energy storage circuit; the second energy storage circuit includes a second capacitor C2, and the third energy storage circuit includes a third capacitor C3; the first electrode plate C2b of the second capacitor C2 is coupled to the second conductive connection portion L2;

[0241] The active layers of the first output transistor T10 and the second output transistor T11 are formed by a continuous semiconductor layer, and the semiconductor layer extends along the first direction;

[0242] The first electrode of the first output transistor T10 is coupled to the second electrode of the second output transistor T11, the first electrode of the first output transistor T10 is coupled to the eighteenth conductive connection portion L18, and the eighteenth conductive connection portion L18 is coupled to the signal output line E1 through the twenty-fourth via H24;

[0243] The second electrode D10 of the first output transistor T10 is coupled to the second first voltage line V12;

[0244] The first electrode S11 of the second output transistor T11 is coupled to the second voltage line V2;

[0245] The gate of the first output transistor T10 is coupled to the second conductive connection portion L2, and the gate of the second output transistor T11 is coupled to the first plate C3a of the third capacitor C3.

[0246] In Figures 6 - 11 In at least one of the illustrated embodiments, the first electrode of T10 and the second electrode of T11 are integrally formed, L18 and the first electrode of T10 are integrally formed, D10 and V12 are integrally formed, S11 and V2 are integrally formed, the gate of T10 and L2 are integrally formed, and the gate of T11 and C3a are integrally formed.

[0247] In at least one embodiment of the present invention, the first output transistor T10 and the second output transistor T11 are disposed between the second voltage line V2 and the second second voltage line V12, facilitating the coupling of the second electrode of T10 to V12 and the coupling of the first electrode of T11 to V2.

[0248] As Figures 6 - 11 shown, V12 is disposed on a side of V2 closer to the display area.

[0249] As Figure 6 and Figure 8 shown, in at least one embodiment of the present invention, the gate of T10 may include a first first output gate pattern G101 and a second first output gate pattern G102; the gate of T11 may include a first second output gate pattern G111 and a second second output gate pattern G112;

[0250] G111, G112, G101, and G102 are arranged in sequence along a first direction;

[0251] G111, G112, G101, and G102 all extend along a second direction;

[0252] G101 and G102 are coupled to each other, and G111 and G112 are coupled to each other.

[0253] The second electrode of the second output transistor T11 includes a first second electrode pattern D112; the first electrode of the first output transistor T10 includes a first first electrode pattern S101 and a second first electrode pattern S102 that are coupled to each other;

[0254] Multiplex S101 as the second second electrode pattern included in the second electrode of the second output transistor T11, such that the first electrode of T10 is coupled to the second electrode of T11.

[0255] In Figures 6 - 11 In at least one of the illustrated embodiments, G101 and G102 are integrally formed, G111 and G112 are integrally formed, and D112, S101, and S102 are integrally formed.

[0256] In a specific implementation, the active layer of the first output transistor may include at least two first output conductive portions and at least one first output channel portion disposed opposite to each other along a first direction; each of the first output channel portions is disposed between two adjacent first output conductive portions;

[0257] The first output channel portions correspond one-to-one with the first output gate patterns, and the orthographic projection of each of the first output channel portions on the substrate is located within the orthographic projection of the corresponding first output gate pattern on the substrate.

[0258] As Figure 7 shown, the one labeled 1011 is the first first output conductive portion, the one labeled 1012 is the second first output conductive portion, the one labeled 1013 is the third first output conductive portion, the one labeled 1021 is the first output channel portion, and the one labeled 1022 is the second output channel portion;

[0259] The one labeled 1111 is the first second output conductive portion, the one labeled 1112 is the second output conductive portion, the one labeled 1121 is the first second output channel portion, and the one labeled 1122 is the second second channel portion.

[0260] As Figures 6 - 11 shown, D112 is coupled to the first second output conductive portion 1111 through the twenty-fifth via H25, S11 is coupled to the second second output conductive portion 1112 through the twenty-sixth via H26, S101 is coupled to the first first output conductive portion 1011 through the twenty-seventh via H27, D10 is coupled to the second first output conductive portion 1012 through the twenty-eighth via H28, and S102 is coupled to the third first output conductive portion 1013 through the twenty-ninth via H29.

[0261] In at least one embodiment of the present invention, as Figure 1 、 Figures 6 - 11As shown, the shift register unit includes a first first voltage line V11, a second first voltage line V12, a second voltage line V2, a first clock signal line CB, a second clock signal line CK, a signal output line E1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first output transistor T10, and a second output transistor T11;

[0262] The gate G1 of the first transistor T1 is coupled to the first first voltage line V11, the first electrode of the first transistor T1 is coupled to the first plate C2a of the second capacitor C2, and the second electrode of the first transistor T1 is coupled to the gate G2 of the second transistor T2;

[0263] The gate G2 of the second transistor T2 is coupled to the second electrode of the first transistor T1;

[0264] The second plate C2b of the second capacitor C2 is coupled to the first clock signal line CB;

[0265] The first electrode of the third transistor T3 is coupled to the first first voltage line V11, the second electrode of the third transistor T3 is coupled to the second electrode D2 of the second transistor T2;

[0266] The gate G3 of the third transistor T3 is coupled to the first electrode of the second transistor T2;

[0267] The gate G4 of the fourth transistor T4 is coupled to the second clock signal line CB; the second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5; the first electrode of the fifth transistor T5 is coupled to the second electrode of the sixth transistor T6; the first electrode of the sixth transistor T6 is coupled to the second voltage line V2;

[0268] The gate G5 of the fifth transistor T5 is coupled to the first clock signal line CB, and the second electrode of the third transistor T3 is coupled to the gate G6 of the sixth transistor T6;

[0269] The first electrode of the eighth transistor T8 is coupled to the second voltage line V2, the first electrode of the seventh transistor T7 is coupled to the second plate C1b of the first capacitor C1, the first plate C1a of the first capacitor C1 is coupled to the gate G6 of the sixth transistor T6; the second electrode of the seventh transistor T7 is coupled to the second electrode of the eighth transistor T8;

[0270] The gate G8 of the eighth transistor T8 is coupled to the second electrode of the first transistor T1, and the gate G7 of the seventh transistor T7 is coupled to the gate G5 of the fifth transistor T5;

[0271] The first electrode of the ninth transistor T9 is coupled to the gate G7 of the seventh transistor T7, and the second electrode of the ninth transistor T9 is coupled to the second plate C1b of the first capacitor C1; the gate G9 of the ninth transistor T9 is coupled to the first plate C1a of the first capacitor C1;

[0272] The first plate C3a of the third capacitor C3 is coupled to the second electrode of the eighth transistor T8, and the second plate C3b of the third capacitor C3 is coupled to the second voltage line V2;

[0273] The first electrode of the first output transistor T10 is coupled to the second electrode of the second output transistor T11. The second electrode of the second output transistor T11 is coupled to the signal output line E1. The second electrode D10 of the first output transistor T10 is coupled to the second first voltage line V12. The first electrode S11 of the second output transistor T11 is coupled to the second voltage line V2; the gate of the first output transistor T10 is coupled to the first electrode of the first transistor T1, and the gate of the second output transistor T11 is coupled to the first plate C3b of the third capacitor C3;

[0274] The positive projection of the first plate C3a of the third capacitor C3 on the substrate, the positive projection of the second plate C3b of the third capacitor C3 on the substrate, and the positive projection of the second voltage line V2 on the substrate at least partially overlap.

[0275] As Figures 6 - 11 shown, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the first capacitor C1 are disposed between the first first voltage line V11 and the second voltage line V2. The second transistor T2, the third transistor T3, and the second capacitor C2 are disposed between the first second voltage line V12 and the first clock signal line CB;

[0276] The first clock signal line CB and the second clock signal line CK are disposed on a side of the first first voltage line V11 away from the second voltage line V2;

[0277] The first output transistor T10 and the second output transistor T11 are disposed between the second voltage line V2 and the second first voltage line V12; the second first voltage line V12 is disposed on a side of the second voltage line V2 away from the first first voltage line V11.

[0278] As Figures 6 - 11 shown, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are arranged in sequence along a first direction;

[0279] the eighth transistor T8, the seventh transistor T7, and the first capacitor C1 are arranged in sequence along the first direction;

[0280] the eighth transistor T8, the fourth transistor T4, and the third transistor T3 are arranged in sequence along a second direction;

[0281] the first capacitor C1, the first transistor T1, and the second transistor T2 are arranged in sequence along the second direction;

[0282] At least a part of the first clock signal line CB, at least a part of the second clock signal line CK, at least a part of the first first voltage line V11, at least a part of the second first voltage line V12, and at least a part of the second voltage line V2 extend along the first direction.

[0283] In at least one embodiment of the present invention, that the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the first capacitor C1 are disposed between the first first voltage line V11 and the second voltage line V2 may mean that: the orthographic projection of the first transistor T1 on the substrate, the orthographic projection of the fourth transistor T4 on the substrate, the orthographic projection of the fifth transistor T5 on the substrate, the orthographic projection of the sixth transistor T6 on the substrate, the orthographic projection of the seventh transistor T7 on the substrate, the orthographic projection of the eighth transistor T8 on the substrate, the orthographic projection of the ninth transistor T9 on the substrate, and the orthographic projection of the first capacitor C1 on the substrate are disposed between the orthographic projection of the first first voltage line V11 on the substrate and the orthographic projection of the second voltage line V2 on the substrate;

[0284] The second transistor T2, the third transistor T3 and the second capacitor C2 are arranged between the first second voltage line V12 and the first clock signal line CB, which may refer to: the orthographic projection of the second transistor T2 on the substrate, the orthographic projection of the third transistor T3 on the substrate and the orthographic projection of the second capacitor C2 on the substrate are arranged between the orthographic projection of the first second voltage line V12 on the substrate and the orthographic projection of the first clock signal line CB on the substrate;

[0285] The first clock signal line CB and the second clock signal line CK are arranged on a side of the first first voltage line V11 away from the second voltage line V2, which may refer to: the orthographic projection of the first clock signal line CB on the substrate and the orthographic projection of the second clock signal line CK on the substrate are arranged on a side where the orthographic projection of the first first voltage line V11 on the substrate is away from the orthographic projection of the second voltage line V2 on the substrate;

[0286] The first output transistor T10 and the second output transistor T11 being arranged between the second voltage line V2 and the second first voltage line V12 may refer to: the orthographic projection of the first output transistor T10 on the substrate and the orthographic projection of the second output transistor T11 on the substrate are arranged between the orthographic projection of the second voltage line V2 on the substrate and the orthographic projection of the second first voltage line V12 on the substrate;

[0287] The second first voltage line V12 being arranged on a side of the second voltage line V2 away from the first first voltage line V11 may refer to: the orthographic projection of the second first voltage line V12 on the substrate being arranged on a side of the orthographic projection of the second voltage line V2 on the substrate away from the orthographic projection of the first first voltage line V11 on the substrate.

[0288] Optionally, the display substrate of at least one embodiment of the present invention may further include a plurality of rows of pixel circuits disposed on the display area of the substrate, wherein the pixel circuits include a light emitting control terminal;

[0289] The shift register unit corresponds to at least one row of pixel circuits;

[0290] The shift register unit comprises a signal output line, and the signal output line of the shift register unit is coupled to the light emitting control end of the at least one row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control end of the at least one row of pixel circuits.

[0291] When manufacturing the display substrate according to at least one embodiment of the present invention, first, a semiconductor material layer is disposed on a substrate, and a patterning process is performed on the semiconductor material layer to form active layers of respective transistors; a schematic diagram of the active layer is as shown in Figure 7 shown;

[0292] A first gate insulating layer is fabricated on a side of the active layer facing away from the substrate;

[0293] On a side of the first gate insulating layer facing away from the active layer, a first gate metal layer is fabricated, and a patterning process is performed on the first gate metal layer, as shown in Figure 8 shown, to form gates of respective transistors included in the shift register unit, first electrodes of respective capacitors, and patterns for conductive connection;

[0294] Using the gates of the respective transistors as a mask, doping is performed on a portion of the active layer not covered by the gates, such that the portion of the active layer not covered by the gates is formed into a conductive portion, and the portion of the active layer covered by the gates is formed into a channel portion; the conductive portion serves as a first electrode or a second electrode; or, the conductive portion is coupled to the first electrode or the second electrode;

[0295] A second gate insulating layer is fabricated on a side of the first gate metal layer facing away from the substrate;

[0296] A second gate metal layer is disposed on a side of the second gate insulating layer facing away from the first gate metal layer, and a patterning process is performed on the second gate metal layer, as shown in Figure 9 shown, to form signal output lines, and second electrodes of respective capacitors in the shift register unit; an insulating layer is disposed on a side of the second gate metal layer facing away from the second gate insulating layer;

[0297] As shown in Figure 10 shown, a plurality of vias are disposed on the substrate provided with the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer, and the insulating layer;

[0298] A source-drain metal layer is disposed on a side of the insulating layer facing away from the second gate metal layer, and a patterning process is performed on the source-drain metal layer, as shown in Figure 11 shown, to form a start signal line ESTV, a first clock signal line CB, a second clock signal line CK, a first first voltage line V11, a second first voltage line V12, a second voltage line V2, a first electrode of a first output transistor T10, a second electrode of the first output transistor T10, a first electrode of a second output transistor T11, a second electrode of the second output transistor T11, and patterns for conductive connection.

[0299] The display device according to at least one embodiment of the present invention includes the display substrate according to at least one embodiment of the present invention.

[0300] The display device provided by at least one embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0301] Unless otherwise defined, the technical terms or scientific terms used in the present invention should have the ordinary meanings understood by those of ordinary skill in the art to which the present invention belongs. The "first", "second" and similar terms used in the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to indicate relative position relationships, and when the absolute position of the object being described changes, the relative position relationships may also change accordingly.

[0302] It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0303] In the description of the above embodiments, the specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0304] The above is the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A display substrate, characterized in that, It includes a substrate and a shift register unit disposed on the substrate; the shift register unit includes a first first voltage line, a second voltage line, an on-off control circuit, a first energy storage circuit, and a fourth node control circuit; the substrate includes an edge region and a display region, and the shift register unit is disposed in the edge region; the on-off control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor; the fourth node control circuit includes a second transistor; At least a part of the second voltage line and the first first voltage line extends along a first direction; The second voltage line, the first capacitor, the first transistor, the first first voltage line, and the second transistor are arranged along a second direction; the second transistor, the first first voltage line, the first transistor, the first capacitor, and the second voltage line are arranged in sequence along the direction close to the display region; The first direction intersects with the second direction; The shift register unit further includes a fifth node control circuit; the fifth node control circuit includes a ninth transistor; the gate of the ninth transistor is coupled to the first plate of the first capacitor; The ninth transistor is located between the first capacitor and the second voltage line; The shift register unit further includes a first output circuit, a second output circuit, and a second first voltage line; the first output circuit includes a first output transistor, and the second output circuit includes a second output transistor; the first output transistor and the second output transistor are located between the second voltage line and the second first voltage line, and the second first voltage line is located on the side of the second voltage line close to the display region.

2. The display substrate according to claim 1, wherein The first transistor includes a first active pattern, and at least a part of the first active pattern extends along the first direction; The gate of the first transistor is in a different layer from the first first voltage line; the gate of the first transistor is coupled to a first conductive connection portion, and the first conductive connection portion is coupled to the first first voltage line through a via.

3. The display substrate according to claim 1 or 2, characterized in that, The shift register unit further includes a first clock signal line, a second clock signal line, a second energy storage circuit, and a fourth node control circuit, and the second energy storage circuit includes a second capacitor; The second capacitor is located on the side of the first first voltage line away from the display region; The first clock signal line and the second clock signal line are located on the side of the second capacitor away from the first first voltage line.

4. The display substrate according to claim 3, characterized in that, The first plate of the second capacitor is coupled to a second conductive connection portion, and the first electrode of the first transistor is electrically connected to a third conductive connection portion through a via, and the third conductive connection portion is coupled to the second conductive connection portion through a via, so that the first electrode of the first transistor is coupled to the first plate of the second capacitor; The second plate of the second capacitor is coupled to a first connection conductive portion, and the first connection conductive portion is coupled to the first clock signal line through a via, so that the second plate of the second capacitor is coupled to the first clock signal line.

5. The display substrate according to claim 4, wherein A positive projection of a second electrode plate of the second capacitor on the substrate does not overlap with a positive projection of the first first voltage line on the substrate.

6. The display substrate according to claim 3, characterized in that, A gate of the second transistor is coupled to a fourth conductive connection portion; A second electrode of the first transistor is coupled to a fifth conductive connection portion through a via; The fourth conductive connection portion is coupled to the fifth conductive connection portion through a via, so that the second electrode of the first transistor is coupled to the gate of the second transistor.

7. The display substrate according to claim 3, wherein The fourth node control circuit further includes a third transistor; the third transistor is disposed between the first clock signal line and the first first voltage line; A first electrode of the third transistor is coupled to the first first voltage line, and a second electrode of the third transistor is coupled to a sixth conductive connection portion through a via; the sixth conductive connection portion is coupled to a second electrode of the second transistor through a via, so that the second electrode of the third transistor is coupled to the second electrode of the second transistor; A gate of the third transistor is coupled to a seventh conductive connection portion and an eighth conductive connection portion respectively, and the seventh conductive connection portion is coupled to the second clock signal line through a via; A first electrode of the second transistor is coupled to a ninth conductive connection portion through a via, and the ninth conductive connection portion is coupled to the eighth conductive connection portion through a via, so that the first electrode of the second transistor is coupled to the gate of the third transistor.

8. The display substrate according to claim 1, wherein The shift register unit further includes a first node control circuit; the second voltage line is located on a side of the first first voltage line close to the display area; the first node control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; the fourth transistor, the fifth transistor, and the sixth transistor are disposed between the first first voltage line and the second voltage line; The fourth transistor includes a fourth active pattern, the fifth transistor includes a fifth active pattern, and the sixth transistor includes a sixth active pattern; the fourth active pattern, the fifth active pattern, and the sixth active pattern are integrally formed; A first end of the sixth active pattern is coupled to the second voltage line; a second end of the fourth active pattern is coupled to the fifth conductive connection portion through a via.

9. The display substrate according to claim 8, wherein The fourth node control circuit further includes a third transistor; the fourth transistor is located on a side of the first first voltage line away from the third transistor; a gate of the third transistor is coupled to a seventh conductive connection portion and an eighth conductive connection portion respectively, the seventh conductive connection portion is coupled to the second clock signal line through a via, and the eighth conductive connection portion is coupled to a gate of the fourth transistor, so that the gate of the fourth transistor is coupled to the second clock signal line; A gate of the fifth transistor is coupled to a tenth conductive connection portion, and the tenth conductive connection portion is coupled to the first clock signal line through a via, so that the gate of the fifth transistor is coupled to the first clock signal line; The second electrode of the third transistor is coupled to the sixth conductive connection portion through a via. The gate of the sixth transistor is coupled to the eleventh conductive connection portion, and the eleventh conductive connection portion is coupled to the sixth conductive connection portion through a via, so that the gate of the sixth transistor is coupled to the second electrode of the third transistor.

10. The display substrate according to claim 8, wherein, The shift register unit further includes a third node control circuit; the first energy storage circuit includes a first capacitor; the third node control circuit includes a seventh transistor and an eighth transistor; the eighth transistor and the seventh transistor are disposed between the first first voltage line and the second voltage line; The seventh transistor includes a seventh active pattern, and the eighth transistor includes an eighth active pattern; the seventh active pattern and the eighth active pattern are integrally formed; The first end of the eighth active pattern is coupled to the twelfth conductive connection portion through a via, and the twelfth conductive connection portion is coupled to the second voltage line, so that the first end of the eighth active pattern is coupled to the second voltage line; The first end of the seventh active pattern is coupled to the thirteenth conductive connection portion through a via, and the thirteenth conductive connection portion is coupled to the second plate of the first capacitor through a via, so that the first end of the seventh active pattern is coupled to the second plate of the first capacitor; The first plate of the first capacitor is coupled to the gate of the sixth transistor; The gate of the eighth transistor is coupled to the fourteenth conductive connection portion, the fourteenth conductive connection portion is coupled to the fifth conductive connection portion through a via, and the fifth conductive connection portion is coupled to the second electrode of the first transistor through a via, so that the gate of the eighth transistor is coupled to the second electrode of the first transistor; The gate of the seventh transistor is coupled to the gate of the fifth transistor.

11. The display substrate according to claim 10, wherein The ninth transistor includes a ninth active pattern, and at least a part of the ninth active pattern extends in a first direction; The first end of the ninth active pattern is coupled to the fifteenth conductive connection portion through a via, the gate of the seventh transistor is coupled to the sixteenth conductive connection portion, and the fifteenth conductive connection portion is coupled to the sixteenth conductive connection portion through a via, so that the first end of the ninth active pattern is coupled to the gate of the seventh transistor; the second end of the ninth active pattern is coupled to the thirteenth conductive connection portion through a via, so that the second end of the ninth active pattern is coupled to the second plate of the first capacitor.

12. The display substrate according to claim 11, wherein The shift register unit further includes a third energy storage circuit, and the third energy storage circuit includes a third capacitor; The orthographic projection of the first plate of the third capacitor on the substrate, the orthographic projection of the second plate of the third capacitor on the substrate, and the orthographic projection of the second voltage line on the substrate at least partially overlap; The first plate of the third capacitor is coupled to the seventeenth conductive connection portion through a via, and the seventeenth conductive connection portion is coupled to the second end of the eighth active pattern through a via, so that the first plate of the third capacitor is coupled to the second end of the eighth active pattern; The second electrode plate of the third capacitor is coupled to the second voltage line through a via hole.

13. The display substrate according to claim 1, wherein The shift register unit further includes a signal output line, a second energy storage circuit, and a third energy storage circuit; the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor; the first electrode plate of the second capacitor is coupled to the second conductive connection portion; The active layer of the first output transistor and the active layer of the second output transistor are formed by a continuous semiconductor layer, and the semiconductor layer extends in the first direction; The first electrode of the first output transistor is coupled to the second electrode of the second output transistor, the first electrode of the first output transistor is coupled to the eighteenth conductive connection portion, and the eighteenth conductive connection portion is coupled to the signal output line through a via hole; The second electrode of the first output transistor is coupled to the second first voltage line; The first electrode of the second output transistor is coupled to the second voltage line; The gate of the first output transistor is coupled to the second conductive connection portion, and the gate of the second output transistor is coupled to the first electrode plate of the third capacitor.

14. The display substrate according to claim 1, characterized in that, The shift register unit includes a first first voltage line, a second first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a signal output line, a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first output transistor, and a second output transistor; The gate of the first transistor is coupled to the first first voltage line, the first electrode of the first transistor is coupled to the first electrode plate of the second capacitor, and the second electrode of the first transistor is coupled to the gate of the second transistor; The gate of the second transistor is coupled to the second electrode of the first transistor; The second electrode plate of the second capacitor is coupled to the first clock signal line; The first electrode of the third transistor is coupled to the first first voltage line, and the second electrode of the third transistor is coupled to the second electrode of the second transistor; The gate of the third transistor is coupled to the first electrode of the second transistor; The gate of the fourth transistor is coupled to the second clock signal line; the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor; the first electrode of the fifth transistor is coupled to the second electrode of the sixth transistor; the first electrode of the sixth transistor is coupled to the second voltage line; The gate of the fifth transistor is coupled to the first clock signal line, and the second electrode of the third transistor is coupled to the gate of the sixth transistor; The first electrode of the eighth transistor is coupled to the second voltage line, the first electrode of the seventh transistor is coupled to the second electrode plate of the first capacitor, and the first electrode plate of the first capacitor is coupled to the gate of the sixth transistor; the second electrode of the seventh transistor is coupled to the second electrode of the eighth transistor; The gate of the eighth transistor is coupled to the second electrode of the first transistor, and the gate of the seventh transistor is coupled to the gate of the fifth transistor; The first electrode of the ninth transistor is coupled to the gate of the seventh transistor, and the second electrode of the ninth transistor is coupled to the second plate of the first capacitor; The gate of the ninth transistor is coupled to the first plate of the first capacitor; The first plate of the third capacitor is coupled to the second electrode of the eighth transistor, and the second plate of the third capacitor is coupled to the second voltage line; The first electrode of the first output transistor is coupled to the second electrode of the second output transistor. The second electrode of the second output transistor is coupled to the signal output line. The second electrode of the first output transistor is coupled to the second first voltage line. The first electrode of the second output transistor is coupled to the second voltage line. The gate of the first output transistor is coupled to the first electrode of the first transistor. The gate of the second output transistor is coupled to the first plate of the third capacitor; The positive projection of the first plate of the third capacitor on the substrate, the positive projection of the second plate of the third capacitor on the substrate, and the positive projection of the second voltage line on the substrate at least partially overlap.

15. The display substrate according to claim 14, wherein The first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the first capacitor are disposed between the first first voltage line and the second voltage line. The second transistor, the third transistor, and the second capacitor are disposed between the first second voltage line and the first clock signal line; The first clock signal line and the second clock signal line are disposed on a side of the first first voltage line away from the second voltage line; The first output transistor and the second output transistor are disposed between the second voltage line and the second first voltage line. The second first voltage line is disposed on a side of the second voltage line away from the first first voltage line.

16. The display substrate according to claim 15, wherein The fourth transistor, the fifth transistor, and the sixth transistor are arranged in sequence along a first direction; The eighth transistor, the seventh transistor, and the first capacitor are arranged in sequence along the first direction; The eighth transistor, the fourth transistor, and the third transistor are arranged in sequence along a second direction; The first capacitor, the first transistor, and the second transistor are arranged in sequence along the second direction; At least a part of the first clock signal line, at least a part of the second clock signal line, at least a part of the first first voltage line, at least a part of the second first voltage line, and at least a part of the second voltage line extend along the first direction.

17. The display substrate according to claim 1, wherein The display substrate further includes a plurality of pixel circuits disposed on the display area of the substrate, and the pixel circuit includes a light emission control terminal; The shift register unit corresponds to at least one row of the pixel circuits; The shift register unit includes a signal output line, and the signal output line of the shift register unit is coupled to the light emission control terminal of the at least one row of pixel circuits for providing a light emission control signal to the light emission control terminal of the at least one row of pixel circuits.

18. A display device, characterized in that, Comprising a display substrate as described in any one of claims 1 to 17.

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