Apparatus comprising parallel pipelines and method of manufacturing the same

Abstract

This application relates to an apparatus including parallel pipelines and methods of manufacturing the same. Descriptions relate to methods, apparatuses, and systems of an apparatus. The apparatus can include (1) a read state circuit configured to control a schedule / timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate timing of data output from the parallel pipelines.

Description

Technical Field

[0001] The disclosed embodiments relate to devices, and more specifically, to semiconductor devices having mechanisms for managing data pipelines. Background Technology

[0002] A device (e.g., a processor, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and / or process information. For example, the device may include a memory device, such as a volatile memory device, a non-volatile memory device, or a combination thereof. Memory devices such as Dynamic Random Access Memory (DRAM) can utilize electrical energy to store and access data. For example, the memory device may include a DDR RAM device that implements a dual data rate (DDR) interfacing scheme (e.g., DDR4, DDR5, etc.) for high-speed data transfer.

[0003] With technological advancements and increasing applications in other fields, the market continuously seeks faster, more efficient, and smaller devices. To meet market demands, semiconductor devices are pushed to their limits through various improvements. Generally, device improvements may include increasing circuit density, increasing operating speed or otherwise reducing operating latency, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. However, such improvements can often pose challenges to subsequent data processing (e.g., due to a reduced time window for achieving the target transformation) and, if not handled properly, can introduce error sources into data transmission. Summary of the Invention

[0004] According to one aspect of this application, an apparatus is provided. The apparatus includes: an external clock circuit configured to receive an external clock having an external frequency, wherein the external clock is shared with an external device; a command circuit coupled to the external clock circuit and configured to receive a command from the external device; a set of pipelines coupled to the command circuit and configured to process data units according to the received command, wherein the set of pipelines includes even-numbered pipelines and odd-numbered pipelines, wherein the even-numbered pipelines and odd-numbered pipelines are configured to process alternating portions of stored data units according to even-numbered internal clocks and odd-numbered internal clocks, respectively; a read-state circuit coupled to the external clock circuit and the command circuit, the read-state circuit being configured to: identify the external clock as a sequence of alternating even-numbered pulses and odd-numbered pulses, wherein the even-numbered pulses are associated with the even-numbered internal clocks. The system includes: aligning the internal clock with the odd-numbered pulses and the odd-numbered internal clock; generating one or more enable signals to indicate whether the read command was received on an odd-numbered or even-numbered pulse of the external clock; and a timing control circuit coupled to the read state circuit and the set of pipelines, the timing control circuit being configured to: time-separate a first output sequence and a second output sequence corresponding to the first and second read commands respectively when the second received command follows the first received command with minimal separation; and maintaining the separation between the first read data and the second read data provided in response to the first read command and the second read command respectively when the first read command and the second read command are separated by an odd number of clock pulses of the external clock.

[0005] According to another aspect of this application, a system is provided. The system includes: a set of pipelines configured to process data units according to received commands, wherein the set of pipelines comprises N number of pipelines, each pipeline configured to process 1 / N portions of the data unit according to a corresponding internal clock having an internal frequency of 1 / N of an external frequency as an external clock; a processing state circuit configured to: identify the external clock as a sequence of N number of pulses, wherein each pulse in the sequence corresponds to one of the N number of pipelines; and generate one or more enable signals for each received command, wherein the one or more enable signals indicate the reception time of a corresponding command based on the position in the sequence of N number of pulses; and a timing control circuit coupled to the processing state circuit and the set of pipelines, the timing control circuit being configured to coordinate the combination of outputs from the N number of pipelines to correspond to an output sequence of the data unit, wherein the output sequence is controlled according to the one or more enable signals.

[0006] According to another aspect of this application, a method is provided. The method includes: processing each 1 / N portion of a data unit according to a received command and a corresponding internal clock having an internal frequency of 1 / N of an external frequency as an external clock; identifying the external clock as a sequence of N pulses, wherein each pulse in the sequence corresponds to one of N pipelines; generating one or more enable signals for each received command, wherein the one or more enable signals indicate the reception time of a corresponding command according to a position in the sequence of N pulses; and coordinating the combination of outputs from the N pipelines to correspond to an output sequence of the data unit, wherein the output sequence is controlled according to the one or more enable signals.

[0007] According to another aspect of this application, an apparatus is provided. The apparatus includes: an internal clock circuit configured to generate first and second internal clock signals based on an external clock signal (CK), wherein each of the first and second internal clock signals (DLL0, 180) has a frequency lower than the frequency of the external clock signal, and the phases of the first and second internal clock signals are offset from each other; and a read state circuit configured to: generate an even-number read enable signal (RS_E) in response to receiving a read command in an even-number clock cycle, the even-number read enable signal being configured to activate a first number of pulses of the first internal clock signal and a second number of pulses of the second internal clock signal, different from the first number; and generate an odd-number read enable signal (RS_O) in response to receiving the read command in an odd-number clock cycle, the odd-number read enable signal being configured to activate the second number of pulses of the first internal clock signal and the first number of pulses of the second internal clock signal. Attached Figure Description

[0008] Figure 1 This is a block diagram of a device according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram of a timing control circuit according to an embodiment of the present invention.

[0010] Figures 3A to 3C A timing diagram of the internal and external clocks according to an embodiment of the present invention is provided.

[0011] Figures 4A to 4B A timing diagram illustrating back-to-back commands according to an embodiment of the present invention is provided.

[0012] Figures 5A to 5B This describes a timing control circuit configured to use interleaved enable signals according to an embodiment of the present invention.

[0013] Figure 5CA timing diagram illustrating the interleaved enable signal according to an embodiment of the present invention is provided.

[0014] Figures 6A to 6C This describes a timing control circuit configured to use a chopper circuit according to an embodiment of the present invention.

[0015] Figure 6D A timing diagram of a chopper circuit according to an embodiment of the present invention is provided.

[0016] Figure 7 This is a flowchart illustrating an example method of operating a device according to an embodiment of the present invention.

[0017] Figure 8 This is a schematic diagram of a system including an apparatus according to an embodiment of the technology of the present invention. Detailed Implementation

[0018] As described in more detail below, the technology disclosed herein relates to a device, system having a memory device, and related methods for managing parallel pipelines, such as those used in memory systems. The device (e.g., a memory device and / or a system containing a memory device) may include a set of parallel data pipelines (e.g., even-numbered pipelines and odd-numbered pipelines) for processing data, for example, in response to a read command (e.g., a read burst). The device may use corresponding internal clocks (e.g., “even-numbered” clocks or DLL0, “odd-numbered” clocks or DLL180, etc.) with a reduced frequency relative to an external clock. The internal clocks may be phased with each other by a predetermined amount (e.g., 180°). The internal clocks can be used to coordinate the delivery timing of the device's output paths. In other words, the internal clocks can be used to output read data from the parallel pipelines to an external interface (e.g., a data (DQ) pad). Thus, even-numbered pipelines can process read data driven by even-numbered clocks, while odd-numbered pipelines can process read data driven by odd-numbered clocks.

[0019] As an illustrative example, an external device (e.g., a controller) may interact with a memory device (e.g., DDR memory) according to an external clock. Thus, the external device may issue a read command according to the external clock and receive the provided read data according to the external clock. In some embodiments, the memory device may implement N pipelines (e.g., two pipelines), each pipeline processing 1 / N of the read data (e.g., each of the two pipelines processes 1 / 2). The pipelines may operate according to a corresponding internal clock with a frequency of 1 / N of the external clock frequency. Therefore, parallel pipelines can be used to reduce the clock frequency of internal operations, thereby reducing and eliminating errors caused by increased clock speeds (e.g., signal switching rates exceeding corresponding time requirements).

[0020] Because read commands can be processed simultaneously using parallel data pipelines, the device may actually lose the granularity provided by the external clock. Therefore, the device can track which pipelines and internal clocks correspond to the first bit of the output data. For an illustrative example of two pipelines, the device can arbitrarily label alternating pulses of the external clock as even and odd pulses. Even-numbered pipelines and even-numbered internal clocks can correspond to even-numbered external clock pulses, and odd-numbered pipelines and odd-numbered internal clocks can correspond to odd-numbered external clock pulses. When processing a read command, the device can track the even / odd state of the external clock when receiving the read command. If a read command is received on an even-numbered clock pulse, the device can use an even-numbered enable signal (e.g., enabling even-numbered circuitry, "even-numbered pointer") to coordinate the delivery of the first bit of the output data. If a read command is received on an odd-numbered clock pulse, the device can use an odd-numbered enable signal (e.g., enabling odd-numbered circuitry, "odd-numbered pointer") to coordinate the delivery of the first bit of the output data.

[0021] Parallel pipelines may require additional consideration to handle back-to-back processes. When two read commands are separated by an odd number of clock pulses, the two read commands can begin at an alternating pipeline. Therefore, the device can alternate between even-numbered and odd-numbered enable signals to deliver data. As an illustrative example, a first read command can be received at an even-numbered clock pulse, and a second read command can be received at an odd-numbered clock pulse. Therefore, the first read command can begin on an even-numbered pipeline, and the second read command can begin on an odd-numbered pipeline. Alternatively, the device can initially use an even-numbered enable signal and then switch to using an odd-numbered enable signal. In such cases, timing conflicts may occur when processing the first and second read commands as the number of clock pulses separating the two read commands decreases. When insufficient or a threshold number of clock pulses separate the two read commands, the device may not have enough time to switch from one enable signal to the other, and the two enable signals may overlap. As described in more detail below, this conflict is referred to as a “gapless burst” or gapless switching. Without sufficient time gaps, even and odd clocks may fail to deliver bits of output data to the output path at the correct time, potentially leading to errors in the output data. For example, if gapless bursts are not handled properly, the last bit of the first output data may be ignored or merged with the leading bit of the second read command.

[0022] As described in detail below, embodiments of the present invention may include circuitry / functions configured to coordinate enable signals and coordinate bit outputs of parallel pipelines. For example, a device (e.g., a memory device) may include timing control circuitry configured to use (1) a set of interleaved enable signals, or (2) chopper circuitry for managing the timing of enable signals for parallel data pipelines.

[0023] Interleaved enable signals may comprise a sequential set of individual enable signals for each data pipeline that are interleaved in time (e.g., an even set with early and late even enable signals, and an odd set with early and late odd enable signals). For each pipeline, the timing control circuitry may use (1) an early enable signal to initiate and handle the delivery of the leading bit of the output data, and (2) a late enable signal to handle the delivery of the trailing bit of the output data. When using multiple enable signals, the early enable signal of one data pipeline may be offset or separated in time from the early enable signal of another data pipeline. Similarly, the late enable signal of one data pipeline may be offset from the late enable signal of another data pipeline. Therefore, the timing control circuitry may use the late enable signal to ensure that the correct trailing bit of the output data is delivered simultaneously or concurrently with the use of the early enable signal to transition between two read commands.

[0024] A chopper circuit removes the unused processing duration (e.g., the end clock pulse) of the current read command and applies it as a new preamble for the next read command. For example, when the output data contains cyclic redundancy check (CRC) data, the total number of bits cannot be divided by four (e.g., the remainder when dividing the total number of output bits by four is a positive / non-zero integer). This situation can also correspond to a maximum limit on the length of the output bits. Therefore, the chopper circuit removes the end duration after the maximum output length (e.g., a clock pulse matching a positive / non-zero integer remainder) and appends this end duration before the preamble of the next read command. Using a chopper circuit, the timing control circuit can ensure separation between the delivery of the end bit of the current read command and the delivery of the preamble of the next read command. Therefore, the timing control circuit can handle even and odd enable signals in gapless burst situations and ensure timely and error-free delivery of output data bits.

[0025] Figure 1 This is a block diagram of a device 100 (e.g., a semiconductor die assembly comprising a 3DI device or a die stacked package) according to an embodiment of the present invention. For example, device 100 may include DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.) or may include a portion of one or more dies / chips. In some embodiments, device 100 may include DDR-type synchronous DRAM (SDRAM) integrated on a single semiconductor chip.

[0026] Device 100 may include an array of memory cells, such as memory array 150. Memory array 150 may include multiple memory banks (e.g., memory banks 0 to 15), and each memory bank may include multiple word lines (WL), multiple bit lines (BL), and multiple memory cells arranged at the intersections of the word lines and bit lines. Memory cells may include any of several different memory media types, including capacitive, magnetoresistive, ferroelectric, phase-change, etc. The selection of word lines WL may be performed by row decoder 140, and the selection of bit lines BL may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit line BL, and the SAMP may be connected to at least one corresponding local I / O line pair (LIOT / B), which may then be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that can act as a switch. Memory array 150 may also include board lines and corresponding circuitry for managing the operation of the board lines.

[0027] Device 100 may employ multiple external terminals, including command terminals and address terminals respectively coupled to the command bus and address bus to receive command signals (CMD) and address signals (ADDR). Device 100 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals CK and CKF, data terminals DQ, RDQS, DBI, and DMI, and power supply terminals VDD, VSS, and VDDQ.

[0028] Address signals and memory address signals can be supplied from the outside to the command and address terminals. Figure 1 (Not shown in the diagram). The address signal and memory address signal supplied to the address terminal can be transmitted to the address decoder 110 via the command / address input circuit 105 (e.g., command circuit). The address decoder 110 can receive the address signal and supply the decoded row address signal (XADD) to the row decoder 140 and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the memory address signal (BADD) and supply the memory address signal to both the row decoder 140 and the column decoder 145.

[0029] Command signals (CMD), address signals (ADDR), and chip select signals (CS) can be supplied from the memory controller to command and address terminals. Command signals can represent various memory commands from the memory controller (e.g., access commands, which may include read and write commands). Chip select signals can be used to select device 100 to respond to commands and addresses supplied to the command and address terminals. When a valid chip select signal is provided to device 100, commands and addresses can be decoded, and memory operations can be performed. The command signals can be provided as internal command signals ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry for decoding internal command signals ICMD to generate various internal signals and commands for performing memory operations (e.g., row command signals for selecting word lines and column command signals for selecting bit lines). Command decoder 115 may further include one or more registers for tracking various counts or values ​​(e.g., counts of refresh commands received by device 100 or counts of self-refresh operations performed by device 100).

[0030] Read data can be read from memory cells in memory array 150 specified by row addresses (e.g., addresses provided with valid commands) and column addresses (e.g., addresses provided with read commands). Read commands can be received by command decoder 115, which provides internal commands to input / output circuitry 160, enabling read data to be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuitry 160 according to the RDQS clock signal. Read data can be provided at a time defined by read delay information RL, which is programmable in device 100, for example, programmed in a mode register (…). Figure 1 (Not shown in the text). The read delay information RL can be defined in terms of the clock pulses of the CK clock signal. For example, the read delay information RL can be the number of clock pulses of the CK signal after device 100 receives a read command when the associated read data is provided.

[0031] Write data can be supplied to data terminals DQ, DBI, and DMI. Write commands can be received by command decoder 115, which can provide internal commands to input / output circuitry 160, such that write data can be received by data receivers in input / output circuitry 160 and supplied to memory array 150 via input / output circuitry 160 and read / write amplifier 155. Write data can be written to memory cells specified by row and column addresses. Write data can be supplied to the data terminals at a time defined by write latency (WL) information. Write latency (WL) information is programmable in device 100, for example, programmed in a mode register (…). Figure 1(Not shown in the text). The write delay (WL) information can be defined in terms of the clock pulses of the CK clock signal. For example, the write delay (WL) information can be the number of clock pulses of the CK signal after the device 100 receives the write command when the associated write data is received.

[0032] Power supply potentials VDD and VSS can be supplied to the power supply terminals. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the line decoder 140, the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0033] A power supply potential VDDQ can also be supplied to the power supply terminals. The power supply potential VDDQ can be supplied together with the power supply potential VSS to the input / output circuit 160. In an embodiment of the invention, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of the invention, the power supply potential VDDQ can be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ can be used for the input / output circuit 160 so that power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0034] External clock signals and complementary external clock signals can be supplied to the clock terminal and the data clock terminal. External clock signals CK and CKF can be supplied to clock input circuit 120 (e.g., an external clock circuit). The CK and CKF signals are complementary. The complementary clock signals can have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0035] The input buffer included in clock input circuit 120 can receive an external clock signal. For example, the input buffer can receive a clock / enable signal when enabled by a clock / enable signal from command decoder 115. Clock input circuit 120 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can be enabled based on the internal clock signal ICLK received from command / address input circuit 105 and a clock signal (…). Figure 1 (Not shown in the image) to provide various phase and frequency-controlled internal clock signals. For example, the internal clock circuit 130 may include a clock path that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1 (Not shown). The internal clock circuit 130 may additionally provide input / output (I / O) clock signals. The I / O clock signals may be supplied to the input / output circuit 160 and may be used as timing signals to determine the output timing for reading data and the input timing for writing data. The I / O clock signals may be provided at multiple clock frequencies (e.g., half the frequency of the external clock signal) and / or different phases (e.g., providing I / O clock signals with phase shifts of 0, 90, 180, and / or 270 degrees from the external clock signal), allowing data to be output from and input to the device 100 at different data rates. Higher clock frequencies may be desirable when high memory speeds are desired. Lower clock frequencies may be desirable when lower power consumption is desired. The internal clock signal ICLK may also be supplied to a timing generator, and thus various internal clock signals can be generated.

[0036] Device 100 can be connected to any of several electronic devices or components thereof capable of temporarily or permanently storing information using memory. For example, the host device of device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or components thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of several other products. In one embodiment, the host device can be directly connected to device 100, but in other embodiments, the host device can be indirectly connected to a memory device (e.g., via a networking connection or via an intermediary device).

[0037] Command / address input circuitry 105 may include read status (RS) circuitry 190, configured to control the timing / schedule associated with parallel pipelines. In some embodiments, RS circuitry 190 may be configured to generate and control a set of enable signals (e.g., even-number enable signals and / or odd-number enable signals) based on a read command received at command / address input circuitry 105. RS circuitry 190 may provide the set of enable signals to timing control circuitry (TM) 195. When a read command is received at command / address input circuitry 105, RS circuitry 190 may determine whether the command was received on an even-number clock or an odd-number clock. Based on this determination, RS circuitry 190 may generate one or more corresponding enable signals to control the timing of corresponding operations across the even-number and / or odd-number pipelines. For example, when a read command is received on an even-number clock pulse, read status circuitry 190 may generate an even-number enable signal (e.g., RS_E) to indicate that a read command was received on an even-number pulse. When a read command is received on an odd-numbered clock pulse, the read status circuit 190 can generate an odd-numbered enable signal (e.g., RS_0) to indicate that a read command has been received on an odd-numbered pulse. In some embodiments, circuit 190 can be a processing status circuit. The processing status circuit can be configured to generate and control the set of enable signals in a manner similar to that of an RS circuit based on a read or write command received at command / address input circuit 105.

[0038] In some embodiments (e.g., when the timing control circuitry 195 is implemented with an interleaved enable mechanism), the read status circuitry 190 and / or the timing control circuitry 195 may be configured to generate one or more additional enable signals for each data pipeline. For example, if a read command is received on an even-numbered clock, the read status circuitry 190 and / or the timing control circuitry 195 may generate a first even-numbered enable signal (e.g., RS_E1), followed by a second even-numbered enable signal (e.g., RS_E2). If a read command is received on an odd-numbered clock, the read status circuitry 190 may generate a first odd-numbered enable signal (e.g., RO_E1), followed by a second odd-numbered enable signal (e.g., RS_O2).

[0039] Input / output circuitry 160 may include timing control circuitry 195 configured to use data enable signals to coordinate the output of data from parallel pipelines. For example, in response to an even-numbered enable signal, timing control circuitry 195 may use DLL0 (even-numbered clock) to output data from even-numbered pipelines as the first output data (via, for example, a DQ pad). For an odd-numbered enable signal, timing control circuitry 195 may use DLL180 (odd-numbered clock) to output data from odd-numbered pipelines as the first output data.

[0040] Figure 2It is a timing control circuit according to an embodiment of the present invention (e.g., Figure 1 A block diagram 200 of a timing control circuit 195 is provided. The timing control circuit 195 may include an even-numbered circuit 202 that operates in response to or corresponding to an even-numbered enable signal, and an odd-numbered circuit 212 that operates in response to or corresponding to an odd-numbered enable signal. The even-numbered circuit 202 can be utilized when a read command is received on an even-numbered pulse of an external clock. For the even-numbered circuit 202, the timing control circuit 195 may generate an even-numbered enable signal RS_E. The even-numbered enable signal RS_E may indicate that the read command begins on an even-numbered pipeline, and that the clock signal DLL0 of the even-numbered clock delivers the first bit of the read data. The even-numbered circuit 202 may include a shift register 204 configured to perform shift operations synchronized with the clock signal DLL0 (e.g., an even-numbered clock) and the clock signal DLL180 (e.g., an odd-numbered clock). The shift register 204 may contain n stages of flip-flop circuitry (FF_1 to FF_n) connected in cascade and / or parallel, and may be controlled by an even-numbered enable signal RS_E.

[0041] In some embodiments, shift register 204 may include eight stages of flip-flop circuits (FF_1 to FF_8 of even-numbered circuits 202), wherein flip-flop circuits FF_1 to FF_4 are cascaded and flip-flop circuits FF_5 to FF_8 are connected in parallel. Clock signal DLL0 may normally be input to the clock nodes of flip-flop circuits FF_1 to FF_4, while clock signal DLL180 may normally be input to the clock nodes of flip-flop circuits FF_5 to FF_8. When clock signal DLL0 is activated, even-numbered enable signal RS_E controls the operation of the first-stage flip-flop circuit FF_1, and even-numbered enable signal RS_E may be shifted to the subsequent stages of flip-flop circuits FF_2 to FF_8. Even-numbered enable signal RS_E may then control the operation of FF_2 to FF_4 in response to the activation of clock signal DLL0, and even-numbered enable signals RS_E at FF_5 to FF_8 may be latched in response to the activation of clock signal DLL180. In some embodiments, even-numbered circuit 202 may enable cyclic redundancy check (CRC), and shift register 204 may include two additional stages of flip-flop circuits FF_9 and FF_10. When CRC is enabled, timing control circuit 195 may generate or receive an RdCRC enable signal. The RdCRC enable signal may control the operation of the last two stages of flip-flop circuits FF_9 and FF_10 in response to the activation of clock signals DLL0 and DLL180, respectively.

[0042] Even-numbered enable signals RS_E and RdCRC enable signals, which control the operation of flip-flop circuits FF_1 to FF_4 and FF_9 in response to the activation of clock signal DLL0, can form the sequence RdClk0_E[0:4] of clock signal elements 0 to 4. Even-numbered enable signals RS_E and RdCRC enable signals, latched by flip-flop circuits FF_5 to FF_8 and FF_10 in response to the activation of clock signal DLL180, can form the sequence RdClk180_E[0:4] of clock signal elements 0 to 4. Timing control circuit 195 can then supply RdClk0_E[0:4] to merging circuit 208 and RdClk180_E[0:4] to merging circuit 218. Even-numbered circuit 202 can begin generating RdClk0_E[0:4] before RdClk180_E[0:4] because the read command is received on an even-numbered clock. Therefore, the first bit of the read output can be the first bit generated by the even-numbered pipeline.

[0043] Odd circuit 212 can be used when a read command is received on an odd pulse of an external clock. For odd circuit 212, timing control circuit 195 can generate an odd enable signal RS_O. The odd enable signal RS_O indicates that the read command begins on an odd pipeline, and that the clock signal DLL180 of the odd clock delivers the first bit of the read data. Odd circuit 212 may include a shift register 214 configured to perform shift operations synchronized with clock signal DLL180 (e.g., an odd clock) and clock signal DLL0 (e.g., an even clock). Shift register 214 may include n stages of flip-flops (FF_1 to FF_n) connected in cascade and / or parallel configurations and can be controlled by the odd enable signal RS_O.

[0044] In some embodiments, shift register 214 may include eight stages of flip-flop circuitry (FF_11 to FF_18 of odd-numbered circuitry 212), wherein flip-flop circuitry FF_11 to FF_14 are cascaded and flip-flop circuitry FF_15 to FF_18 are connected in parallel. Clock signal DLL180 may be normally input to the clock nodes of flip-flop circuitry FF_11 to FF_14, while clock signal DLL0 may be normally input to the clock nodes of flip-flop circuitry FF_15 to FF_18. When clock signal DLL180 is activated, odd-numbered enable signal RS_0 controls the operation of the first-stage flip-flop circuitry FF_11, and odd-numbered enable signal RS_0 may be shifted to the subsequent stages of flip-flop circuitry FF_12 to FF_18. Odd-numbered enable signal RS_0 may then control the operation of FF_12 to FF_14 in response to the activation of clock signal DLL180, and odd-numbered enable signals RS_0 at FF_15 to FF_18 may be latched in response to the activation of clock signal DLL0. In some embodiments, odd-numbered circuit 212 may enable cyclic redundancy check (CRC), and shift register 214 may include two additional stages of flip-flop circuits FF_19 and FF_20. When CRC is enabled, timing control circuit 195 may generate or receive an RdCRC enable signal (e.g., read the CRC enable signal). The RdCRC enable signal may control the operation of the last two stages of flip-flop circuits FF_19 and FF_20 in response to the activation of clock signals DLL180 and DLL0, respectively.

[0045] In response to the activation of clock signal DLL180, the odd enable signals RS_O and RdCRC enable signals latched by flip-flop circuits FF_11 to FF_14 and FF_19 can form the sequence RdClk180_O[0:4] of clock signal elements 0 to 4. In response to the activation of clock signal DLL0, the odd enable signals RS_O and RdCRC enable signals latched by flip-flop circuits FF_15 to FF_18 and FF_20 can form the sequence RdClk0_O[0:4] of clock signal elements 0 to 4. Timing control circuit 195 can subsequently supply the sequence RdClk180_O[0:4] to merging circuit 218 and the sequence RdClk0_O[0:4] to merging circuit 208. Merging circuit 208 can output the sequence RdClk0[0:4], while merging circuit 218 can output the sequence RdClk180[0:4]. Odd-numbered circuit 212 can begin generating RdClk180_O[0:4] before RdClk0_O[0:4] because the read command is received on an odd-numbered clock. Therefore, the first bit of the read output can be the first bit generated by the odd-numbered pipeline.

[0046] Merging circuits 208 and 218 may each be configured to include a set of logic gates that combine outputs from even and odd circuits to generate a coordinated clock signal for the corresponding pipeline. For example, merging circuit 208 may include a circuit system for combining RdClk0_E[0:4] and RdClk0_O[0:4] to generate RdClk0[0:4]. In some embodiments, merging circuits 208 and 218 may each include a set of OR gates that receive corresponding coordinated bits (e.g., RdClk bits 0 to 3) from even and odd circuits. Thus, the merging circuits may allow valid clock bits from either the even or odd circuit to pass as a read clock.

[0047] The number of OR gates in merging circuits 208 and 218 can correspond to the number of flip-flop circuits in shift registers 204 and 214. For example, if shift registers 204 and 214 each contain n levels of flip-flop circuits, then merging circuits 208 and 218 can each be configured with n OR gates.

[0048] Figures 3A to 3C A timing diagram of the internal and external clocks according to an embodiment of the present invention is provided. Figure 3A A timing diagram 300A illustrates the internal clock signals DLL0, DLL90, DLL180, and DLL270, and the external clock signal CLK, according to embodiments of the present invention. Clock circuit (e.g., Figure 1 The clock input circuit 120 can process an external clock signal CLK generated by an external device according to an external frequency. The RS circuit 190 can identify the external clock signal as a repeating sequence of N clock pulses. Each pulse in the sequence can correspond to one of N pipelines that process data according to a command received at command circuit 105. In some embodiments, the external clock signal CLK can be a sequence of two clock pulses, where each pulse in the repeating sequence of two pulses can correspond to one of two pipelines (e.g., an even number of pipelines or an odd number of pipelines). For illustrative purposes, embodiments of the invention will be described using a two-pipeline configuration where N = 2 and the external clock corresponds to both even and odd pulses. However, it should be understood that the device can be implemented with any number of pipelines (i.e., N > 2).

[0049] In some embodiments, such as for a DDR device, the internal clock circuit 130 may generate internal clock signals DLL0, DLL90, DLL180, and DLL270 based on an external clock signal CLK. Each internal clock signal may have an internal frequency that is 1 / N of the external frequency. In some embodiments, when the external clock signal CLK is a sequence of two pulses corresponding to two pipelines, the internal frequency may be 1 / 2 of the external frequency (e.g., when N = 2). Each internal clock signal may be phase-shifted relative to each other by a predetermined amount. For example, DLL90 may be phase-shifted by 90 degrees from DLL0, DLL180 may be phase-shifted by 90 degrees from DLL90, and DLL270 may be phase-shifted by 90 degrees from DLL180. As an illustrative example, DLL0 may be aligned with the rising edge of a first external clock pulse, and DLL90 may be aligned with the falling edge of a first external clock pulse. Similarly, DLL180 may be aligned with the rising edge of a second external clock pulse that immediately follows the first external clock pulse, and DLL270 may be aligned with the falling edge of the second external clock pulse. For DDR implementations, each of DLL0, DLL90, DLL180, and DLL270 can be used to coordinate data communication (e.g., reading data) between the memory device and the controller / host.

[0050] Figure 3B The description corresponds to the embodiments of the present invention. Figure 2 Timing diagram 300B illustrates the even-numbered circuit 202. Timing diagram 300B may illustrate internal clock signals DLL0 and DLL180 and an external clock signal CLK. In some embodiments, the external clock signal CLK may be a sequence of two clock pulses having an even-numbered clock pulse and an odd-numbered clock pulse. In other words, the external clock signal CLK may be identified as a sequence of alternating even-numbered and odd-numbered clock pulses. The even-numbered clock pulses of the external clock signal CLK may be aligned with the even-numbered internal clock or DLL0, and the odd-numbered clock pulses of the external clock signal CLK may be aligned with the odd-numbered internal clock or DLL180. Although not shown in timing diagram 300B, the falling edges of the even-numbered and odd-numbered pulses may be aligned with DLL90 and DLL270 described above.

[0051] For the example illustrated by timing diagram 300B, command circuit 105 can receive a read command (RD) on an even-numbered clock pulse from an external source. In response to receiving RD, RS circuit 190 can generate an even-numbered enable signal RS_E. For a DDR implementation, the even-numbered pipeline can receive the even-numbered enable signal and process bits 0, 1, 4, 5, 8, 9, 12, 13, 16, and 17 of the data stored at the address accompanying RD. The odd-numbered pipeline can process bits 2, 3, 6, 7, 10, 11, 14, and 15 of the stored data unit. In other words, the even-numbered pipeline can process a portion of the bits of the stored data unit, and the odd-numbered pipeline can process another portion of the bits of the stored data unit. The even-numbered enable signal RS_E can mark / indicate that DLL0 delivers the first bit of the read data provided in response to the received command RD (e.g., DLL0 delivers bit 0).

[0052] In some embodiments, RS circuit 190 may generate an even number of enable signals RS_E within one or more clock pulses following the receipt of command RD. For example, in timing diagram 300B, an even number of enable signals RS_E may be generated within two clock pulses following the receipt of command RD.

[0053] Timing control circuitry 195 can be configured to coordinate a sequence controlled by an even-number enable signal RS_E and an odd-number enable signal RS_O, which is used to combine outputs from the pipeline to correspond to data units. In response to the even-number enable signal RS_E marking / indicating DLL0 to deliver the first bit of read data, even-number clock DLL0 and odd-number clock DLL180 can be used to deliver different portions of the read data. The device can use DLL0 to deliver bits 0, 4, 8, 12, and 16, which are positioned or aligned in conjunction with the rising edge of an even-number clock pulse of the external clock signal CLK. The device can use DLL180 to deliver bits 2, 6, 10, and 14, which are positioned or aligned in conjunction with the rising edge of an odd-number clock pulse of the external clock signal CLK. In timing diagram 300B, the first bit or bit 0 can be selected based on the receipt of the even-number enable signal RS_E. The selected bit can be driven on the next rising edge of DLL0. In other words, bit 0 can be driven by one or more clock pulses after being selected. Accordingly, bits 1 through 16 are also driven by one or more clock pulses after being selected.

[0054] Figure 3C The description corresponds to the embodiments of the present invention. Figure 2Timing diagram 300C for odd-numbered circuit 212. Timing diagram 300C illustrates internal clock signals DLL0 and DLL180 and an external clock signal CLK. In some embodiments, the external clock signal CLK may be a sequence of two clock pulses having an even-numbered clock pulse and an odd-numbered clock pulse. In other words, the external clock signal CLK may be identified as a sequence of alternating even-numbered and odd-numbered clock pulses. The even-numbered clock pulses of the external clock signal CLK may be aligned with the even-numbered internal clock or DLL0. The odd-numbered clock pulses of the external clock signal CLK may be aligned with the odd-numbered internal clock or DLL180. Although not shown in timing diagram 300C, the falling edges of the even-numbered and odd-numbered pulses may be aligned with DLL90 and DLL270 described above.

[0055] For the example illustrated by timing diagram 300C, command circuit 105 can receive a read command RD on an odd-numbered clock pulse from, for example, an external device. In response to receiving RD, RS circuit 190 can generate an odd-numbered enable signal RS_O. For a DDR implementation, the odd-numbered pipeline can receive the odd-numbered enable signal RS_O and process bits 0, 1, 4, 5, 8, 9, 12, 13, 16, and 17 of the data stored at the address accompanying RD. The even-numbered pipeline can process bits 2, 3, 6, 7, 10, 11, 14, and 15 of the stored data unit. In other words, the odd-numbered pipeline can process a portion of the bits of the stored data unit, and the even-numbered pipeline can process another portion of the bits. The odd-numbered enable signal RS_O can mark / indicate that DLL 180 delivers the first bit of the read data provided in response to the received command RD (e.g., DLL 180 delivers bit 0).

[0056] In some embodiments, RS circuit 190 may generate an odd-numbered enable signal RS_O within one or more clock pulses following the receipt of command RD. For example, in timing diagram 300C, an odd-numbered enable signal RS_O may be generated within two clock pulses following the receipt of command RD.

[0057] Timing control circuitry 195 can be configured to coordinate a sequence controlled by an even-number enable signal RS_E and an odd-number enable signal RS_O, which is used to combine outputs from N pipelines to correspond to data units. In response to the odd-number enable signal RS_O marking / indicating that DLL180 delivers the first bit of read data, odd-number clock DLL180 and even-number clock DLL0 can be used to deliver different portions of the read data. The device can use DLL180 to deliver bits 0, 4, 8, 12, and 16, which are positioned or aligned with the rising edge of an odd-number clock pulse of the external clock signal CLK. The device can use DLL0 to deliver bits 2, 6, 10, and 14, which are positioned or aligned with the rising edge of an even-number clock pulse of the external clock signal CLK. In timing diagram 300C, the first bit or bit 0 can be selected based on the receipt of the odd-number enable signal RS_O. The selected bit can be driven on the next rising edge of DLL180. In other words, bit 0 can be driven by one or more clock pulses after being selected. Accordingly, bits 1 through 16 are also driven by one or more clock pulses after being selected.

[0058] Figures 4A to 4B A timing diagram illustrating back-to-back commands according to an embodiment of the present invention is provided. The timing diagram illustrates the operation of a parallel pipeline in response to two received commands (e.g., a read command). When a back-to-back command is received on a matching pulse, for example, arriving with an even-numbered pulse, the enable signal can remain on, and the same circuitry can be used to coordinate the output. In contrast, when a back-to-back command is received on different pulses (e.g., even for the preceding command and odd for the following command), the device may need to switch processing circuitry or pipeline coordination. Therefore, Figures 4A to 4B This can describe the operation for non-matching arrivals of back-to-back commands.

[0059] Figure 4A The diagram 400A illustrates the timing of back-to-back commands received under fully separated conditions. Figure 1 The command circuit 105 can receive the first command RD0 on an even-numbered clock pulse of the external clock CLK. In response to receiving the first command RD0 on an even-numbered clock pulse, the RS circuit 190 can generate... Figure 2An even-numbered enable signal RS_E is generated. The even-numbered enable signal RS_E coordinates the read data output, as described above. The even-numbered enable signal RS_E can then form an envelope around a burst of read data (e.g., first read data) provided by the first command RD0, and can be used to deliver bits of the read data. An odd number of clock pulses after receiving the first command RD0, the command circuit 105 can receive a second read command RD1 on an odd-numbered clock pulse of the external clock CLK. In response to the second command RD1, the RS circuit 190 can generate an odd-numbered enable signal RS_O to coordinate the read data output. In other words, the device 100 can switch from using an even-numbered enable signal to an odd-numbered enable signal. The odd-numbered enable signal RS_O can then form an envelope around a burst of read data (e.g., second read data) provided by the second command RD1, and can be used to deliver bits of the read data.

[0060] In some embodiments, due to the delay between generating the enable signal and issuing the burst of read data, a separation margin may exist between the time the enable signal is generated and the time the burst of read data is driven or output from the memory device. Similarly, a separation margin may exist between the time the enable signal is deactivated and the time the burst of read data is completed. The larger the delay and time difference, the larger the margin. The smaller the delay and time difference, the smaller the margin. Therefore, the enable signal can be generated before issuing the burst to ensure that the enable signal can encompass all bits of the read data.

[0061] In timing diagram 400A, a first command RD0 and a second command RD1 can be received with sufficient separation. Sufficient separation is achieved when the corresponding number of clock pulses meets a predetermined threshold, which may be associated with the duration required to execute the command (e.g., the output bit length). In some embodiments, when cyclic redundancy check (CRC) is not enabled, the two commands are sufficiently separated when at least eight clock pulses separate the first command RD0 from the second command RD1. When CRC is enabled, the two commands are sufficiently separated when at least nine clock pulses separate the first command RD0 from the second command RD1 to account for CRC data. Due to the sufficient separation between the two commands, device 100 has sufficient time to switch from one enable signal to another (e.g., from an even enable signal to an odd enable signal, or vice versa) and maintain the separation between the first read data and the second read data. Therefore, device 100 can correctly deliver all bits of the first read data using the first enable signal and then promptly switch to delivering all bits of the second read data using the second enable signal. In other words, when there is sufficient separation between the two commands, the first enable signal can always encompass the entire burst of bits of data read by the first command, and the second enable signal can always encompass the entire burst of bits of data read by the second command.

[0062] For example, as shown in timing diagram 400A, when the first command RD0 is received on an even-numbered pulse, RS circuit 190 can first generate an even-numbered enable signal RS_E. Device 100 can then use the even-numbered enable signal to deliver bits of the first read data. RS circuit 190 can then receive the second command RD1 on an odd-numbered pulse and subsequently generate an odd-numbered enable signal RS_O. Because there is sufficient separation between the first command RD0 and the second command RD1, device 100 has completed delivering all bits of the first read data when using the odd-numbered enable signal RS_O. Therefore, device 100 can use the odd-numbered enable signal RS_O to deliver all bits of the second read data without conflicting with the delivery of the first read data. Although timing diagram 400A shows a scenario where a command received on an even-numbered pulse is followed by a command received on an odd-numbered pulse, a similar scenario can occur where a first command is received on an odd-numbered pulse followed by a second command received on an even-numbered pulse. Therefore, RS circuit 190 can generate an odd-numbered enable signal RS_O for the first command and an even-numbered enable signal RS_E for the second command. Device 100 can use the odd-numbered enable signal RS_O to deliver bits of the first read data and the even-numbered enable signal RS_E to deliver bits of the second read data.

[0063] Figure 4B The illustration shows a timing diagram 400B illustrating back-to-back commands received without sufficient separation. In some embodiments, timing conflicts may occur when consecutively received commands are separated by a certain number of clock pulses, such as nine clock pulses (e.g., corresponding to 10 output data units) when a CRC read is required. In such cases, device 100 may not have enough time to switch from one enable signal to another (e.g., from an even enable signal to an odd enable signal, or vice versa). For example, the last bit of the first read data (e.g., provided by the first command RD0) may correspond to the first enable signal (e.g., the even enable signal RS_E), while the leading bit of the second read data (e.g., provided by the second command RD1) may correspond to the second enable signal (e.g., the odd enable signal RS_O). Therefore, device 100 may not have enough time to deliver all the first read data before switching to the second enable signal. In other words, when there is insufficient separation between the two commands, the first enable signal cannot encompass the entire burst of bits of the first read data. Both even and odd enable signals can be activated simultaneously. Figure 2The circuitry includes both even and odd outputs, thus simultaneously delivering both even and odd outputs to the merging circuitry. Simultaneous output delivery can cause output conflicts and corruption at the merging circuitry. Insufficient separation can be termed gapless burst scenario 402 or gapless switching, where, when a switch to the second enable signal occurs, the last bit of the first read data may be ignored or merged with the leading bit of the second read data.

[0064] For example, as shown in timing diagram 400B, when the first command RD0 is received on an even-numbered pulse, RS circuit 190 may first generate an even-numbered enable signal RS_E. Device 100 may then use the even-numbered enable signal to deliver bits of the first read data. RS circuit 190 may then receive the second command RD1 on an odd-numbered pulse and subsequently generate an odd-numbered enable signal RS_O. Due to insufficient separation between the first command RD0 and the second command RD1, device 100 has not yet completed delivering all bits of the first read data when using the odd-numbered enable signal RS_O. Nevertheless, device 100 continues to use the odd-numbered enable signal RS_O to deliver bits of the second read data, resulting in the last bit of the first read data not being delivered or being merged with the leading bit of the second read data. Gapless burst scenario 402 can lead to errors or corruption in the output data. Although the timing diagram 400B shows a scenario where a command received on an even-numbered pulse is followed by a command received on an odd-numbered pulse, a similar scenario can occur where a first command is received on an odd-numbered pulse followed by a second command received on an even-numbered pulse. Therefore, RS circuit 190 can generate an odd-numbered enable signal RS_O for the first command and an even-numbered enable signal RS_E for the second command. Device 100 can use the odd-numbered enable signal RS_O to deliver bits of the first read data and the even-numbered enable signal RS_E to deliver bits of the second read data.

[0065] Figures 5A to 5B A timing control circuit 195 configured to use interleaved enable signals according to an embodiment of the present invention is described. Figure 5A This is a block diagram 500A of a timing control circuit 195 configured to use interleaved enable signals RS_E1 552, RS_E2 554, RS_O1 562 and RS_O2 564 according to an embodiment of the present invention. Figure 1The device 100 may include an interleaved enable generator 501 configured to generate RS_E1 552, RS_E2 554, RS_O1 562, and / or RS_O2 564. The interleaved enable generator 501 may include logic and drivers for generating RS_E1 552, RS_E2 554, RS_O1 562, and / or RS_O2 564. For example, the interleaved enable generator 501 may include logic and / or delay circuitry configured to generate RS_E2 554 or RS_O2 564 after a predetermined delay duration following RS_E1 552 or RS_O1 562, respectively.

[0066] In some embodiments, RS circuit 190 may include interleaved enable generator 501. For example, when a read command is received on an even-numbered clock pulse, RS circuit 190 may use interleaved enable generator 501 to send RS_E1 552 and subsequently RS_E2 554 to timing control circuit 195. Alternatively, when a read command is received on an odd-numbered clock pulse, RS circuit 190 may send RS_O1 562, followed by RS_O2 564. In other embodiments, timing control circuit 195 may include interleaved enable generator 501. RS circuit 190 may generate a first enable signal or trigger signal and send it to interleaved enable generator 501. Interleaved enable generator 501 may respond by generating interleaved enable signals, as described above.

[0067] The timing control circuit 195 may include an interleaved even-number circuit 502 that operates in response to or corresponding to an even-number enable signal, and an interleaved odd-number circuit 512 that operates in response to or corresponding to an odd-number enable signal. The interleaved even-number circuit 502 may be used when a command is received on an even-number pulse of an external clock.

[0068] The interleaved even-number circuit 502 may include shift registers 504 and 510, each configured to perform shift operations synchronized with an even-number clock signal DLL0 and an odd-number clock signal DLL180. Shift registers 510 and 504 may each include a predetermined number of cascaded and / or parallel-connected flip-flops, controlled by an early even-number enable signal RS_E1 and a late even-number enable signal RS_E2, respectively. Shift register 510 may be operated or enabled according to RS_E1 552, and shift register 504 may be operated or enabled according to RS_E2 554. Therefore, shift register 510 may generate the initial portion of an internal clock pulse (e.g., RdClk0_E[0:x<4]), and shift register 504 may generate the subsequent portion of an internal clock pulse (e.g., RdClk0_E[x+1:4]).

[0069] In some embodiments, shift register 510 may include a four-stage flip-flop circuit (FF_1 to FF_4 of interleaved even-number circuit 502) controllable by data at an early even-number enable signal RS_E1, wherein flip-flop circuits FF_1 to FF_2 are cascaded and flip-flop circuits FF_3 to FF_4 are connected in parallel. Clock signal DLL0 may normally be input to the clock nodes of flip-flop circuits FF_1 to FF_2, and clock signal DLL180 may normally be input to the clock nodes of flip-flop circuits FF_3 to FF_4. When clock signal DLL0 is activated, early even-number enable signal RS_E1 controls the operation of the first-stage flip-flop circuit FF_1, and early even-number enable signal RS_E1 may be shifted to the subsequent stages of flip-flop circuits FF_2 to FF_4. Early even-number enable signal RS_E1 may then control the operation of FF_2 in response to activation of clock signal DLL0, and early even-number enable signal RS_E1 may then control the operation of FF_3 to FF_4 in response to activation of clock signal DLL180.

[0070] Shift register 504 may contain four stages of flip-flop circuits (FF_5 to FF_8 of interleaved even-number circuits 502), wherein flip-flop circuits FF_5 to FF_6 are cascaded and flip-flop circuits FF_7 to FF_8 are connected in parallel. Clock signal DLL0 may normally be input to the clock nodes of flip-flop circuits FF_5 to FF_6, while clock signal DLL180 may normally be input to the clock nodes of flip-flop circuits FF_7 to FF_8. When clock signal DLL0 is activated, late even-number enable signal RS_E2 controls the operation of the first-stage flip-flop circuit FF_5, and late even-number enable signal RS_E2 may be shifted to the subsequent stages of flip-flop circuits FF_6 to FF_8. Late even-number enable signal RS_E2 may then control the operation of FF_6 in response to the activation of clock signal DLL0, and late even-number enable signal RS_E2 may then control the operation of FF_7 to FF_8 in response to the activation of clock signal DLL180. In some embodiments, the interleaved even-number circuit 502 may enable cyclic redundancy check (CRC), and the shift register 504 may include two additional stages of flip-flop circuits FF_9 and FF_10. When CRC is enabled, the timing control circuit 195 may generate or receive an RdCRC enable signal. The RdCRC enable signal may control the operation of the last two stages of the flip-flop circuits FF_9 and FF_10 in response to the activation of clock signals DLL0 and DLL180, respectively.

[0071] In response to the activation of clock signal DLL0, even-numbered enable signals and RdCRC enable signals latched by trigger circuits FF_1 to FF_2, FF_5 to FF_6, and FF_9 can form a sequence RdClk0_E[0:4] of clock signal elements 0 to 4. In response to the activation of clock signal DLL180, even-numbered enable signals and RdCRC enable signals latched by trigger circuits FF_3 to FF_4, FF_7 to FF_8, and FF_10 can form a sequence RdClk180_E[0:4] of clock signal elements 0 to 4. Timing control circuit 195 can subsequently supply RdClk0_E[0:4] to merging circuit 508 and RdClk180_E[0:4] to merging circuit 518. In some embodiments, merging circuit 508 and merging circuit 518 may respectively correspond to... Figure 2 The merging circuits 208 and 218.

[0072] When a command is received on an odd-numbered pulse of an external clock, an interleaved odd-numbered circuit 512 can be used. The interleaved odd-numbered circuit 512 may include shift registers 514 and 520, each configured to perform shift operations synchronized with a clock signal DLL0 for even-numbered clocks and a clock signal DLL 180 for odd-numbered clocks. Shift registers 520 and 514 may each include a predetermined number of flip-flops connected in cascade and / or parallel, controlled by an early odd-numbered enable signal RS_O1 and a late odd-numbered enable signal RS_O2, respectively. Shift register 520 may be operated or enabled according to RS_O1 562, and shift register 514 may be operated or enabled according to RS_O2 564. Therefore, shift register 520 can generate the initial portion of the internal clock pulse (e.g., RdClk180_O[0:x<4]), and shift register 504 can generate the subsequent portion of the internal clock pulse (e.g., RdClk180_O[x+1:4]).

[0073] In some embodiments, shift register 520 may include a four-stage flip-flop circuit (FF_11 to FF_14 of interleaved odd circuit 512) controllable by data at an early odd enable signal RS_O1, wherein flip-flop circuits FF_11 to FF_12 are cascaded and flip-flop circuits FF_13 to FF_14 are connected in parallel. Clock signal DLL180 may typically be input to the clock nodes of flip-flop circuits FF_11 to FF_12, while clock signal DLL0 may typically be input to the clock nodes of flip-flop circuits FF_13 to FF_14. When clock signal DLL180 is activated, early odd enable signal RS_O1 controls the operation of the first-stage flip-flop circuit FF_11, and early odd enable signal RS_O1 may be shifted to the subsequent stages of flip-flop circuits FF_12 to FF_14. The early odd enable signal RS_O1 can then control the operation of FF_12 in response to the activation of the clock signal DLL180, and the early odd enable signal RS_O1 can then control the operation of FF_13 to FF_14 in response to the activation of the clock signal DLL0.

[0074] Shift register 514 may contain four stages of flip-flop circuits (FF_15 to FF_18 of interleaved odd circuit 512), wherein flip-flop circuits FF_15 to FF_16 are cascaded and flip-flop circuits FF_17 to FF_18 are connected in parallel. Clock signal DLL180 may normally be input to the clock nodes of flip-flop circuits FF_15 to FF_16, while clock signal DLL0 may normally be input to the clock nodes of flip-flop circuits FF_17 to FF_18. When clock signal DLL180 is activated, late odd enable signal RS_O2 controls the operation of the first-stage flip-flop circuit FF_15, and late odd enable signal RS_O2 may be shifted to the subsequent stages of flip-flop circuits FF_16 to FF_18. Late odd enable signal RS_O2 may then control the operation of FF_16 in response to the activation of clock signal DLL180, and late odd enable signals RS_O2 at FF_17 to FF_18 may be latched in response to the activation of clock signal DLL0. In some embodiments, the interleaved odd-number circuit 512 may enable cyclic redundancy check (CRC), and the shift register 514 may include two additional stages of flip-flop circuits FF_19 and FF_20. When CRC is enabled, the timing control circuit 195 may generate or receive an RdCRC enable signal. The RdCRC enable signal may control the operation of the last two stages of the flip-flop circuits FF_19 and FF_20 in response to the activation of clock signals DLL180 and DLL0, respectively.

[0075] In response to the activation of clock signal DLL180, the odd enable signals and RdCRC enable signals latched by trigger circuits FF_11 to FF_12, FF_15 to FF_16, and FF_19 can form a sequence RdClk180_O[0:4] of clock signal elements 0 to 4. In response to the activation of clock signal DLL0, the odd enable signals and RdCRC enable signals latched by trigger circuits FF_13 to FF_14, FF_17 to FF_18, and FF_20 can form a sequence RdClk0_O[0:4] of clock signal elements 0 to 4. Timing control circuit 195 can then supply the sequence RdClk0_O[0:4] to merging circuit 508 and the sequence RdClk180_O[0:4] to merging circuit 518. In some embodiments, merging circuit 508 and merging circuit 518 can respectively correspond to... Figure 2 The merging circuits 208 and 218. The merging circuit 508 can output the sequence RdClk0[0:4], while the merging circuit 518 can output the sequence RdClk180[0:4].

[0076] Figure 5BA timing diagram 500B illustrating an interleaved enable signal according to an embodiment of the present invention is provided. Timing control circuitry 195 may be configured to use interleaved enable signals to deliver bits of output data provided by a command. The interleaved enable signal may comprise an even set having an early even enable signal and a late even enable signal, and an odd set having an early odd enable signal and a late odd enable signal. The early even enable signal may be offset from the late even enable signal, and the early odd enable signal may be offset from the late odd enable signal. For example, the early enable signal 530 may be an early even enable signal RS_E1, and the late enable signal 532 may be a late even enable signal RS_E2. Alternatively, the early enable signal 530 may be an early odd enable signal RS_O1, and the late enable signal 532 may be a late odd enable signal RS_O2. In some embodiments, RS circuitry 190 may generate early enable signal 530 and late enable signal 532. Timing control circuitry 195 may subsequently receive the interleaved enable signal from RS circuitry 190. In other embodiments, timing control circuit 195 may generate an early enable signal 530 and a late enable signal 532.

[0077] Both the early enable signal 530 and the late enable signal 532 can last for a duration less than the burst length of the output data bits. Therefore, the early enable signal 530 can encompass the leading bits of the output data (e.g., the early partition of the burst) and coordinate the delivery of leading bits for even and odd pipelines. The late enable signal 532 can encompass the trailing bits of the output data (e.g., the late partition of the burst) and coordinate the delivery of trailing bits for even and odd pipelines. For example, the early enable signal 530 can handle the delivery of bits 0 to x of the output data, while the late enable signal 532 can handle the delivery of bits x+1 to n of the output data. The value of n can represent the identifier or bit number of the last bit (e.g., the least significant bit or the most significant bit) in the output data, and x can represent a value between 0 and n.

[0078] In some embodiments, the timing control circuit 195 may use interleaved enable signals to coordinate the delivery of bits of output data, even when the first and second commands are received without sufficient separation (e.g., Figure 4B The same applies to the seamless, sudden situation 402. The following section discusses... Figure 5C and 6C Describe more details on using interleaved enable signals in gapless burst scenario 402 or gapless handover scenario.

[0079] Figure 5C A timing diagram 500C for interleaved enable signals according to an embodiment of the present invention is illustrated. In the timing diagram 500C, back-to-back commands that are not sufficiently separated (e.g., for a duration less than a predetermined threshold) can be received. Figure 1Command circuit 105 can receive a first command RD0 on an even-numbered clock pulse of external clock CLK. In response, RS circuit 190 can generate an early even-number enable signal RS_E1. The early even-number enable signal RS_E1 can mark / indicate that the first command RD0 starts with an even-numbered pipeline, and DLL0 delivers the first bit of the read data provided in response to the first command RD0 (e.g., the first read data). The early even-number enable signal RS_E1 can subsequently form an envelope around the burst of the preamble bit of the first read data and can be used to deliver the preamble bit. Timing control circuit 195 can use the early even-number enable signal RS_E1 to coordinate the delivery of bits 0 to x of the first read data (e.g., via...). Figure 1 The I / O circuit 160 is as described above. After generating an early enable signal, the RS circuit 190 can generate a late even enable signal RS_E2. The late even enable signal RS_E2 can form an envelope around the burst of the last bit of the first read data and can be used to deliver the last bit. The timing control circuit 195 can use the late even enable signal RS_E2 to deliver bits x+1 to n of the first read data. For example, after the timing control circuit 195 delivers 8 leading bits (e.g., bits 0 to 7) of the first read data using the early even enable signal RS_E1, the timing control circuit 195 can switch to delivering 10 last bits (e.g., bits 8 to 17) of the first read data using the late even enable signal RS_E2.

[0080] In gapless scenario 502, command circuit 105 may receive the second command RD1 while timing control circuit 195 is still using the late even-number enable signal RS_E2 to deliver the last bit of the first read data. The second command RD1 may be received on an odd-numbered clock pulse of external clock CLK. In response to receiving the second command RD1, RS circuit 190 may generate an early odd-number enable signal RS_O1 and subsequently a late odd-number enable signal RS_O2. The early and late odd-number enable signals may be delivered, marked / indicated, enveloped, and coordinated for their respective aspects in a similar manner to the even-number enable signals.

[0081] By using an early enable signal and a late enable signal for each of the first and second commands, the early even enable signal RS_E1 prevents overlap and conflict with the early odd enable signal RS_O1. Similarly, the late even enable signal RS_E2 prevents overlap and conflict with the late odd enable signal RS_O2. The early and late enable signals ensure a time gap between the early enable signals RS_E1 and RS_O1, thereby ensuring that the two early enable signals do not coexist simultaneously. Therefore, even for the gapless scenario 502, the timing control circuit 195 can ensure that the correct end bit of the first read data is delivered without conflicting / colliding with the delivery of the leading bit of the second read data. The overlap between the late even enable signal RS_E2 and the early odd enable signal RS_O1 does not disrupt delivery because the early enable signal and the late enable signal are separate enable signals for handling different partitions of the read data. For example, FF10 of circuit 502 can output RdClk180_E[4] for RD0, while FF11 of circuit 512 outputs RdClk180_O[0] for RD1. However, since RS_E1 is disabled and separated from RS_O1, FF3 output from circuit 502 can be disabled, thereby preventing any collisions at the merging circuit 518 for RdClk180[0]. Based on the interleaving enable signal, timing control circuit 195 can provide a smooth transition between two data bursts and ensure that the correct data is delivered for these bursts without collisions or corruption.

[0082] Figures 6A to 6C This describes an embodiment of the invention configured to use a chopper circuit 600A. Figure 1 The timing control circuit 195. Figure 6A This is a block diagram of a chopper circuit 600A according to an embodiment of the present invention. The chopper circuit 600A may include components corresponding to or respectively matched to... Figure 2 The even-numbered circuit 202, shift register 204, odd-numbered circuit 212, and shift register 214 described herein are further defined by even-numbered circuit 602, shift register 604, odd-numbered circuit 612, and shift register 614. Therefore, the sequences RdClk0_E[0:4], RdClk0_O[0:4], RdClk180_E[0:4], and RdClk180_O[0:4] can correspond to... Figure 2 The sequences RdClk0_E[0:4], RdClk0_O[0:4], RdClk180_E[0:4], and RdClk180_O[0:4] are described in the diagram. The chopper circuit 600A may include a chopper-merging circuit 608 and a chopper-merging circuit 618.

[0083] Figure 6B This is an embodiment of the technology according to the present invention. Figure 6AA block diagram of chopper-merging circuits 608 and 618 is provided. Chopper-merging circuits 608 and 618 may include circuitry configured to combine outputs from even and odd circuits to generate a coordinated clock signal for a corresponding pipeline. For example, chopper-merging circuit 608 may include logic gates that combine RdClk0_E[0:4] with RdClk0_O[0:4] to generate RdClk0[0:4]. In some embodiments, each of chopper-merging circuits 608 and 618 may include a set of OR gates 632 to 636 and 642 to 646, respectively, that receive corresponding coordinated bits (e.g., RdClk bits 1 to 3) from even and odd circuits. For a first clock bit, chopper-merging circuits 608 and 618 may include circuitry for analyzing / combining the first and last bits of a single command or back-to-back command. For example, chopper-merging circuit 608 may include:

[0084] ● An inverter or NOT gate 622, whose output RdClk0_E[0] is the logical negation.

[0085] ● NOR gate 620, whose outputs RdClk0_O[0] and RdClk0_O[4] are logic NOR gates, and

[0086] ●OR gate 630, whose output inverter 622 output is logically ORed with the output of NOR gate 620 as RdClk0[0].

[0087] Additionally, the chopper merging circuit 618 may include:

[0088] ● An inverter or NOT gate 652, whose output RdClk180_O[0] is the logical NOT of...

[0089] ●NOR gate 650, whose outputs RdClk180_E[0] and RdClk180_E[4] are logic NOR gates, and

[0090] ●OR gate 640, whose output inverter 652 output is logically ORed with the output of NOR gate 650 as RdClk180[0].

[0091] The chopper-merging circuit 608 may include a buffer gate 638 that outputs RdClk0_E[4] as RdClk0[4], and the chopper-merging circuit 618 may include a buffer gate 648 that outputs RdClk180_O[4] as RdClk180[4]. Therefore, the merging circuits 608 and 618 may generate a repeating pattern that is not divisible by 4 (e.g., where the combined length of RdClk0 and RdClk180 divided by four produces a non-zero remainder).

[0092] The circuit design of merging circuits 608 and 618 (e.g., the number of gates) may depend on the number of flip-flops in shift registers 604 and 614 (e.g., the number of bits in the output / combined data). For example, if shift registers 604 and 614 each contain n stages of flip-flop circuitry, then merging circuits 608 and 618 may each be configured with at least n+2 gates.

[0093] Figure 6C Description of embodiments according to the present invention Figure 6A Timing diagram 600C for chopper circuit 600A. The illustrated example corresponds to receiving commands on even-numbered clock pulses, and RS circuit 190 can generate an even-numbered enable signal RS_E. The chopper circuit 600A is configured with... Figure 1 The timing control circuit 195 can receive an even-number enable signal RS_E from the RS circuit 190. The chopper circuit 600A can then output RdClk0[0:4] and RdClk180[0:4] as sequences of internal clock signals DLL0 and DLL180, respectively. The timing control circuit 195 can use the sequence RdClk0[0:4] to deliver bits 0 to 1, 4 to 5, 8 to 9, 12 to 13, and 16 to 17 of the read data provided by the received command. The timing control circuit 195 can use the sequence RdClk180[0:4] to deliver bits 2 to 3, 6 to 7, 10 to 11, and 14 to 15 of the read data provided by the received command.

[0094] The read data and / or the corresponding sequence of RdClk0[0:4] combined with RdClk180[0:4] may have a length that is not divisible by 4 (e.g., when the read data contains cyclic redundancy check data), wherein the remainder after dividing by the total number of output bits of the read data can be a positive integer / non-zero integer. The chopper circuit 600A (by, for example, a chopper-merging circuit) can remove the clock pulse for delivering the last bit of the read data sequence RdClk180[4] corresponding to the remainder (e.g., the remainder bit) and append it before the clock pulse of the next command sequence RdClk180[0]. In other words, the chopper circuit 600A can internally stop or “chop” the burst of the remainder bit and apply it as the preamble burst of the next command. For example, when the length of the output data is 18 bits, the chopper circuit 600A can use the first and / or last logic gate in the chopper-merging circuit to stop the burst of the 19th and 20th bits of the output data, and apply the burst as the 1st and 2nd bits of the next read command.

[0095] In some embodiments, when the first command and the second command are received without sufficient separation (e.g., Figure 4BIn the gapless burst scenario 402 of timing diagram 400B, timing control circuit 195 can use chopper circuit 600A to coordinate the delivery of output data. Since the burst of the last bit of the output data provided by the first command (e.g., first read data) is stopped or "clipped" and applied as the preamble burst of the second command, the delivery of the last bit of the first read data no longer conflicts with the delivery of the preamble bit of the output data provided by the second command (e.g., second read data). In other words, using chopper circuit 600A, timing control circuit 195 can ensure separation between the delivery of the last bit of the current read command and the delivery of the preamble bit of the next read command. Therefore, timing control circuit 195 can handle even and odd enable signals in gapless burst scenario 402 and ensure timely and error-free delivery of output data bits.

[0096] Figure 6D Description of embodiments according to the present invention Figure 6A The timing diagram 600D of the chopper circuit 600A is shown. The illustrated example corresponds to receiving a first command RD0 on an odd-numbered clock pulse, a second command RD1 on an odd-numbered clock pulse, and a third command RD2 on an even-numbered clock pulse. For each of the three read commands, the chopper circuit 600A can output RdClk0[0:4] and RdClk180[0:4] as output sequences of internal clock signals DLL0 and DLL180, respectively. The timing control circuit 195 can use the sequence RdClk180[0:4] to coordinate the output of bits 0 to 1, 4 to 5, 8 to 9, 12 to 13, and 16 to 17 of the read data (e.g., the first and second read data) provided by the first and second received commands, and uses the sequence RdClk0[0:3] to coordinate the output of bits 2 to 3, 6 to 7, 10 to 11, and 14 to 15 of the read data. The timing control circuit 195 may use the sequence RdClk0[0:4] to coordinate the output of bits 0 to 1, 4, 5, 8 to 9, 12 to 13, and 16 to 17 of the read data (e.g., the third read data) provided by the third receive command, and may use the sequence RdClk180[0:3] to deliver bits 2 to 3, 6 to 7, 10 to 11, and 14 to 15 of the read data.

[0097] When cyclic redundancy check is enabled in timing diagram 600D, the corresponding output sequence of the read data and / or RdClk0[0:4] combined with RdClk180[0:4] of the first command RD0 can have a length that is not divisible by 4 (e.g., 5 to 7 bits, 9 to 11 bits, 17 to 19 bits, etc.). For example, RdClk180[0:4] and RdClk0[0:3] can be used to coordinate the delivery of the first and second read data. Additionally, RdClk0[0:4] and RdClk180[0:3] can be used to coordinate the delivery of the third read data. Therefore, the chopper-merging circuits 608 and 618 can effectively create a processing cycle corresponding to the maximum length that is not divisible by 4.

[0098] As an illustrative example, when two sequential or back-to-back signals are received on the same even / odd pulses (e.g., even and even, or odd and odd), the corresponding processing loop can form a gap 650, where the clock pulse RdClk0[4] can remain unused to coordinate the output of the bits of the first read data. Since the same even / odd circuit (e.g., a phase shifter) can be used to generate (1) the end of the preceding clock sequence of the first read data and (2) the beginning of the subsequent clock sequence of the second read data, the resulting sequences will be sequential and non-overlapping.

[0099] Alternatively, when two sequential or back-to-back signals are received on different clock pulses (e.g., even and odd, or odd and even), the corresponding coordinated outputs may overlap. During the overlap period, the outputs of both coordinated circuits may be valid. Chopper-merging circuits 608 and 610 may include additional logic of bits [0] and / or bits [4] to account for overlap, as described above. Continuing to the second command RD1, chopper circuit 600A may remove or ignore RdClk0 [4] of the second command RD1 and output RdClk0 [0] of the third command RD2 separately while outputting RdClk180 [4] concurrently. By chopping or stopping the last clock cycle RdClk0 [4] of the second command RD1 and coordinating the selection of RdClk0 [0], chopper circuit 600A may retain the last clock cycle and give the time to RdClk0 [0] of the third command RD2. Therefore, the chopper circuit 600A can shorten the duration required to coordinate the output of the second read data bit (e.g., only 9 clock pulses exist between the second command RD1 and the third command RD2).

[0100] Figure 7 This describes the operation of the device according to embodiments of the present invention (e.g., Figure 1A flowchart of an example method 700 for device 100. Method 700 can be used to implement the command / address input circuit, input / output circuit, clock input circuit, RS circuit, and / or timing control circuit described above. Additionally, method 700 can be used to implement any timing diagram described above (e.g., Figures 3B to 3C Timing diagram 300B to 300C, Figures 5B to 5C Timing diagrams 500B to 500C and / or Figures 6C to 6D Timing diagram 600C to 600D).

[0101] At block 702, device 100 may receive commands from an external device. The received commands may be commands issued by the external device to request data to be read from device 100. In some embodiments, device 100 may implement N pipelines, each processing 1 / N portions of the data. For example, device 100 may implement two pipelines (e.g., an even-numbered pipeline and an odd-numbered pipeline), each processing 1 / 2 portions of the data.

[0102] At block 704, device 100 can process the stored data according to an internal clock. Device 100 can process each 1 / N portion of the stored data according to a corresponding internal clock. The corresponding internal clock may have an internal frequency that is 1 / N of the external frequency of the external clock. For example, when N=2, device 100 can process alternating portions of the data according to even-numbered internal clocks (e.g., DLL0) and odd-numbered internal clocks (e.g., DLL180) that each have a frequency as 1 / 2 of the external frequency.

[0103] At block 706, device 100 may identify an external clock as a sequence of N clock pulses. Each pulse in the sequence may correspond to one of the N pipelines that process data according to a received command. For example, when N = 2 (e.g., 2 pipelines, i.e., an even number of pipelines and an odd number of pipelines), device 100 may identify the external clock as a sequence of 2 clock pulses or alternating even and odd pulses. Even pulses may be aligned with an even number of internal clocks, and odd pulses may be aligned with an odd number of internal clocks.

[0104] At block 708, device 100 may generate an enable signal for the command. Device 100 may generate one or more enable signals for each received command. The one or more enable signals may represent the time when the corresponding command was received according to its position in a sequence of N pulses of an external clock. For example, when N=2, device 100 may generate one or more enable signals to indicate whether the command was received on an odd or even pulse of the external clock. In some embodiments, the one or more enable signals may include an even enable signal and an odd enable signal. In various embodiments, the one or more enable signals may include an early even enable signal followed by a late even enable signal, and / or may include an early odd enable signal followed by a late odd enable signal. The early even enable signal may be offset in time from the late even enable signal. The early odd enable signal may be offset in time from the late odd enable signal.

[0105] At block 710, device 100 can coordinate the output of stored data. Device 100 can coordinate an output sequence (e.g., a combination of RdClk0 and RdClk180) for combining outputs from N number of pipelines to correspond to the data. The output sequence may contain a sequence of clock signal elements / pulses generated by the timing control circuitry described above (e.g., a merging circuitry of the timing control circuitry). The output sequence can be controlled according to one or more enable signals to coordinate the output of data. For example, device 100 can receive a first command, followed by a second command with minimal separation. Device 100 can temporally separate a first output sequence and a second output sequence corresponding to the first received command and the second received command, respectively. The first output sequence can be used to coordinate the output of a first read data provided in response to the first command. The second output sequence can be used to coordinate the output of a second read data provided in response to the second command. Device 100 can maintain the separation between the first read data and the second read data when the first command and the second command are separated by an odd number of clock pulses from an external clock.

[0106] In some embodiments, device 100 may use one or more enable signals to maintain the separation. When the first and second commands are received on even and odd cycles respectively, device 100 may use an early even enable signal to control one or more preamble clock signal elements / pulses of the first output sequence and coordinate the output of one or more preamble bits of the first read data. Device 100 may use a late even enable signal to control one or more end clock signal elements / pulses of the first output sequence and coordinate the output of one or more end bits of the first read data. Then, device 100 may use an early odd enable signal to control one or more preamble clock signal elements / pulses of the second output sequence and coordinate the output of one or more preamble bits of the second read data. Device 100 may use a late odd enable signal to control one or more end clock signal elements / pulses of the second output sequence and coordinate the output of one or more end bits of the second read data. When the first and second commands are received on odd and even cycles respectively, device 100 may similarly use an interleaved set of odd enable signals to control the first output sequence and an interleaved set of even enable signals to control the second output sequence.

[0107] In various embodiments, device 100 may use the chopper circuit described above to maintain separation. The chopper circuit may remove one or more end pulses of the first output sequence. After removing the end pulses, the chopper circuit may append one or more end pulses of the first output sequence before one or more preamble pulses of the second output sequence.

[0108] Figure 8 This is a schematic diagram of a system including an apparatus according to an embodiment of the technology according to the present invention. (See above reference) Figures 1 to 7 Any of the aforementioned devices (e.g., memory devices) described can be incorporated into or implemented in a memory (e.g., memory device 800) or any of a large number of larger and / or more complex systems, a representative example of which is... Figure 8 The system 880 is schematically shown in the diagram. System 880 may include a memory device 800, a power supply 882, a driver 884, a processor 886, and / or other subsystems or components 888. The memory device 800 may include components similar to those described above. Figures 1 to 7The described devices share generally similar features and therefore may include a variety of features for executing direct read requests from a host device. The resulting system 880 can perform any of a wide range of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 880 may include, but are not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. The components of system 880 may be housed in a single unit or (e.g., via a communication network) distributed across multiple interconnected units. The components of system 880 may also include remote devices and any of a wide variety of computer-readable media.

[0109] As should be understood from the foregoing, specific embodiments of the technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Furthermore, certain aspects of the new technology described in the context of particular embodiments may be combined or removed in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are intended to exhibit such advantages to fall within the scope of the technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

[0110] In the embodiments described above, the device has been described in the context of a DRAM device. However, devices configured according to other embodiments of the present invention may include other types of suitable storage media besides or replacing DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0111] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transferring, and / or manipulating data structures. The term "data structure" includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. Furthermore, as used herein, the term "dynamic" describes a process, function, action, or implementation that occurs during the operation, use, or deployment of the corresponding device, system, or embodiment, and after or concurrently with the running of the manufacturer's firmware or third-party firmware. Dynamic processes, functions, actions, or implementations may occur after or after design, manufacturing, and initial testing, setup, or configuration.

[0112] The embodiments described above are given in sufficient detail to enable those skilled in the art to make and use them. However, those skilled in the art will understand that the technology may have additional embodiments, and that the technology may be used without the foregoing reference. Figure 1 The following are some details of the implementation of the embodiments described in 6.

Claims

1. An apparatus comprising: An external clock circuit configured to receive an external clock with an external frequency, wherein the external clock is shared with an external device; A command circuit coupled to the external clock circuit and configured to receive commands from the external device; A set of pipelines coupled to the command circuit and configured to process data units according to a received command, wherein the set of pipelines includes an even number of pipelines and an odd number of pipelines, wherein the even number of pipelines and the odd number of pipelines are configured to process alternating portions of the stored data units according to an even number of internal clocks and an odd number of internal clocks, respectively. A status read circuit, coupled to the external clock circuit and the command circuit, is configured to: The external clock is identified as a sequence of alternating even and odd pulses, wherein the even pulses are aligned with the even internal clock and the odd pulses are aligned with the odd internal clock. as well as Generate one or more enable signals to indicate whether the read command was received on an odd or even pulse of the external clock; as well as A timing control circuit, coupled to the read status circuit and the set of pipelines, is configured to: When the second received command follows the first received command with minimal separation, the time separation corresponds to the first output sequence and the second output sequence of the first received command and the second received command, respectively. as well as When the first read command and the second read command are separated by an odd number of clock pulses from the external clock, the separation between the first read data and the second read data provided in response to the first read command and the second read command, respectively, is maintained.

2. The device of claim 1, wherein the one or more enable signals comprise an early even enable signal followed by a late even enable signal, and / or comprise an early odd enable signal followed by a late odd enable signal.

3. The device according to claim 2, wherein the timing control circuit is configured to: The early even-number enable signal is used to coordinate the output of one or more preamble bits of the first read data; The late even-number enable signal is used to coordinate the output of one or more last bits of the first read data; Using the early odd-number enable signal, the output of one or more preamble bits of the second read data is coordinated, wherein the early odd-number enable signal is offset from the early even-number enable signal; and The late odd enable signal is used to coordinate the output of one or more end bits of the second read data, wherein the late odd enable signal is offset from the late even enable signal.

4. The device according to claim 1, wherein: The first read command is received on the even-numbered pulse. The second read command is received on the odd-numbered pulse. The first bit of the first read data is output to the external device according to the even-numbered internal clock, and The first bit of the second read data is output to the external device according to the odd-numbered internal clock.

5. The device according to claim 1, wherein the timing control circuit is configured to: Remove one or more of the trailing pulses from the first output sequence; and The one or more end pulses of the first output sequence are appended before the one or more pre-lead pulses of the second output sequence.

6. The device according to claim 5, wherein: The first read data includes cyclic redundancy check data, and The first read data and the first output sequence have lengths that are not divisible by four.

7. The device according to claim 6, wherein: The first read data includes 6 bits, 10 bits, or 18 bits, and The cyclic redundancy check data corresponds to two of the six, ten, or eighteen bits of the first read data.

8. The device according to claim 1, wherein: The device includes a dual data rate DDR memory device; The timing control circuit is configured to maintain the separation between the first read data and the second read data when the first read command and the second read command are separated by nine pulses of the external clock.

9. A system comprising: A set of pipelines configured to process data units according to a received command, wherein the set of pipelines comprises N pipelines, each pipeline being configured to process 1 / N portions of the data unit according to a corresponding internal clock having an internal frequency of 1 / N of an external frequency as an external clock. The state processing circuit is configured to: The external clock is identified as a sequence of N pulses, wherein each pulse in the sequence corresponds to one of the N pipelines; as well as Generate one or more enable signals for each received command, wherein the one or more enable signals represent the receiving time of the corresponding command according to the position in the sequence of N pulses; as well as A timing control circuit, coupled to the processing state circuit and the set of pipelines, is configured to coordinate the combination of outputs from the N number of pipelines to correspond to an output sequence of the data unit, wherein the output sequence is controlled according to one or more enable signals. The timing control circuit is configured to: When the second received command follows the first received command with minimal separation, the time separation corresponds to the first output sequence and the second output sequence of the first received command and the second received command, respectively. as well as When the first read command and the second read command are separated by an odd number of clock pulses from the external clock, the separation between the first read data and the second read data provided in response to the first read command and the second read command, respectively, is maintained.

10. The system according to claim 9, wherein: The set of pipelines comprises an even number of pipelines and an odd number of pipelines, where N=2, wherein the even number of pipelines and the odd number of pipelines are configured to process alternating portions of the stored data units according to an even number of internal clocks and an odd number of internal clocks, respectively; and The processing state circuit is configured to: The external clock is identified as a sequence of alternating even and odd pulses, wherein the even pulses are aligned with the even internal clock and the odd pulses are aligned with the odd internal clock. as well as Generate one or more enable signals to indicate whether a read command was received on an odd or even pulse of the external clock.

11. The system of claim 10, wherein the one or more enable signals include an early even enable signal followed by a late even enable signal, and / or include an early odd enable signal followed by a late odd enable signal.

12. The system of claim 11, wherein the timing control circuit is configured to: The early odd enable signal is used to coordinate the output of one or more preamble bits of the first read data; The late odd enable signal is used to coordinate the output of one or more end bits of the first read data; Using the early even-number enable signal, the output of one or more preamble bits of the second read data is coordinated, wherein the early even-number enable signal is offset from the early odd-number enable signal; and The late even enable signal is used to coordinate the output of one or more end bits of the second read data, wherein the late even enable signal is offset from the late odd enable signal.

13. A method comprising: Each 1 / N portion of the data unit is processed according to the received command and the corresponding internal clock, which has an internal frequency of 1 / N that serves as an external clock. The external clock is identified as a sequence of N pulses, wherein each pulse in the sequence corresponds to one of N pipelines; as well as For each received command, one or more enable signals are generated, wherein the one or more enable signals represent the reception time of the corresponding command according to the position in the sequence of N pulses; as well as Coordination is used to combine the outputs from the N number of pipelines to correspond to the output sequence of the data unit, wherein the output sequence is controlled according to one or more enable signals. The method further includes: When the second received command follows the first received command with minimal separation, the time separation corresponds to the first output sequence and the second output sequence of the first received command and the second received command, respectively. as well as When the first read command and the second read command are separated by an odd number of clock pulses from the external clock, the separation between the first read data and the second read data provided in response to the first read command and the second read command, respectively, is maintained.

14. The method of claim 13, further comprising: The alternating portions of the stored data units are processed according to the even-numbered internal clock and the odd-numbered internal clock, where N=2; The external clock is identified as a sequence of alternating even and odd pulses, wherein the even pulses are aligned with the even internal clock and the odd pulses are aligned with the odd internal clock. as well as Generate one or more enable signals to indicate whether a read command was received on an odd or even pulse of the external clock.

15. The method of claim 14, further comprising: Remove one or more trailing pulses from the first output sequence; as well as The one or more end pulses of the first output sequence are appended before the one or more pre-lead pulses of the second output sequence.

16. The method of claim 15, wherein: The first read data includes cyclic redundancy check data, and The first read data and the first output sequence have lengths that are not divisible by four.

17. An apparatus comprising: An internal clock circuit is configured to generate first and second internal clock signals based on an external clock signal (CK), wherein the frequency of each of the first and second internal clock signals (DLL0, 180) is lower than the frequency of the external clock signal, and the phases of the first and second internal clock signals are offset from each other. The status reading circuit is configured to: In response to receiving a read command in an even clock cycle, an even read enable signal (RS_E) is generated, which is configured to activate a first number of pulses of the first internal clock signal and a second number of pulses of the second internal clock signal that is different from the first number. as well as In response to receiving the read command in an odd clock cycle, an odd read enable signal (RS_O) is generated, which is configured to activate the second number of pulses of the first internal clock signal and the first number of pulses of the second internal clock signal. as well as A timing control circuit, coupled to the read state circuit, is configured to: When the second received command follows the first received command with minimal separation, the time separation corresponds to the first output sequence and the second output sequence of the first received command and the second received command, respectively. as well as When the first read command and the second read command are separated by an odd number of clock pulses from the external clock, the separation between the first read data and the second read data provided in response to the first read command and the second read command, respectively, is maintained.

18. The device of claim 17, further comprising a timing control circuit (TM), the timing control circuit being configured to: When the even-number read enable signal is generated, the parallel-to-serial conversion of the read data is coordinated at least in part based on the first number of pulses of the first internal clock signal and the second number of pulses of the second internal clock signal; and When the odd-number read enable signal is generated, the parallel-to-serial conversion of the read data is coordinated at least in part based on the second number of pulses of the first internal clock signal and the first number of pulses of the second internal clock signal.

19. The device of claim 18, wherein the first number of pulses is 5 and the second number of pulses is 4.

Images