Apparatus and method for low-density parity-check code decoding
By applying correction techniques in low-density parity-check code decoding, bit words are mapped to shorter intermediate bit words and the message determination process is optimized, solving the problem of insufficient resource utilization in hardware implementation and improving the balance between decoding performance and complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NOKIA NETWORKS OY
- Filing Date
- 2022-08-10
- Publication Date
- 2026-06-02
AI Technical Summary
Existing low-density parity-check code decoding methods suffer from insufficient resource utilization in hardware implementation, especially in the representation and propagation of bit words, resulting in poor decoding complexity and performance.
By applying correction techniques in variable nodes, bit words are mapped to shorter intermediate bit words, and corrections such as fractional or offset corrections are applied during the mapping process to reduce the length of bit words. At the same time, lookup tables are used to optimize the message determination process and improve resource utilization.
It significantly reduces the resource requirements for representing bit words in hardware implementation, improves the balance between decoding performance and complexity, and enhances the efficiency and effectiveness of LDPC decoding.
Smart Images
Figure CN115706587B_ABST
Abstract
Description
Technical Field
[0001] Various example embodiments relate to apparatus and methods for decoding low-density parity-check codes. Background Technology
[0002] Low-density parity-check (LDPC) codes are forward error-correcting codes used to correct bit errors that occur during data transmission on a physical medium. Summary of the Invention
[0003] Various embodiments of this disclosure are set forth in the independent claims. The methods and apparatus according to the independent claims have incorporated corrections to examine node messages in the variable-node. Because the practical implementation of the LDPC decoder represents values with bit words of finite size, and because messages are represented by bit words shorter than the total log-likelihood ratio, the methods and apparatus according to the independent claims make better use of the available level of bit words in the LDPC code decoding process, and thus improve the performance of the LDPC decoding process.
[0004] This document discloses a method for performing low-density parity-check code decoding in a first processing device, comprising: receiving a first bit word of a first length correlated with the log-likelihood ratio of bits of a signal; obtaining a second bit word of a second length shorter than the first length, wherein obtaining the second bit word includes applying a correction to the first bit word; and determining a message based on a set of second bit words, wherein the set of second bit words includes the second bit word.
[0005] In one aspect of the invention, applying correction includes: mapping a first bit word to an intermediate bit word of a first length, wherein the value represented by the intermediate bit word is a fraction of the value represented by the first bit word.
[0006] In one aspect of the invention, applying correction includes: mapping a first bit word to an intermediate bit word of a first length, wherein the magnitude of the value represented by the intermediate bit word is the magnitude of the value represented by the first bit word minus an offset.
[0007] In one aspect of the invention, applying the correction includes: looking up the second bitword in a table that includes a mapping from the first bitword to the second bitword, wherein the mapping includes the correction.
[0008] The method may include: determining the symbol of the message based on the product of the symbols of the second bit words in the second bit word set; and determining the size of the message based on the minimum size of the second bit words in the second bit word set.
[0009] This method may include determining the first bitword based on the difference between the total log-likelihood ratio and the previously calculated message.
[0010] An apparatus for decoding low-density parity-check codes includes components for: receiving a first bit word of a first length associated with the log-likelihood ratio of bits of a signal; obtaining a second bit word of a second length shorter than the first length, wherein obtaining the second bit word includes applying a correction to the first bit word; and determining a message based on a set of second bit words, wherein the set of second bit words includes the second bit word.
[0011] In one aspect of the invention, the apparatus includes a component configured for applying correction to map a first bit word to an intermediate bit word of a first length, wherein the value represented by the intermediate bit word is a fraction of the value represented by the first bit word.
[0012] In one aspect of the invention, the apparatus includes a component configured for applying correction to map a first bit word to an intermediate bit word of a first length, wherein the magnitude of the value represented by the intermediate bit word is the magnitude of the value represented by the first bit word minus an offset.
[0013] In one aspect of the invention, the apparatus includes a component configured for applying correction to look up a second bitword in a table comprising a mapping from a first bitword to a second bitword, wherein the mapping includes correction.
[0014] In one aspect of the invention, the apparatus includes a component configured to determine the symbol of a message based on the product of the symbols of the second bit words in the second bit word set; and to determine the magnitude of the message based on the minimum magnitude of the second bit words in the second bit word set.
[0015] In one aspect of this disclosure, the apparatus includes a component configured to determine a first bitword based on the difference between the total log-likelihood ratio and a previously calculated message.
[0016] The non-transient computer-readable medium disclosed herein includes program instructions for causing the apparatus to perform at least a method. Attached Figure Description
[0017] Figure 1 A portion of a first embodiment of a device for decoding low-density parity-check codes is schematically depicted.
[0018] Figure 2 A sequence diagram depicts the steps of a first embodiment of a method for use in low-density parity-check code decoding.
[0019] Figure 3 The first exemplary bit word is depicted.
[0020] Figure 4A portion of a second embodiment of the apparatus for decoding low-density parity-check codes is schematically depicted.
[0021] Figure 5 A sequence diagram depicts the steps of a second embodiment of a method for use in low-density parity-check code decoding.
[0022] Figure 6 A second exemplary bit word is depicted.
[0023] Figure 7 The first process of computing the messages corresponding to the variable node and the check node is described.
[0024] Figure 8 The second process for calculating messages corresponding to variable nodes and check nodes is described. Detailed Implementation
[0025] LDPC codes are block codes that take K information bits and encode them into a codeword of N bits. In the example disclosed in this paper, it includes K information bits in addition to the NK parity bits. The code rate R of the LDPC code is R = K / N.
[0026] Examples of technologies that use LDPC codes include wireless technologies such as 5G; coaxial cable technologies such as DOCSIS 3.1; digital subscriber line technologies such as MGfast; passive optical network technologies such as IEEE 802.3ca and G.9804.2; and power line technologies such as G.hn.
[0027] An LDPC codeword comprises K information bits corresponding to information such as data bits. An LDPC codeword also comprises NK bits corresponding to NK redundant parity bits. In this example, the first K bits of the N bits of the LDPC codeword correspond to the K information bits, and the last NK bits of that sequence correspond to the parity bits.
[0028] The characteristics of LDPC are described by a binary (NK)×N parity check matrix H. Matrix H comprises N columns corresponding to the N bits of an LDPC codeword. Matrix H also comprises NK rows corresponding to the parity constraints that any valid codeword of the LDPC code should satisfy. In some embodiments, the LDPC code can be shortened by setting some information bits to a fixed value, such as 0, and not transmitting these bits. Similarly, in some embodiments, the LDPC code can be punctured by not transmitting some of the encoded bits. Using puncturing and shortening, the (NK)×N parity check matrix H can be used to encode K'≤K bits into codewords of length N'≤N bits, which can be non-systematic.
[0029] The parity constraint in this example is that the XOR sum (exclusive OR sum) of the bits of the LDPC codewords indicated in the rows of the parity check matrix must be 0. In this context, this means that the matrix elements are all 1s. This can be formally expressed as matrix multiplication followed by modulo-2 operations, for example:
[0030] mod(Hv, 2) = 0
[0031] Where v is a column vector of data bits and parity bits.
[0032] Iterative belief propagation can be used to decode LDPC codes. Iterative belief propagation calculates the received bit v based on the received signal. i The initial log-likelihood ratio llr in，i As input. Initial log-likelihood ratio llr in，i Given the received sample y i bit v i The probability P that is 0 is related to the given received sample y. i bit v i The logarithm of the ratio of probabilities of being 1:
[0033]
[0034] For example, in the case of digital equalization, the log-likelihood ratio (llr) can also be calculated based on a set of received samples. in，i For a punctured bit, the initial log-likelihood ratio llr in，t It can be set to 0, and for shortened bits, it is set to a high positive value. The LDPC code decoding process based on belief propagation is an iterative process, where the message is transmitted from variable node v. i Send to verification node c j Conversely, the same applies. In the LDPC code decoding process, N codeword bits are mapped one-to-one to variable nodes v. i Verify node c j This corresponds to NK check constraints. This means there are NK check nodes c. j Used.
[0035] In this example, the confidence propagation process is a sum-product algorithm. During the confidence propagation process, the initial log-likelihood ratio lr... in，i Assigned to N variable nodes v i Total log-likelihood ratio During belief propagation, messages are iteratively propagated between N variable nodes and NK check nodes. There are two types of messages: variable-to-check node messages propagating from a variable node to a check node, and check node-to-variable node messages propagating from a check node to a variable node. For each non-zero element in the parity check matrix H, there is one message of each type. During this process, an initial value is assigned to each check node-to-variable node message whose corresponding element in the parity check matrix is 1.
[0036] Then, the iterative belief propagation process begins, where the propagation starts from variable node v. i To the verification node c j Message from variable node to verification node It is calculated as follows in the k-th iteration:
[0037]
[0038] Next, based on the variable node to verification node message To calculate the message from the verification node to the variable node In this example, the verification node c j To variable node v i Message from the verification node to the variable node It is based on the variable node v. i In addition to the message, to this verification node c j The information is determined by all variable nodes and verification node messages:
[0039]
[0040] Then, the total log-likelihood ratio for each variable node For example, it is updated via the following:
[0041]
[0042] or
[0043]
[0044] Here, The symbol corresponds to the current estimated bit value of bit i in the codeword.
[0045] The confidence propagation process is repeated iteratively until, for example, a valid codeword is obtained, or a fixed number of iterations are reached. The check node to variable node messages can be updated in different sequences. Two sequences are: hierarchical scheduling, where check node to variable node messages are updated sequentially (i.e., one check node at a time), and flooding scheduling, where check node to variable node messages are updated in parallel for all check nodes.
[0046] In another example, the size of the check node-to-variable node message sent to a specific variable node is equal to the size of the received check node-to-variable node messages. The variable node v to be sent i Messages from variable nodes to verification nodes, excluding received messages The absolute value of the smallest size is used as an approximation. Verification node to variable node. The symbol can be calculated as the product of the symbols of the associated variable node to the check node message.
[0047] This implementation is a minimal sum decoder, which is mathematically formulated as follows:
[0048]
[0049] When the minimum message size is similar, these approximations overestimate the verification node to variable node message.
[0050] This effect can be compensated for by applying corrections.
[0051] The exemplary correction is a decaying minimum-sum decoder, where the messages from the check node to the variable node are scaled using a factor ρ<1. The corresponding decaying minimum-sum algorithm is mathematically formulated as follows:
[0052]
[0053] Another exemplary correction is the offset minimum sum decoder, where the offset c is subtracted from the message from the check node to the variable node. offset >0. The corresponding minimum offset algorithm is mathematically formulated as follows:
[0054]
[0055] Corrected minimum sum decoders, such as attenuated minimum sum decoders and offset minimum sum decoders, offer a good trade-off between decoding complexity and decoding performance.
[0056] When implementing a minimum sum of decay or minimum sum of offset algorithms in a custom hardware implementation, it will represent the variable node to check node message. and / or check node to variable node message and / or total LLR value Minimizing the number of bits has a significant impact on the required resources. Therefore, especially in hardware implementations, reducing the number of representation variable nodes to check node messages is crucial. and / or check node to variable node message The value and / or total LLR value The number of bits is key to obtaining a high-performance and cost-effective solution.
[0057] In the minimal and decoder of the correction, corrections, such as attenuation or offset, are traditionally applied after the minimal operation. Therefore, the check node to variable node message... The full range of values available due to the bit representation of these messages in the hardware implementation is not used.
[0058] Applying corrections earlier in the processing allows the check node to use the full range of available values for the variable node message.
[0059] Message from variable node to verification node From variable node v i Send to verification node c j and / or check node to variable node message From check node c j Send to variable node v i This depends on the structure of the LDPC code. In this example, the non-zero entries in the NK rows of the parity check matrix H, which includes check constraints, define the variable node-to-check node message. From variable node v i Send to verification node c j And the message from the verification node to the variable node. From verification node c j Send to variable node v i Variable node v i Represented by the columns of matrix H. Verification node c j This is represented by the rows of matrix H. If the matrix elements of matrix H in the corresponding row and column are non-zero, then the variable node is sent to the check node message. From variable node v i Send to verification node c j And transmit the verification node to the variable node message. From verification node c j Send to variable node v i Otherwise, no messages are exchanged between these nodes.
[0060] Figure 1 A first embodiment of the apparatus 102 for LDPC code decoding is schematically depicted.
[0061] The apparatus 102 according to the first embodiment is configured to receive a first bit word 104 of a first length associated with the log-likelihood ratio of bits of a signal.
[0062] The apparatus 102 according to the first embodiment is configured to map a first bit word 104 to an intermediate bit word 108 of a first length in a first operation 106.
[0063] In this example, the first operation 106 includes determining the intermediate bit word 108 as a fraction of the first bit word 104. In the context of this disclosure, a fraction refers to a fraction of the value represented by a bit word and is less than 1. The fraction can be determined by a binary shift operation or by the sum of several binary shift operations performed on a portion of the first bit word 104 representing the size.
[0064] The score can be determined by mapping the first bitword 104 to the intermediate bitword 108 using a predetermined mapping. The mapping preferably defines a one-to-one mapping from any possible first bitword to an intermediate bitword. Several first bitwords can be mapped to the same intermediate bitword.
[0065] The mapping from the first bit word 104 to the intermediate bit word 108 may include looking up the intermediate bit word 108 in a first table that includes the mapping from the first bit word 104 to the intermediate bit word 108.
[0066] The apparatus 102 according to the first embodiment is configured to map an intermediate bit word 108 to a second bit word 112 in a second operation 110. In this example, the second operation 110 includes determining that the second bit word 112 has fewer bits than the intermediate bit word 108. The second operation 110 may include mapping the intermediate bit word 108 to the second bit word 112 according to a predetermined mapping. The mapping preferably defines a one-to-one mapping of any possible intermediate bit word to a second bit word. Several intermediate bit words may be mapped to the same second bit word.
[0067] The mapping from intermediate bit word 108 to second bit word 112 can be included by looking up the second bit word 112 in a second table that includes the mapping from intermediate bit word 108 to second bit word 112.
[0068] This means that the apparatus 102 according to the first embodiment is configured to map the first bit word 104 to the second bit word 112. The second bit word 112 has a second length that is shorter than the first length.
[0069] The apparatus 102 according to the first embodiment is configured to store the second bit word 112 into a memory. Various aspects of processing the second bit word 112 are described below.
[0070] The apparatus 102 according to the first embodiment may include a non-transient computer-readable medium including program instructions for causing the first apparatus to perform steps in a first method for low-density parity-check code decoding.
[0071] The following is for reference. Figure 2 Describe the first method.
[0072] The first method includes step 202.
[0073] In step 202, a first bit word 104 of a first length is received.
[0074] Next, proceed to step 204.
[0075] In step 204, the first bit word 104 is mapped to an intermediate bit word 108 of the first length using the first operation 106.
[0076] The intermediate bit word 108 can be a fraction or size offset of the first bit word 104.
[0077] Next, proceed to step 206.
[0078] In step 206, the intermediate bit word 108 is mapped to the second bit word 112 using the second operation 110.
[0079] Next, proceed to step 208.
[0080] In step 208, the second bit word 112 is stored.
[0081] The following describes various aspects of processing the second bit word 112.
[0082] Figure 3 A first exemplary bit word is depicted, wherein the first bit word 104 and the intermediate bit word 108 each have 4 bits, while the second bit word 112 has 3 bits. Figure 3 Only positive values are depicted. Only bitwords where the first bit or sign bit is 0 and therefore represents a positive message are shown. The first bit in a bitword is the sign bit, and if it is 1, then the value is negative. Bitwords for negative values also exist. These bitwords represent variable nodes v. i and check node c j The length of the bitword between nodes is less than the length of the bitword processed in the variable node. This significantly reduces the resources required for communication.
[0083] Figure 4 A second embodiment 402 of the apparatus for LDPC code decoding is schematically depicted.
[0084] The apparatus 402 according to the second embodiment is configured to receive a first bit word 404 of a first length.
[0085] The apparatus 402 according to the second embodiment is configured to map a first bitword 404 to a second bitword 408 in a first operation 406 while applying a correction. In this example, the first operation 406 includes determining that the second bitword 408 has fewer bits than the first bitword 404. The first operation 406 may include mapping the first bitword 404 to the second bitword 408 according to a predetermined mapping including the correction. The mapping preferably defines a one-to-one mapping of any possible first bitword to a second bitword. Several first bitwords may be mapped to the same second bitword.
[0086] The mapping from the first bitword 404 to the second bitword 408 may include looking up the second bitword 408 in a table that includes the mapping from the first bitword 404 to the second bitword 408, while applying a correction.
[0087] This means that the apparatus 402 according to the second embodiment is configured to map the first bit word 404 to the second bit word 408. The second bit word 408 has a second length that is shorter than the first length.
[0088] The apparatus 402 according to the second embodiment is configured to store the second bit word 408 in a memory.
[0089] According to the second embodiment, device example 402 may include a non-transient computer-readable medium including program instructions for causing the second device to perform steps in a second method for low-density parity-check code decoding.
[0090] The following is for reference. Figure 5 Describe the second method.
[0091] The second method includes step 502.
[0092] In step 502, a first bit word of a first length 404 is received.
[0093] Next, proceed to step 504.
[0094] In step 504, the first bit word 404 is mapped to a second bit word 408 of a second length using the first operation 406. The mapping includes correction.
[0095] Next, proceed to step 506.
[0096] In step 506, the second bit word 408 is stored.
[0097] Figure 6 A first exemplary bit word is depicted, wherein the first bit word 404 has 4 bits, and the second bit word 408 has 3 bits. Figure 6Only positive values are depicted. Only bitwords where the first bit or sign bit is 0 and therefore represents a positive message are shown. The first bit in a bitword is the sign bit, and if it is 1, then the value is negative. Bitwords for negative values also exist. These bitwords represent variable nodes v. i and check node c j The length of the bitwords exchanged between nodes is less than the length of a bitword representing, for example, a total of 11rs processed in a variable node. This significantly reduces the resources required for communication.
[0098] Bit words can typically represent signed values in various formats, such as signed-major representation or two's complement representation. 404 only indicates a positive value in the mentioned representation format.
[0099] For mapping, linear mappings can be used, for example, 0000 corresponds to 0, 0001 corresponds to 1, 0010 corresponds to 2, 0011 corresponds to 3, 0100 corresponds to 4, 0101 corresponds to 5, 0110 corresponds to 6, and 0111 corresponds to 7.
[0100] For mapping, non-linear mapping can be used, for example, 000 corresponds to 0, 001 corresponds to 1, 010 corresponds to 3 and 011 corresponds to 5.
[0101] Using this method, the range of messages can be further significantly increased. This is achieved, for example, by implementing a block for performing the second operation based on a lookup table that produces the correct size of the output message level based on the size of the input message.
[0102] Figure 7 The first process for computing a check node-to-variable node message 700 corresponding to a variable node and a check node is described. The first process involves one iteration or update of the LDPC decoder to determine the decoded bit value 702 depending on the input log-likelihood ratio 704.
[0103] Decoding bit 702 is the symbol for the total log-likelihood ratio 706.
[0104] The total log-likelihood ratio 706 is determined by the addition 708 of the check node to variable node message 700 with a value 710, which is determined by the difference 711 between the previously determined total log-likelihood ratio sampled from the memory 712 of the previously determined total log-likelihood ratio and the previously determined check node to variable node message sampled from the memory 714 of the previously determined check node to variable node message. In this example, the value 710 and the check node to variable node message 700 are related to the same variable node v. i and the same check section c jThe relevant values are then summed to 708, which is the value of the variable node v. i The total log-likelihood ratio is 706.
[0105] The set of first bit words 716-1,...,716-h is used to determine the check node to variable node message 700. The set of first bit words 716-1,...,716-h is determined based on the corresponding previously determined total log-likelihood ratio sampled from the memory 712 of the previously determined total log-likelihood ratio and the corresponding previously determined check node to variable node message sampled from the memory 714 of the previously determined check node to variable node message.
[0106] Based on the configuration provided by matrix H, the check node to variable node message 700 is determined by processing the set of second bit words 722-1,...,722-h. The set of second bit words 722-1,...,722-h is determined by applying the corresponding corrections 724-1,...,724-h to the corresponding first bit words 716-1,...,716-h. The first bit words 716-1,...,716-h are bit words of a first length, and the second bit words 722-1,...,722-h are bit words of a second length. The second bit words 722-1,...,722-h can be referenced as above. Figure 1 or Figure 4 The set of second bitwords 722-1,...,722-h can be provided to the processing 720 in the corresponding intermediate message. In this example, the processing 720 can be configured to select the size of the bitword with the smallest absolute value of the set of second bitwords 722-1,...,722-h as the size of the check node to variable node message 700, and calculate the sign of its check node to variable node message 700 as the product of the signs of the set of second bitwords 722-1,...,722-h.
[0107] The first processing can be performed in parallel or sequentially, for example, through the same processing unit.
[0108] Processing can be shared across different variable nodes or check nodes. For example, for the same check node but different variable nodes, the same first bitword can be reused to compute the check node to variable node message.
[0109] Figure 8 A second process is described, which computes a check node-to-variable node message 802 corresponding to a variable node and a check node. This second process involves an iteration or update of the LDPC decoder to determine the decoded bit value 804 based on the input log-likelihood ratio 806.
[0110] Decoded bit 804 is the sign of the total log-likelihood ratio. The total log-likelihood ratio is determined by the sum 808 of the set of check node to variable node messages sampled from memory 810, which includes previously determined check node to variable node messages, and the input log-likelihood ratios sampled from memory 820, which includes the set of input log-likelihood ratios.
[0111] The set of check node to variable node messages 802 is determined based on the set of first bit words 816-1,...,816-h. The set of first bit words 816-1,...,816-h is determined based on the corresponding input log-likelihood ratio sampled from memory 820, which includes the set of input log-likelihood ratios, and the corresponding sum 818-1,...,818-h of the previously determined set of check node to variable node messages sampled from memory 810, which includes the previously determined set of check node to variable node messages.
[0112] Based on the configuration provided by matrix H, the check node to variable node message 802 is determined by processing the set of second bit words 822-1,...,822-h. The set of second bit words 822-1,...,822-h is determined by applying the corresponding corrections 824-1,...,824-h to the corresponding first bit words 816-1,...,816-h. The first bit words 816-1,...,816-h are bit words of a first length, and the second bit words 822-1,...,822-h are bit words of a second length. The second bit words 822-1,...,822-h can be referenced as above. Figure 1 or Figure 4 The determination is made as described above. The set of second bitwords 822-1,...,822-h can be provided to the processor 820 in the corresponding message. In this example, the processor 820 can be configured to select the size of the bitword with the smallest absolute value of the set of second bitwords 822-1,...,822-h as the size of the check node to variable node message 800, and to calculate the sign of its check node to variable node message 800 as the product of the signs of the set of second bitwords 822-1,...,822-h.
[0113] This process can be performed in parallel or sequentially, for example, through the same processing unit.
[0114] Processing can be shared across different variable nodes or check nodes. For example, for the same check node and different variable nodes, the same first bitword can be reused to compute the check node to variable node message.
[0115] The sum 808 can be determined using a separate block or by using one of the sum blocks used to determine the first bit word.
Claims
1. A method for using a minimum sum decoder in low-density parity-check code decoding, wherein the method comprises: - The first bit word of the first length (104; 404; 716-1, ..., 716-h; 816-1, ..., 816-h) is received (202, 502) and correlated with the log-likelihood ratio of the bits of the signal. - Obtain a second bit word (112; 408; 722-1, ..., 722-h; 822-1, ..., 822-h) of a second length shorter than the first length, wherein obtaining the second bit word (112; 408; 722-1, ..., 722-h; 822-1, ..., 822-h) includes applying a correction to the first bit word (104; 404; 716-1, ..., 716-h; 816-1, ..., 816-h); - The message (700, 802) is determined based on the set of second bit words (722-1, ..., 722-h; 822-1, ..., 822-h) provided by the parity check matrix, wherein the set of second bit words (722-1, ..., 722-h; 822-1, ..., 822-h) includes the second bit words (112; 408; 722-1, ..., 722-h; 822-1, ..., 822-h). - The symbol of the message (700, 802) is determined by the product of the symbols of the second bit words (112, 408) in the set of second bit words (722-1, ..., 722-h; 822-1, ..., 822-h); and The size of the message (700, 802) is determined by the minimum size of the second bitword (112, 408) in the set of second bitwords (722-1, ..., 722-h; 822-1, ..., 822-h).
2. The method of claim 1, wherein applying the correction comprises: The first bit word (104) is mapped (204) to an intermediate bit word (108) of the first length, wherein the value represented by the intermediate bit word (108) is a fraction of the value represented by the first bit word (104).
3. The method of claim 1, wherein applying the correction comprises: The first bit word (104) is mapped (204) to an intermediate bit word (108) of the first length, wherein the magnitude of the value represented by the intermediate bit word (108) is the magnitude of the value represented by the first bit word (104) minus the offset.
4. The method of claim 1, wherein applying the correction (504) comprises: Look up (504) the second bit word (408) in a table that includes a mapping from the first bit word (404) to the second bit word (408), wherein the mapping includes the correction.
5. The method according to any one of the preceding claims, comprising: The first bitword (716-1, ..., 716-h; 816-1, ..., 816-h) is determined based on the difference between the total log-likelihood ratio and the previously calculated messages (700, 802).
6. An apparatus (102, 402) for decoding a low-density parity-check code using a minimum-sum decoder, wherein the apparatus (102, 402) includes components for: - The first bit word of the first length (104; 404; 716-1, ..., 716-h; 816-1, ..., 816-h) is received (202, 502) and correlated with the log-likelihood ratio of the bits of the signal. - Obtain a second bit word (112; 408; 722-1, ..., 722-h; 822-1, ..., 822-h) of a second length shorter than the first length, wherein obtaining the second bit word (112; 408; 722-1, ..., 722-h; 822-1, ..., 822-h) includes applying a correction to the first bit word (104; 404; 716-1, ..., 716-h; 816-1, ..., 816-h); - The message (700, 802) is determined based on the set of second bit words (722-1, ..., 722-h; 822-1, ..., 822-h) provided by the parity check matrix, wherein the set of second bit words (722-1, ..., 722-h; 822-1, ..., 822-h) includes the second bit words (112; 408; 722-1, ..., 722-h; 822-1, ..., 822-h). - The symbol of the message (700, 802) is determined by the product of the symbols of the second bit words (112, 408) in the set of second bit words (722-1, ..., 722-h; 822-1, ..., 822-h); and The size of the message (700, 802) is determined by the minimum size of the second bitword (112, 408) in the set of second bitwords (722-1, ..., 722-h; 822-1, ..., 822-h).
7. The apparatus (102) of claim 6, wherein the apparatus (102) includes a component configured to: map (204) the first bit word (104) to an intermediate bit word (108) of the first length for applying the correction, wherein the value represented by the intermediate bit word (108) is a fraction of the value represented by the first bit word (104).
8. The apparatus (102) according to claim 6, wherein the apparatus (102) includes a component configured to: map (204) the first bit word (104) to an intermediate bit word (108) of the first length for applying the correction, wherein the magnitude of the value represented by the intermediate bit word (108) is the magnitude of the value represented by the first bit word (104) minus an offset.
9. The apparatus (402) of claim 6, wherein the apparatus (402) includes a component configured to: look up (504) the second bit word (408) in a table including a mapping from the first bit word (404) to the second bit word (408), wherein the mapping includes the correction.
10. The apparatus (102, 402) according to any one of claims 6 to 9, wherein the apparatus (102, 402) includes a component configured to determine the first bit word (716-1, ..., 716-h; 816-1, ..., 816-h) based on the difference between the total log-likelihood ratio and the previously calculated message (700, 802).
11. A non-transient computer-readable medium comprising program instructions for causing a device to perform at least the method according to any one of claims 1 to 5.