Display panel and its manufacturing method, display device

Abstract

A display panel includes: a substrate, a circuit structure layer, and a light-emitting structure layer disposed on the substrate. The substrate includes a first display area and a second display area located at least one side of the first display area. The circuit structure layer includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, and a plurality of connecting lines extending from the second display area to the first display area. The light-emitting structure layer includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one first pixel circuit is electrically connected to at least one first light-emitting element via at least one connecting line. At least one second pixel circuit is electrically connected to at least one second light-emitting element. The orthographic projections of the plurality of connecting lines onto the substrate do not overlap with the orthographic projections of the anodes of the plurality of second light-emitting elements onto the substrate.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display panel and its manufacturing method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, cameras are often installed on display devices to meet shooting needs. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display panel, a method for manufacturing the same, and a display device.

[0005] In one aspect, this disclosure provides a display panel, comprising: a substrate, a circuit structure layer, and a light-emitting structure layer. The substrate includes a first display area and a second display area located at least one side of the first display area. The circuit structure layer is located on the substrate and includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, as well as a plurality of connecting lines extending from the second display area to the first display area. The light-emitting structure layer is located on the side of the circuit structure layer away from the substrate and includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements via at least one connecting line, configured to drive the at least one first light-emitting element to emit light. At least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements, configured to drive the at least one second light-emitting element to emit light. The orthographic projections of the plurality of connecting lines onto the substrate do not overlap with the orthographic projections of the anodes of the plurality of second light-emitting elements onto the substrate.

[0006] In some exemplary embodiments, the plurality of first pixel circuits and the plurality of first light-emitting elements do not overlap in their orthographic projection on the substrate.

[0007] In some exemplary embodiments, the plurality of connecting lines form a grid pattern on the orthographic projection of the substrate.

[0008] In some exemplary embodiments, the plurality of connecting lines are made of a transparent conductive material.

[0009] In some exemplary embodiments, within the second display area, the plurality of first pixel circuits are located on the side of the plurality of second pixel circuits that are away from the first display area.

[0010] In some exemplary embodiments, the second display area is located on at least one side of the first display area along a first direction, and the plurality of first pixel circuits are located on the side of the plurality of second pixel circuits away from the first display area along the first direction.

[0011] In some exemplary embodiments, the plurality of first pixel circuits are spaced apart between the plurality of second pixel circuits.

[0012] In some exemplary embodiments, the orthographic projection of the anode of the at least one second light-emitting element onto the substrate overlaps with the orthographic projection of the connected second pixel circuit onto the substrate.

[0013] In some exemplary embodiments, in a direction perpendicular to the display panel, the circuit structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate; the plurality of connecting lines are located on the third conductive layer.

[0014] In some exemplary embodiments, the plurality of first pixel circuits are located along a first direction on the side of the plurality of second pixel circuits away from the first display area, and the fourth conductive layer includes: a signal line extending along a second direction, wherein the first direction intersects the second direction.

[0015] In some exemplary embodiments, the signal lines of the fourth conductive layer include a plurality of power connection segments extending along a second direction; the third conductive layer includes a power connection island, through which adjacent power connection segments are electrically connected.

[0016] In some exemplary embodiments, the semiconductor layer includes: an active layer of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits; the first conductive layer includes: gates of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits and first capacitor plates of storage capacitors; the second conductive layer includes: second capacitor plates of storage capacitors of the plurality of first pixel circuits and the plurality of second pixel circuits; the third conductive layer includes: a plurality of overlapping islands configured to realize electrical connections between transistors and electrical connections between transistors and signal lines extending along a first direction.

[0017] In some exemplary embodiments, the display panel further includes: an encapsulation structure layer located on the side of the light-emitting structure layer away from the substrate, and a touch structure layer located on the side of the encapsulation structure layer away from the substrate. The touch structure layer includes a plurality of touch electrodes, the plurality of touch electrodes including a metal mesh pattern. The orthographic projection of the metal mesh pattern of the touch structure layer onto the substrate covers the orthographic projection of the plurality of connecting lines onto the substrate.

[0018] In some exemplary embodiments, the orthographic projection of the plurality of connecting lines on the substrate does not overlap with the orthographic projection of the anode of the unconnected first light-emitting element on the substrate.

[0019] On the other hand, embodiments of this disclosure provide a display device including a display panel as described above.

[0020] On the other hand, this disclosure provides a method for fabricating a display panel, for fabricating the display panel as described above. The method includes: fabricating a circuit structure layer on a substrate, the circuit structure layer including a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of connecting lines extending from the second display area to a first display area in a second display area, the second display area being located on at least one side of the first display area; and a light-emitting structure layer on the side of the circuit structure layer away from the substrate, the light-emitting structure layer including a plurality of first light-emitting elements in the first display area and a plurality of second light-emitting elements in the second display area. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements through at least one connecting line, configured to drive at least one first light-emitting element to emit light; at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements, configured to drive at least one second light-emitting element to emit light. The orthographic projections of the plurality of connecting lines on the substrate and the orthographic projections of the anodes of the plurality of second light-emitting elements on the substrate do not overlap.

[0021] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0023] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0024] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0025] Figure 3 for Figure 2 The provided timing diagram for the pixel circuit;

[0026] Figure 4 This is a partial schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0027] Figure 5 This is a planar schematic diagram of a first pixel circuit according to at least one embodiment of the present disclosure;

[0028] Figure 6 for Figure 5 A partial cross-sectional view along the Q-Q' direction;

[0029] Figure 7 for Figure 5 A partial schematic diagram of the second display area after the semiconductor layer has been formed;

[0030] Figure 8 for Figure 5 A partial schematic diagram of the second display area after the first conductive layer has been formed;

[0031] Figure 9 for Figure 5 A partial schematic diagram of the second display area after the formation of the second conductive layer;

[0032] Figure 10 for Figure 5 A partial schematic diagram of the second display area after the formation of the third insulating layer;

[0033] Figure 11 for Figure 5 A partial schematic diagram of the second display area after the formation of the third conductive layer;

[0034] Figure 12 for Figure 5 A partial schematic diagram of the second display area after the fourth insulating layer has been formed;

[0035] Figure 13 This is a schematic diagram showing the extension of the connecting line according to at least one embodiment of the present disclosure;

[0036] Figure 14 This is a schematic diagram of the architecture of the touch structure layer according to at least one embodiment of the present disclosure;

[0037] Figure 15 This is a schematic diagram of the structure of a touch electrode in the form of a metal mesh according to at least one embodiment of the present disclosure;

[0038] Figure 16 This is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0039] Figure 17 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0040] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0041] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0042] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0043] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0044] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0045] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0046] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0047] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0048] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0049] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0050] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0051] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0052] With the development of display technology, existing notch or waterdrop screen designs have gradually become insufficient to meet users' demands for high screen-to-body ratios. A series of display devices with translucent display areas have emerged. In these devices, optical sensors (such as cameras) and other hardware can be placed in the translucent display area. Because no holes are needed, true full-screen displays are possible while ensuring the practicality of the display device. However, current full-screen products suffer from complex manufacturing processes, long average manufacturing times for each step, and high production costs.

[0053] This embodiment provides a display panel, including: a substrate, a circuit structure layer and a light-emitting structure layer disposed on the substrate. The substrate includes a first display area and a second display area located at least one side of the first display area. The circuit structure layer includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, and a plurality of connecting lines extending from the second display area to the first display area. The light-emitting structure layer includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements via at least one connecting line, configured to drive the at least one first light-emitting element to emit light. At least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements, configured to drive the at least one second light-emitting element to emit light. The orthographic projections of the plurality of connecting lines onto the substrate do not overlap with the orthographic projections of the anodes of the plurality of second light-emitting elements onto the substrate.

[0054] The display panel provided in this embodiment, by setting multiple connecting lines located in the circuit structure layer and bypassing the anode arrangement of the second light-emitting element, can meet the circuit design of the display panel without adding manufacturing processes or damaging the display effect, thereby achieving full-screen display.

[0055] In some exemplary embodiments, the orthogonal projection of multiple connecting lines onto the substrate can form a grid pattern. In this example, by having the connecting lines bypass the anode of the second light-emitting element, vias in the area where the second pixel circuit is located can be avoided as much as possible, thus preventing moiré patterns that may be caused by straight lines and improving the display effect of the display panel.

[0056] In some exemplary embodiments, multiple connecting lines can be made of a transparent conductive material. This example ensures the light transmittance of the display panel by using a transparent conductive material for the connecting lines.

[0057] In some exemplary embodiments, within the second display area, a plurality of first pixel circuits may be located on the side of a plurality of second pixel circuits away from the first display area. For example, the second display area may be located on at least one side of the first display area along a first direction, and the plurality of first pixel circuits may be located on the side of the plurality of second pixel circuits away from the first display area along the first direction. In this example, by setting the first pixel circuits to be located on the side of the second pixel circuits away from the first display area, it is possible to avoid compressing the second pixel circuits to arrange the first pixel circuits, without changing the arrangement and size of the second pixel circuits, and also avoid adding redundant pixel circuits, thereby improving the reliability and display effect of the display panel.

[0058] In some exemplary embodiments, in a direction perpendicular to the display panel, the circuit structure layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate; multiple connection lines may be located in the third conductive layer. This example, by placing the connection lines in the third conductive layer, eliminates the need for a separate film layer for the connection lines, thereby reducing the film layer fabrication process, lowering the complexity of the fabrication process, reducing the average fabrication time required for product processing steps, and improving the design compatibility of the display panel while reducing manufacturing costs.

[0059] The following examples illustrate the solution of this embodiment.

[0060] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display panel may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display panel may include a first display area A1 and a second display area A2 located on at least one side of the first display area A1. For example, the second display area A2 may surround the first display area A1. The first display area A1 may be located at the top center of the display area AA. However, this embodiment is not limited to this. For example, the first display area A1 may be located at other positions such as the upper left corner or the upper right corner of the display area AA.

[0061] In some examples, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be other shapes such as rectangle, pentagon, or hexagon.

[0062] In some examples, such as Figure 1As shown, the first display area A1 can be a light-transmitting display area, also known as an under-display camera (FDC) area. The second display area A2 can be a non-light-transmitting display area, also known as a normal display area. The light transmittance of the first display area A1 can be greater than that of the second display area A2. For example, the orthographic projection of hardware such as a photosensor (e.g., a camera, infrared sensor) on the display panel can be located within the first display area A1 of the display panel. In some examples, the first display area A1 can be circular, and the size of the orthographic projection of the photosensor on the display panel can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area can be rectangular, and the size of the orthographic projection of the photosensor on the display panel can be less than or equal to the size of the inscribed circle of the first display area.

[0063] In some examples, such as Figure 1 As shown, the resolution of the second display area A2 can be approximately the same as the resolution of the first display area A1. However, this embodiment is not limited to this. In other examples, the ratio of the resolution of the second display area A2 to the resolution of the first display area A1 can be approximately 0.8 to 1.2.

[0064] In some examples, the display area AA may include at least a plurality of regularly arranged pixel units, a plurality of first signal lines extending along a first direction X (e.g., scan lines, reset control lines, and light emission control lines), and a plurality of second signal lines extending along a second direction Y (e.g., data lines and power lines). The first direction X and the second direction Y may be located in the same plane, and the first direction X intersects the second direction Y; for example, the first direction X may be perpendicular to the second direction Y.

[0065] In some examples, a pixel unit of the display area AA may include three sub-pixels, which may be red, green, and blue sub-pixels respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be red, green, blue, and white sub-pixels respectively.

[0066] In some examples, at least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C structure, an 8T1C structure, a 7T1C structure, or a 5T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0067] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0068] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0069] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described using a 7T1C structure as an example. Figure 3 for Figure 2 The provided timing diagram for the pixel circuit is shown.

[0070] In some examples, such as Figure 2As shown, the pixel circuit of this example may include: six switching transistors (T1, T2, T4 to T7), one driving transistor T3, and one storage capacitor Cst. The six switching transistors are, respectively, a data write transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0071] In some examples, the driving transistor and the six switching transistors can be either P-type or N-type transistors. Using the same type of transistors in the pixel circuitry simplifies the manufacturing process, reduces the complexity of the display panel manufacturing, and improves product yield. In some possible implementations, the driving transistor and the six switching transistors can include both P-type and N-type transistors.

[0072] In some examples, the driving transistor and the six switching transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OTFTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OTFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OTFTs offer advantages such as low leakage current. Integrating LTPS and OTFTs onto a single display panel to form a low-temperature polycrystalline oxide (LTPS+Oxide) display panel leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0073] In some examples, such as Figure 2As shown, the pixel circuit can be electrically connected to the scan line GL, data line DL, first power line PL1, second power line PL2, light emission control line EML, initial signal line INIT, first reset control line RST1, and second reset control line RST2. In some examples, the first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data line DL can be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset signal RESET2 to the pixel circuit.

[0074] In some examples, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GL to be input to the scan signal SCAN. That is, the second reset signal RESET2(n) received by the nth row of pixel circuits is the scan signal SCAN(n) received by the nth row of pixel circuits, where n is a positive integer. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 can be input with a second reset control signal RESET2 different from the scan signal SCAN. In some examples, in the nth row of pixel circuits, the first reset control line RST1 can be connected to the scan line GL of the (n-1)th row of pixel circuits to be input to the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the number of signal lines on the display panel can be reduced, and a narrow bezel on the display panel can be achieved.

[0075] In some examples, such as Figure 2As shown, the driving transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the data writing transistor T4 is electrically connected to the scan line GL, the first terminal of the data writing transistor T4 is electrically connected to the data line DL, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply line PL1, and the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T3. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3. The second terminal of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1. The first terminal of the first reset transistor T1 is electrically connected to the initial signal line INIT. The second terminal of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2. The first terminal of the second reset transistor T7 is electrically connected to the initial signal line INIT. The second terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3. The second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0076] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2; the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3; the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6; and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0077] The following reference Figure 3 right Figure 2 The operation of the pixel circuit shown will be explained. Specifically, using... Figure 2 The pixel circuit shown here comprises multiple P-type transistors, which will be used as an example for illustration. In this example, the second reset control line RST2 can be connected to the scan line GL to receive the scan signal SCAN.

[0078] In some examples, such as Figure 2 and Figure 3 As shown, during a single frame display period, the operation of the pixel circuit can include: a first stage S1, a second stage S2, and a third stage S3.

[0079] The first stage, S1, is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1. The initial signal provided by the initial signal line INIT is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. During this stage, the light-emitting element EL does not emit light.

[0080] The second stage, S2, is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is low, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high. The data line DL outputs the data signal DATA. During this stage, because the second electrode of the storage capacitor Cst is low, the driving transistor T3 is turned on. The low scan signal SCAN turns on the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7. Threshold compensation transistor T2 and data write transistor T4 are turned on, allowing the data voltage Vdata output from data line DL to be supplied to first node N2 via second node N2, the turned-on drive transistor T3, third node N3, and the turned-on threshold compensation transistor T2. The difference between the data voltage Vdata output from data line DL and the threshold voltage of drive transistor T3 is charged into storage capacitor Cst. The voltage at the first capacitor plate of storage capacitor Cst (i.e., first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from data line DL and Vth is the threshold voltage of drive transistor T3. Second reset transistor T7 is turned on, allowing the initial signal Vinit provided by initial signal line INIT to be supplied to the anode of light-emitting element EL, initializing (resetting) the anode of light-emitting element EL, clearing its internal pre-stored voltage, completing the initialization, and ensuring that light-emitting element EL does not emit light. The first reset control signal RESET1 provided by first reset control line RST1 is a high-level signal, causing the first reset transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, which disconnects the first light emission control transistor T5 and the second light emission control transistor T6.

[0081] The third stage, S3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control signal line EML is low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The first voltage signal VDD output from the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0082] During the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and its first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0083] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[(VDD-Vdata)] 2 ;

[0084] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0085] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the driving transistor T3.

[0086] Figure 4 This is a partial schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 4 As shown, the first display area A1 of the display panel may include a plurality of first light-emitting elements 21 arranged in an array; the second display area A2 may include a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12 arranged in an array, as well as a plurality of second light-emitting elements (not shown). In this example, the second display area A2 may surround the first display area A1. Within the second display area A2, the plurality of first pixel circuits 11 may be located along a first direction X on the side of the plurality of second pixel circuits 12 away from the first display area A1. For example, the plurality of first pixel circuits 11 may be located at the edge of the second display area A2 near the peripheral area in the first direction X. The plurality of first pixel circuits 11 may be arranged near the left and right border areas.

[0087] In some examples, such as Figure 4As shown, multiple pixel circuits arranged along the first direction X can be referred to as a row of pixel circuits, and multiple pixel circuits arranged along the second direction Y can be referred to as a column of pixel circuits. Within the second display area A2, at least one column of first pixel circuits 11 can be arranged at the edge of the multiple columns of second pixel circuits 12. For example, multiple columns (e.g., three, four, or five columns) of first pixel circuits 11 can be arranged on opposite sides of the multiple columns of second pixel circuits 12 along the first direction X. The number of columns of first pixel circuits 11 arranged on opposite sides of the multiple columns of second pixel circuits 12 along the first direction X can be the same (e.g., three columns of first pixel circuits are arranged on each opposite side). This example, by placing the first pixel circuits at the edge of the second pixel circuits, eliminates the need to compress the second pixel circuits during arrangement, avoiding excessive redundant pixel circuits. Furthermore, it maintains the arrangement and size of the second pixel circuits, improving their reliability and ultimately enhancing the display effect of the display panel.

[0088] In some examples, at least one first pixel circuit 11 in the second display area A2 can be electrically connected to at least one first light-emitting element 21 in the first display area A1 via at least one connecting line, and is configured to drive the first light-emitting element 21 to emit light. The orthographic projection of the first light-emitting element 21 onto the substrate and the orthographic projection of the electrically connected first pixel circuit 11 onto the substrate may not overlap. For example, one end of the connecting line may be electrically connected to the first pixel circuit 11, and the other end may extend from the second display area A2 to the first display area A1 and be electrically connected to the first light-emitting element 21 in the first display area A1. At least one second pixel circuit 12 in the second display area A2 can be electrically connected to at least one second light-emitting element, and is configured to drive the second light-emitting element to emit light. The orthographic projection of the second light-emitting element onto the substrate and the orthographic projection of the electrically connected second pixel circuit 12 onto the substrate may overlap.

[0089] In some examples, such as Figure 4 As shown, the first display area A1 may have a first center line OO' along the first direction X. The first light-emitting element 21 in the left half of the first display area A1 within the first center line OO' can be electrically connected via connecting lines to multiple (e.g., three) columns of first pixel circuits 11 near the left edge of the second display area. The first light-emitting element 21 in the right half of the first display area A1 within the first center line OO' can be electrically connected via connecting lines to multiple (e.g., three) columns of first pixel circuits 11 near the right edge of the second display area. In this example, one first pixel circuit can be configured to drive one first light-emitting element to emit light, or it can be configured to drive two or more first light-emitting elements emitting the same color light to emit light. However, this embodiment is not limited to this.

[0090] Figure 5This is a planar schematic diagram of a first pixel circuit according to at least one embodiment of the present disclosure. Figure 6 for Figure 5 A partial cross-sectional view along the Q-Q' direction.

[0091] In some examples, such as Figure 5 As shown, in a plane parallel to the display panel, the display panel may include scan lines GL(n), light emission control lines EML(n), first reset control lines RST1(n) and RST1(n+1), initial signal lines INIT(n) and INIT(n+1), data lines DL, multiple power connection segments (e.g., power connection terminals 411 and 412), and a first pixel circuit. The first pixel circuit may include multiple transistors and a storage capacitor Cst. The multiple transistors may include: a driving transistor T3, a data writing transistor T4, a threshold compensation transistor T2, a first reset transistor T1, a second reset transistor T7, a first light emission control transistor T5, and a second light emission control transistor T6.

[0092] exist Figure 5 The diagram illustrates multiple transistors T1 to T7 of the first pixel circuit in row n, the second reset transistor T7' of the first pixel circuit in row (n-1), and the first reset transistor T1' of the first pixel circuit in row (n+1). Figure 5 As shown, the first reset transistor T1 of the first pixel circuit in row n is electrically connected to the first reset control line RST1(n), which is also electrically connected to the scan line GL(n-1) connected to the first pixel circuit in row (n-1). The second reset transistor T7' of the first pixel circuit in row (n-1) is also electrically connected to the first reset control line RST1(n), thus realizing the input scan signal SCAN(n-1). Similarly, the first reset transistor T1' of the first pixel circuit in row (n+1) is electrically connected to the first reset control line RST1(n+1), which is also electrically connected to the scan line GL(n) connected to the first pixel circuit in row n. The second reset transistor T7' of the first pixel circuit in row n is also electrically connected to the first reset control line RST1(n+1), thus realizing the input scan signal SCAN(n).

[0093] In some examples, such as Figure 6As shown, in the direction perpendicular to the display panel, the circuit structure layer of the display panel may include: a semiconductor layer 30, a first conductive layer 31, a second conductive layer 32, a third conductive layer 33, and a fourth conductive layer 34 sequentially disposed on the substrate 100. A first insulating layer 101 may be disposed between the semiconductor layer 30 and the first conductive layer 31; a second insulating layer 102 may be disposed between the first conductive layer 31 and the second conductive layer 32; a third insulating layer 103 may be disposed between the second conductive layer 32 and the third conductive layer 33; and a fourth insulating layer 104 may be disposed between the third conductive layer 33 and the fourth conductive layer 34. A fifth insulating layer may be disposed on the side of the fourth conductive layer 34 away from the substrate 100. In some embodiments, the first insulating layer 101 to the third insulating layer 103 may be inorganic material layers, and the fourth insulating layer 104 and the fifth insulating layer may be organic material layers. However, this embodiment is not limited in this respect.

[0094] The structure of a display panel is illustrated below using an example of the fabrication process. The "patterning process" described in this disclosure, for metallic, inorganic, or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern."

[0095] In this embodiment of the disclosure, "A and B are in the same layer" or "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is its dimension in the direction perpendicular to the display panel. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0096] In some examples, the fabrication process of the display panel may include the following operations.

[0097] (1). Provide a substrate. In some examples, the substrate can be a flexible substrate or a rigid substrate. For example, the rigid substrate can be made of materials such as glass or quartz. The flexible substrate can be made of materials such as polyimide (PI). The flexible substrate can be a single-layer structure or a stacked structure composed of an inorganic material layer and a flexible material layer. However, this embodiment is not limited thereto.

[0098] (2). Form a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate in the second display area, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer in the second display area.

[0099] Figure 7 is Figure 5 a partial schematic diagram of the second display area after forming the semiconductor layer. In some examples, as Figure 7 shown, the semiconductor layer in the second display area can at least include: active layers of multiple transistors in the first pixel circuit, for example, including the first active layer T10 of the first reset transistor in the first pixel circuit, the second active layer T20 of the threshold compensation transistor, the third active layer T30 of the driving transistor, the fourth active layer T40 of the data writing transistor, the fifth active layer T50 of the first light-emitting control transistor, the sixth active layer T60 of the second light-emitting control transistor, and the seventh active layer T70 of the second reset transistor. Among them, the first active layer T10 to the seventh active layer T70 can be an integrally connected structure. The first active layer T10 and the seventh active layer T70' of the first pixel circuit in the previous row can be an integral structure, and the seventh active layer T10 and the first active layer T10' of the first pixel circuit in the next row can be an integral structure.

[0100] In some examples, as Figure 7 shown, the shapes of the first active layers T10 and T10' can be generally "n"-shaped, the shape of the second active layer T20 can be generally "7"-shaped, the shape of the third active layer T30 can be generally "ji"-shaped, the shape of the fourth active layer T40 can be generally "I"-shaped, and the shapes of the fifth active layer T50, the sixth active layer T06, the seventh active layer T70 and T70' can be generally "L"-shaped.

[0101] In some examples, the active layer of each transistor can include a first region, a second region, and a channel region located between the first region and the second region. In some examples, as Figure 7As shown, the first region T10-1 of the first active layer T10 also serves as the first region of the seventh active layer T70' of the seventh transistor T7' of the first pixel circuit in the previous row; the second region T10-2 of the first active layer T10 also serves as the first region T20-1 of the second active layer T20; the first region T30-1 of the third active layer T30 also serves as the second region T40-2 of the fourth active layer T40 and the second region T50-2 of the fifth active layer T50; the second region T30-2 of the third active layer T30 also serves as the second region T20-2 of the second active layer T20 and the first region T60-1 of the sixth active layer T60; and the second region T60-2 of the sixth active layer T60 also serves as the second region T70-2 of the seventh active layer T70.

[0102] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The first conductive film is patterned by a patterning process to form a first insulating layer covering the semiconductor layer and a first conductive layer disposed on the first insulating layer of the second display area.

[0103] Figure 8 for Figure 5 A partial schematic diagram of the second display area after the first conductive layer has been formed. In some examples, such as... Figure 8As shown, the first conductive layer of the second display area may include at least: a first capacitor plate Cst-1 of the storage capacitor of the first pixel circuit, gates of a plurality of transistors of the first pixel circuit (e.g., including the gate T13 of the first reset transistor of the first pixel circuit, the gate T23 of the threshold compensation transistor, the gate T33 of the driving transistor, the gate T43 of the data writing transistor, the gate T53 of the first light-emitting control transistor, the gate T63 of the second light-emitting control transistor, and the gate T73 of the second reset transistor), a scan line GL(n) extending along the first direction X, a light-emitting control line EML(n), a first reset control line RST1(n), and RST1(n+1). The first capacitor plate Cst-1 of the storage capacitor Cst may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first capacitor plate Cst-1 on the substrate overlaps with the orthographic projection of the third active layer T30 of the driving transistor T3 on the substrate. The first capacitor plate Cst-1 of the storage capacitor Cst may also serve as the gate T33 of the driving transistor T3. The scan line GL(n), the gate T43 of the data writing transistor T4, and the gate T23 of the threshold compensation transistor T2 can be a single integrated structure. The light emission control line EML(n), the gate T53 of the first light emission control transistor T5, and the gate T63 of the second light emission control transistor T6 can be a single integrated structure. The first reset control line RST1(n), the gate T13 of the first reset transistor T1, and the gate T73' of the second reset transistor T7' of the previous row's first pixel circuit can be a single integrated structure. The first reset control line RST1(n+1), the gate T73 of the second reset transistor T7, and the gate T13' of the first reset transistor T1' of the next row's first pixel circuit can be a single integrated structure.

[0104] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second conductive film is patterned by a patterning process to form a second insulating layer covering the first conductive layer and a second conductive layer disposed on the second insulating layer of the second display area.

[0105] Figure 9 for Figure 5 A partial schematic diagram of the second display area after the formation of the second conductive layer. In some examples, such as... Figure 9As shown, the second conductive layer of the second display area may include at least: a second capacitor plate Cst-2 of the storage capacitor Cst of the first pixel circuit, a shielding electrode BK, and initial signal lines INIT(n) and INIT(n+1) extending along the first direction X. The orthographic projection of the second capacitor plate Cst-2 of the storage capacitor Cst onto the substrate may be located between the orthographic projections of the scan line GL(n) and the light emission control line EML(n) onto the substrate. The orthographic projection of the second capacitor plate Cst-2 of the storage capacitor Cst onto the substrate may overlap with the orthographic projection of the first capacitor plate Cst-1 onto the substrate. The second capacitor plate Cst-2 of the storage capacitor Cst may be provided with a cutout region OP, which may include a second insulating layer covering the first capacitor plate Cst-1, and the orthographic projection of the first capacitor plate Cst-1 onto the substrate may include the orthographic projection of the cutout region OP onto the substrate. The shielding electrode BK is located on the side of the scan line GL(n) away from the storage capacitor Cst. The shielding electrode BK is configured to shield the impact of data voltage jumps on critical nodes, preventing data voltage jumps from affecting the potential of critical nodes in the first pixel circuit, thereby improving the display effect.

[0106] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate on which the aforementioned structure is formed, and the third insulating layer is formed by a patterning process. The third insulating layer has multiple vias.

[0107] Figure 10 for Figure 5 A partial schematic diagram of the second display area after the formation of the third insulating layer. In some examples, such as... Figure 10 As shown, the third insulating layer of the second display area can be provided with multiple vias, for example, it may include first vias V1 to eleventh vias V11. Specifically, the third insulating layer, second insulating layer, and first insulating layer within the first vias V1 to sixth vias V6 can be removed, exposing the surface of the semiconductor layer. The third insulating layer and second insulating layer within the seventh via V7 can be removed, exposing the surface of the first conductive layer. The third insulating layer within the eighth vias V8 to eleventh vias V11 can be removed, exposing the surface of the second conductive layer.

[0108] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the aforementioned structure is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer located on the third insulating layer.

[0109] Figure 11 for Figure 5 A partial schematic diagram of the second display area after the formation of the third conductive layer. In some examples, such as... Figure 11As shown, the third conductive layer of the second display area may include at least: multiple overlapping islands (e.g., the first overlapping island 401 to the seventh overlapping island 407) and multiple connecting lines (not shown).

[0110] In some examples, the first overlapping island 401 can be electrically connected to the first region T10-1 of the first active layer of the first reset transistor of the first pixel circuit through the first via V1, and can also be electrically connected to the initial signal line INIT(n) through the eighth via V8. The second overlapping island 402 can be electrically connected to the first region T40-1 of the fourth active layer of the data write transistor of the first pixel circuit through the third via V3. The third overlapping island 403 can be electrically connected to the shielding electrode BK through the ninth via V9. The fourth overlapping island 404 can be electrically connected to the first region T20-1 of the second active layer of the threshold compensation transistor through the second via V2, and can also be electrically connected to the first capacitor plate Cst-1 of the storage capacitor Cst through the seventh via V7. The fifth overlapping island 405 can be electrically connected to the first region T50-1 of the fifth active layer of the first light-emitting control transistor through the fourth via V4, and can also be electrically connected to the second capacitor plate Cst-2 of the storage capacitor Cst through the tenth via V10. The sixth overlapping island 406 can be electrically connected to the second region T60-2 of the sixth active layer of the second light-emitting control transistor through the fifth via V5. The seventh overlapping island 407 can be electrically connected to the first region T70-1 of the seventh active layer of the second reset transistor of the first pixel circuit through the sixth via V6, and can also be electrically connected to the initial signal line INIT(n+1) through the eleventh via V11.

[0111] In some examples, the connecting line connected to the first pixel circuit can be integrated with the sixth overlapping island 406. The connecting line can extend from the second display area to the first display area and be electrically connected to the anode of the first light-emitting element located in the first display area, thereby realizing the electrical connection between the first pixel circuit and the first light-emitting element.

[0112] In some examples, the third conductive layer can be made of a transparent conductive material, such as indium tin oxide (ITO). This example, by making the third conductive layer a transparent conductive material and placing the connecting lines on the third conductive layer, reduces the impact of the connecting line arrangement on the light transmittance of the first display area, ensuring both the display effect and light transmittance of the first display area. In this example, the third conductive layer only has overlapping islands for bonding, without through-path traces along the second direction Y, allowing the connecting lines located on the third conductive layer to extend along the first direction X to electrically connect the first pixel circuit and the first light-emitting element.

[0113] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate on which the aforementioned structure is formed, and the fourth insulating layer is formed by a patterning process. The fourth insulating layer may have multiple vias.

[0114] Figure 12 for Figure 5 A partial schematic diagram of the second display area after the formation of the fourth insulating layer. In some examples, such as... Figure 12 As shown, the fourth insulating layer of the second display area can be provided with multiple vias, for example, it may include vias V21 to V24. The fourth insulating layer within vias V21 to V24 can be removed to expose the surface of the third conductive layer.

[0115] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned structure is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the fourth insulating layer of the second display area.

[0116] In some examples, such as Figure 5 As shown, the fourth conductive layer of the second display area may include at least: a data line DL and multiple power connection segments (e.g., power connection segments 411 and 412). The data line DL may extend along the second direction Y and be electrically connected to the second overlapping island 402 through the twenty-first via V21, thereby achieving an electrical connection with the first terminal of the data writing transistor of the first pixel circuit. Multiple power connection segments may extend along the second direction Y. Power connection segment 411 may be electrically connected to the third overlapping island 403 through the twenty-second via V22, and may also be electrically connected to the fifth overlapping island 405 through the twenty-third via V23. Power connection segment 412 may be electrically connected to the fifth overlapping island 405 through the twenty-fourth via V24. Power connection segments 411 and 412 may be electrically connected through the fifth overlapping island 405. In the second direction Y, power connection segments 411 and 412 can be spaced apart. In the region where the pixel circuit is located, adjacent power connection segments 411 and 412 can be electrically connected to the storage capacitor and the first light-emitting control transistor through the fifth overlapping island 405. In the interval region of the pixel circuit, adjacent power connection segments 411 and 412 can be a single integrated structure. In this example, the power connection segment is electrically connected to the pixel circuit through the fifth overlapping island, which avoids the power connection segment located in the fourth conductive layer directly connecting to the pixel circuit through vias exposing the semiconductor layer. This avoids defects caused by vias with excessive depth in the fabrication process and ensures the transmission effect of the first voltage signal. However, this embodiment is not limited to this. In other examples, the power connection segment located in the fourth conductive layer can be a single integrated structure to achieve the transmission of the first voltage signal. In other examples, the third overlapping island can be omitted, and the power connection segment can be directly electrically connected to the shielding electrode located in the second conductive layer.

[0117] In some examples, the structure of the second pixel circuit in the second display area is roughly the same as that of the first pixel circuit, and therefore will not be described again here. The second light-emitting control transistor of the second pixel circuit can be electrically connected to the anode of the second light-emitting element through the sixth overlapping island located in the third conductive layer; alternatively, the fourth conductive layer may further include an anode connection electrode, and the second light-emitting control transistor of the second pixel circuit can be electrically connected to the anode of the second light-emitting element through the sixth overlapping island located in the third conductive layer and the anode connection electrode located in the fourth conductive layer. This embodiment is not limited in this respect.

[0118] In some examples, after forming the aforementioned structure, the first display area may include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate. Subsequently, an anode thin film may be deposited on the substrate with the aforementioned pattern, and the anode thin film may be patterned using a patterning process to form an anode layer; the anode layer may include the anode of a first light-emitting element located in the first display area and the anode of a second light-emitting element located in the second display area. Subsequently, a pixel definition film is coated, and a pixel definition layer is formed using a masking, exposure, and development process. The pixel definition layer may have multiple pixel openings exposing the anode layer. An organic light-emitting layer is formed within the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode thin film is deposited, and the cathode thin film may be patterned using a patterning process to form a cathode pattern; the cathode is connected to the organic light-emitting layer. Subsequently, an encapsulation structure layer is formed on the cathode; for example, the encapsulation structure layer may include a stacked structure of inorganic / organic / inorganic materials.

[0119] In some examples, the first, second, and third insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first and second insulating layers can be referred to as gate insulating (GI) layers, and the third insulating layer can be referred to as interlayer insulating (ILD) layers. The fourth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The first, second, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. For example, the first and second conductive layers can be made of molybdenum, and the fourth conductive layer can be made of a titanium-aluminum-titanium laminate. The semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), and polycrystalline silicon (p-Si). That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited in this regard.

[0120] The structure and fabrication process of the display panel in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased as needed. For example, the connection line between the first pixel circuit and the first light-emitting element can be located between the third conductive layer and the fourth conductive layer, or between the third conductive layer and the second conductive layer; in this case, the multiple connection lines can be made of transparent conductive material, and the third conductive layer can be made of metal material.

[0121] The preparation process of this exemplary embodiment can be realized using currently mature preparation equipment, is well compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0122] Figure 13 This is a schematic diagram showing the extension of the connecting line according to at least one embodiment of the present disclosure. Figure 13 The diagram uses two connecting lines 13 as an example to illustrate how the connecting lines extend between the second display area A2 and the first display area A1. In some examples, such as... Figure 13As shown, the arrangement of the first light-emitting elements in the first display area A1 can be roughly the same as the arrangement of the second light-emitting elements in the second display area A2. For example, a pixel circuit in the display area may include four sub-pixels, such as a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a third color light. In some examples, the first color light can be blue light, the second color light can be red light, and the third color light can be green light. In the first direction X, the first sub-pixels P1 and P2 are arranged in one row with intervals, and the third sub-pixels P3 and P4 are arranged in another row with intervals, and the rows containing the first and second sub-pixels P1 and P2 are misaligned with the rows containing the third and fourth sub-pixels P3 and P4. In the second direction Y, the first sub-pixel P1 and the second sub-pixel P2 can be arranged in a column with intervals, and the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged in a column with intervals, and the column where the first sub-pixel P1 and the second sub-pixel P2 are located is misaligned with the column where the third sub-pixel P3 and the fourth sub-pixel P4 are located.

[0123] In some examples, such as Figure 13 As shown, one end of the connecting line 13 can be electrically connected to the first pixel circuit 11, and the other end can extend from the second display area A2 to the first display area A1 and be electrically connected to the anode 210 of the corresponding first light-emitting element 21. Within the second display area A2, the orthographic projection of the connecting line 13 onto the substrate and the orthographic projection of the anode 220 of the second light-emitting element onto the substrate may not overlap. In other words, the connecting line 13 can be arranged in the gap area between the anodes 220 of the second light-emitting elements. The orthographic projection of the anode of the second light-emitting element onto the substrate may overlap with the orthographic projection of the connected second pixel circuit onto the substrate. For example, the orthographic projection of the anode of the second light-emitting element onto the substrate may cover all or most of the vias of the second pixel circuit opened in the third insulating layer onto the substrate. In this way, the connecting line 13, by bypassing the anode 220 of the second light-emitting element, can avoid the vias opened in the third insulating layer as much as possible, thereby avoiding moiré patterns that may be caused by straight-lined connecting lines.

[0124] In some examples, such as Figure 13As shown, the orthographic projection of the multiple connecting lines 13 onto the substrate can form a grid. For example, two adjacent connecting lines 13 extending in the same direction (e.g., a direction intersecting both the first direction X and the second direction Y) can be wound sequentially around the anodes 220 of the six second light-emitting elements and around the anodes 220 of the two second light-emitting elements, thus bypassing the anodes of the second light-emitting elements 220. The winding method of the multiple connecting lines 13 in the first display area A1 can be similar to the winding method in the second display area A2. The multiple connecting lines 13 in the first display area A1 can bypass the anodes of the first light-emitting elements that are not connected, and finally be electrically connected to the anode 210 of the first light-emitting elements to which they are connected.

[0125] This example, by designing the routing of the connecting lines and placing them on the third conductive layer, reduces the fabrication process of the display panel. It eliminates the need to fabricate multiple transparent conductive layers on the side of the fourth conductive layer away from the substrate to arrange the connecting lines. Furthermore, the routing method in this example still meets the display panel's performance requirements, thus enabling a full-screen display. The display panel design in this example offers good adaptability and compatibility. Moreover, the fabrication process in this example closely resembles the actual production line process, facilitating its adoption in real-world production and reducing the manufacturing cost of full-screen displays.

[0126] In some examples, the display panel may also include a touch structure layer disposed on the side of the encapsulation structure layer away from the substrate. For example, a structure forming the touch structure layer on a thin-film encapsulation (TFE) layer. The integrated display and touch structures offer advantages such as thinness and foldability, meeting the requirements of flexible folding products. Touch on TFE structures mainly include Flexible Multi-Layer On Cell (FMLOC) and Flexible Single-Layer On Cell (FSLOC) structures. The FMLOC structure operates based on mutual capacitance detection, typically using two metal layers to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) detects the mutual capacitance between the driving and sensing electrodes to achieve touch operation. The FSLOC structure operates based on self-capacitance (or voltage) detection, typically using a single metal layer to form the touch electrode. The integrated circuit detects the self-capacitance (or voltage) of the touch electrode to achieve touch operation.

[0127] Figure 14 This is a schematic diagram of the architecture of a touch structure layer according to at least one embodiment of the present disclosure. In this example, two overlapping metal layers forming mutual capacitance are used for illustration. In some examples, such as... Figure 14As shown, the display area may include multiple first touch units 510 and multiple second touch units 520. The first touch units 510 may extend along a first direction X, and the multiple first touch units 510 may be arranged sequentially along a second direction Y. The second touch units 520 may extend along the second direction Y, and the multiple second touch units 520 may be arranged sequentially along the first direction X. Each first touch unit 510 may include multiple first touch electrodes 511 and multiple first connecting portions 512 arranged sequentially along the first direction X, with the first touch electrodes 511 and first connecting portions 512 alternately arranged and sequentially connected. Each second touch unit 520 may include multiple second touch electrodes 521 arranged sequentially along the second direction Y, with the multiple second touch electrodes 521 spaced apart, and adjacent second touch electrodes 521 connected to each other via second connecting portions 522. In some examples, the film layer where the second connecting portion 522 is located may be different from the film layer where the first touch electrodes 511 and the second touch electrodes 521 are located.

[0128] In some examples, multiple first touch electrodes 511, multiple second touch electrodes 521, and multiple first connection portions 512 can be disposed on the same layer of the touch layer and formed by the same patterning process. The first touch electrodes 511 and the first connection portions 512 can be an integral structure interconnected with each other. The second connection portions 522 can be disposed on a bridging layer, and adjacent second touch electrodes 521 can be electrically connected to each other through vias. A touch insulating layer can be disposed between the touch layer and the bridging layer. In other examples, multiple first touch electrodes 511, multiple second touch electrodes 521, and multiple second connection portions 522 can be disposed on the same layer of the touch layer. The second touch electrodes 521 and the second connection portions 522 can be an integral structure interconnected with each other. The first connection portions 512 can be disposed on a bridging layer, and adjacent first touch electrodes 511 can be interconnected with each other through vias. In some exemplary embodiments, the first touch electrode can be a sensing (Rx) electrode, and the second touch electrode can be a driving (Tx) electrode. Alternatively, the first touch electrode can be a driving (Tx) electrode, and the second touch electrode can be a sensing (Rx) electrode. However, this embodiment is not limited to this.

[0129] In some examples, the first touch electrode 511 and the second touch electrode 521 can be in the form of a metal mesh, which is formed by multiple interwoven metal wires. The metal mesh includes multiple mesh patterns, and each mesh pattern is a polygon composed of multiple metal wires. In some examples, the mesh pattern formed by the metal wires can be a regular shape or an irregular shape, and the edges of the mesh pattern can be straight lines or curves; this disclosure does not limit the specific shapes. In some examples, the linewidth of the metal wires can be less than or equal to 5 micrometers (μm). The first and second touch electrodes in the form of a metal mesh have advantages such as low resistance, small thickness, and fast response speed.

[0130] Figure 15 This is a schematic diagram of the structure of a touch electrode in the form of a metal mesh, according to at least one embodiment of the present disclosure. Figure 15 for Figure 14 A magnified view of a portion of region S0. In this example, the grid pattern can be rhomboid, and the edges of the grid pattern can be curved. For example... Figure 15 As shown, to insulate the first touch electrode 511 and the second touch electrode 521 from each other, multiple cuts can be provided on the metal mesh. These cuts break the metal lines of the mesh pattern, forming an invalid connection area 601 between the first touch electrode 511 and the second touch electrode 521, thereby isolating the mesh patterns of the first touch electrode 511 and the second touch electrode 521. In some embodiments, the cut can be a straight line or a broken line formed by connecting some straight lines, further solving the visualization problem at the cut line break.

[0131] In some examples, each grid pattern in the invalid connection area 601 may have a cutout that severs the metal lines of the grid pattern, dividing each grid pattern into two parts: one part belonging to the first touch electrode 511 and the other part belonging to the second touch electrode 521, or one part belonging to the second touch electrode 521 and the other part belonging to the first touch electrode 511. In some examples, the first connecting portion 512 and the first touch electrode 511 may be an integral structure configured to connect the two first touch electrodes 511. For example, the first connecting portion 512 may be a grid pattern connecting the two first touch electrodes 511. The second connecting portion 522 and the second touch electrode 521 are disposed in separate layers and configured to connect the two second touch electrodes 521. For example, the second connecting portion 522 may include two parallel arc-shaped connecting lines, one end of each arc-shaped connecting line connected to one second touch electrode 521 and the other end connected to the other second touch electrode 521.

[0132] In some examples, the projection of the interconnects within the circuit structure layer onto the substrate can be covered by the projection of the metal mesh pattern of the touch electrodes onto the substrate. The interconnects within the circuit structure layer can be arranged in the same manner as the metal mesh pattern of the touch electrodes. This avoids the interconnects affecting the display and touch performance of the display panel.

[0133] Figure 16 This is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 16As shown, within the second display area A2, multiple first pixel circuits 11 can be spaced apart among multiple second pixel circuits 12. For example, the display panel of this example can employ a pixel circuit compression scheme. By reducing the size of the second pixel circuits in the first direction X, the first pixel circuits 11 and second pixel circuits 12 can be arranged in the first direction X, thereby distributing the multiple first pixel circuits 11 among the multiple second pixel circuits 12. For example, the first direction X can be a row direction, and in the same row of pixel circuits, the first pixel circuits 11 can be spaced apart among the multiple second pixel circuits 12. The remaining structure of the display panel of this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0134] This embodiment also provides a method for fabricating a display panel, comprising: fabricating a circuit structure layer on a substrate, the circuit structure layer including a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of connecting lines extending from the second display area to a first display area in a second display area, the second display area being located on at least one side of the first display area; a light-emitting structure layer on the side of the circuit structure layer away from the substrate, the light-emitting structure layer including a plurality of first light-emitting elements in the first display area and a plurality of second light-emitting elements in the second display area; at least one first pixel circuit being electrically connected to at least one first light-emitting element through at least one connecting line, configured to drive at least one first light-emitting element to emit light; at least one second pixel circuit being electrically connected to at least one second light-emitting element, configured to drive at least one second light-emitting element to emit light. Wherein, the orthographic projections of the plurality of connecting lines on the substrate and the orthographic projections of the anodes of the plurality of second light-emitting elements on the substrate do not overlap.

[0135] The method for preparing the display panel in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0136] At least one embodiment of this disclosure also provides a display device, including the display panel described above.

[0137] Figure 17 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 17 As shown, this embodiment provides a display device, including: a display panel 91 and a photosensor 92 located on the light-emitting side of a display structure layer away from the display panel 91. The orthographic projection of the photosensor 92 on the display panel 91 overlaps with the first display area A1.

[0138] In some examples, the display panel 91 can be a flexible OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel. The display device can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments disclosed herein are not limited thereto.

[0139] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate, comprising a first display area and a second display area located at least one side of the first display area; a circuit structure layer located on the substrate, comprising a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, and a plurality of connection lines extending from the second display area to the first display area; a light-emitting structure layer located on the side of the circuit structure layer away from the substrate, comprising a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area; at least one first pixel circuit in the plurality of first pixel circuits is electrically connected to at least one first light-emitting element in the plurality of first light-emitting elements through at least one connection line, and is configured to drive the at least one first light-emitting element to emit light; at least one second pixel circuit in the plurality of second pixel circuits is electrically connected to at least one second light-emitting element in the plurality of second light-emitting elements, and is configured to drive the at least one second light-emitting element to emit light; the plurality of connection lines do not overlap with the anodes of the plurality of second light-emitting elements in the projection of the substrate; in a direction perpendicular to the display panel, the circuit structure layer comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the substrate; the fourth conductive layer comprises a signal line extending in the second direction, and the signal line of the fourth conductive layer comprises a plurality of power connection segments extending in the second direction; the third conductive layer comprises a power overlap island, and adjacent power connection segments are electrically connected through the power overlap island.

2. The display panel of claim 1, wherein, The plurality of first pixel circuits and the plurality of first light-emitting elements do not overlap in the projection of the substrate.

3. The display panel of claim 1, wherein, The plurality of connection lines form a grid pattern in the projection of the substrate.

4. The display panel of claim 1, wherein, The plurality of connection lines are made of transparent conductive material.

5. The display panel of claim 1, wherein, In the second display area, the plurality of first pixel circuits are located on the side of the plurality of second pixel circuits away from the first display area.

6. The display panel of claim 5, wherein, The second display area is located on at least one side of the first display area along a first direction, and the plurality of first pixel circuits are located on the side of the plurality of second pixel circuits away from the first display area along the first direction.

7. The display panel of claim 1, wherein, The plurality of first pixel circuits are distributed between the plurality of second pixel circuits.

8. The display panel of claim 1, wherein, The anode of the at least one second light-emitting element overlaps with the connected second pixel circuit in the projection of the substrate.

9. The display panel of claim 1, wherein, The plurality of connection lines are located in the third conductive layer.

10. The display panel of claim 9, wherein, The plurality of first pixel circuits are located on the side of the plurality of second pixel circuits away from the first display area along a first direction, and the first direction intersects the second direction.

11. The display panel of claim 9, wherein, The semiconductor layer comprises active layers of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits; the first conductive layer comprises gates of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits and first capacitor plates of storage capacitors; the second conductive layer comprises second capacitor plates of storage capacitors of the plurality of first pixel circuits and the plurality of second pixel circuits; and the third conductive layer comprises a plurality of overlapping islands configured to realize electrical connections between transistors and electrical connections between transistors and signal lines extending in the first direction.

12. The display panel of claim 1, wherein, The display panel further comprises an encapsulation structure layer located on a side of the light-emitting structure layer away from the substrate, and a touch structure layer located on a side of the encapsulation structure layer away from the substrate, the touch structure layer comprising a plurality of touch electrodes, the plurality of touch electrodes comprising a metal mesh pattern. The metal mesh pattern of the touch structure layer covers the orthographic projection of the plurality of connection lines on the substrate.

13. The display panel of claim 1, wherein, The orthographic projection of the plurality of connection lines on the substrate does not overlap with the orthographic projection of the anodes of the unconnected first light-emitting elements on the substrate.

14. A display device comprising: A display panel as claimed in any one of claims 1 to 13.

15. A method for manufacturing a display panel, characterized by, A method for manufacturing a display panel as claimed in any one of claims 1 to 13, the method comprising: manufacturing a circuit structure layer on a substrate, the circuit structure layer comprising a plurality of first pixel circuits in a second display area, a plurality of second pixel circuits in the second display area, and a plurality of connection lines extending from the second display area to a first display area, the second display area being located on at least one side of the first display area; manufacturing a light-emitting structure layer on a side of the circuit structure layer away from the substrate, the light-emitting structure layer comprising a plurality of first light-emitting elements in the first display area and a plurality of second light-emitting elements in the second display area, at least one first pixel circuit of the plurality of first pixel circuits being electrically connected to at least one first light-emitting element of the plurality of first light-emitting elements via at least one connection line and configured to drive the at least one first light-emitting element to emit light, at least one second pixel circuit of the plurality of second pixel circuits being electrically connected to at least one second light-emitting element of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light; and the orthographic projection of the plurality of connection lines on the substrate does not overlap with the orthographic projection of the anodes of the plurality of second light-emitting elements on the substrate.

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