Thermal head driving integrated circuit and semiconductor device

Abstract

This invention provides an integrated circuit and semiconductor device for driving a heat head. The integrated circuit for driving a heat head does not have a fixed input direction for the signal that causes it to operate; the signal can be input from either the left or right side of the chip, and signal attenuation can be suppressed. An integrated circuit (1) for driving a heat head includes: an input / output circuit (30) for cascaded connection; and input / output switching signal input terminals (22, 24) for switching whether the input / output circuit (30) is configured as an input circuit or an output circuit.

Description

Technical Field

[0001] This invention relates to integrated circuits and semiconductor devices for driving thermal heads. Background Technology

[0002] There are many examples of using cascaded integrated circuits for hot head driving (hereinafter, integrated circuits are sometimes simply referred to as ICs). In order to optimize the substrate area for mounting the hot head driving IC, the hot head driving IC has internal wiring that runs through the IC (see, for example, Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 63-56466

[0004] In most cases, the IC for driving the hot head is functionally designed as a rectangular shape with a large aspect ratio. The signal that activates the IC becomes unidirectional, for example, input from the right side of the IC and output from the left. Furthermore, if the same signal pads at both ends of the IC are wired internally, signal attenuation is significant, resulting in poor usability. Therefore, there are limitations such as limited design freedom on rigid or flexible substrates for mounting the hot head driver IC, or the inability to configure multiple IC chips. Summary of the Invention

[0005] The purpose of this invention is to provide a hot head driver IC that can input and output signals from either the left or right side of the IC chip without fixing the input and output direction of the signal that drives the hot head driver IC, and can suppress signal attenuation.

[0006] The integrated circuit for driving a hot head according to the present invention includes: a signal input / output circuit for activating the IC for driving a hot head; and an input / output switching signal input terminal for switching whether the signal input / output circuit is set as an input circuit or as an output circuit.

[0007] According to the IC for driving the hot head according to the present invention, the signal that enables the IC to operate can be input from the left or right side of the IC chip, the design freedom of the rigid substrate or flexible substrate on which the IC is mounted is increased, and signal attenuation can be suppressed. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example of a hot-head driving IC according to the first embodiment of the present invention.

[0009] Figure 2 This is a circuit diagram illustrating an example of the input / output circuit according to the first embodiment of the present invention.

[0010] Figure 3This is an example of a cascaded connection of a semiconductor device using the hot-head driving IC of the present invention.

[0011] Figure 4 This is another cascaded connection example of a semiconductor device using the hot-head driving IC of the present invention.

[0012] Figure 5 This is a circuit diagram illustrating an example of the input / output circuit of the second embodiment of the present invention.

[0013] Figure 6 This is a block diagram illustrating an example of a hot-head driving IC according to the second embodiment of the present invention.

[0014] Figure 7 This is a circuit diagram illustrating an example of a PMOS transistor according to the third embodiment of the present invention.

[0015] Figure 8 This is a diagram illustrating an example of the structure of a MOS transistor according to the fourth embodiment of the present invention.

[0016] Figure 9 This is a diagram illustrating another example of the structure of a MOS transistor according to the fourth embodiment of the present invention.

[0017] Figure 10 This is a diagram illustrating an example of the structure of a MOS transistor.

[0018] Label Explanation

[0019] 1. 100: Integrated circuit (IC) for driving the hot head;

[0020] 2: Output circuit;

[0021] 3, 3a: AND circuit;

[0022] 4, 4a: Latch circuit;

[0023] 5: Shift register;

[0024] 6, 7, 10: Buffer circuit;

[0025] 8: Input terminals for data signal lines;

[0026] 9: Output terminal of data signal line;

[0027] 11: Data transmission clock signal input terminal;

[0028] 12: Data transmission clock signal output terminal;

[0029] 15, 16: Strobe signal input / output terminals;

[0030] 19, 20: Latch signal input / output terminals;

[0031] 21, 23: Inverters;

[0032] 22, 24: Input terminals for input / output switching signals;

[0033] 30, 30a, 30b, 30c, 30d: Input / output circuits;

[0034] 34b1, 34b2, 34b3, 34b4: Fuses;

[0035] 57: Gate length. Detailed Implementation

[0036] [First Implementation]

[0037] Hereinafter, the first embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a circuit diagram showing an example of the hot head driving IC 1 in this embodiment.

[0038] Figure 1 The shown IC 1 for driving the hot head includes: a shift register 5 with multiple D-type flip-flops (hereinafter referred to as D-FF), a serial data input terminal 8, a serial data output terminal 9, a serial data transmission clock input terminal 11, a serial data transmission clock output terminal 12, buffer circuits 6, 7, and 10, a latch circuit 4, latch signal input / output terminals 19 and 20, an AND circuit 3, strobe signal input / output terminals 15 and 16, input / output circuits 30a, 30b, 30c, and 30d, an output circuit 2, input / output switching signal input terminals 22 and 24, and inverters 21 and 23.

[0039] This describes the internal connections of IC 1, the driver for the hot head. The serial data input terminal 8 is connected to the shift register 5 via buffer circuit 6. The input and output terminals of multiple D-FFs in the shift register 5 are connected in series. The output terminals of the internal D-FFs of the shift register 5 are connected to the input terminals of the next stage D-FFs and the input terminals of the latch circuits 4 corresponding to each D-FF. The output terminal of the final stage D-FF is connected to the input terminal of the corresponding latch circuit 4 and is connected to the serial data output terminal 9 via buffer circuit 7. The serial data transmission clock input terminal 11 is connected to the serial data transmission clock output terminal 12 and is connected to the clock input terminals of each D-FF inside the shift register 5 via buffer circuit 10.

[0040] The latch signal input / output terminal 19 is connected to the latch signal input terminal of each latch circuit 4 via the input / output circuit 30a, and then to the latch signal input / output terminal 20 via the input / output circuit 30b. Each output of each latch circuit 4 is connected to the first input terminal of the corresponding AND circuit 3. The input / output switching signal input terminal 22 is connected to the input / output switching terminal DIRb of the input / output circuit 30b, and is connected to the input / output switching terminal DIRa of the input / output circuit 30a via the inverter 21.

[0041] The strobe signal input / output terminal 15 is connected to the second input terminal of each AND circuit 3 via input / output circuit 30c, and then to the strobe signal input / output terminal 16 via input / output circuit 30d. Each output of each AND circuit 3 is connected to the input terminal of output circuit 2. The input / output switching signal input terminal 24 is connected to the input / output switching terminal DIRd of input / output circuit 30d, and then to the input / output switching terminal DIRc of input / output circuit 30c via inverter 23. Output circuit 2 outputs a signal to drive the hothead.

[0042] Figure 2 This is a circuit diagram showing an example of the input / output circuit 30 of this embodiment. The input / output circuit 30 of this embodiment includes a first input / output terminal TA31, a second input / output terminal TB32, an input / output switching terminal DIR33, a first P-channel MOS transistor (hereinafter referred to as PMOS transistor) 34, a second PMOS transistor 35, a third PMOS transistor 37, a first N-channel MOS transistor (hereinafter referred to as NMOS transistor) 38, a second NMOS transistor 39, a third NMOS transistor 40, a fourth NMOS transistor 41, a NAND circuit 42, a NOR circuit 43, a first inverter 44, a second inverter 45, a first resistor 46, and a second resistor 47.

[0043] The connections of input / output circuit 30 are explained below. Input / output terminal TA31 is connected to the drain terminal of the second PMOS transistor 35, the drain terminal of the first NMOS transistor 38, the first input terminal of NAND circuit 42, and the first input terminal of NOR circuit 43. Input / output terminal TB32 is connected to the drain terminal of the third PMOS transistor 37, the drain terminal of the fourth NMOS transistor 41, the first terminal of the first resistor 46, and the first terminal of the second resistor 47. Input / output switching terminal DIR33 is connected to the second input terminal of NAND circuit 42, the input terminal of the first inverter 44, and the gate terminal of the first PMOS transistor 34. The output of the first inverter 44 is connected to the second input terminal of NOR circuit 43 and the gate terminal of the second NMOS transistor 39.

[0044] The source terminal of the first PMOS transistor 34 is connected to the VDD terminal. The drain terminal of the first PMOS transistor 34 is connected to the source terminal of the second PMOS transistor 35. The gate terminals of the second PMOS transistor 35 and the first NMOS transistor 38 are connected to the output terminal of the second inverter 45. The source terminal of the first NMOS transistor is connected to the drain terminal of the second NMOS transistor 39. The source terminal of the second NMOS transistor 39 is connected to the GND terminal.

[0045] The output of NAND circuit 42 is connected to the gate terminal of the third PMOS transistor 37. The source terminal of the third PMOS transistor 37 is connected to the VDD terminal. The output of NOR circuit 43 is connected to the gate terminal of the third NMOS transistor 40. The drain terminal of the third NMOS transistor 40 is connected to the second terminal of the first resistor 46. The source terminal of the third NMOS transistor 40 is connected to the GND terminal.

[0046] The gate and source terminals of the fourth NMOS transistor 41 are connected to the GND terminal. The second terminal of the second resistor 47 is connected to the input terminal of the second inverter 45.

[0047] The operation of input / output circuit 30 is explained below. When a high-level signal is input to input / output switching terminal DIR33, the first PMOS transistor 34 and the second NMOS transistor 39 are turned off. The inverter formed by the second PMOS transistor 35 and the first NMOS transistor 38 is not powered and does not operate. When a high-level signal is input to the first input / output terminal TA31, the third PMOS transistor 37 is turned on via NAND circuit 42, and the third NMOS transistor 40 is turned off via NOR circuit 43. The second input / output terminal TB32 outputs a high-level signal. When a low-level signal is input to the first input / output terminal TA31, the third PMOS transistor 37 is turned off via NAND circuit 42, and the third NMOS transistor 40 is turned on via NOR circuit 43. The second input / output terminal TB32 outputs a low-level signal. Input / output circuit 30 operates as a buffer circuit for outputting the signal from the first input / output terminal TA31 to the second input / output terminal TB32.

[0048] When a low-level signal is input to the input / output switching terminal DIR33, the third PMOS transistor 37 is turned off via the NAND circuit 42, and the third NMOS transistor 40 is turned off via the NOR circuit 43. The first PMOS transistor 34 and the second NMOS transistor 39 become on. The inverter composed of the second PMOS transistor 35 and the first NMOS transistor 38 is powered and operates as an inverter. The signal input to the second input / output terminal TB32 is output from the first input / output terminal TA31 via the second inverter 45 and the inverter composed of the second PMOS transistor 35 and the first NMOS transistor 38. The input / output circuit 30 operates as a buffer circuit for outputting the signal from the first input / output terminal TA31 to the second input / output terminal TB32.

[0049] The fourth NMOS transistor 41, the first resistor 46, and the second resistor 47 are inserted as electrostatic discharge (ESD) countermeasures for the second input / output terminal TB32.

[0050] The input / output circuit 30 is described with MOS transistors 34, 35, and 37 as PMOS transistors and MOS transistors 38, 39, and 41 as NMOS transistors. However, the polarities of the VDD and VSS terminals can be interchanged, making MOS transistors 34, 35, and 37 NMOS transistors and MOS transistors 38, 39, and 41 PMOS transistors. In this case, the PMOS and NMOS transistors can be distinguished by referring to one as a first-type MOS transistor and the other as a second-type MOS transistor. Furthermore, the VDD and VSS terminals can be distinguished by referring to one as a first power supply terminal and the other as a second power supply terminal.

[0051] Figure 3 An example is shown of a semiconductor device built into which four hot-head driving ICs, IC 1a to IC 1d, of the present invention are cascaded together. Figure 3 In (a), a high-level signal is input to the input / output switching signal input terminals 22a-22d and 24a-24d of each IC. A strobe signal is input to the strobe signal input / output terminal 15a of the hot-head driver IC 1a, and output from the strobe signal input / output terminal 16a, and then input to the strobe signal input / output terminal 15b of the cascaded hot-head driver IC 1b. Similarly, the strobe signal is sequentially transmitted from the cascaded hot-head driver IC 1b to the hot-head driver IC 1d via the hot-head driver IC 1c. Like the strobe signal, the latch signal is also sequentially transmitted from the hot-head driver IC 1a to the hot-head driver IC 1d.

[0052] exist Figure 3 In (b), a high-level signal is input to the input / output switching signal input terminals 22a-22d of each IC. A low-level signal is input to the input / output switching signal input terminals 24a-24d of each IC. Figure 3 Similarly, in (a), the strobe signal is passed sequentially from the hot head driver IC 1a to the hot head driver IC 1d. The latch signal is passed sequentially from the hot head driver IC 1d to the hot head driver IC 1a in the reverse order of the strobe signal.

[0053] exist Figure 3 In step (c), a low-level signal is input to the input / output switching signal input terminals 22a to 22d of each IC. A high-level signal is input to the input / output switching signal input terminals 24a to 24d of each IC. The strobe signal is passed sequentially from the hot-head driver IC 1d to the hot-head driver IC 1a. The latch signal is passed sequentially from the hot-head driver IC 1a to the hot-head driver IC 1d in the reverse order of the strobe signal.

[0054] exist Figure 3 In (d), low-level signals are input to the input / output switching signal input terminals 22a-22d and 24a-24d of each IC. The strobe signal is sequentially transmitted from the hot-head driver IC 1d to the hot-head driver IC 1a. Similarly, the latch signal is sequentially transmitted from the hot-head driver IC 1d to the hot-head driver IC 1a.

[0055] As explained above, according to the hot-head driving IC 1 of the present invention, the semiconductor device incorporating the hot-head driving IC 1 can be flexibly designed to allow for the placement of the terminals for inputting strobe signals and latch signals to the hot-head driving IC 1 on either the left or right side of the IC chip. This increases the design freedom of rigid or flexible substrates in which the hot-head driving IC 1 is mounted. Here, examples of strobe signals and latch signals have been described, but the data transmission clock signal input terminal 11 and data transmission clock signal output terminal 12 can also be used as input / output terminals.

[0056] Figure 4 Another embodiment of the semiconductor device built into the IC 1 for driving the hot head of the present invention is shown. Figure 4In (a), low-level signals are input to the input / output switching signal input terminals 22a, 22b, 24a, and 24b of the hot-head driver ICs 1a and 1b, and high-level signals are input to the input / output switching signal input terminals 22c, 22d, 24c, and 24d of the hot-head driver ICs 1c and 1d. A strobe signal is input to the strobe signal input / output terminal 16b of the hot-head driver IC 1b and output from the strobe signal input / output terminal 15b, and then input to the strobe signal input / output terminal 16a of the cascaded hot-head driver IC 1a. Simultaneously, a strobe signal is input to the strobe signal input / output terminal 15c of the hot-head driver IC 1c and output from the strobe signal input / output terminal 16c, and then input to the strobe signal input / output terminal 15d of the cascaded hot-head driver IC 1d.

[0057] The latch signal is input to the latch signal input / output terminal 20b of the hot-head driver IC 1b, and output from the latch signal input / output terminal 19b, and then input to the latch signal input / output terminal 20a of the cascaded hot-head driver IC 1a. Simultaneously, the latch signal is input to the latch signal input / output terminal 19c of the hot-head driver IC 1c, and output from the latch signal input / output terminal 20c, and then input to the latch signal input / output terminal 19d of the cascaded hot-head driver IC 1d.

[0058] Built-in Figure 4 The semiconductor device of the hot-head drive IC 1 of the present invention shown in (a) can input strobe signals and latch signals from the central portion of the cascaded connection. This increases the design freedom of signal routing. Furthermore, since the number of hot-head drive ICs 1 through which the strobe signals and latch signals pass is halved, the delay of the strobe signals and latch signals caused by the hot-head drive IC 1 is reduced. The hot-head drive IC 1 can operate at a higher speed.

[0059] exist Figure 4 In (b), high-level signals are input to the input / output switching signal input terminals 22a, 22b, 24a, and 24b of the hot-head driving ICs 1a and 1b, and low-level signals are input to the input / output switching signal input terminals 22c, 22d, 24c, and 24d of the hot-head driving ICs 1c and 1d. A strobe signal is input to the strobe signal input / output terminal 15a of the hot-head driving IC 1a and output from the strobe signal input / output terminal 16a, and then input to the strobe signal input / output terminal 15b of the cascaded hot-head driving IC 1b. Simultaneously, a strobe signal is input to the strobe signal input / output terminal 16d of the hot-head driving IC 1d and output from the strobe signal input / output terminal 15d, and then input to the strobe signal input / output terminal 16c of the cascaded hot-head driving IC 1c.

[0060] The latch signal is input to the latch signal input / output terminal 19a of the hot-head driver IC 1a, and output from the latch signal input / output terminal 20a, and then input to the latch signal input / output terminal 19b of the cascaded hot-head driver IC 1b. Simultaneously, the latch signal is input to the latch signal input / output terminal 20d of the hot-head driver IC 1d, and output from the latch signal input / output terminal 19d, and then input to the latch signal input / output terminal 20c of the cascaded hot-head driver IC 1c.

[0061] Built-in Figure 4 The semiconductor device of IC 1 for driving the hot head shown in (b) of the present invention can input strobe signals and latch signals from both ends of a cascaded connection after splitting. This increases the design freedom of signal routing. Furthermore, with... Figure 4 Similarly to example (a), since the number of hot-head driver ICs 1 that the strobe signal and latch signal pass through is halved, the delay of the strobe signal and latch signal caused by the hot-head driver IC 1 is reduced. The hot-head driver IC 1 can operate at a higher speed.

[0062] As explained above, the design freedom of the signal wiring of the semiconductor device incorporating the hot-head driver IC is increased according to this embodiment. Furthermore, by inserting input / output circuits, signal attenuation can be suppressed. By segmenting the cascaded connection of the hot-head driver IC, the number of hot-head driver ICs (cascaded connection stages) through which drive signals such as strobe signals pass can be reduced, signal delay is reduced, and thus higher-speed signals can be input to activate the device. In this embodiment, in Figure 4 In (b), an example of dividing the cascaded connection into two parts is described, but it can also be divided into three or more parts. By dividing the cascaded connection into multiple parts, the semiconductor device can be operated by receiving higher-speed signals. In this embodiment... Figure 3 and Figure 4 The example shown illustrates a configuration of four IC chips for the heat head driver. However, even when more IC chips, such as ten or more IC chips, are cascaded together, good operation can still be achieved without signal attenuation.

[0063] [Second Implementation]

[0064] Hereinafter, the second embodiment of the present invention will be described with reference to the accompanying drawings. Figure 5 This is a circuit diagram showing an example of the input / output circuit 30a of this embodiment. Structural elements identical to those in the first embodiment are labeled with the same reference numerals, and descriptions are omitted.

[0065] The input / output circuit 30a of the second embodiment is obtained by changing the insertion position of the second inverter 45 of the input / output circuit 30 of the first embodiment. The input terminal of the second inverter 45 is connected to the first input / output terminal TA31. The output terminal of the second inverter 45 is connected to the first input terminal of the NAND circuit 42 and the first input terminal of the NOR circuit 43. The gate terminal of the second PMOS transistor 35a and the gate terminal of the first NMOS transistor 38a are connected to the second terminal of the second resistor 47.

[0066] Figure 6 This is a circuit diagram illustrating an example of the IC 100 for driving the hot head according to this embodiment. In this embodiment, the input signal of the input / output circuit 30a is logically opposite to the output signal, and it operates as an inverter. The input latch signal terminal of the latch circuit 4a is set to a negative logic input terminal. Similarly, the input strobe signal terminal of the AND circuit 3a is set to a negative logic input terminal.

[0067] In this embodiment, the transistor sizes of the second PMOS transistor 35a and the first NMOS transistor 38a, whose gate terminals are connected to the second input / output terminal TB32, and the first PMOS transistor 34a and the second NMOS transistor 39a, which supply current to the second PMOS transistor 35a and the first NMOS transistor 38a, are larger than the transistor size of the first inverter 44 or the second inverter 45 (not shown) that constitutes the signal inside the IC 100 for driving the hot head.

[0068] The second input / output terminal TB32 is led out to the outside of the hothead driver IC 100. By enlarging the second PMOS transistor 35a and the first NMOS transistor 38a, whose gate terminals are connected to the second input / output terminal TB, the gate terminal withstand voltage of the two transistors is increased, making the second input / output terminal TB less susceptible to external static electricity and other influences. The ESD (Electro Static Discharge) resistance of the hothead driver IC 100 is improved. Furthermore, the first input / output terminal TA31 is connected internally to the internal wiring along the long side of the IC chip within the hothead driver IC 100. By enlarging the first PMOS transistor 34a, the second PMOS transistor 35a, the first NMOS transistor 38a, and the second NMOS transistor 39a, the current supply capability of the first input / output terminal TA31 to the internal wiring of the hothead driver IC 100 is increased, suppressing signal waveform distortion via the internal wiring.

[0069] As explained above, the hot-head driving IC according to this embodiment has improved ESD resistance at its input terminals, which can suppress distortion of signal waveforms transmitted through the internal wiring of the IC.

[0070] [Third Implementation]

[0071] The third embodiment of the present invention will be described. In this embodiment, at least one of the first PMOS transistor 34a, the second PMOS transistor 35a, the first NMOS transistor 38a, and the second NMOS transistor 39a of the second embodiment is formed by connecting a plurality of series-connected MOS transistors in parallel with a fuse element. The first PMOS transistor 34a and the second NMOS transistor 39a operate to supply current to the inverter formed by the second PMOS transistor 35a and the first NMOS transistor 38a.

[0072] Reference Figure 7 This describes an example of the MOS transistor in this embodiment. Figure 7 In this process, multiple PMOS transistors 34an (n = 1, 2, 3, ...) such as PMOS transistors 34a1 and PMOS transistors 34a2, and multiple fuse elements 34bn (n = 1, 2, 3, ...) such as fuse elements 34b1 and fuse elements 34b2 connected in series with the PMOS transistors 34an are connected in parallel to form the first PMOS transistor 34a.

[0073] The internal wiring connected to the first input / output terminal TA31 has wiring resistance and wiring capacitance. When the current supply capability of the input / output circuit 30a is too large relative to the internal wiring, the output signal overshoots. When the current supply capability of the input / output circuit 30a is too small relative to the internal wiring, the output signal waveform is dulled. By cutting off several fuse elements 34bn, the number of MOS transistors forming the first PMOS transistor 34a can be adjusted, and the current supply capability of the input / output circuit 30a can be set to minimize the distortion of the output signal to the internal wiring. Cutting off fuse elements 34bn produces the same effect as changing the gate width of the first PMOS transistor 34a. The fuse elements 34bn can be composed of fuse elements that are cut off by a large current, fuse elements that are cut by a laser, MOS transistors with floating gates that can electrically rewrite the on / off state, etc.

[0074] Here, an example is given of a first PMOS transistor 34a consisting of multiple PMOS transistors 34an, but the second PMOS transistor 35a, the first NMOS transistor 38a, and the second NMOS transistor 39a can also adopt the same structure.

[0075] As explained above, the hot-head driving IC according to this embodiment can minimize the distortion of the signal waveform through the internal wiring of the hot-head driving IC.

[0076] [Fourth Implementation]

[0077] The fourth embodiment of the present invention will be described. In this embodiment, the size (length) of at least one of the first PMOS transistor 34a, the second PMOS transistor 35a, the first NMOS transistor 38a, and the second NMOS transistor 39a from the second embodiment in the direction connecting the source and drain electrodes is formed to be larger than the size (length) of the transistor (not shown) constituting the signal input to the IC 100 for driving the hot head. By changing the gate length, the current supply capability of such a MOS transistor can be varied.

[0078] Reference Figure 8 and Figure 9 This describes the MOS transistor of this embodiment. Figure 8 (a) is a diagram of the MOS transistor 34b1 as viewed from above. Figure 8 (b) is the AB cross-sectional view of PMOS transistor 34b1. Figure 9 (a) is a diagram of the PMOS transistor 34b2 as viewed from above. Figure 9 (b) is a CD cross-sectional view of PMOS transistor 34b2. Figure 8 The PMOS transistor 34b1 shown is formed by a source electrode 51, a drain electrode 52, a gate electrode 53, an oxide insulating film 54, a source electrode contact hole 55, and a drain electrode contact hole 56. The gate length 57 is the distance between the source electrode 51 and the drain electrode 52. Figure 9 The PMOS transistor 34b2 shown is formed by a source electrode 51, a drain electrode 52a, a gate electrode 53a, an oxide insulating film 54a, a source electrode contact hole 55, and a drain electrode contact hole 56a. The gate length 57a is the spacing between the source electrode 51 and the drain electrode 52a. The gate length 57a of PMOS transistor 34b1 is smaller than that of PMOS transistor 34b2. The dimension 58 in the direction connecting the source and drain electrodes of PMOS transistor 34b1 is the same as that of PMOS transistor 34b2 in the direction connecting the source and drain electrodes.

[0079] Reference Figure 10 A comparative example illustrating a MOS transistor. Figure 10 (a) is a diagram of the PMOS transistor 34b viewed from above. Figure 10 (b) is the EF cross-sectional view of PMOS transistor 34b. Figure 10The PMOS transistor 34b shown is formed by a source electrode 51, a drain electrode 52b, a gate electrode 53, an oxide insulating film 54b, a source electrode contact hole 55, and a drain electrode contact hole 56b. The gate length 57 is the spacing between the source electrode 51 and the drain electrode 52b. The gate length 57 of the MOS transistor 50b is equal to the gate length 57 of the PMOS transistor 34b1. The size 58b of the PMOS transistor 34b in the direction connecting the source and drain electrodes is smaller than that of the PMOS transistors 34b1 and 34b2.

[0080] Figure 8 The PMOS transistor 34b1 shown is Figure 10 The PMOS transistor 34b shown has the same gate length. PMOS transistors 34b1 and 34b have approximately the same on-resistance. Here, the transistor size 58 of PMOS transistor 34b1 in the direction connecting the source and drain electrodes is larger than the transistor size 58b of PMOS transistor 34b. PMOS transistor 34b1 can be replaced with PMOS transistor 34b2, which has its gate length 57 increased as in the case of gate length 57a, without changing the transistor size 58.

[0081] Generally, the on-resistance of a MOS transistor can be adjusted by changing its gate length. Adjusting the on-resistance allows for a change in the current supply capability of the MOS transistor. Thus, PMOS transistors 34b1 and 34b2, which are larger than PMOS transistor 34b, can have their current supply capabilities changed by altering their gate lengths. Furthermore, the source electrode 51 and drain electrode 52 of PMOS transistor 34b1 are sometimes formed by top-side ion implantation, using the gate electrode 53 as part of a mask. According to this manufacturing method, the gate electrode width 57 and gate length 57 can be formed to the same size. Changes in the gate length 57 can be achieved by changing the mask of the gate electrode 53.

[0082] Here, an example of the first PMOS transistor 34a being constructed from PMOS transistor 34b1 is given, but the second PMOS transistor 35a, the first NMOS transistor 38a, and the second NMOS transistor 39a can also adopt the same structure.

[0083] The internal wiring connected to the first input / output terminal TA31 has wiring resistance and wiring capacitance. When the current supply capability of the input / output circuit 30a is too large relative to the internal wiring, the output signal overshoots. When the current supply capability of the input / output circuit 30a is too small relative to the internal wiring, the output signal waveform is dulled. By making the size of the connection between the source and drain electrodes of at least one of the first PMOS transistor 34, the second PMOS transistor 35, the first NMOS transistor 38, and the second NMOS transistor 39 larger than that of the third PMOS transistor 37, the input / output circuit of this embodiment can be configured to have a current supply capability that minimizes waveform distortion of the output signal to the internal wiring.

[0084] As explained above, the hot-head driving IC according to this embodiment can minimize the distortion of the signal waveform through the internal wiring of the hot-head driving IC.

Claims

1. An integrated circuit for driving a hot head, the integrated circuit for driving a hot head having: Cascaded input / output circuits for signals; and The input / output switching signal input terminal switches whether the cascaded connection signal input / output circuit is set as an input circuit or an output circuit. The input / output circuit for the cascaded connection signal includes a first to a third first-conductivity MOS transistor, a first to a third second-conductivity MOS transistor, a NAND circuit, a NOR circuit, a first inverter, and terminals 1 to 3. The first terminal is connected to the drain terminal of the second first conductivity type MOS transistor, the drain terminal of the first second conductivity type MOS transistor, the first input terminal of the NAND circuit, and the first input terminal of the NOR circuit. The second terminal is connected to the drain terminal of the third first conductivity type MOS transistor, the drain terminal of the third second conductivity type MOS transistor, the gate terminal of the second first conductivity type MOS transistor, and the gate terminal of the first second conductivity type MOS transistor. The third terminal is connected to the second input terminal of the NAND circuit, the input terminal of the first inverter, and the gate terminal of the first first conductivity type MOS transistor. The output terminal of the first inverter is connected to the second input terminal of the NOR circuit and the gate terminal of the second MOS transistor. The output terminal of the NAND circuit is connected to the gate terminal of the third, first-conductivity MOS transistor. The output terminal of the NOR circuit is connected to the gate terminal of the third MOS transistor of the second conductivity type. The source terminal of the first MOS transistor of the first conductivity type is connected to the first power supply terminal, and the drain terminal is connected to the source terminal of the second MOS transistor of the first conductivity type. The drain terminal of the second MOS transistor of the second conductivity type is connected to the source terminal of the first MOS transistor of the second conductivity type. The source terminal of the second MOS transistor of the second conductivity type is connected to the second power supply terminal, and the source terminal of the third MOS transistor of the first conductivity type is connected to the first power supply terminal. The source terminal of the third MOS transistor of the second conductivity type is connected to the second power supply terminal.

2. The integrated circuit for driving a hot head according to claim 1, wherein, The input / output circuit for the cascaded connection signal also includes a second inverter. The second inverter is inserted between the second terminal, the gate terminal of the second first conductivity type MOS transistor, and the gate terminal of the first second conductivity type MOS transistor. The input terminal of the second inverter is connected to the second terminal. The output terminal of the second inverter is connected to the gate terminal of the second first conductivity type MOS transistor and the gate terminal of the first second conductivity type MOS transistor.

3. The integrated circuit for driving a hot head according to claim 1, wherein, The input / output circuit for the cascaded connection signal also includes a second inverter. The second inverter is inserted between the first terminal, the first input terminal of the NAND circuit, and the first input terminal of the NOR circuit. The input terminal of the second inverter is connected to the first terminal. The output terminal of the second inverter is connected to the first input terminal of the NAND circuit and the first input terminal of the NOR circuit.

4. The integrated circuit for driving a hot head according to claim 3, wherein, The input / output circuit for the cascaded connection signal also has a fourth second-conductivity MOS transistor. The drain terminal of the fourth MOS transistor of the second conductivity type is connected to the second terminal, and the gate terminal and the source terminal are connected to the second power supply terminal.

5. The integrated circuit for driving a hot head according to claim 3, wherein, At least one of the first first-conductivity MOS transistors, the second first-conductivity MOS transistor, the first second-conductivity MOS transistor, and the second second-conductivity MOS transistor is composed of a transistor whose size ratio is larger than that of either the first inverter or the second inverter.

6. The integrated circuit for driving a hot head according to claim 3, wherein, At least one of the first first conductivity type MOS transistor, the second first conductivity type MOS transistor, the first second conductivity type MOS transistor, and the second second conductivity type MOS transistor is configured by connecting multiple MOS transistors in parallel.

7. The integrated circuit for driving a hot head according to claim 3, wherein, At least one of the first first conductivity type MOS transistor, the second first conductivity type MOS transistor, the first second conductivity type MOS transistor, and the second second conductivity type MOS transistor is composed of a transistor whose source electrode to drain electrode distance ratio is larger than that of the transistor constituting either the first inverter or the second inverter.

8. A semiconductor device comprising an integrated circuit for driving a hot head as described in any one of claims 1 to 7.

9. The semiconductor device according to claim 8, wherein, The integrated circuit for driving the hot head consists of two or more groups connected in cascade.

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