A method of manufacturing a MEMS structure

Abstract

The application relates to a manufacturing method of a MEMS structure, which comprises the following steps: providing a first wafer; depositing a metal layer on a first surface of the first wafer; performing isotropic first etching on the metal layer by taking a patterned photoresist as a mask to obtain a patterned metal layer; performing anisotropic second etching on the first surface of the first wafer by taking the photoresist as a mask to obtain a protruding patterned standard unit layer, wherein the lateral size of the patterned metal layer is smaller than the lateral size of the protruding patterned standard unit layer. The method provided by the application has the advantages that the lateral size difference of the patterned metal layer is provided to perform buffering, and the flow of molten metal to a device functional area during metal layer bonding is reduced.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor structures, and more specifically to a method for manufacturing a MEMS structure. Background Technology

[0002] Currently, eutectic bonding is a crucial method for achieving wafer-level packaging of MEMS products. Eutectic bonding not only provides excellent sealing but also enables wire interconnection, thus its application in MEMS processes is increasingly widespread. Wafer-level eutectic bonding involves growing metal layers in the bonding regions of two wafers to be bonded. Under specific temperature and pressure conditions, the surfaces of the bonding metal layers come into contact, forming a relatively low-temperature molten alloy. After cooling, a solid seal is formed.

[0003] In related technologies, during the eutectic bonding process, the molten liquid alloy may overflow into the functional areas of the chip under certain pressure, affecting the normal use of the device. Summary of the Invention

[0004] This application is made to address the aforementioned problems. According to one aspect of this application, a method for manufacturing a MEMS structure is provided, the method comprising: providing a first wafer; depositing and forming a metal layer on a first surface of the first wafer; performing an isotropic first etching on the metal layer using a patterned photoresist as a mask to obtain a patterned metal layer; and performing an anisotropic second etching on the first surface of the first wafer using the photoresist as a mask to obtain a raised patterned standard cell layer, wherein the lateral dimension of the patterned metal layer is smaller than the lateral dimension of the raised patterned standard cell layer.

[0005] For example, the first etching includes etching the metal layer by wet etching.

[0006] For example, the second etching includes etching the first surface of the first wafer by means of dry etching.

[0007] For example, the lateral dimension of the patterned standard cell layer extending beyond the patterned metal layer is no greater than 10% of the lateral dimension of the patterned standard cell layer.

[0008] For example, the side surface of the patterned metal layer away from the patterned standard cell layer is a first etching surface, and the side surface closer to the patterned standard cell layer is a second etching surface, wherein the area of ​​the first etching surface is smaller than the area of ​​the second etching surface.

[0009] For example, a cap wafer is formed on the second surface of the first wafer and bonded thereto.

[0010] For example, at least one cavity is formed in the cap wafer facing the first wafer.

[0011] For example, the capped wafer is fused to the second surface of the first wafer through the oxide layer.

[0012] For example, the method further includes removing the photoresist by cleaning with an organic solvent.

[0013] For example, the method further includes bonding the patterned standard cell layer to a third wafer after obtaining the raised patterned standard cell layer.

[0014] The manufacturing method in this application uses the same patterned photoresist as a mask to etch the metal layer and the substrate respectively through isotropic first etching and anisotropic second etching, thereby obtaining a patterned metal layer and a raised patterned standard cell layer. The lateral dimension of the metal layer is smaller than the lateral dimension of the raised patterned standard cell layer, which serves as a buffer area to provide a buffer for overflowing metal during subsequent bonding, preventing it from directly entering the functional area of ​​the device and effectively improving production yield. Attached Figure Description

[0015] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0016] Figure 1 A schematic diagram of a MEMS structure in related technologies is shown.

[0017] Figure 2 A flowchart of a manufacturing method in an embodiment of this application is shown.

[0018] Figures 3(a)-3(e) Cross-sectional views of the MEMS structure in each step of the manufacturing method in the embodiments of this application are shown.

[0019] Reference numerals: 310, first wafer; 320, metal layer; 330, oxide layer; 340, cap wafer; 350, cavity; 360, photoresist; 370, standard cell layer. Detailed Implementation

[0020] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0024] To fully understand this invention, detailed steps and structures will be set forth in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0025] likeFigure 1 The diagram shown is a schematic of a semi-MEMS structure in related technologies.

[0026] In related technologies, a raised standard cell layer 120 is formed on the first surface of wafer 110, and a metal layer 130 is formed on the surface of the standard cell layer 120. When forming the metal layer 130 and the standard cell layer 120, two photomasks are used for the etching processes of the standard cell layer 120 and the metal layer 130, respectively. To prevent large overlay errors between the two structural layers and alignment deviations, a metal edge design is used to surround the standard cell layer 120 at the anchor points of the bonding region, thus forming a metal edge 140. This makes the area of ​​the metal layer 130 larger than the area of ​​the standard cell layer 120. During subsequent eutectic bonding, there is a risk of metal overflow into the functional area, affecting the normal operation of the device.

[0027] To address the aforementioned problems, this application provides a method for manufacturing a MEMS structure, the method comprising the following steps:

[0028] S210, provides the first wafer.

[0029] S220, a metal layer is deposited on the first surface of the first wafer to form a metal layer.

[0030] S230. Using patterned photoresist as a mask, perform isotropic first etching on the metal layer to obtain a patterned metal layer.

[0031] S240. Using photoresist as a mask, perform anisotropic second etching on the first surface of the first wafer to obtain a raised patterned standard cell layer, wherein the lateral dimension of the patterned metal layer is smaller than the lateral dimension of the raised patterned standard cell layer.

[0032] The MEMS structure manufacturing method in this application uses the same patterned photoresist as a mask to etch the metal layer and the substrate respectively through isotropic first etching and anisotropic second etching, thereby obtaining a patterned metal layer and a raised patterned standard cell layer. The lateral dimension of the metal layer is smaller than the lateral dimension of the raised patterned standard cell layer, which serves as a buffer area to provide a buffer for overflowing metal during subsequent bonding, preventing it from directly entering the functional area of ​​the device and effectively improving production yield.

[0033] For example, an isotropic first etching is performed on the surface of the metal layer, during which etching occurs at the same rate in all directions of the metal layer. Therefore, in addition to vertical etching, lateral etching is also performed on the metal layer in areas masked by photoresist, thereby reducing the lateral dimensions of the metal layer in these masked areas. The isotropic first etching type can be wet etching.

[0034] For example, an anisotropic second etching is performed on the first surface of the first wafer. During the etching process, only the first surface of the first wafer is etched vertically to form a raised, patterned standard cell layer. Because the anisotropic etching process preferentially removes material in a specific direction, the area of ​​the first surface of the first wafer not covered by photoresist is less likely to be etched laterally. During the first and second etching processes on the metal layer and the first surface of the first wafer, a lateral dimensional difference will appear between the patterned metal layer and the patterned standard cell layer, which can be used as a buffer region during metal layer bonding.

[0035] Using the same patterned photoresist as a mask for the first surface and metal layer of the first wafer, anisotropic second etching and isotropic first etching are performed respectively, which can greatly reduce the overlay error between the two structural layers and reduce the alignment deviation.

[0036] The method in the embodiment of this application will be further described below with reference to Figure 3:

[0037] Referring to Figure 3(a), in this embodiment, a cap wafer 340 is further formed on the second surface of the first wafer 310 and bonded thereto. At least one cavity 350 is formed in the cap wafer 340 facing the first wafer 310. The cavity 350 primarily serves as a space for accommodating micro-devices (such as gyroscopes and accelerometers) in subsequent processes. Bonding the cap wafer 340 to the second surface of the first wafer 310 also provides protection for the first wafer 310. In some embodiments, the cap wafer 340 and the second surface of the first wafer 310 are fused-bonded through an oxide layer 330. The oxide layer 330 is formed between the cap wafer 340 and the second surface of the first wafer 310, and also on the inner sidewall of the cavity 350. Exemplarily, the oxide layer 330 may be made of silicon oxide.

[0038] The first wafer 310 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other compound semiconductors, or may include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). In some embodiments, the first wafer 310 is formed by thinning a silicon wafer. Although several examples of materials that can form the first wafer 310 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of the invention.

[0039] Referring to Figure 3(b), a metal layer 320 is deposited on the first surface of the first wafer 310, and a patterned photoresist 360 is formed on the side of the metal layer 320 facing away from the first wafer 310. For example, the material of the metal layer 320 includes aluminum, germanium, copper, titanium, tungsten, etc., and the specific material can be selected according to the actual situation.

[0040] For example, various deposition processes commonly used in the art can be used to form the metal layer 320, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and selective epitaxial growth (SEG), etc., and this application does not limit the methods thereto.

[0041] Referring to Figure 3(c), using patterned photoresist 360 as a mask, isotropic first etching is performed on metal layer 320 to obtain patterned metal layer 320. During the isotropic etching process, longitudinal and lateral etching are performed to reduce the lateral dimension of each corresponding metal layer 320. Exemplarily, the first etching method can be wet etching.

[0042] As shown in Figure 3(d), using the patterned photoresist 360 as a mask again, anisotropic second etching is performed on the exposed first surface of the first wafer 310 to obtain a raised patterned standard cell layer 370. During the anisotropic etching process, only the first surface of the first wafer 310 is etched longitudinally. Because the patterned metal layer 320 is also etched laterally, the lateral dimension of the patterned metal layer 320 is smaller than the lateral dimension of the raised patterned standard cell layer 370, forming a buffer region between them. This prevents the overflowing molten metal from entering other areas during bonding through the metal layer 320.

[0043] For example, the side surface of the patterned metal layer 320 away from the patterned standard cell layer 370 is a first etching surface, and the side surface closer to the patterned standard cell layer 370 is a second etching surface, wherein the area of ​​the first etching surface is smaller than the area of ​​the second etching surface.

[0044] The etching process creates a curved or inclined transition surface between the first and second etched surfaces, resulting in a lateral dimension of the metal layer 320 that is smaller than that of the patterned standard cell layer 320. The cross-section of the patterned metal layer 320 forms a trapezoidal or inverted bowl-shaped structure, which is more effective in preventing overflow. For example, the protruding patterned standard cell layer 370 extends beyond the lateral dimension of the patterned metal layer 320 by no more than 10% of its lateral dimension. This maintains structural integrity while ensuring sufficient space to reduce overflow during metal bonding.

[0045] As shown in Figure 3(e), after the patterned metal layer 320 and the raised patterned standard cell layer 370 are formed, the photoresist 360 is removed by cleaning with an organic solvent, exposing the patterned metal layer 320.

[0046] The manufacturing method in this application embodiment further includes bonding a patterned metal layer 320 to a third wafer. During the bonding process, the molten metal overflows into the buffer area between the metal layer 320 and the standard cell layer 370, reducing its impact on the device.

[0047] In summary, the MEMS structure manufacturing method in this application uses the same patterned photoresist 360 as a mask to etch the metal layer 320 and the substrate through isotropic first etching and anisotropic second etching, respectively, thereby obtaining the patterned metal layer 320 and the raised patterned standard cell layer 370. The lateral dimension of the metal layer 320 is smaller than the lateral dimension of the raised patterned standard cell layer 370, which serves as a buffer area to provide a buffer for overflowing metal during subsequent bonding, preventing it from directly entering the functional area of ​​the device and effectively improving production yield.

[0048] As shown in Figure 3(e), this application embodiment also provides a MEMS structure obtained by the above-described manufacturing method.

[0049] The MEMS structure includes a first wafer 310, a standard cell layer 370 formed on a first surface of the first wafer 310, and a metal layer 320 covering the standard cell layer 370, wherein the lateral dimension of the metal layer 320 is smaller than the lateral dimension of the standard cell layer 370. A cap wafer 340 is also formed on the second surface of the first wafer 310. The cap wafer 340 is fused-bonded to the second surface of the first wafer 310 through an oxide layer 330. A plurality of cavities 350 facing the first wafer 310 are formed in the cap wafer 340. The oxide layer 330 is formed between the cap wafer 340 and the second surface of the first wafer 310, and on the inner sidewalls of the cavities 350, for bonding the first wafer 310.

[0050] Cavity 350 is a vacuum chamber used to house micro-devices (e.g., gyroscopes and accelerometers). The vacuum level of cavity 350 is less than 10. -8 Pa, a higher vacuum level can effectively improve the quality factor of devices (such as gyroscopes and accelerometers), reduce mechanical thermal noise, and improve zero-bias stability.

[0051] In the MEMS structure of this application, the lateral dimension of the metal layer 320 is smaller than that of the standard cell layer 370, thus forming a buffer region. During the subsequent bonding process, it provides a buffer for the overflowing metal, which can prevent it from directly entering the functional area of ​​the device, reduce the impact on the device, and improve its stability.

[0052] This application also provides an electronic device, including the aforementioned MEMS device.

[0053] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including the aforementioned MEMS device. The electronic device in this embodiment of the invention has better stability due to the use of the aforementioned MEMS device.

[0054] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0055] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0056] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0057] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0058] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0059] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A method for manufacturing a MEMS structure, characterized in that, The method includes: Provide the first wafer; A metal layer is deposited on the first surface of the first wafer; Using patterned photoresist as a mask, the metal layer is subjected to an isotropic first etching to obtain the patterned metal layer; Using the photoresist as a mask, anisotropic second etching is performed on the first surface of the first wafer to obtain a raised patterned standard cell layer, wherein the lateral dimension of the patterned metal layer is smaller than the lateral dimension of the raised patterned standard cell layer.

2. The method according to claim 1, characterized in that, The first etching includes: The metal layer is etched using a wet etching method.

3. The method according to claim 1, characterized in that, The second etching includes: The first surface of the first wafer is etched using a dry etching method.

4. The method according to claim 1, characterized in that, The lateral dimension of the patterned standard cell layer extending beyond the patterned metal layer is no greater than 10% of the lateral dimension of the patterned standard cell layer.

5. The method according to claim 4, characterized in that, The surface of the patterned metal layer away from the patterned standard cell layer is a first etching surface, and the surface closer to the patterned standard cell layer is a second etching surface, wherein the area of ​​the first etching surface is smaller than the area of ​​the second etching surface.

6. The method according to claim 1, characterized in that, A cap wafer is formed on the second surface of the first wafer and bonded thereto.

7. The method according to claim 6, characterized in that, At least one cavity facing the first wafer is formed in the cap wafer.

8. The method according to claim 6, characterized in that, The cap wafer is fused to the second surface of the first wafer through an oxide layer.

9. The method according to any one of claims 1-8, characterized in that, The method further includes removing the photoresist by cleaning with an organic solvent.

10. The method according to any one of claims 1-8, characterized in that, The method further includes bonding the patterned standard cell layer with the protruding metal layer to a third wafer after obtaining the patterned standard cell layer.

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