storage device

Abstract

An embodiment provides a storage device capable of suppressing the writing of data in storage cells that are not intended for writing during a write operation. The storage device includes: a storage cell array, in which memory strings are arranged, the memory strings comprising a plurality of storage cells formed by connecting in parallel a cell transistor corresponding to a first potential application electrode and a resistive switching memory region; and a potential setting circuit for setting the potential of the first potential application electrode. Before setting the first potential application electrode of the storage cell intended for writing to a potential where the cell transistor is in an off state, the potential setting circuit sets the potential of the first potential application electrode of the storage cell not intended for writing to a potential where the cell transistor remains on during the write operation. After setting the first potential application electrode of the storage cell intended for writing to a potential where the cell transistor is in an on state, the potential of the first potential application electrode of the storage cell not intended for writing to a potential prior to the write operation.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-138579 (filed on August 27, 2021). This application incorporates all the contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a storage device. Background Technology

[0004] The industry has proposed a storage device that integrates resistive random access memory (ReRAM), phase change memory (PCM), and interfacial phase change memory (iPCM) elements on a semiconductor substrate. Summary of the Invention

[0005] The problem to be solved by the embodiments of the present invention is to provide a storage device that can suppress the writing of data in storage cells that are not intended for writing during a write operation.

[0006] The storage device of the embodiment includes: a storage cell array, in which memory strings are arranged, the memory strings comprising a plurality of storage cells formed by connecting in parallel a cell transistor corresponding to a first potential application electrode and a resistive switching memory region; and a potential setting circuit for setting the potential of the first potential application electrode. Before setting the first potential application electrode of the storage cell to be written to a potential where the cell transistor is in an off state, the potential setting circuit sets the potential of the first potential application electrode of storage cells not to be written to a potential where the cell transistor remains on during the write operation. After setting the first potential application electrode of the storage cell to be written to a potential where the cell transistor is in an on state, the potential of the first potential application electrode of the storage cell not to be written to a potential prior to the write operation. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a memory system having a storage device with an implementation method.

[0008] Figure 2 It is a circuit diagram representing the structure of memory blocks.

[0009] Figure 3It is a circuit diagram that shows the current path flowing within a memory cell when the unit transistor is in the ON state.

[0010] Figure 4 It is a circuit diagram that shows the current path flowing within a memory cell when the unit transistor is in the off state.

[0011] Figure 5 It is a schematic cross-sectional view showing the cross-section of the memory cylinder.

[0012] Figure 6 It is a schematic cross-sectional view showing the cross-section of the memory cell array.

[0013] Figure 7 It is along Figure 6 A sectional view along line A1-A1.

[0014] Figure 8 It is along Figure 6 A sectional view along line B1-B1.

[0015] Figure 9 It is along Figure 6 A sectional view of line C1-C1.

[0016] Figure 10 It is a cross-sectional view with the storage unit extracted.

[0017] Figure 11 It is along Figure 6 A sectional view along line D1-D1.

[0018] Figure 12 It is along Figure 6 A sectional view along line E1-E1.

[0019] Figure 13 It is a circuit diagram for extracting a memory string.

[0020] Figure 14 It is a schematic cross-sectional view of a memory string being extracted.

[0021] Figure 15 A timing diagram showing the operating waveform of the memory device in the comparative example.

[0022] Figure 16 A timing diagram representing a comparison example.

[0023] Figure 17 It is a circuit diagram used to illustrate erroneous writes that occur in a storage device.

[0024] Figure 18 A timing diagram showing the operation waveform of the storage device in the embodiment.

[0025] Figure 19This is a block diagram illustrating the potential setting circuit of the storage device in an embodiment.

[0026] Figure 20 This is a block diagram illustrating another potential setting circuit of the storage device in an embodiment.

[0027] Figure 21 This is a block diagram illustrating the configuration of memory blocks in a storage device according to a variation of the implementation.

[0028] Figure 22 It is a diagram used to illustrate the hierarchical structure.

[0029] Figure 23 A timing diagram showing the operation waveform of a storage device in a variation of the implementation. Detailed Implementation

[0030] Next, the embodiments will be described with reference to the accompanying drawings. In the following description of the drawings, the same or similar parts will be labeled with the same or similar symbols. The drawings are schematic diagrams. Furthermore, the embodiments shown below exemplify apparatus or methods used to concretize the technical concept, and do not specify the material, shape, structure, arrangement, etc., of the parts. Various modifications can be added to the embodiments.

[0031] First, refer to Figure 1 The configuration of the memory system 1 of the memory chip 100, which is used as an implementation method, will be described.

[0032] Figure 1 The memory system 1 shown includes a memory chip 100 and a controller 200. The combination of the memory chip 100 and the controller 200 can constitute, for example, a semiconductor device. Examples of the combination of the memory chip 100 and the controller 200 include memory cards or SSDs (Solid State Drives).

[0033] The memory chip 100 has multiple storage cells and stores data non-volatilely. The controller 200 is connected to the memory chip 100 via a memory bus and to the host computer 300 via a host bus. The controller 200 controls the memory chip 100. Additionally, the controller 200 accesses the memory chip 100 in response to host commands received from the host computer 300. The host computer 300 is, for example, a digital camera or a personal computer. The host bus is a bus based on the interface standard between the controller 200 and the host computer 300. The memory bus transmits and receives signals according to the interface standard between the controller 200 and the memory chip 100.

[0034] Next, for Figure 1The configuration of the controller 200 shown will be described. The controller 200 includes a host interface circuit (host I / F) 210, an internal memory (RAM) 220, a processor (CPU (Central Processing Unit)) 230, a buffer memory 240, a memory interface circuit (memory I / F) 250, and an ECC (Error Check and Correction) circuit 260.

[0035] The host interface circuit 210 is connected to the host 300 via the host bus. The host interface circuit 210 transmits host instructions and data received from the host 300 to the processor 230 and the buffer memory 240, respectively. In addition, the host interface circuit 210, in response to commands from the processor 230, transmits data stored in the buffer memory 240 to the host 300.

[0036] Built-in memory 220 serves as the operating area for processor 230. Built-in memory 220 stores firmware or various management tables such as offset tables, history tables, and flag tables used to manage memory chip 100. Built-in memory 220 is, for example, a semiconductor memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0037] The processor 230 controls the overall operation of the controller 200. For example, when the processor 230 receives a read-related host instruction from the host 300, it responds to the host instruction by causing the memory interface circuit 250 to issue a read instruction (memory instruction) to the memory chip 100. The processor 230 performs the same action when it receives a write-related host instruction from the host 300. In addition, the processor 230 performs various processes (wear leveling, etc.) to manage the memory chip 100.

[0038] The buffer memory 240 temporarily stores data written to or read from the memory chip 100.

[0039] The memory interface circuit 250 is connected to the memory chip 100 via the memory bus and manages the communication between the memory chip 100 and the controller 200. Based on commands received from the processor 230, the memory interface circuit 250 sends various signals to the memory chip 100 and receives various signals from the memory chip 100.

[0040] The ECC circuit 260 performs error detection and error correction processing related to the data stored in the memory chip 100. When writing data, the ECC circuit 260 generates an error correction code and assigns it to the written data. Additionally, when reading data, the ECC circuit 260 decodes the read data.

[0041] Next, for Figure 1 The configuration of the memory chip 100 shown will be described. The memory chip 100 includes a memory cell array 110, a row decoder 120, a potential setting circuit 130, a sense amplifier 140, an address register 150, an instruction register 160, and a sequencer 170.

[0042] The memory cell array 110 includes memory blocks BLK0 to BLK3, each having multiple non-volatile memory cells that establish corresponding rows (word lines) and columns (bit lines). Without limiting the memory blocks BLK0 to BLK3, they are referred to as memory block BLK. Figure 1 The diagram illustrates four memory blocks BLK0 to BLK3 as an example of a memory cell array 110, but the number of memory blocks BLK in the memory cell array 110 is not limited to four. The memory cell array 110 stores data sent from the controller 200.

[0043] The line decoder 120 selects any one of the memory blocks BLK0 to BLK3 based on the block address BA in the address register 150, and then selects the word line in the selected memory block BLK.

[0044] The voltage setting circuit 130 includes a voltage generation circuit 131 and a driver circuit 132. The voltage generation circuit 131 generates a voltage to be supplied to the memory block BLK. The driver circuit 132 supplies voltage to the selected memory block BLK via the row decoder 120 based on the page address PA in the address register 150. The driver circuit 132 may also include, for example, a source line driver.

[0045] Although detailed descriptions follow, the memory cells of the memory cell array 110 are configured such that a cell transistor corresponding to any one of the multiple word lines is connected in parallel with a resistive switching memory region. The potential setting circuit 130 controls the conduction state of the cell transistors of the memory cells by setting the potential of the word lines, and adjusts the timing of the potential setting for each word line. The potential set by the potential setting circuit 130 and the timing of the set potential are controlled by the sequencer 170.

[0046] The sense amplifier 140 has a sense amplifier module provided for each bit line. During data readout, it senses the data read from the memory cell array 110 via the bit lines, performs necessary calculations, and generates data DAT. Then, the sense amplifier 140 outputs the data DAT to the controller 200. During data writeout, the sense amplifier 140 transmits the data DAT received from the controller 200 to the memory cell array 110 via the bit lines.

[0047] Address register 150 stores the address ADD received from controller 200. Address ADD includes the block address BA and page address PA. Instruction register 160 stores the instruction CMD received from controller 200.

[0048] The sequencer 170 controls the overall operation of the memory chip 100 based on the instruction CMD stored in the instruction register 160.

[0049] Next, refer to Figure 2 The structure of the memory block BLK in the memory cell array 110 will be explained. For example... Figure 2 As shown, the memory block BLK contains, for example, four string components SU (SU0 to SU3). Furthermore, the number of string components SU within the memory block BLK is arbitrary. Each string component SU contains multiple memory strings MS. The memory cell array 110 is configured with multiple memory strings MS arranged in a single array.

[0050] Each memory string MS comprises, for example, n+1 memory cells MC (MC0, MC1, ..., MCn) and a selection transistor ST1 (n being a natural number greater than or equal to 1). The memory cells MC0, MC1, ..., MCn in the memory string MS are connected in series between the selection transistor ST1 and the source line SL. Hereinafter, without limitation on the memory cells MC0, MC1, ..., MCn, they will be referred to as memory cells MC. The number of memory cells MC in each memory string MS can be, for example, 8, 32, 48, 64, 96, or 128, etc., and is not limited. The selection transistor ST1 is, for example, an n-channel MOS (Metal-Oxide-Semiconductor) transistor.

[0051] As described above, the memory string MS comprises multiple memory cells MC connected in series with a selection transistor ST1 that selects the memory cells MC. Specifically, the selection transistor ST1 is connected to the first end of the series connection structure of the multiple memory cells MC constituting the memory string MS, and the source line SL is connected to the second end. Furthermore, the number of selection transistors ST1 included in each memory string MS is arbitrary, and the memory string MS only needs to include at least one selection transistor ST1.

[0052] The memory cell MC is configured by connecting a cell transistor SW and a resistive switching memory region MR in parallel. The first main electrode of the cell transistor SW is connected to the first terminal of the resistive switching memory region MR, and the second main electrode of the cell transistor SW is connected to the second terminal of the resistive switching memory region MR. For example, the first main electrode is the drain electrode, and the second main electrode is the source electrode. The conduction of the control transistor SW is controlled by the voltage applied to the gate electrode of the cell transistor SW. Hereinafter, the gate electrode of the cell transistor SW will also be referred to as the "control gate of the memory cell MC". The cell transistor SW is, for example, an n-channel MOS transistor.

[0053] The resistive switching region (MR) functions as the storage element within the memory cell (MC) and is also known as the "resistive switching layer" or "resistive switching element." The MR is a phase-change material whose resistance varies depending on its crystallization state. Hereinafter, the change in the crystallization state of a phase-change material is referred to as a "phase change." The MR is a resistive switching type memory element that becomes either a low-resistance state or a high-resistance state depending on its phase change.

[0054] In the memory chip 100, signals are recorded by utilizing the difference in relative resistance values ​​of the resistive switching memory region MR. The state in which the resistive switching memory region MR is in a low-resistance state is called the "set state," and the state in which it is in a high-resistance state is called the "reset state." For example, if the crystalline state of the resistive switching memory region MR changes and becomes amorphous, then the resistive switching memory region MR becomes a high-resistance state. On the other hand, if the crystalline state of the resistive switching memory region MR changes and becomes crystallized, then the resistive switching memory region MR becomes a low-resistance state. An example of a resistive switching memory region MR is an alloy-type phase transfer element (Ge2Sb2Te5).

[0055] The control gates of the memory cells MC0 of the multiple memory strings MS contained in the same memory block BLK are all connected to word line WL0. Similarly to memory cell MC0, the control gates of the memory cells MC1, ..., MCn of the multiple memory strings MS contained in the same memory block BLK are all connected to word lines WL1, ..., WLn, respectively. Hereinafter, without limitation, word lines WL0, WL1, ..., WLn will be referred to as word lines WL. A memory cell MC is, for example, configured by connecting a cell transistor SW corresponding to any one of the n+1 word lines WL0, WL1, ..., WLn in parallel with a resistive switching memory region MR. Hereinafter, the word line WL corresponding to the memory cell MC will also be referred to as the "word line of the memory cell MC".

[0056] Furthermore, in the following explanation, multiple storage cells MC connected to the word line WL common within each string component SU are referred to as cell groups (CUs). Moreover, the set of 1-bit data stored in a cell group is called a "page". Therefore, when 2 bits of data are stored in one storage cell MC, the cell group stores 2 pages of data.

[0057] The gate electrodes of multiple selection transistors ST1 within the string assembly SU are all connected to the selection gate line SGD. More specifically, the gate electrodes of multiple selection transistors ST1 within the string assembly SU0 are all connected to the selection gate line SGD0. Similar to the string assembly SU0, the gate electrodes of multiple selection transistors ST1 within the string assembly SU1 are all connected to the selection gate line SGD1. The gate electrodes of multiple selection transistors ST1 within the string assembly SU2 are all connected to the selection gate line SGD2. The gate electrodes of multiple selection transistors ST1 within the string assembly SU3 are all connected to the selection gate line SGD3. Hereinafter, without limiting the selection gate lines SGD0, SGD1, ..., they will be referred to as the selection gate line SGD.

[0058] The selection of gate line SGD and word line WL is independently controlled by the line decoder 120.

[0059] The drain electrodes of the selection transistor ST1 of memory strings MS located in the same column within the memory cell array 110 are commonly connected to bit lines BL0, BL1, ..., BLm (where m is a natural number greater than or equal to 1). Hereinafter, without specifying each of the bit lines BL0, BL1, ..., BLm, they will be referred to as bit line BL. Current is supplied to the memory strings MS from the bit line BL via the selection transistor ST1. Hereinafter, the current supplied to the memory strings MS from the bit line BL will also be referred to as "cell current". The bit line BL connects the memory strings MS across multiple memory blocks BLK. Furthermore, the source electrodes of multiple memory cells MCn are commonly connected to the source line SL.

[0060] In other words, the string component SU includes multiple memory strings MS connected to different bit lines BL and connected to the same select gate line SGD. Additionally, the memory block BLK includes multiple string components SU that are common to the word line WL. Furthermore, the memory cell array 110 includes multiple memory blocks BLK that are common to the bit lines BL.

[0061] The write and read operations of the memory cell MC are performed by controlling the potentials applied to the word line WL, the select gate line SGD, the source line SL, and the bit line BL. Hereinafter, the word line WL will be referred to as the first potential application electrode, the select gate line SGD as the second potential application electrode, the source line SL as the third potential application electrode, and the bit line BL as the fourth potential application electrode.

[0062] The operation of the memory cell MC will be explained below. The cell transistor SW, described in detail below, is a structure in which the semiconductor layer and the gate electrode face each other, separated by a gate insulating film. By applying a predetermined voltage to the gate electrode to form an inversion layer in the semiconductor layer, the cell transistor SW is turned on.

[0063] In the memory cell array 110, the cell transistor SW of the memory cell MC selected as the target of a write or read operation (hereinafter also referred to as "the selected memory cell MC") is in the off state (non-conducting state). Therefore, cell current flows through the resistive switching memory region MR in the selected memory cell MC. On the other hand, in the unselected memory cell MC (hereinafter also referred to as "the unselected memory cell MC"), the cell transistor SW is in the on state (conducting state). Therefore, cell current also flows through the cell transistor SW in the unselected memory cell MC.

[0064] When the resistive switching memory region MR of the selected memory cell MC is in a high resistance state (reset state), the cell current flowing to the resistive switching memory region MR is small. Therefore, the potential of the bit line BL decreases slowly. On the other hand, when the resistive switching memory region MR of the selected memory cell MC is in a low resistance state (set state), the cell current flowing to the resistive switching memory region MR is large. Therefore, the potential of the bit line BL decreases rapidly. Therefore, based on the rate of change of the potential of the bit line BL, it is possible to determine whether the resistive switching memory region MR is in a reset state or a set state. The resistance of the resistive switching memory region MR of the selected memory cell MC accounts for a sufficiently large proportion of the total resistance from the bit line BL to the source line SL. Therefore, it is possible to determine whether the resistive switching memory region MR of the selected memory cell MC is in a high resistance state or a low resistance state.

[0065] Figure 3This indicates the current path of the cell current Icell flowing through the memory cell MC when the cell transistor SW is in the ON state. For example... Figure 3 As shown, when the unit transistor SW is in the ON state, an inversion layer is formed in the semiconductor layer of the unit transistor SW, and the unit current Icell flows through the inversion layer. Furthermore, the resistance value of the resistive switching memory region MR in its low-resistance state is more than 10 times (one bit) higher than the resistance value of the semiconductor layer in the ON state of the unit transistor SW. Therefore, even when the unit transistor SW is in the ON state and the resistive switching memory region MR is in its low-resistance state, the unit current Icell still flows through the unit transistor SW.

[0066] Figure 4 This represents the current path of the cell current Icell flowing through the memory cell MC when the cell transistor SW is in the off state. When the cell transistor SW is in the off state, since an inversion layer is not formed on the semiconductor layer of the cell transistor SW, therefore... Figure 4 As shown, the cell current Icell flows through the resistive switching memory region MR. Furthermore, the resistance value of the resistive switching memory region MR in its high-resistance state is more than 10 times (one bit) lower than the resistance value of the semiconductor layer in the off state of the cell transistor SW. Therefore, even when the cell transistor SW is in the off state, the cell current Icell still flows through the resistive switching memory region MR in its high-resistance state.

[0067] The following describes an example of the construction of the memory cell array 110 formed on a semiconductor substrate. First, referring to... Figure 5 The memory pillars MP included in the memory cell array 110 will be described below. The memory pillar MP is a memory cell MC formed by three-dimensionally stacking a conductive layer and an insulating film. Figure 5 This is an example of the cross-sectional structure of a memory cylinder MP.

[0068] The memory cylinder MP has a configuration in which conductive layers 22 and insulating layers 35 are alternately stacked along the Z direction. The conductive layers 22 are formed as plates extending along an XY plane perpendicular to the Z direction. Multiple conductive layers 22 are used as word lines WL0, WL1, ..., WLn, respectively. The conductive layers 22 contain, for example, tungsten (W). The Z direction is also referred to as the "first direction", and the direction in which the conductive layers 22 extend is referred to as the "second direction".

[0069] In the memory pillar MP, a memory aperture MH is formed that extends through the conductive layer 22 and the insulating layer 35 in the Z direction. The memory aperture MH is, for example, a cylindrical shape extending along the Z direction. Inside the memory aperture MH (inner wall), an insulating layer 33, a semiconductor layer 32, a resistive switching layer 31, and a core 30 are sequentially disposed. That is, the memory pillar MP has a cylindrical insulating layer 33 that covers the inner wall of the memory aperture MH and extends along the Z direction, a cylindrical semiconductor layer 32 that covers the inner wall of the insulating layer 33 and extends along the Z direction, and a cylindrical resistive switching layer 31 that covers the inner wall of the semiconductor layer 32 and extends along the Z direction.

[0070] The core 30, for example, has a cylindrical shape extending along the Z direction. The core 30 can, for example, be made of a material with higher thermal resistance than silicon oxide (SiO2). Alternatively, the core 30 can also be made of a vacuum or an inert gas.

[0071] The vacuum level when the core 30 is under vacuum can be set, for example, to 10 under low vacuum conditions. 5 Pa~10 2 Pa, 10 Pa under medium vacuum 2 Pa~10 -1 The range of Pa. Additionally, the vacuum level of the core 30 can also be set to, for example, 10 under high vacuum. -1 Pa~10 -5 Pa, 10 Pa under ultra-high vacuum. -5 Pa~10 -8 The range of Pa.

[0072] When the core 30 is made of an inert gas, rare gases such as helium, neon, argon, krypton, xenon, radon, oxalis, or nitrogen can be used.

[0073] The resistive switching layer 31 covers the side (outer periphery) of the core 30 and is in contact with the core 30. The resistive switching layer 31 extends, for example, along the Z direction and is formed into a cylindrical shape. By applying a material with higher thermal resistance than silicon oxide, a vacuum, or an inert gas to the core 30, the heating temperature in the resistive switching layer 31 can be increased.

[0074] Semiconductor layer 32 covers the outer periphery of resistive switching layer 31 and is in contact with resistive switching layer 31. Semiconductor layer 32 extends along the Z direction, for example, and is formed into a cylindrical shape. The thickness of resistive switching layer 31 is, for example, less than 20 nm. The diameter of core 30 is greater than the thickness of resistive switching layer 31, for example, more than tens of nm.

[0075] An insulating layer 33 covers the side surface of the semiconductor layer 32. The insulating layer 33 may include, for example, a portion configured in a cylindrical shape. The insulating layer 33 may contain, for example, an insulator such as silicon oxide. Additionally, a conductive layer 22 covers a portion of the side surface of the insulating layer 33 and is in contact with the insulating layer 33.

[0076] Multiple conductive layers 22, arranged separately in the Z direction, serve as word lines WL0, WL1, ..., WLn. Semiconductor layer 32 is the semiconductor layer forming the inversion layer of the unit transistor SW. Insulating layer 33, covering the sides of semiconductor layer 32, is the gate insulating film of unit transistor SW. The conduction state of unit transistor SW is controlled based on the potential of the conductive layers 22, which serve as word lines WL. Furthermore, resistive switching layer 31 functions as the resistive switching storage region MR of memory cell MC. Thus, in memory column MP, multiple memory cells MC are connected in series along the Z direction.

[0077] When selecting a memory cell MC, the cell current Icell flows in a region where the resistive switching layer 31, which is connected to the semiconductor layer 32, has a thinner film thickness. Therefore, the film thickness of the resistive switching layer 31 can be made sufficiently thin compared to the diameter of the core 30. By making the film thickness of the resistive switching layer 31 sufficiently thin compared to the diameter of the core 30, a higher current density can be set in the resistive switching layer 31. As a result, the heat generation temperature in the memory cell MC increases, and the localization of the heat generation site is improved. By improving the localization of the heat generation site, the heat generation temperature in memory cells MC adjacent to the selected memory cell MC can be suppressed, reducing interference (data corruption) to adjacent memory cells MC.

[0078] Next, an example of the construction of the memory cell array 110 will be described. Furthermore, in the following figures, the X direction corresponds to the extension direction of the bit line BL, the Y direction corresponds to the extension direction of the word line WL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate 20 on which the memory cell array 110 is formed.

[0079] Figure 6 This illustrates an example of the cross-sectional structure of the memory cell array 110. For example... Figure 6 As shown, the memory cell array 110 includes, for example, conductive layers 21 to 24. Conductive layers 21 to 24 are disposed above the semiconductor substrate 20.

[0080] Specifically, a conductive layer 21 is disposed above the semiconductor substrate 20 in the Z direction, separated by an insulating layer (not shown). For example, a circuit such as a sense amplifier 140 may be disposed in the insulating layer between the semiconductor substrate 20 and the conductive layer 21. The conductive layer 21 is formed, for example, in a plate shape extending along the XY plane and serves as a source line SL. The conductive layer 21 contains, for example, silicon (Si).

[0081] Above the conductor layer 21 in the Z direction, an insulating layer 35 and a conductor layer 22 are alternately deposited. The conductor layer 22 is formed, for example, as a plate extending along the XY plane. A plurality of conductor layers 22, which are arranged separately from each other, are used as word lines WLn, ..., WL0 from the semiconductor substrate 20 side.

[0082] Above the uppermost conductive layer 22 (WL0) in the Z direction, a conductive layer 23 is disposed, separated by an insulating layer. The conductive layer 23 extends along the Y direction and is broken in the X direction for each of the following selection gates SP. The broken conductive layers 23 serve as selection gate lines SGD0 to SGD3, respectively. The conductive layer 23 contains, for example, tungsten W.

[0083] Above the conductive layer 23 in the Z direction, a conductive layer 24 is disposed, separated from an insulating layer. For example, the conductive layer 24 is formed as a line extending in the X direction and serves as a bit line BL. The conductive layer 24 contains, for example, copper (Cu).

[0084] like Figure 6 As shown, a cylindrical select post SP, penetrating the conductive layer 23 and extending to the bottom of the memory pillar MP, is provided above the memory pillar MP in the Z direction. The select post SP includes a semiconductor layer 32 and an insulating layer 33 that extend continuously from the memory pillar MP along the Z direction. Specifically, an SGD hole SH penetrating the conductive layer 23 in the Z direction is formed in the select post SP, and the insulating layer 33 and the semiconductor layer 32 are sequentially disposed inside (on the inner wall) of the SGD hole SH. That is, the select post SP has a cylindrical insulating layer 33 covering the inner wall of the SGD hole SH and extending along the Z direction, and a cylindrical semiconductor layer 32 covering the inner wall of the insulating layer 33 and extending along the Z direction. Furthermore, the conductive layer 23 covers a portion of the side surface of the insulating layer 33 in the select post SP and is in contact with the insulating layer 33. Also, similar to the memory pillar MP, a core 30 may be provided inside the semiconductor layer 32 in the select post SP.

[0085] The bottom edge of the semiconductor layer 32 of the selector pillar SP is in contact with the semiconductor layer 32, resistive switching layer 31, and core 30 of the memory pillar MP. Furthermore, the layer containing the boundary between the memory via MH and the SGD via SH is contained in the layer between the uppermost conductive layer 22 and conductive layer 23.

[0086] The bottom of the core 30, resistive switching layer 31, semiconductor layer 32, and insulating layer 33 of the memory column MP are in contact with the conductive layer 21. That is, the semiconductor layer 32 is electrically connected to the conductive layer 21, which serves as the source line SL (the electrode to which the third potential is applied).

[0087] The portion of the semiconductor layer 32 that spans the memory pillar MP and the select pillar SP that constitutes the unit transistor SW is referred to as "first semiconductor layer 321", and the portion that constitutes the select transistor ST1 is referred to as "second semiconductor layer 322". Similarly, the portion of the insulating layer 33 that spans the memory pillar MP and the select pillar SP that constitutes the unit transistor SW is referred to as "first insulating layer 331", and the portion that constitutes the select transistor ST1 is referred to as "second insulating layer 332".

[0088] That is, the unit transistor SW has a first semiconductor layer 321 covering the sides of the resistive switching layer 31, which serves as the resistive switching memory region MR, and a first insulating layer 331 covering the sides of the first semiconductor layer 321. In the unit transistor SW, one word line WL (first potential application electrode) is positioned opposite to the first semiconductor layer 321, separated by the first insulating layer 331. When the unit transistor SW is turned on, an inversion layer is formed in the first semiconductor layer 321. The select transistor ST1 has a second semiconductor layer 322 and a second insulating layer 332 covering the sides of the second semiconductor layer 322. In the select transistor ST1, the select gate line SGD (second potential application electrode) is positioned opposite to the second semiconductor layer 322, separated by the second insulating layer 332. When the select transistor ST1 is turned on, an inversion layer is formed in the second semiconductor layer 322.

[0089] As described above, the memory string MS has a configuration in which the selection transistor ST1, a plurality of memory cells MC, and the source line SL (the electrode to which the third potential is applied) are connected in series along the Z direction in this order. The first semiconductor layer 321 and the second semiconductor layer 322 are formed continuously, and the first insulating layer 331 and the second insulating layer 332 are formed continuously.

[0090] Next, refer to Figure 7 The planar pattern configuration of the conductive layer 23 will be explained. For example... Figure 7 As shown, an insulating layer 33 and a semiconductor layer 32 are disposed within the SGD hole SH that penetrates the conductive layer 23. The conductive layer 23 functions as the selection gate lines SGD0 to SGD3 of the selection transistor ST1. The insulating layer 33 functions as the gate insulating film of the selection transistor ST1, and the semiconductor layer 32 functions as the semiconductor layer of the selection transistor ST1. By using the selection transistor ST1, the memory cell MP can be selected for each word line WL. That is, by turning on the selection transistor ST1, cell current can flow through the memory cell MC of the memory cell MP connected to the selected transistor ST1 in the on state.

[0091] Next, refer to Figure 8 The planar pattern of the memory cell MC as viewed from the Z direction is explained. For example... Figure 8 As shown, a core 30, a resistive switching layer 31, a semiconductor layer 32, and an insulating layer 33 are disposed within a memory hole MH that penetrates the insulating layer 35. Figure 8 The resistive switching layer 31, semiconductor layer 32, and insulating layer 33 shown correspond to the memory cell MC as viewed from the Z direction. In the on-state of the cell transistor SW, the cell current flows through the semiconductor layer 32.

[0092] Next, refer to Figure 9 and Figure 10 The planar pattern configuration including the conductive layer 22 will be described. Figure 9 It is along Figure 6 A sectional view of line C1-C1. Figure 10 From Figure 9 A cross-sectional view of a storage unit (MC) extracted from memory.

[0093] like Figure 9 and Figure 10 As shown, the memory cell MC is located at the intersection of the plate-shaped word line WL and the memory cylinder MP. Specifically, as... Figure 10 As shown, within the memory via MH that penetrates the conductor layer 22, an insulating layer 33, a semiconductor layer 32, a resistive switching layer 31, and a core 30 are disposed. The conductor layer 22 functions as the word line WL. The insulating layer 33 functions as the gate insulating film of the unit transistor SW of the memory cell MC, and the semiconductor layer 32 functions as the semiconductor layer of the unit transistor SW. The resistive switching layer 31 functions as the resistive switching memory region MR of the memory cell MC.

[0094] Figure 11 This represents a planar pattern configuration including a conductive layer 21 that functions as a source line SL. The conductive layer 21 is set to a fixed low potential to allow cell current to flow from the bit line BL through the memory string MS. (Example:) Figure 11 As shown, conductor layer 21 and conductor layer 22 are both plate-shaped.

[0095] Figure 12 Indicates and Figure 6 Cross-sectional structure of the orthogonal orientation of the memory cell array 110. (Refer to...) Figure 6 and Figure 12 Therefore, it can be seen that the memory column MP is in a concentric circle shape with the core 30 as the center.

[0096] The operation of the memory chip 100 of the storage device according to the embodiment will be described in general terms below. The read and write operations of the memory chip 100 are performed by passing cell current between the bit line BL and the source line SL.

[0097] Reference Figure 13 and Figure 14 The method for selecting the memory cell (MC) to perform read or write operations is briefly described. Figure 13 This is a circuit diagram for extracting a memory string MS. Figure 14 It is a cross-sectional view of a memory string MS extracted from the memory.

[0098] like Figure 13 and Figure 14 As shown, a predetermined voltage (positive voltage) is applied to the selection gate line SGD of the selection transistor ST1 connected to the memory pillar MP to which the desired memory cell MC (e.g., memory cell MC2) belongs. By applying the predetermined voltage to the selection gate line SGD of the selection transistor ST1, an inversion layer is formed in the semiconductor layer of the selection transistor ST1. This results in a state (on-state) where the cell current Icell can be turned on in the memory pillar MP to which the desired memory cell MC belongs.

[0099] Furthermore, a predetermined voltage (e.g., -2V) is applied to the word line WL2 of the selected memory cell MC2, such that the unit transistor SW is in the off state. On the other hand, a predetermined voltage (e.g., +7V) is applied to the word lines WL0, WL1, WL3, ..., WLn of the unselected memory cells MC, such as WL0, WL1, WL3, ..., WLn, such as WL0, WL1, WL3, ..., WLn, such as WL0, WL1, WL2, WL2, WL3, ..., WLn, such as WL0, WL1, WL2, WL3, ..., WLn, WL2, such as WL0, WL1, WL2, WL3, ..., WLn, WL2, WL3, WL4 ... Figure 14 As shown, since the core 30 is located in the center of the memory column MP, the cell current Icell flows in the resistive switching layer 31 surrounding the core 30 in the selected memory cell MC2.

[0100] As described above, in the memory chip 100, the resistive switching layer 31 through which the cell current Icell flows can be selected during both read and write operations. When comparing the operation of the memory chip 100 with that of a three-bit NAND flash memory, the memory chip 100 has the following advantages: it can operate at a lower voltage and a higher speed, and therefore, there are fewer limitations on the number of overwrite cycles and the write time can be shorter.

[0101] As explained above, the memory chip 100 is a structure in which the memory cell MC is formed by connecting the cell transistor SW and the resistive switching memory region MR in parallel. A semiconductor memory device that integrates resistive switching memory elements such as the resistive switching memory region MR is also called a resistive switching memory.

[0102] Unlike three-dimensional NAND flash memory, the memory chip 100, which is a resistive random access memory, does not include an erase operation.

[0103] Furthermore, the write or read operation of the memory chip 100 is performed by turning on the selection transistor ST1 and allowing cell current to flow between the bit line BL and the source line SL. Therefore, it is not necessary to select all memory strings MS, but rather to select any bit line unit (column unit) connected to the already selected selection gate line SGD.

[0104] For memory strings MS that do not undergo write or read operations, for example, the voltage of the source line SL is set to the voltage of the bit line BL. If this is done, then no write or read operations will be performed on the unselected memory cells MC.

[0105] In addition, in the memory chip 100, like the three-dimensional NAND flash memory, there is no need to perform the erase operation in memory block BLK units, and the write operation can be performed in select transistor ST1 units.

[0106] The word line WL is selected from any memory cell MC with respect to the stacking direction (Z direction). Therefore, the word line WL can be shared among the control gates of multiple memory cells MC in the same XY plane. Additionally, the source line SL can also be shared among multiple memory strings MS. In particular, the source line SL can be shared among multiple memory strings MS that are adjacent in the extension direction of the bit line.

[0107] The word line WL and source line SL are plate-shaped extending along the XY plane. In the memory chip 100, only one memory cell MC is selected for each bit line BL. The selection of memory cell MC in the memory chip 100 is not performed if the selection transistor ST1 is turned on and no cell current flows from the bit line BL to the source line SL. Therefore, even when the plate-shaped word line WL and source line SL are selected, only the memory cell MC connected to the already selected word line WL is selected directly below the bit line BL connected to the selected transistor ST1 which is turned on.

[0108] In resistive random access memory (RRAM), signal recording is performed by utilizing the difference in resistance values ​​of the RRAM regions MR. In other words, signal recording is achieved through reset writing (setting the RRAM regions MR to a high resistance state) or setting writing (setting the RRAM regions MR to a low resistance state).

[0109] As described above, cell current flows through the selected memory cell MC via the bit line BL. Therefore, the sequencer 170 is configured, for example, to output a control signal in a manner that performs a read operation on the bit line BL. Simultaneously with each bit line BL, the sequencer 170 can also output control signals in a manner that performs reset write and set write.

[0110] As described above, in a resistive random access memory (RRAM), a voltage is applied to the word line WL such that the cell transistor SW of the selected memory cell MC is in the off state, and the cell transistor SW of the non-selected memory cell MC is in the on state. Furthermore, in a RRAM, a voltage is applied to the select gate line SGD when the select transistor ST1 corresponding to the selected memory cell MC is turned on. Here, "the select transistor ST1 corresponding to the selected memory cell MC" refers to the select transistor ST1 connected to the memory pillar MP to which the selected memory cell MC belongs (hereinafter, the same). By turning on the select transistor ST1, the bit line BL and the memory pillar MP to which the selected memory cell MC belongs are made conductive. The cell current Icell flows within the semiconductor layer 32 of the cell transistor SW in the non-selected memory cell MC, and flows in the resistive random access memory region MR in the selected memory cell MC.

[0111] Figure 15 This is a timing diagram illustrating the operation of a resistive random access memory (RRAM) of a comparative example having a memory cell array 110 with the same configuration as memory chip 100. The following will describe... Figure 15 The timing diagram shown will be used for explanation. Hereinafter, the word line WL of the memory cell MC selected as the write or read target will also be referred to as the "select word line (select first potential application electrode)". That is, the select word line is the first potential application electrode for establishing the corresponding write or read target for the selected memory cell MC. The word line WL of the non-selected memory cell MC will also be referred to as the "non-select word line".

[0112] Additionally, the bit line BL connected to the write target or read target of the selection transistor ST1 corresponding to the selected memory cell MC is also called the "selection bit line BL". The bit line BL connected to the selection transistor ST1 corresponding to the non-selected memory cell MC is also called the "non-selection bit line BL". Furthermore, the selection gate line SGD of the selection transistor ST1 corresponding to the selected memory cell MC is also recorded as "selection SGD", and the selection gate line SGD of other selection transistors ST1 is recorded as "non-selection SGD".

[0113] First, the readout operation will be explained. Hereinafter, when the potential of word line WL is at level H, the unit transistor SW is in the ON state; when the potential of word line WL is at level L (H > L), the unit transistor SW is in the OFF state. Additionally, when the potential of the select gate line SGD is at level H, the select transistor ST1 is in the ON state; when the potential of the select gate line SGD is at level L, the select transistor ST1 is in the OFF state.

[0114] exist Figure 15At time T11, sequencer 170 maintains the potential of the non-select bit line BL and the source line SL at level L. Additionally, sequencer 170 maintains the potential of the non-select word line at level H. Sequencer 170 causes the potential of the select word line to decrease from level H starting at time T11, and after time T12, maintains the potential of the select word line at level L.

[0115] At time T12, the sequencer 170 raises the potential of the select gate line SGD from level L to level H. On the other hand, the potential of the non-select SGD remains at level L. Furthermore, since the potential of the non-select word line remains at level H, the cell transistor SW of the non-selected memory cell MC remains on.

[0116] Then, at time T12, the sequencer 170 sets the select bit line BL (READ) of the read target to a floating state after raising its potential. Thus, when the resistive switching memory region MR of the selected memory cell MC is in a high-resistance state (reset), the potential of the select bit line BL (READ) slowly decreases, maintaining approximately the same potential until time T14, as shown by the solid line. On the other hand, when the resistive switching memory region MR of the selected memory cell MC is in a low-resistance state (set), the potential of the select bit line BL (READ) drops rapidly, as shown by the dashed line. The "H level / L level" of the bit line BL's potential after a fixed time following the application of voltage to the select bit line BL is sensed by the sense amplifier 140 and then used for readout operation.

[0117] Next, we will explain the write operation. The operation at time T11 is the same as the read operation.

[0118] If the sequencer 170 applies a write pulse (voltage) to the select bit line BL (WRITE) at time T12, and causes the potential of the select bit line BL to drop rapidly from time T13, then a reset write is performed to set the resistive switching memory region MR to a high-resistance state. Alternatively, if the sequencer 170 applies a write pulse (voltage) to the select bit line BL (WRITE) at time T12, and causes the potential of the select bit line BL to drop slowly from time T13, then a setting write is performed to set the resistive switching memory region MR to a low-resistance state. In this case, the potential of the non-select bit line BL (NON-SELECT) remains the same as the source line SL (e.g., L level).

[0119] As described above, the memory cell MC is selected by applying a predetermined voltage to the bit line BL. If the potential of the unselected bit line BL rises, it results in the misselection of the memory cell MC, leading to an erroneous write. Therefore, it is sufficient to selectively apply a voltage to the bit line BL corresponding to the memory cell MC that is to be read or written.

[0120] However, in Figure 15 In the timing diagram shown, the potential of the non-selected word line WL is maintained at a fixed level H during the write operation. However, in order to increase the potential of the select bit line BL, the potential of the non-selected word line can also be increased during the write operation in accordance with the rise in the potential of the select bit line BL. By increasing the potential of the non-selected word line, the cell transistor SW of the non-selected memory cell MC belonging to the memory string MS connected to the select bit line BL can be reliably kept in the ON state.

[0121] Figure 16 This is an example of a timing diagram illustrating the operation of a memory device in a write operation where the potential of the non-select word line rises in response to a rise in the potential of the select bit line BL. The following will... Figure 16 The timing diagram shown is a comparative example. The timing diagram of the comparative example is explained below.

[0122] At time T21, the potential of the selected SGD rises from the L level (e.g., -2V) when the selected transistor ST1 is off to the H level (e.g., +7V) when the selected transistor ST1 is on. On the other hand, the potential of the unselected SGD remains at the L level.

[0123] Additionally, at time T21, the potential of the selected word line drops from the first potential V1 (e.g., +4V) to the third potential V3 (e.g., -2V) at level L, while the potential of the non-selected word line rises from the first potential V1 to the second potential V2 (e.g., +7V) at level H. The first potential V1 is the potential of the word line WL in the wait state when the memory chip 100 is not performing write or read operations. The first potential V1 is the potential when the unit transistor SW is in the ON state. The third potential V3 is a voltage lower than the threshold voltage Vth of the unit transistor SW, and is the potential when the unit transistor SW is in the OFF state. The second potential V2 is the potential that ensures the unit transistor SW remains ON even when the potential of the selected bit line BL is at level H during a write operation.

[0124] After the transition of each potential from time T21 is completed, at time T22, the potential of the select bit line BL rises from the L level (e.g., 0V) to the H level (e.g., +4V). Then, if the potential of the select bit line BL drops rapidly from time T23, a reset write is performed to set the resistive switching memory region MR to a high resistance state. Alternatively, if the potential of the select bit line BL drops slowly from time T23, a set write is performed to set the resistive switching memory region MR to a low resistance state.

[0125] After the transition of the select bit line BL is complete, at time T24, the select SGD potential drops from level H to level L. Additionally, at time T24, the select word line potential rises from level 3 V3 to level 1 V1, and the non-select word line potential drops from level 2 V2 to level 1 V1.

[0126] In the timing diagram of the comparative example, when the selection transistor ST1 corresponding to the selected memory cell MC is on, the cell transistor SW of the selected memory cell MC is off, and the cell transistor SW of the unselected memory cell MC is on. Therefore, the cell current Icell flows through the resistive switching memory region MR of the selected memory cell MC, causing the resistive switching memory region MR to reach a high temperature for write operation. By setting the potential of the unselected word line to a second potential V2, which is higher than the first potential V1, the cell transistor SW of the unselected memory cell MC remains on even when the potential of the selection bit line BL is at level H.

[0127] However, in Figure 16 In the timing diagram of the comparative example shown, during the write operation, as described below, there is a possibility of interference (data corruption) occurring, where data is written to a non-selected memory cell MC that is not the object to be written. (Refer to...) Figure 17 This section explains the erroneous write operation (interference) of the non-selected memory cell MC.

[0128] Figure 17 This is a circuit diagram showing a configuration where the first memory string MS1 and the second memory string MS2 are connected in parallel between the select bit line BL and the source line SL. The word line WL of the first memory string MS1 is shared with the word line WL of the second memory string MS2. Here, we will study the case where the selected memory cell MC2 is established corresponding to the word line WL2 of the first memory string MS1.

[0129] With memory cell MC2 selected, the cell transistor SW of memory cell MC2 is turned off. Then, in the first memory string MS1, the selection transistor ST1 and the cell transistors SW of all other memory cells MC except for memory cell MC2 are turned on. Then, the cell current Icell flows through the resistive switching storage region MR of memory cell MC2 and the cell transistors SW of the other memory cells MC in the first memory string MS1. In this way, memory cell MC2 is written.

[0130] On the other hand, in the second memory string MS2, since the selection transistor ST1 is in the off state, no cell current Icell flows. However, if from... Figure 16 At time T21, as the potential of the select word line decreases, the threshold voltage Vth of the cell transistor SW falls below the potential of the select word line. Therefore, the cell transistor SW corresponding to the memory cell MC2a established with the word line WL2 of the second memory string MS2 becomes disconnected. Consequently, in the second memory string MS2, the memory cell MC, connected between the disconnected select transistor ST1 and the disconnected memory cell MC2a, is connected to the source line SL via the resistive switching storage region MR, but is essentially in a floating state. Figure 17 In the diagram, the area enclosed by the dashed line F represents the floating state.

[0131] The potential of the floating region is determined by its coupling capacitance with the surrounding components. Therefore, by turning off the cell transistor SW of memory cell MC2a, the potential of the non-selectable word line rises, causing the potential of the floating region to rise as well. Hereinafter, the potential change of the floating region caused by the coupling capacitance is referred to as "boost." As a result of the boost, the potential rise of the floating region generates a potential difference dV across the resistive switching memory region MR of memory cell MC2a. This potential difference dV causes current to flow through the resistive switching memory region MR, resulting in erroneous writing to the memory cell MC2a of the non-selectable second memory string MS2.

[0132] Hereinafter, the memory string MS that is not selected (excluding the memory string MS containing the already selected memory cell MC) and that corresponds to the select word line will also be referred to as a "false selected memory cell". Figure 17 In the circuit diagram shown, memory cell MC2a of the second memory string MS2 is a false selection memory cell. The memory cell MC that becomes floating during the write operation is the memory cell MC connected between the selection transistor ST1 of the non-selected memory string MS and the false selection memory cell. Furthermore, due to the boost voltage, the false selection memory cell is mistakenly written to (interference).

[0133] As described above, the false write caused by the voltage boost at the start of the write operation has been explained, but the same applies at the end of the write operation. That is, if the potential of the non-select word line fluctuates during a period when the potential of the select word line is lower than the threshold voltage Vth of the cell transistor SW, a false write to the memory cell will occur due to the local voltage boost.

[0134] In this regard, in the storage device of the embodiment, by adjusting the timing of the set potential for each word line WL by the potential setting circuit 130 as described below, it is possible to suppress the writing of non-selected memory cells MC caused by local voltage boost.

[0135] During the write operation, the potential setting circuit 130 sets the potential of the select word line and the non-select word line at different timings. Hereinafter, the non-select word line whose potential is set at a different timing than the select word line will also be referred to as the "set non-select word line". Setting the non-select word line includes at least establishing a corresponding non-select word line for the memory cell MC that is in a floating state as described above. That is, setting the non-select word line includes at least establishing a corresponding non-select word line for the memory cell MC connected between the select transistor ST1 of the non-select memory string MS and the dummy select memory cell.

[0136] Specifically, at the start of the write operation, before setting the potential of the select word line to the potential at which the cell transistor SW is turned off, the potential setting circuit 130 sets the potential of the non-select word line to the potential at which the cell transistor SW remains on. Furthermore, at the end of the write operation, after setting the potential of the select word line to the potential before the write operation, the potential setting circuit 130 sets the potential of the non-select word line to the potential at the potential before the write operation. The potential at which the cell transistor SW is turned off is, for example, the threshold voltage of the cell transistor SW.

[0137] Reference Figure 18 The method for setting the potential of the word line WL of the storage device according to the embodiment will be described.

[0138] At time T31 (timing 1), all word lines WL are set to the first potential V1. The first potential V1 is the potential when the unit transistor SW is in the ON state, for example, +4V.

[0139] Next, at time T32 (second timing), which is later than time T31, the second potential V2 is set to maintain the cell transistor SW in the on state for the non-select word line. This second potential V2 is a potential at which the cell transistor SW remains on even when the potential of the select bit line BL rises during the write operation; for example, it is 7V. Additionally, at time T32, the potential of the select SGD is set from the L level (e.g., -2V) when the select transistor ST1 is off to the H level (e.g., +7V) when the select transistor ST1 is on. On the other hand, the potential of the non-select SGD remains at the L level.

[0140] Then, at time T33 (the third timing step), which is later than time T32, the select word line is set to the third potential V3, where the cell transistor SW is in the off state. The third potential V3 is a potential lower than the threshold voltage Vth of the cell transistor SW, for example, -2V. If the potential of the select word line falls below the threshold voltage Vth of the cell transistor SW during the process of the select word line potential decreasing from the first potential V1 to the third potential V3, then the cell transistor SW of the selected memory cell MC becomes off. With the cell transistor SW in the off state, current flows through the resistive switching memory region MR of the selected memory cell MC during subsequent write operations.

[0141] In this write operation, the potential of the select bit line BL is set from L level (e.g., 0V) to H level (e.g., +4V). Then, if the potential of the select bit line BL drops rapidly, a reset write is performed to set the resistive switching memory region MR to a high resistance state. On the other hand, if the potential of the select bit line BL drops slowly, a set write is performed to set the resistive switching memory region MR to a low resistance state.

[0142] After performing a write operation on the selected memory cell MC, at time T34 (4th timing), which is later than time T33, the select word line is set to potential V1. Then, at time T35 (5th timing), which is later than time T34, the set non-select word line is set to potential V1. Additionally, the potential of the select SGD is changed from H level to L level.

[0143] As mentioned above, according to the reference Figure 18 The described method for setting the potential of the word line WL involves setting the potential of the non-selected word line to rise at the start of the write operation, and then causing the potential of the selected word line to begin to fall. Furthermore, at the end of the write operation, the potential of the selected word line rises, and then the potential of the non-selected word line is set to fall. Therefore, localized voltage spikes are avoided, and writes to falsely selected memory cells are suppressed.

[0144] Reference Figure 18The method for setting the potential of the word line WL as described is, for example, using... Figure 19 The potential setting circuit 130 shown is used to perform this operation. Figure 19 The voltage generation circuit 131 of the voltage setting circuit 130 shown has a first variable power supply 1311 and a second variable power supply 1312. The first variable power supply 1311 and the second variable power supply 1312 are power supplies that allow the output voltage to be variable. The first variable power supply 1311 generates a voltage supplied to the non-selection word line in the range of a first potential V1 to a second potential V2. The second variable power supply 1312 generates a voltage supplied to the selection word line in the range of a first potential V1 to a third potential V3.

[0145] Figure 19 The driver circuit 132 of the voltage setting circuit 130 shown supplies the voltage generated by the voltage generation circuit 131 to the word lines WL of the memory cell array 110 via the line decoder 120. The driver circuit 132 has a selector 1321 that selects either the voltage generated by the first variable power supply 1311 or the voltage generated by the second variable power supply 1312 to be supplied to the line decoder 120. The selector 1321 supplies the voltage generated by the first variable power supply 1311 to the non-selected word lines and supplies the voltage generated by the second variable power supply 1312 to the selected word lines.

[0146] The output of selector 1321 is input to row decoder 120 via global word lines GWL corresponding to the word lines WL of memory blocks BLK (e.g., memory blocks BLK0 to BLK3) of memory cell array 110. Row decoder 120 uses block decoder 1201 to control the voltage supply to word lines WL for each memory block BLK.

[0147] Figure 19 The voltage setting circuit 130 shown simultaneously supplies voltage to all non-selected word lines of the selected memory block BLK. That is, in the case of… Figure 19 In the memory chip 100 of the voltage setting circuit 130 shown, the set non-select word lines include all word lines WL except for the select word line of the already selected memory block BLK.

[0148] Alternatively, the potential setting circuit 130 can also be... Figure 20 The structure shown. Figure 20 The voltage setting circuit 130 shown includes a voltage generation circuit 131, an upper non-selection word line power supply 1313, a lower non-selection word line power supply 1314, and a selection word line power supply 1315.

[0149] The upper non-select word line power supply 1313 supplies voltage to the memory cell MC connected between the dummy select memory cell and the select transistor ST1, establishing the corresponding non-select word line (upper non-select word line). The lower non-select word line power supply 1314 supplies voltage to the memory cell MC connected between the dummy select memory cell and the source line SL, establishing the corresponding non-select word line (lower non-select word line). The upper non-select word line power supply 1313 and the lower non-select word line power supply 1314 output voltages ranging from potential V1 to potential V2. The select word line power supply 1315 outputs voltages ranging from potential V1 to potential V3 supplied to the select word line.

[0150] Figure 20 The driver circuit 132 shown selects any one of the voltages generated by the upper non-select word line power supply 1313, the lower non-select word line power supply 1314, or the select word line power supply 1315, and supplies it to the row decoder 120. The row decoder 120's selector 1321 supplies the upper non-select word line with the voltage generated by the upper non-select word line power supply 1313, and the lower non-select word line with the voltage generated by the lower non-select word line power supply 1314. Then, the selector 1321 supplies the select word line with the voltage generated by the select word line power supply 1315. The row decoder 120 uses the block decoder 1201 to control the voltage supply to the word line WL for each memory block BLK.

[0151] The non-selection character line is set to the upper non-selection character line, and the lower non-selection character line is any non-selection character line other than the set non-selection character line. According to... Figure 20 The voltage setting circuit 130 shown can independently control the voltage of the set non-select word line and the voltage of other non-select word lines. For example, the voltage setting circuit 130 can also supply different voltages to the set non-select word line and other non-select word lines, or supply voltages at different times.

[0152] As explained above, in the method for setting the potential of the word line WL in the storage device of the embodiment, at the start of the write operation, after the transition of setting the potential of the non-selected word line is completed, the selected memory cell MC is turned off. Furthermore, in the method for setting the potential of the word line WL, at the end of the write operation, after turning on the selected memory cell MC, the potential of the non-selected word line is transitioned. Therefore, the storage device according to the embodiment does not generate local voltage boosts and can suppress writing to the non-selected memory cell MC.

[0153] <Example of Variation>

[0154] Storage devices for variations of the implementation method, such as... Figure 21As shown, each of the memory blocks BLK having the memory cell array 110 has a configuration of multiple segments containing multiple memory strings MS (hereinafter also referred to as "segment configuration"). Figure 21 The memory block BLK shown has a first segment SG1 and a second segment SG2.

[0155] In a memory block BLK composed of segments, a memory string MS belongs to any one of multiple segments. Furthermore, the memory string MS belonging to any one segment is selectively connected to the bit line BL. That is, the selection transistor ST1 of a memory string MS belonging to one segment is selectively connected to the bit line BL, while the selection transistor ST1 of memory strings MS belonging to other segments is not connected to the bit line BL. Each segment is composed of multiple memory strings MS connected to the bit line BL simultaneously.

[0156] In a memory device with a segmented memory block (BLK), write and read operations on memory cells (MCs) are managed in segment units. By employing a segmented structure, the range of memory cells (MCs) with a common word line (WL) can be expanded.

[0157] In a memory block BLK composed of segments, there is a connection device for selectively connecting any segment of the segment to the bit line BL. Figure 21 The memory block BLK shown has a segment transistor STE as the connection device. The segment transistor STE is connected between each of the multiple memory strings MS that are common to the bit line BL and the bit line BL. Using the segment transistor STE, the memory string MS connected to the bit line BL is selected in segment units.

[0158] In the section containing the selected memory cell MC, the segment transistor STE configured between the bit line BL and the memory string MS is in the ON state. On the other hand, in the section not containing the selected memory cell MC, the segment transistor STE configured between the bit line BL and the memory string MS is in the OFF state. The segment transistor STE is, for example, a MOS transistor whose ON state is controlled by applying a voltage to the gate line (hereinafter also referred to as "SEG") connected to the control gate.

[0159] exist Figure 21 In the study, it was observed that the segment transistor STE connected to the selection transistor ST1 differs for each memory string MS. However, the segment transistor STE connected to multiple memory strings MS belonging to the same segment can also be common.

[0160] exist Figure 21The selected memory cell MC is the one belonging to segment 1 SG1 and connected to the source line SL, indicated by the dashed line A. Therefore, in segment 1, segment transistor STE is in the ON state. On the other hand, in segment 2, which does not contain the selected memory cell MC, segment transistor STE is in the OFF state. Therefore, in segment 1 SG1, cell current flows from bit line BL to source line SL, while in segment 2 SG2, cell current does not flow from bit line BL to source line SL. Figure 21 In the configuration, the section transistor STE and the selection transistor ST1 in the ON state are displayed as "ON", and the section transistor STE and the selection transistor ST1 in the OFF state are displayed as "OFF".

[0161] in addition, Figure 21 The memory block BLK shown has local bit lines LBL1 to LBL3. Hereinafter, without specifying each of the local bit lines LBL1 to LBL3, it will be referred to as local bit line LBL. By configuring the local bit line LBL between bit line BL and source line SL, the memory string MS can be configured into multiple segments. Hereinafter, the segments of the memory string MS will also be referred to as "tiers". For example, the memory string MS can be connected between bit line BL and local bit line LBL, between local bit lines LBL, and between local bit line LBL and source line SL.

[0162] In a memory block BLK composed of segments, a group of memory strings that connects multiple memory strings MS in parallel within a segment is connected in series with a group of memory strings that connects multiple other memory strings MS in parallel via a local bit line LBL. Figure 21 The memory block BLK shown is composed of 3 local bit lines LBL and 4 memory strings MS configured between the bit lines BL and the source line SL.

[0163] exist Figure 21 In the memory block BLK shown, the memory cell MC belonging to the memory string MS of the level closest to the source line SL is selected. The selection transistor ST1 corresponding to the selected memory cell MC is set to the ON state. On the other hand, the selection transistor ST1 of the non-selected memory string MS containing the level of the selected memory cell MC (hereinafter also referred to as the "selection level") is set to the OFF state. The non-selection SGD of the selection level is also referred to as the "non-conducting SGD". Moreover, the selection gate line SGD other than the non-conducting SGD of the selection level, that is, the selection gate line SGD of the selection transistor ST1 corresponding to the selected memory cell MC, is referred to as the "conducting SGD". On the other hand, the selection transistor ST1 of the memory string MS that does not belong to the level of the selected memory cell MC is set to the ON state.

[0164] The following is for reference Figure 22 The cell current flowing through the selected memory cell MC in the memory block BLK with local bit lines LBL is explained. Figure 22 This is a block diagram showing a two-tiered structure with a local bit line LBL configured between the bit line BL and the source line SL. Here, the area between the bit line BL and the local bit line LBL is designated as Tier-1, and the first memory string group (1st MS group) is configured in Tier-1. Conversely, the area between the local bit line LBL and the source line SL is designated as Tier-2, and the second memory string group (2nd MS group) is configured in Tier-2.

[0165] exist Figure 22 In this process, the memory cell MC_s belonging to Tier 1 is selected, and Tier 1 is the selection level. The selection transistor ST1 corresponding to the memory cell MC_s is set to the ON state, while the selection transistor ST1 of the non-selected memory string MS in Tier 1 is set to the OFF state. Furthermore, the selection transistor ST1 of Tier 2 is set to the ON state.

[0166] Therefore, as Figure 22 As shown, the cell current Icell flowing in the selected memory cell MC_s is equal to the sum of the cell currents flowing in all memory strings MS in Tier 2. Therefore, by configuring the local bit line LBL in the memory block BLK, even if the number of stacked layers of the word line WL increases, that is, even if the distance from the bit line BL to the source line SL becomes longer, the amount of cell current flowing in the selected memory cell MC can be ensured. When selecting a Tier 2 memory cell MC, the same principle applies as when selecting a Tier 1 memory cell MC, ensuring the amount of cell current flowing in the selected memory cell MC. In other words, the amount of cell current flowing in the selected Tier 2 memory cells MCs is equal to the sum of the cell currents flowing in all memory strings MS in Tier 1.

[0167] Next, return to Figure 21 The description of the memory block BLK shown examines the range of memory cells MC that become floating during a write operation. Here, like... Figure 21Similar to the case indicated by the dashed line A, we will examine the case where the memory cell MC belonging to the first segment SG1 and configured between the local bit line LBL3 and the source line SL is selected. The selected memory cell MC is the memory cell MC closest to the source line SL. In this case, the memory cell MC belonging to the second segment SG2 and indicated by the dashed line B is a false selection memory cell. In the second segment SG2, the segment transistor STE and the false selection memory cell are in the off state. Here, in the second segment SG2, the selection transistor ST1 of the memory string MS configured between the bit line BL and the local bit line LBL3, and the selection transistor ST1 of the memory string MS belonging to the false selection memory cell are in the on state. Therefore, in Figure 21 In the diagram, the area enclosed by the dashed line C and marked with a shadow is in a floating state.

[0168] As mentioned above, in memory blocks BLK with local bit lines LBL in their segment structure, the range of floating states is sometimes quite wide. As a result, the coupling capacitance is large, and the time for the potential difference dV across the resistive switching memory region MR to generate pseudo-selected memory cells becomes longer.

[0169] Figure 23 about Figure 21 The write operation shown in memory block BLK is an example of a timing diagram illustrating the operation of a memory device in an implementation that suppresses the potential difference dV. Figure 23 In this context, the gate line of the segment transistor STE belonging to the selected memory cell MC is recorded as "selection SEG", and the gate line of the segment transistor STE in other segments is recorded as "non-selection SEG".

[0170] At time T41, the select gate line SGD and all word lines WL are set to the first potential V1. The first potential V1 is the potential at which the select transistor ST1 and the cell transistor SW are turned on, for example, +4V.

[0171] Next, at time T42, the SGD is turned on and the non-select word line is set to a second potential V2, where the select transistor ST1 and the cell transistor SW remain on. This second potential V2 is, for example, 7V, a potential at which the select transistor ST1 and the cell transistor SW remain on even when the select bit line BL rises during a write operation. Additionally, at time T42, the potential of the select SEG is changed from the L level (e.g., -2V) when the segment transistor STE is off to the H level (e.g., +7V) when the segment transistor STE is on. The potential of the non-select SEG remains at the L level.

[0172] Then, at time T43, the non-conducting SGD and the select word line are set to a third potential V3 (e.g., -2V) where the select transistor ST1 and the cell transistor SW are off. If the threshold voltage Vth of the cell transistor SW falls below the potential of the select word line during the drop from the first potential V1 to the third potential V3, then the cell transistor SW of the selected memory cell MC becomes off. With the cell transistor SW off, current flows through the resistive switching memory region MR of the selected memory cell MC during subsequent write operations.

[0173] In this write operation, the potential of the select bit line BL is set from L level (e.g., 0V) to H level (e.g., +4V). Then, if the potential of the select bit line BL drops rapidly, a reset write is performed to set the resistive switching memory region MR to a high resistance state. On the other hand, if the potential of the select bit line BL drops slowly, a set write is performed to set the resistive switching memory region MR to a low resistance state.

[0174] After performing a write operation on the selected memory cell MC, at time T44, the SGD and select word line are set to the first potential V1. Then, at time T45, the SGD and select word line are set to the first potential V1. Additionally, the potential of the select SEG is changed from H level to L level.

[0175] As described above, after the transition of SGD and the setting of the non-select word line potential is completed, the cell transistor SW of the selected memory cell MC is turned off. Then, after turning on the cell transistor SW of the selected memory cell MC, SGD is turned on and the setting of the non-select word line is set to the potential before the write operation. That is, referring to... Figure 23 The described write operation is similar to the reference in the following aspects. Figure 18 The described write operations differ: the potential of the non-select word line is set to be the same as the potential of the on SGD, and the potential of the select word line is set to be the same as the potential of the off SGD. This is based on the following reasons.

[0176] In memory block BLK, during the wait state, the switch on bit line BL connected to memory string MS is turned off. This switch... Figure 17 The memory block BLK shown contains the selection transistor ST1. Figure 21 The memory block BLK shown contains segment transistors (STEs). In the wait state, transistors other than the switch are in the ON state. Transistors in the ON state during the wait state... Figure 17 The memory block BLK shown contains the unit transistor SW. Figure 21The memory block BLK shown contains the cell transistor SW and the selection transistor ST1.

[0177] exist Figure 21 In the memory block BLK shown, during a write operation, the selection transistor ST1 for the segment containing the memory cell MC to be written is connected to the bit line BL. On the other hand, the selection transistor ST1 for the segment not containing the memory cell MC is not connected to the bit line BL. Furthermore, during a write operation, the cell current Icell flows from the bit line BL through the selection transistor ST1 for the segment containing the memory cell MC to the resistive switching memory region MR of the selected memory cell MC.

[0178] Therefore, in Figure 21 In the memory block BLK shown, except for the selection transistor ST1 at the selection level, the conduction state of the selection transistor ST1 is synchronized with the conduction state of the cell transistor SW of the non-selected memory cell MC. For example, the conduction state of the selection transistor ST1 corresponding to the selected memory cell MC is synchronized with the conduction state of the cell transistor SW of the non-selected memory cell MC.

[0179] The more memory cells MC contained in the memory cell array 110, the longer the potential difference dV is likely to occur across the resistive switching memory region MR of the selected memory cell. In other words, in a memory block BLK that is composed of segments and has local bit lines LBL, interference caused by voltage boost is more likely to occur.

[0180] The time for generating a potential difference dV in the storage device of the variation of the implementation is shorter than that of the comparative example, where the potentials of the select word line and the non-select word line transition simultaneously. In other words, by setting the selected memory cell MC to an off state after the potential of the set non-select word line transitions, and then setting the non-select word line to a transition state after the potential of the selected memory cell MC turns on, the time for generating a potential difference dV can be shortened. As a result, writing to falsely selected memory cells can be suppressed.

[0181] As explained above, the more memory cells MC included in the memory cell array 110, the greater the suppression effect of the storage device in the embodiment on writing to spurious selected memory cells. For example, when the memory block BLK is composed of segments and has a local bit line LBL, writing to non-selected memory cells MC can be suppressed.

[0182] (Other implementation methods)

[0183] The above description illustrates a resistive switching memory region (MR) using an alloy-type phase transfer element (Ge2Sb2Te5) as the memory cell MC. However, other elements can also be used in the resistive switching memory region MR. For example, the resistive switching memory region MR can also be a structure formed by alternating layers of Sb2Te3 and GeTe as interface-type phase transfer elements, or a structure formed by alternating layers of BiSbTe and GeTe. Furthermore, the resistive switching memory region MR can be a structure formed by alternating layers of Ge, Sb, and Te, or a structure containing chalcogenide materials. Alternatively, the resistive switching memory region MR can also contain TiO2 as a resistive switching film. X WO X HfO X TaO X Any of these or an MTJ (Magnetic Tunnel Junction). Here, the MTJ can also be composed of any alloy such as CoFe alloy or NiFe alloy.

[0184] Furthermore, as described above, the case where the unit transistor SW is in the ON state when the word line WL is at a positive potential and in the OFF state when the word line WL is at a negative potential has been explained. However, the relationship between the potential of the word line WL and the ON state of the unit transistor SW is not limited to the described case. For example, the example of the unit transistor SW being an n-channel MOS transistor has been described above, but the unit transistor SW can also be a p-channel MOS transistor.

[0185] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

[0186] Explanation of symbols

[0187] 1: Memory System

[0188] 100: Memory chip

[0189] 110: Memory cell array

[0190] 120: Line Decoder

[0191] 130: Potential setting circuit

[0192] 131: Voltage Generation Circuit

[0193] 132: Driver circuit

[0194] 140: Sensing Amplifier

[0195] 150: Address Register

[0196] 160: Instruction Register

[0197] 170: Sequencer

[0198] BL: Bitline

[0199] LBL: Local Bitline

[0200] MC: Storage Unit

[0201] MR: Resistive Switching Memory Region

[0202] MS: Memory String

[0203] SGD: Select Gate Line

[0204] SL: Source Line

[0205] ST1: Select Transistor

[0206] SW: Unit Transistor

[0207] WL: Word line.

Claims

1. A storage device comprising: A memory cell array has multiple memory cells and multiple memory strings arranged in a row. Each memory cell has a cell transistor and a resistive switching memory region connected in parallel to any one of a plurality of first potential application electrodes. Each memory string contains multiple memory cells connected in series with a selection transistor that selects the memory cell. as well as The potential setting circuit controls the conduction state of the unit transistor by setting the potential of the first potential application electrode, and adjusts the timing of setting the potential for each of the first potential application electrodes; At the first end of the series connection configuration of the plurality of memory cells constituting the memory string, a selection transistor whose conduction state is controlled by the potential of a second potential application electrode is connected; and at the second end of the series connection configuration, a third potential application electrode is connected. During the write operation to the memory cell, the potential setting circuit Before setting the potential of the first potential application electrode corresponding to the memory cell to be written to the potential at which the cell transistor is turned off, the potential of the first potential application electrode of the setting object other than the first potential application electrode is set to the potential at which the cell transistor remains on during the write operation. After setting the potential of the first potential application electrode to the potential at which the unit transistor is turned on, the potential of the first potential application electrode of the target is set to the potential before the write operation. The first potential application electrode of the set object includes at least the first potential application electrode corresponding to the memory cell connected between the memory cell of the write object and the select transistor.

2. The storage device according to claim 1, wherein During the write operation, the potential setting circuit In the first timing sequence, all electrodes applying the first potential are set to the first potential when the unit transistor is in the ON state. In a second timing sequence that follows the first timing sequence, the first potential application electrode of the target object is set to a second potential that is higher than the first potential and the unit transistor remains in the on state. In a third timing sequence that follows the second timing sequence, the electrode for selecting the first potential is set to a third potential that is lower than the first potential and the unit transistor is in an off state. In the fourth timing sequence, which is later than the third timing sequence, the electrode for selecting the first potential is set to the first potential. In the fifth timing sequence, which is later than the fourth timing sequence, the first potential application electrode of the set object is set to the first potential.

3. The storage device according to claim 1 or 2, wherein The memory cell array is formed on a semiconductor substrate. The resistive switching memory region extends along a first direction orthogonal to the semiconductor substrate. The unit transistor has: The first semiconductor layer extends along the first direction and covers the side of the resistive switching memory region; A first insulating layer extends along the first direction and covers the side surface of the first semiconductor layer; as well as One of the first potential application electrodes extends along a second direction orthogonal to the first direction and is opposed to the first semiconductor layer, separating the first insulating layer; The selection transistor has the following features: The second semiconductor layer extends along the first direction; The second insulating layer extends along the first direction and covers the side surface of the second semiconductor layer; as well as The second potential application electrode extends along the second direction and is opposed to the second semiconductor layer, separating the second insulating layer; The memory string has a configuration in which the selection transistor, a plurality of the unit transistors, and the third potential application electrode are connected in series along the first direction. The first semiconductor layer is continuous with the second semiconductor layer, the first insulating layer is continuous with the second insulating layer, and the first semiconductor layer is electrically connected to the third potential application electrode.

4. The storage device according to claim 1 or 2, wherein The first potential application electrode of the set object includes all the first potential application electrodes except for the selected first potential application electrode.

5. The storage device according to claim 1 or 2, wherein The memory cell array also includes a fourth potential application electrode that supplies current to the memory string via the selection transistor. The memory cell array has: a memory block, each having a plurality of segments containing a plurality of the memory strings; and a connection means for selectively connecting any one of the segments of the memory block to the fourth potential application electrode.

6. The storage device according to claim 5, wherein During the write operation of the storage unit The on-state of the selection transistor contained in the memory string to which the memory cell to be written belongs is synchronized with the on-state of the cell transistor of the memory cell that is not to be written.

7. The storage device according to claim 1 or 2, wherein The storage cell array has local bit lines. A first memory string group formed by connecting multiple memory strings in series and parallel and a second memory string group formed by connecting multiple memory strings in series and parallel are connected in series via the local bit line.

8. The storage device according to claim 1 or 2, wherein the resistive switching storage region is a resistive switching storage element that changes to a low-resistance state or a high-resistance state depending on the crystal state.

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