A decoding implementation method and system of a 64-ary LDPC code

Abstract

The application discloses a decoding implementation method and system of a 64-ary LDPC code, and the method comprises the following steps: S1, initialization, initializing a symbol vector and an amplitude vector, and initializing a check node symbol vector and a check node amplitude vector; S2, check node information updating, rearranging the message transmitted by a variable node, and calculating new check node output information by using a forward-backward recursion algorithm; S3, variable node information updating, rearranging the message transmitted by a check node, and calculating new variable node output information by using a normalization processing method; S4, output result, selecting the information with the maximum confidence in the variable node information as the decoding output of this iteration, multiplying the decoding output with a check matrix H to obtain a check result, and if the check passes or the iteration number is exceeded, the iteration is exited, otherwise, the iteration is repeated. The application can realize the decoding of the 64-ary LDPC code of the new system of Beidou-3.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and system for decoding 64-ary LDPC codes. Background Technology

[0002] Low-Density Parity-Check (LDPC) codes were proposed by Robert G. Gallager in 1962. It wasn't until 1999, when MacKay and Wilberg rediscovered the superior performance of LDPC codes, that they gained widespread attention from coding experts and scholars. LDPC codes are linear block codes with a sparse parity-check matrix. Iterative decoding algorithms allow LDPC codes to approach the Shannon limit in performance. Because quasi-cyclic LDPC decoders are easy to implement in parallel and provide high throughput, they are used in multiple standards. Currently, LDPC code technology has been applied to communication systems based on standards such as CMMB, DTMB, DVB-S2, DVB-T2, ATSC 3.0, and 4G.

[0003] The CNAV1, CNAV2, and CNAV3 messages at the three frequency points B1C, B2a, and B2b of BeiDou-3 all use 64-bit LDPC encoding. Although 64-bit LDPC code is no different from binary LDPC code from the perspective of channel transmission, 64-bit LDPC code has a longer range than binary LDPC code, so it has better error correction capability. At the same time, 64-bit LDPC code converts 6 bits into 1 symbol, which has a strong ability to resist burst errors and is particularly suitable for high-speed information transmission systems.

[0004] However, among existing technologies, how to achieve rapid iterative decoding of the 64-ary LDPC code of the new BeiDou-3 system is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a method and system for decoding 64-ary LDPC codes, so as to solve the technical problem of how to decode 64-ary LDPC codes of the new BeiDou-3 system.

[0006] This invention is achieved using the following technical solution: a method for decoding 64-ary LDPC codes, comprising the following steps:

[0007] S1: Initialization, initialize the sign vector and magnitude vector, and initialize the check node sign vector and check node magnitude vector;

[0008] S2: Update the verification node information, rearrange the messages passed by the variable node, and calculate the new verification node output information through the forward and backward recursive algorithm;

[0009] S3: Update variable node information by rearranging the messages passed by the verification node and calculating the new variable node output information through a normalization process.

[0010] S4: Output the result. Select the information with the highest confidence among the variable node information as the decoding output of this iteration, and then multiply it with the verification matrix H to obtain the verification result. If the verification passes or the number of iterations is exceeded, exit the iteration; otherwise, repeat the iteration.

[0011] Further, step S1 specifically involves: caching the deinterleaved symbol data and amplitude data, predicting the position of the error bit through full match, initializing and caching the symbol vector and amplitude vector, and copying the symbol data and amplitude data into the check node cache to complete the initialization of the check node symbol vector and check node amplitude vector cache.

[0012] Furthermore, step S2 specifically involves: first, rearranging the messages passed by the variable nodes. This rearrangement is equivalent to multiplying the variable message by the non-zero elements in the parity check matrix H. The multiplication operation follows the finite field GF(2^3)^2. 6 The calculation rules are then used to obtain the new verification node output information through the calculation of variable messages. This calculation applies a forward and backward recursive algorithm.

[0013] Furthermore, step S2 includes the following sub-steps:

[0014] S21: The symbol vector Q_idx in the finite field GF(2 6 The symbol vector Q_idx is first transformed into exponential form and multiplied with the parity check matrix H, and then the product is transformed into vector form R_idx.

[0015] S22: Use the forward and backward recursive algorithm to recursively update R_idx and the magnitude vector Q_val to obtain the new symbol vector R_idx_updata and the new magnitude vector R_val_updata;

[0016] S23: Place the new symbol vector R_idx_updata in the finite field GF(2 6 The new symbol vector R_idx_updata is first transformed into exponential form and multiplied with the parity check matrix H. Then, the product is transformed into vector form to update R_idx and R_val.

[0017] Furthermore, step S22 specifically involves using a forward-backward recursive algorithm to decompose R_idx and the magnitude vector Q_val into 6 sorting recursive maximum / minimum operations to obtain a new sign vector R_idx_updata and a new magnitude vector R_val_updata.

[0018] Furthermore, step S3 specifically involves: first, rearranging the messages transmitted by the verification nodes. This rearrangement is equivalent to dividing the verification message by the non-zero elements in the verification matrix H. The division operation follows the finite field GF(2^3)^2. 6 The operation rules are then used to calculate the new variable node output information through the verification message calculation, which is then normalized.

[0019] Furthermore, step S3 includes the following sub-steps:

[0020] S31: Each time symbol data and amplitude data are read from the check node update cache and initialization cache, the synchronization matrix summation algorithm is performed to solve for and output the symbol and amplitude;

[0021] S32: Perform decoding decision and output the decoding result d_sym.

[0022] Furthermore, step S4 includes the following sub-steps:

[0023] S41: Multiply the decoding result d_sym obtained in step S32 with the parity check matrix and take the XOR operation. If the parity check result is 0, the check passes; otherwise, proceed to the next step.

[0024] S42: If the maximum number of iterations has not been reached, update the output symbol and magnitude buffer to the variable node symbol and magnitude buffer.

[0025] A decoding implementation system for a base-64 LDPC code includes an initialization module, a check node information update module, and a variable node information update module. The initialization module initializes the symbol vector and magnitude vector, and initializes the check node symbol vector and check node magnitude vector. The check node information update module rearranges the messages transmitted by the variable nodes and calculates new check node output information using a forward-backward recursive algorithm. The variable node information update module rearranges the messages transmitted by the check nodes, calculates new variable node output information using a normalization method, selects the information with the highest confidence among the variable node information as the decoding output of this iteration, and multiplies it with the check matrix H to obtain the check result. If the check passes or the number of iterations is exceeded, the iteration is terminated; otherwise, the iteration is repeated.

[0026] The beneficial effects of this invention are as follows: Based on the characteristics of non-zero elements in the 64-ary LDPC code parity check matrix, one parity node corresponds to four variable nodes (row weight 4), and one variable node corresponds to two parity nodes (column weight 2). When updating the parity node, a forward-backward recursive algorithm is used to simplify and decompose the parity node with a row weight of 4 into 6 maximum / minimum operations. When updating the variable node, the parity message is divided by the non-zero elements of the parity check matrix, and then normalization is performed. All non-zero elements follow GF(2) during the corresponding parity node update and variable node update processes. 6 The operation rules of the domain are implemented using an improved algorithm based on confidence propagation, which has good performance and low complexity, making it very suitable for hardware implementation. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0031] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] Example 1:

[0033] See Figure 1 A decoding implementation method for a base-64 LDPC code includes the following steps:

[0034] Initialization involves caching the deinterleaved symbol data (pcode_sig_ram) and amplitude data (pcode_mag_ram). Error bit positions are predicted by full match, and the symbol vector and amplitude vector are initialized and cached (fn_idx_ram, fn_val_ram). At the same time, this data is copied into the check node buffer, which initializes the check node symbol vector and amplitude vector buffers (Q_idx_ram, Q_val_ram).

[0035] Verification node information update: First, the messages passed by the variable nodes are rearranged. Rearrangement is equivalent to multiplying the variable messages by the non-zero elements in the verification matrix H. The multiplication operation follows the finite field GF(2). 6 The calculation rules are then used to obtain new verification node output information through the calculation of variable messages. This calculation applies a forward and backward recursive algorithm, but to simplify the calculation, only the 7 variable messages with the highest confidence are taken, and only 7 verification messages are retained in the output. The specific update process includes the following steps:

[0036] a. Transfer the data in the symbol vector buffer (Q_idx_ram) to the finite field GF(2). 6 The symbol vector Q_idx is first transformed into exponential form and then multiplied with the parity check matrix. The result of the product in exponential form is then transformed into vector form R_idx.

[0037] b. The recursive maximum / minimum value calculation is completed jointly by the verification node update control circuit, data flow control circuit 1, and forward / backward recursion circuit. That is, the R_idx and Q_val data are decomposed into 6 sorting recursive maximum / minimum value calculations to obtain R_idx_updata and R_val_updata. The specific 6 recursive update processes are as follows:

[0038] b1.R_idx, Q_val generate four sets of data A_idx[0], B_val[0], A_idx[1], B_val[1] and four sets of data A_idx[3], B_val[3], A_idx[2], B_val[2] respectively through the check node update control circuit and the data flow control circuit 1;

[0039] b2. The four sets of data A_idx[0], B_val[0], A_idx[1], and B_val[1] are used to generate O_idx[0] and O_val[0] through a forward-backward recursion circuit;

[0040] b3. The four sets of data A_idx[3], B_val[3], A_idx[2], and B_val[2] are used to generate O_idx[1] and O_val[1] through a forward-backward recursion circuit;

[0041] b4. The four sets of data, O_idx[1], O_val[1], A_idx[1], and B_val[1], are processed by a forward-backward recursion circuit to generate R_idx_updata[0] and R_val_updata[0].

[0042] b5. The four sets of data, O_idx[1], O_val[1], A_idx[0], and B_val[0], are processed by a forward-backward recursion circuit to generate R_idx_updata[1] and R_val_updata[1].

[0043] b6. The four sets of data, O_idx[0], O_val[0], A_idx[3], and B_val[3], are processed by a forward-backward recursion circuit to generate R_idx_updata[2] and R_val_updata[2].

[0044] b7. The four sets of data, O_idx[0], O_val[0], A_idx[2], and B_val[2], are used to generate R_idx_updata[3] and R_val_updata[3] through a forward-backward recursive circuit.

[0045] c. Perform a finite field GF(2) operation on the symbol vector R_idx_updata. 6 The symbol vector R_idx_updata is first converted into exponential form and multiplied with the parity check matrix. Then, the result of the exponential product is converted into vector form to update the R_idx_ram and R_val_ram caches.

[0046] To update variable node information, the messages transmitted by the check nodes are first rearranged. This rearrangement is equivalent to dividing the check message by the non-zero elements in the check matrix H. The division operation follows the finite field GF(2). 6 The algorithm follows the rules of operation, and then calculates the new variable node output information through the verification message. This calculation is normalized. Among the updated 7 variable node information, the information with the highest confidence is the decoded output of this iteration. It is then multiplied with the verification matrix H to obtain the verification result. If the verification passes or the number of iterations has been exceeded, the iteration is terminated; otherwise, the iteration continues. The specific update process includes the following steps:

[0047] a. Read two sets of symbol and amplitude data from the check node update buffer (R_idx_ram, R_val_ram) and initialization buffer (fn_idx_ram, fn_val_ram). The synchronization matrix summation algorithm is completed jointly by the data control circuit 2 and the summation algorithm circuit to solve for and output the symbol and amplitude (O_idx, O_val). The synchronization matrix summation algorithm requires two solutions. The specific process is as follows:

[0048] a1. The check node update cache (R_idx, R_val) and initialization cache (fn_idx, fn_val) generate six sets of data A_idx[0], A_val[0], B_idx[0], B_val[0], B_idx[1], and B_val[1] respectively through the data flow control circuit 2;

[0049] a2. The four sets of data A_idx[0], A_val[0], B_idx[1], and B_val[1] are used to generate O_idx[0] and O_val[0] through a synchronization matrix summing circuit;

[0050] The four sets of data, A_idx[0], A_val[0], B_idx[0], and B_val[0], are used to generate O_idx[1] and O_val[1] through a synchronous matrix summing circuit.

[0051] b. The four sets of data O_idx[0], O_val[0], B_idx[0], and B_val[0] are passed through the synchronization matrix summation circuit and the decoding decision is performed to output the decoding result d_sym.

[0052] c. Verification: Multiply the decoded data d_sym by the verification matrix (multiplication follows the finite field GF(2)). 6 The operation rules are then executed, and the result is XORed with the output. If the result is 0, the verification passes; otherwise, proceed to the next step.

[0053] d. If the maximum number of iterations has not been reached, update the output symbol and magnitude buffer (O_idx_ram, O_val_ram) to the variable node symbol and magnitude buffer (Q_idx_ram, Q_val_ram).

[0054] A decoding implementation system for a base-64 LDPC code includes an initialization module, a check node information update module, and a variable node information update module. The initialization module initializes the symbol vector and magnitude vector, and initializes the check node symbol vector and check node magnitude vector. The check node information update module rearranges the messages transmitted by the variable nodes and calculates new check node output information using a forward-backward recursive algorithm. The variable node information update module rearranges the messages transmitted by the check nodes, calculates new variable node output information using a normalization method, selects the information with the highest confidence among the variable node information as the decoding output of this iteration, and multiplies it with the check matrix H to obtain the check result. If the check passes or the number of iterations is exceeded, the iteration is terminated; otherwise, the iteration is repeated.

[0055] Based on the characteristics of non-zero elements in a base-64 LDPC code parity-check matrix, this invention assigns one parity node to four variable nodes (row weight 4) and one variable node to two parity nodes (column weight 2). During parity node updates, a forward-backward recursive algorithm simplifies and decomposes the parity node with a row weight of 4 into six maximum / minimum operations. During variable node updates, the parity message is divided by the non-zero elements of the parity-check matrix, followed by normalization. All non-zero elements follow GF(2) during both the corresponding parity node and variable node updates. 6 The algorithm for implementing the operation rules of the domain is based on an improved algorithm of confidence propagation. It has good performance and low complexity, making it very suitable for hardware implementation.

[0056] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0057] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A method for decoding a base-64 LDPC code, characterized in that, Includes the following steps: S1: Initialization, initialize the symbol vector and amplitude vector, and initialize the check node symbol vector and check node amplitude vector; Step S1 specifically involves: caching the deinterleaved symbol data and amplitude data, and predicting the position of the error bit by full match, initializing and caching the symbol vector and amplitude vector, and copying the symbol data and amplitude data into the check node cache to complete the initialization of the check node symbol vector and check node amplitude vector cache. S2: Update the verification node information. Rearrange the messages passed by the variable nodes and calculate the new verification node output information using a forward-backward recursive algorithm. Specifically, step S2 involves: first, rearranging the messages passed by the variable nodes. Rearranging is equivalent to multiplying the variable messages by the non-zero elements in the verification matrix H. The multiplication operation follows the finite field GF(2). 6 The calculation rules are then used to obtain the new verification node output information through the calculation of variable messages. This calculation applies a forward and backward recursive algorithm. Step S2 includes the following sub-steps: S21: The symbol vector Q_idx in the finite field GF(2 6 The symbol vector Q_idx is first transformed into exponential form and multiplied with the parity check matrix H, and then the product is transformed into vector form R_idx. S22: Use the forward and backward recursive algorithm to recursively update R_idx and the magnitude vector Q_val to obtain the new symbol vector R_idx_updata and the new magnitude vector R_val_updata; S23: Place the new symbol vector R_idx_updata in the finite field GF(2). 6 The new symbol vector R_idx_updata is first transformed into exponential form and multiplied with the parity check matrix H. Then, the product result is transformed into vector form to update R_idx and R_val. S3: Update variable node information by rearranging the messages passed by the verification node and calculating the new variable node output information through a normalization process. S4: Output the result. Select the information with the highest confidence among the variable node information as the decoding output of this iteration, and then multiply it with the verification matrix H to obtain the verification result. If the verification passes or the number of iterations is exceeded, exit the iteration; otherwise, repeat the iteration.

2. The decoding implementation method of a base-64 LDPC code as described in claim 1, characterized in that, Step S22 specifically involves using a forward-backward recursive algorithm to decompose R_idx and the magnitude vector Q_val into 6 sorted recursive maximum / minimum operations to obtain a new sign vector R_idx_updata and a new magnitude vector R_val_updata.

3. The decoding implementation method of a base-64 LDPC code as described in claim 1, characterized in that, Step S3 specifically involves: first, rearranging the messages transmitted by the verification nodes. Rearranging is equivalent to dividing the verification message by the non-zero elements in the verification matrix H. The division operation follows the finite field GF(2). 6 The operation rules are then used to calculate the new variable node output information through the verification message calculation, which is then normalized.

4. The decoding implementation method of a base-64 LDPC code as described in claim 3, characterized in that, Step S3 includes the following sub-steps: S31: Each time symbol data and amplitude data are read from the check node update cache and initialization cache, the synchronization matrix summation algorithm is performed to solve for and output the symbol and amplitude; S32: Perform decoding decision and output the decoding result d_sym.

5. The decoding implementation method of a base-64 LDPC code as described in claim 4, characterized in that, Step S4 includes the following sub-steps: S41: Multiply the decoding result d_sym obtained in step S32 with the parity check matrix and take the XOR operation. If the parity check result is 0, the check passes; otherwise, proceed to the next step. S42: If the maximum number of iterations has not been reached, update the output symbol and magnitude buffer to the variable node symbol and magnitude buffer.

6. A decoding implementation system for a base-64 LDPC code, used to implement the decoding implementation method for a base-64 LDPC code as described in any one of claims 1 to 5, characterized in that, It includes an initialization module, a verification node information update module, and a variable node information update module. The initialization module is used to initialize the sign vector and magnitude vector, and to initialize the verification node sign vector and verification node magnitude vector. The verification node information update module is used to rearrange the messages transmitted by the variable node and calculate the new verification node output information through a forward and backward recursive algorithm. The variable node information update module is used to rearrange the messages transmitted by the verification node, calculate the new variable node output information through a normalization processing method, select the information with the highest confidence in the variable node information as the decoding output of this iteration, and then multiply it with the verification matrix H to obtain the verification result. If the verification passes or the number of iterations is exceeded, the iteration is exited; otherwise, the iteration is repeated.

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