Data processing method, storage device and digital power amplifier chip

Abstract

The application discloses a data processing method, a storage device and a digital power amplifier chip. The storage space of the storage device is divided into M storage blocks, and a storage controller can respond to a first write request sent by a source end, a first read request / second write request sent by a microprocessor and a second read request sent by a target end in parallel, so that the first storage block is written during the response to the first write request sent by the source end, the second storage block is read and written during the response to the first read request and the second write request sent by the microprocessor, and the third storage block is read during the response to the second read request sent by the target end, so that the data processing efficiency is greatly improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of signal processing, and particularly relates to a data processing method, a storage device and a digital power amplifier chip. BACKGROUND

[0002] In order to improve the hearing experience of a user, a microprocessor (for example, a DSP) is arranged in a digital power amplifier chip (i.e., a digital power amplifier chip). After an audio data is written into a storage device by a source end, the processor reads the audio data from the storage device, processes the read audio data, and writes the processed audio data into the storage device. Then, a target end reads the audio data processed by the processor from the storage device. The processing of the audio data by the processor includes, but is not limited to, equalization processing and reverberation processing.

[0003] How to control the process of accessing the storage device by the microprocessor, the source end and the target end to achieve higher data processing efficiency is a problem to be solved by those skilled in the art. SUMMARY

[0004] Therefore, the purpose of the application is to provide a data processing method, a storage device and a digital power amplifier chip, which control the process of accessing the storage device by the microprocessor, the source end and the target end to achieve higher data processing efficiency.

[0005] To achieve the above purpose, the application provides the following technical solutions.

[0006] In a first aspect, the application provides a data processing method applied to a storage controller of a storage device, a storage space of the storage device is divided into M storage blocks, each storage block contains a plurality of address-continuous storage units, M is an integer greater than or equal to 3, and the method comprises the following steps:

[0007] In response to a first write request sent by a source end, data is sequentially written into the M storage blocks;

[0008] During the period of writing data into a first storage block in response to the first write request sent by the source end, in response to a first read request sent by a microprocessor, data stored in a second storage block is sent to the microprocessor, in response to a second write request sent by the microprocessor, data processed by the microprocessor is written into the second storage block, the first storage block is any one of the M storage blocks, and the second storage block is a storage block in which data writing by the source end is completed.

[0009] During the period of writing data into the first storage block in response to the first write request sent by the source end, in response to a second read request sent by a target end, data stored in a third storage block is sent to the target end, and the third storage block is a storage block in which data writing by the microprocessor is completed.

[0010] Optionally, based on the data processing method, further comprising:

[0011] In response to the first storage block being filled with data in response to the first write request sent by the source end, an interrupt request is generated and outputted to trigger the microprocessor to send a first read request for the second storage block.

[0012] Optionally, the storage controller comprises an arbitrator; and based on the data processing method, further comprising:

[0013] The arbitrator determines whether the received requests have access conflicts, and in a case where it is determined that there are access conflicts, determines, according to a preset priority, a request having access rights from the requests having access conflicts.

[0014] Optionally, the priority of the second write request, the first read request, the first write request and the second read request decreases one by one.

[0015] Optionally, the second storage block is a storage block whose access order is 1 bit later than that of the first storage block among the M storage blocks.

[0016] Optionally, the third storage block is a storage block whose access order is 1 bit later than that of the second storage block among the M storage blocks.

[0017] In a second aspect, the application provides a storage device, comprising a storage medium and a storage controller; a storage space formed by the storage medium is divided into M storage blocks, each storage block comprising a plurality of address-continuous storage units, and M is an integer greater than or equal to 3;

[0018] The storage controller is configured to: in response to a first write request sent by a source end, sequentially write data into the M storage blocks; during the writing of data into the first storage block in response to the first write request sent by the source end, in response to a first read request sent by a microprocessor, send data stored in a second storage block to the microprocessor, in response to a second write request sent by the microprocessor, write data processed by the microprocessor into the second storage block, the first storage block being any one of the M storage blocks, and the second storage block being a storage block in which the data write of the source end is completed; during the writing of data into the first storage block in response to the first write request sent by the source end, in response to a second read request sent by a target end, send data stored in a third storage block to the target end, the third storage block being a storage block in which the data write of the microprocessor is completed.

[0019] Optionally, based on the storage device, an arbitrator is further provided;

[0020] The arbiter is configured to determine whether the received request causes an access conflict, and in a case where it is determined that an access conflict occurs, determine, according to a preset priority, a request having access authority from the multiple requests causing the access conflict.

[0021] In a third aspect, the present application provides a digital power amplifier chip, comprising the storage device of any one of the above.

[0022] Therefore, the present application has the following beneficial effects:

[0023] The data processing method disclosed by the present application divides the storage space of the storage device into M (M is greater than or equal to 3) storage blocks, and each storage block includes a plurality of address-continuous storage units. The storage controller writes data into each storage block in sequence in response to a first write request sent by a source end; the storage controller performs a read operation (reads data stored in the second data, and the microprocessor processes the data) and a write operation (rewrites the data processed by the microprocessor to the second storage block) on the second storage block (a storage block in which the data write of the source end is completed) in response to a first read request and a second write request sent by the microprocessor during the period in which the storage controller writes data into the first storage block in response to the first write request sent by the source end; and the storage controller performs a read operation on the third storage block (a storage block in which the data write of the microprocessor is completed) in response to a second read request sent by a target end. It can be seen that, based on the data processing method disclosed by the present application, on the basis of dividing the storage space of the storage device into at least three storage blocks, the storage controller can respond to the first write request sent by the source end, the first read request / second write request sent by the microprocessor, and the second read request sent by the target end in parallel, so as to perform the read operation and the write operation on the second storage block in response to the first read request and the second write request sent by the microprocessor during the period in which the write operation is performed on the first storage block in response to the first write request sent by the source end, and perform the read operation on the third storage block in response to the second read request sent by the target end, thereby greatly improving the data processing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0025] Figure 1 A flowchart of a data processing method disclosed by the present application;

[0026] Figure 2 A schematic diagram of the read and write operations on the storage space disclosed by the present application;

[0027] Figure 3A schematic diagram of a storage space division manner disclosed in the present application;

[0028] Figure 4 A schematic diagram of a data processing process in the case of the storage space division manner shown in Figure 3

[0029] Figure 5 A structural schematic diagram of a digital power amplifier chip disclosed in the present application. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0031] In the present application, the storage space of the storage device is divided into M storage blocks, and M is an integer greater than or equal to 3. Each storage block contains a plurality of storage units with consecutive addresses. It should be noted that the division of the storage space of the storage device into M storage blocks refers to logical division.

[0032] As shown in one example in Figure 3 , the storage space of the storage device contains 128 storage units, and the addresses of the 128 storage units are 0 to 127 in sequence. The storage space of the storage device is divided into 4 storage blocks (Block), and each of the 4 storage blocks contains 32 storage units. In order of low to high first address, the 4 storage blocks are referred to as storage block BLK0, storage block BLK1, storage block BLK2 and storage block BLK3 respectively.

[0033] In the example shown in Figure 3 , the width of each storage unit is 32 bits, i.e. each storage unit can store 32 bits of data. It should be noted that the width of each storage unit is 32 bits, which is set based on the characteristics of the audio data processed by the digital power amplifier chip, so that each storage unit can store 16 bits of left channel audio data and 16 bits of right channel audio data, or store 32 bits of IVsense data. In a specific implementation, the bit width of the storage unit is not limited to 32 bits. In addition, Figure 3 This is only one example, and the number of storage units contained in the storage space of the storage device, the number of divided storage blocks, and the number of storage units contained in each storage block can be in other manners.

[0034] ​In digital power amplifier chips with microprocessors (such as DSPs), access to the storage device includes: peripheral access to the storage device and microprocessor access to the storage device. In this application, access requests to the storage space of the storage device are summarized into four types: write requests sent by peripherals; read requests sent by peripherals; read requests sent by the microprocessor; and write requests sent by the microprocessor. The peripheral sending the write request and the peripheral sending the read request may be the same peripheral or different peripherals. Therefore, in this application, access requests to the storage space of the storage device are divided into: a first write request SRC_WRITE sent by the source; a first read request DSP_READ sent by the microprocessor; a second write request DSP_WRITE sent by the microprocessor; and a second read request DST_READ sent by the target. Figure 2 As shown.

[0035] See Figure 1 , Figure 1 This is a flowchart illustrating a data processing method disclosed in this application. The data processing method disclosed in this application is executed by the storage controller of a storage device, and includes:

[0036] S101: Respond to the first write request sent by the source and write data to M storage blocks sequentially.

[0037] The source device sends a first write request to the storage controller, requesting that data be written to the storage device. The storage controller responds to the first write request by writing the data from the source device into the storage space of the storage device. In other words, the storage controller responds to the first write request by sequentially writing the data from the source device into each storage block.

[0038] Optionally, the storage controller writes the data to be written to the source starting from the low address of the storage device.

[0039] S102: During the process of writing data to the first storage block in response to the first write request sent by the source, the data stored in the second storage block is sent to the microprocessor in response to the first read request sent by the microprocessor, and the data processed by the microprocessor is written to the second storage block in response to the second write request sent by the microprocessor.

[0040] The first storage block is any one of the M storage blocks, and the second storage block is the storage block that completes the data writing from the source end.

[0041] In other words, the first write request sent by the source is for a storage block that is full of data from the source. The storage controller responds to the first read request sent by the microprocessor, reading data starting from the beginning address of the storage block containing the source data, and then transmits the read data to the microprocessor. The microprocessor processes the acquired data and, after completing the processing, sends a second write request to the storage controller. The storage controller responds to the second write request sent by the microprocessor, writing back the data to be written by the microprocessor (the data processed by the microprocessor) to the aforementioned second storage block.

[0042] S103: During the process of writing data to the first storage block in response to the first write request from the source end, the data stored in the third storage block is sent to the target end in response to the second read request from the target end.

[0043] The third storage block is the storage block that completes the data writing to the microprocessor.

[0044] In other words, the second read request sent by the target is for a storage block filled with data processed by the microprocessor. The memory responds to the second read request by reading data from the beginning address of the storage block containing the microprocessor-processed data and then transmits the read data to the target.

[0045] It is understandable that the source sending the first write request to the storage controller, the microprocessor sending the first read request / second write request to the storage controller, and the target sending the second read request to the storage controller are all in parallel. That is, the storage controller may receive the first write request from the source, the first read request / second write request from the microprocessor, and the second read request from the target at the same time, and the storage controller will respond to each of the received requests separately.

[0046] It should be noted that the addresses requested for reading / writing in the aforementioned requests are different. The result is that while the storage controller is writing the data to be written to the source end to the first storage block, it performs the following in parallel: reading data from the second storage block (the storage block that has completed the data writing to the source end), transmitting the read data to the microprocessor, processing the data by the microprocessor, and then writing the processed data back to the second storage block; reading data from the third storage block (the storage block that has completed the data writing to the microprocessor), and transmitting the read data to the target end.

[0047] The data processing method disclosed in this application divides the storage space of a storage device into M (greater than or equal to 3) storage blocks, each storage block comprising multiple storage units with contiguous addresses. The storage controller responds to a first write request sent by the source end and sequentially writes data to each storage block. While writing data to the first storage block in response to the first write request sent by the source end, the storage controller also responds to a first read request and a second write request sent by the microprocessor, performing read operations (reading data stored in the second storage block and processing the data by the microprocessor) and write operations (writing the processed data back to the second storage block) on the second storage block (the storage block where the microprocessor has completed the data writing) and responding to a second read request sent by the target end, performing a read operation on the third storage block (the storage block where the microprocessor has completed the data writing). As can be seen, based on the data processing method disclosed in this application, by dividing the storage space of the storage device into at least three storage blocks, the storage controller can respond in parallel to the first write request sent by the source end, the first read request / second write request sent by the microprocessor, and the second read request sent by the target end. This enables the controller to perform read and write operations on the second storage block in response to the first write request sent by the source end while performing a write operation on the first storage block, and to perform a read operation on the third storage block in response to the first read request and the second write request sent by the microprocessor, thereby greatly improving the data processing efficiency.

[0048] In another embodiment of this application, the storage controller generates an interrupt request and outputs the interrupt request when the first storage block is filled with data in response to the first write request sent by the source, so as to trigger the microprocessor to send a first read request for the second storage block.

[0049] Understandably, based on the interrupt mechanism, it can be guaranteed that the first read request sent by the microprocessor is for a storage block that has already completed writing data to the source, and not for a storage block that is currently writing data to the source.

[0050] Of course, other solutions can also be used to achieve this goal. For example: the storage controller responds to the first write request sent by the source end, and filling a storage block with data from the source end needs to be completed within a preset time period. It responds to the first read request and the second write request sent by the microprocessor, reads data from a storage block, processes the data, and then writes the processed data back to the storage block, all within the aforementioned preset time period. It also responds to the second read request sent by the target end, and reads data from a storage block, all within the aforementioned preset time period. Furthermore, the starting address contained in the first write request sent by the source end, the starting address contained in the first read request sent by the microprocessor, and the starting address contained in the first read request sent by the target end differ by a*N, where N is the number of storage units contained in each storage block, and a is an integer greater than or equal to 2.

[0051] In other words, the storage controller's responses to the first write request from the source to complete a read operation on a storage block, the first read request and the second write request from the microprocessor to complete a read / write operation on a storage block, and the second read request from the target to complete a write operation on a storage block, all need to be completed within a preset time period. Furthermore, considering that the starting addresses of the first write request from the source, the first read request from the microprocessor, and the second read request from the target differ by a*N, it can be guaranteed that the first read request from the microprocessor is for a storage block for which data has already been written by the source, and the second read request from the target is for a storage block for which data has already been written by the microprocessor.

[0052] As a preferred embodiment, the second storage block is the storage block whose access order is one position later than the first storage block out of the M storage blocks, and the third storage block is the storage block whose access order is one position later than the second storage block out of the M storage blocks. Based on this embodiment, the target end can obtain the processed data as quickly as possible after data processing is started.

[0053] Here Figure 3 The following explanation uses the storage space partitioning method shown as an example.

[0054] Please see Figure 4 , Figure 4 This is a schematic diagram illustrating the principle of the data processing process, in which the microprocessor uses a DSP.

[0055] Initially, the storage space of the storage device is empty and no data is stored.

[0056] After the initial moment, the source sends a first write request SRC_WRITE. The storage controller responds to the first write request SRC_WRITE, writing the data to be written by the source to the storage space. In this example, the writing starts from the storage cell at address 0, meaning the first write request SRC_WRITE sent by the source contains a starting address of 0. It can be understood that subsequent first write requests SRC_WRITE sent by the source contain a starting address equal to the ending address of the previous first write request SRC_WRITE plus 1.

[0057] When storage block BLK0 is full, the storage controller generates and outputs an interrupt request data_proc_int.

[0058] The DSP receives an interrupt request `data_proc_int` and sends a first read request `DSP_READ` to read data stored in memory block BLK0. The initial `DSP_READ` request sent by the DSP starts at address 0. Subsequent `DSP_READ` requests will start at the address of the previous `DSP_READ` request plus 1. The memory controller responds to the `DSP_READ` request, reads the data indicated by the `DSP_READ` request, and transmits the read data back to the DSP.

[0059] The DSP processes the data read from memory block BLK0 and sends a second write request, DSP_WRITE, after processing. The initial DSP_WRITE request starts at address 0. Subsequent DSP_WRITE requests start at address 1, corresponding to the previous DSP_WRITE request. The memory controller responds to the DSP's DSP_WRITE request by writing the processed data back to memory block BLK0.

[0060] As can be seen, while the storage controller is performing read and write operations on storage block BLK0 in response to the first read request DSP_READ and the second write request DSP_WRITE sent by the DSP, it is also responding to the first write request SRC_WRITE sent by the source to write the data to be written from the source to storage block BLK1. It should be noted that the DSP needs to complete the operations of reading data from storage block BLK0, processing the read data, and writing the processed data back to storage block BLK0 before storage block BLK1 is full.

[0061] When storage block BLK1 is full, the storage controller generates and outputs an interrupt request data_proc_int.

[0062] The DSP receives an interrupt request `data_proc_int` and sends a first read request `DSP_READ` to read data stored in memory block BLK1. The first write request `DSP_READ` sent by the DSP contains a start address that is the end address of the previous first read request `DSP_READ` plus 1. The memory controller responds to the first read request `DSP_READ`, reads the data indicated by `DSP_READ`, and transmits the read data back to the DSP.

[0063] The DSP processes the data read from storage block BLK1 and sends a second write request, DSP_WRITE, after processing. The second write request DSP_WRITE sent by the DSP contains a starting address equal to the ending address of the previous second write request DSP_WRITE plus 1. The storage controller responds to the second write request DSP_WRITE sent by the DSP and writes the data processed by the DSP back to storage block BLK1.

[0064] As can be seen, while the storage controller is performing read and write operations on storage block BLK1 in response to the first read request DSP_READ and the second write request DSP_WRITE sent by the DSP, it is also responding to the first write request SRC_WRITE sent by the source end to write the data to be written from the source end to storage block BLK2. Furthermore, the storage controller is also responding to the second read request DST_READ sent by the target end to read the data stored in storage block BLK0 (which is the data processed by the DSP) and transmit the read data to the target end. It should be noted that the DSP must complete the operations of reading data from storage block BLK1, processing the read data, and writing the processed data back to storage block BLK1 before storage block BLK2 is full.

[0065] The initial second read request (DST_READ) sent by the target end begins at address 0. It can be understood that subsequent second read requests (DST_READ) sent by the target end will begin at address 1, corresponding to the end address of the previous second read request (DST_READ).

[0066] Similarly, while the storage controller responds to the first write request SRC_WRITE sent by the source end to write the data to be written by the source end to storage block BLK3, the storage controller also responds to the first read request DSP_READ and the second write request DSP_WRITE sent by the DSP to perform read and write operations on storage block BLK2, and responds to the second read request DST_READ sent by the target end to read the data in storage block BLK1 and transmit the read data to the target end.

[0067] By setting the initial addresses of the first write request, the first read request, the second write request, and the second read request, the storage controller can perform write operations on the (i+1)th storage block in response to the first write request sent by the source, read and write operations on the ith storage block in response to the first read request and the second write request sent by the DSP, and read operations on the (i-1)th storage block in response to the second read request sent by the target. Here, i refers to the access order.

[0068] In another embodiment of this application, the storage controller includes an arbitrator.

[0069] Correspondingly, the data processing method also includes: an arbitrator determining whether an access conflict has occurred in the received request; and if an access conflict has occurred, determining the request with access rights among the multiple requests that have encountered the access conflict according to a preset priority.

[0070] It should be noted that an access conflict occurs when multiple requests received by the storage controller request access to the same or partially overlapping storage space.

[0071] In this application, after the source writes audio data to the memory, the microprocessor reads the audio data from the memory, processes the read audio data, and then writes the processed audio data back to the memory. The target then reads the processed audio data from the memory. Based on this application scenario, the priorities of each request are set as follows: the priorities of the second write request, the first read request, the first write request, and the second read request decrease sequentially. That is, the priority of the second write request is higher than the priority of the first read request, the priority of the first read request is higher than the priority of the first write request, and the priority of the first write request is higher than the priority of the second read request.

[0072] In the embodiments disclosed above in this application, the storage controller is provided with an arbitrator, which determines whether the first write request, the first read request, the second write request, and the second read request sent by the source end, the microprocessor, and the target end have access conflicts. Furthermore, when it is determined that an access conflict has occurred, the arbitrator determines the request with access rights among the multiple requests that have access conflicts according to a preset priority, so as to avoid data errors.

[0073] This application also provides a storage device.

[0074] The storage device includes a storage medium and a storage controller. The storage space formed by the storage medium is divided into M storage blocks, each storage block containing multiple storage units with contiguous addresses, where M is an integer greater than or equal to 3.

[0075] The storage controller is configured to: respond to a first write request sent by the source end, sequentially write data to M storage blocks; while writing data to the first storage block in response to the first write request sent by the source end, respond to a first read request sent by the microprocessor, send data stored in the second storage block to the microprocessor, and respond to a second write request sent by the microprocessor, write the data processed by the microprocessor to the second storage block, wherein the first storage block is any one of the M storage blocks, and the second storage block is the storage block that has completed the data writing from the source end; while writing data to the first storage block in response to the first write request sent by the source end, respond to a second read request sent by the target end, send data stored in the third storage block to the target end, wherein the third storage block is the storage block that has completed the data writing from the microprocessor. In another embodiment, the storage device further includes an arbitrator.

[0076] The arbitrator is used to: determine whether a received request has an access conflict; and if an access conflict is determined, to identify the request with access rights among the multiple requests that have an access conflict based on a preset priority.

[0077] In the above embodiments of the storage device, the storage controller is further configured to: generate an interrupt request and output the interrupt request when the first storage block is filled with data in response to a first write request sent by the source, so as to trigger the microprocessor to send a first read request for the second storage block.

[0078] Preferably, the second storage block is the storage block whose access order is delayed by 1 bit compared to the first storage block among the M storage blocks.

[0079] Preferably, the third storage block is the storage block whose access order is delayed by 1 bit compared to the second storage block among the M storage blocks.

[0080] In the above scheme, the second storage block is configured as the storage block whose access order is delayed by 1 position compared to the first storage block among the M storage blocks, and the third storage block is configured as the storage block whose access order is delayed by 1 position compared to the second storage block among the M storage blocks. When data processing is started, the target end can obtain the processed data as soon as possible.

[0081] This application also discloses a digital power amplifier chip, which includes any of the storage devices disclosed in this application.

[0082] See Figure 5 , Figure 5 This is a schematic diagram of the structure of a digital power amplifier chip disclosed in this application.

[0083] Figure 5 The digital power amplifier chip shown includes two data links: a downlink consisting of an HSRC (audio rate conversion unit), a downlink buffer rx_fifo, a DSP, and a DAC (digital-to-analog converter); and an uplink consisting of an HSRC_TX, an uplink buffer tx_fifo, and a DSP. Both the uplink buffer tx_fifo and the downlink buffer rx_fifo use the storage devices disclosed above in this application.

[0084] in:

[0085] In the downlink, the HSRC module acts as the source and the DAC as the target. The downlink buffer rx_fifo responds to the first write request SRC_WRITE sent by the HSRC module, the first read request DSP_READ and the second write request DSP_WRITE sent by the DSP, and the second read request DST_READ sent by the DAC, and executes the data processing method disclosed in this application.

[0086] In the uplink, the HSRC_TX module acts as both the source and the destination. The uplink buffer tx_fifo responds to the first write request SRC_WRITE and the second read request DST_READ sent by the HSRC_TX module, as well as the first read request DSP_READ and the second write request DSP_WRITE sent by the DSP, and executes the data processing method disclosed in the above application.

[0087] exist Figure 5 In the digital amplifier chip shown, digital audio data is input to the chip via the I2S interface. The I2S (Inter-IC Sound) bus, also known as the integrated circuit built-in audio bus, is a bus standard for audio data transmission between digital audio devices. The I2S interface, as a general term for data receiving and transmitting modules, transmits digital audio data received from other digital audio devices to the HSRC module, where it performs subsequent digital audio data processing.

[0088] The HSRC module is used to perform sample rate conversion on digital audio data input via the I2S interface, converting digital audio data with different sample rates to a uniform sample rate, such as converting it to a 48kHz signal. After performing sample rate conversion, the HSRC module sends a first write request to the storage controller of the downlink buffer rx_fifo to write the processed digital audio data into the downlink buffer rx_fifo. When the storage block in the downlink buffer rx_fifo is full, an interrupt request is generated.

[0089] In response to the interrupt request, the DSP sends a first read request to read the digital audio data stored in the downlink buffer rx_fifo. After processing the digital audio data, it sends a second write request to write the processed digital audio data back to the downlink buffer rx_fifo. The DAC module sends a second read request to read the DSP-processed digital audio data from the downlink buffer rx_fifo, performs digital-to-analog conversion on the digital audio data, and passes the converted analog audio signal to the amplifier, which amplifies the analog audio signal.

[0090] The HSRC_TX module (TX: short for transmitter) converts digital audio data to the standard rate of the I2S interface, and the converted digital audio data is output via the I2S interface. The HSRC_TX module also receives multiplexed signals (MUX) required by the digital amplifier chip, such as debug signals, current values, and voltage values, and sends these multiplexed signals to the host computer via the I2S interface. The current and voltage signals (IVsense data) required for the speaker protection of the digital amplifier chip are also sent to the host computer via the I2S interface.

[0091] It should be noted that the technical features described in the various embodiments of this specification can be substituted for or combined with each other. Each embodiment focuses on describing the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to mutually. The steps in the methods of the various embodiments of this application can be adjusted, merged, and deleted according to actual needs. The modules and sub-modules in the devices and equipment of the various embodiments of this application can be merged, divided, and deleted according to actual needs.

[0092] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The technical features in each embodiment can be arranged and combined to form new embodiments. For the storage device and digital power amplifier chip disclosed in the embodiments, since they correspond to the data processing methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0094] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing method, characterized in that, A storage controller applied to a storage device, wherein the storage space of the storage device is divided into M storage blocks, each storage block containing multiple storage units with contiguous addresses, and M is an integer greater than or equal to 3, the method comprising: In response to the first write request sent by the source, data is written sequentially to the M storage blocks; During the process of writing data to the first storage block in response to the first write request sent by the source, the data stored in the second storage block is sent to the microprocessor in response to the first read request sent by the microprocessor, and the data processed by the microprocessor is written to the second storage block in response to the second write request sent by the microprocessor. The first storage block is any one of the M storage blocks, and the second storage block is the storage block that completes the data writing from the source. During the process of writing data to the first storage block in response to a first write request sent by the source end, data stored in a third storage block is sent to the target end in response to a second read request sent by the target end. The third storage block is the storage block that completes the data writing to the microprocessor.

2. The data processing method according to claim 1, characterized in that, Also includes: When the first storage block is filled with data in response to the first write request sent by the source, an interrupt request is generated and output to trigger the microprocessor to send a first read request for the second storage block.

3. The data processing method according to claim 1 or 2, characterized in that, The storage controller includes an arbitrator; the data processing method further includes: The arbitrator determines whether an access conflict has occurred upon receiving a request. If an access conflict is determined, it identifies the request with access permission among the multiple requests that have an access conflict based on a preset priority.

4. The data processing method according to claim 3, characterized in that, The priority of the second write request, the first read request, the first write request, and the second read request decreases in that order.

5. The data processing method according to claim 1, characterized in that, The second storage block is the storage block whose access order is delayed by one position compared to the first storage block among the M storage blocks.

6. The data processing method according to claim 1, characterized in that, The third storage block is the storage block whose access order is one position later than that of the second storage block among the M storage blocks.

7. A storage device, characterized in that, It includes a storage medium and a storage controller; the storage space formed by the storage medium is divided into M storage blocks, each storage block contains multiple storage units with consecutive addresses, where M is an integer greater than or equal to 3; The storage controller is configured to: respond to a first write request sent by a source end, sequentially write data to the M storage blocks; while writing data to a first storage block in response to the first write request sent by the source end, respond to a first read request sent by a microprocessor, send data stored in a second storage block to the microprocessor, and respond to a second write request sent by the microprocessor, write the data processed by the microprocessor into the second storage block, wherein the first storage block is any one of the M storage blocks, and the second storage block is the storage block that completes the data writing from the source end; while writing data to the first storage block in response to the first write request sent by the source end, respond to a second read request sent by a target end, send data stored in a third storage block to the target end, wherein the third storage block is the storage block that completes the data writing from the microprocessor.

8. The storage device according to claim 7, characterized in that, It also includes an arbitrator; The arbitrator is used to: determine whether a received request has an access conflict; and if an access conflict is determined, determine the request with access permission among the multiple requests that have an access conflict according to a preset priority.

9. A digital power amplifier chip, characterized in that, Includes the storage device as described in claim 7 or 8.

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