Ejection driver, substrate processing apparatus and method

Abstract

The present invention provides a jet driver capable of being used for various types of heads with minimal changes. The jet driver includes an image board that receives original image data and converts the original image data into a form suitable for the type of head used to thereby generate image data, and an interface board that is physically separated from the image board and receives the image data and transmits the image data to a plurality of heads through a plurality of channels.

Description

TECHNICAL FIELD

[0001] The present invention relates to a jet drive, a substrate processing apparatus, and a method. BACKGROUND

[0002] When manufacturing a display device, an inkjet apparatus can be used. A jet drive of the inkjet apparatus is used to drive a head to jet a chemical or to pattern on a glass substrate.

[0003] On the other hand, depending on a chemical used by the inkjet apparatus or a precision required, various types of heads can be used. However, whenever the head is replaced, the jet drive for driving the head also needs to be changed. To make such a change, a great amount of time and resources are required. SUMMARY

[0004] The present invention relates to a jet drive, a substrate processing apparatus, and a method.

[0005] The present invention relates to a jet drive, a substrate processing apparatus, and a method.

[0006] The present invention relates to a jet drive, a substrate processing apparatus, and a method.

[0007] The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned herein will be clearly understood by persons skilled in the art from the following description.

[0008] An aspect of the jet drive of the present invention for solving the above-mentioned technical problems includes an image board receiving original image data and converting the original image data into a form suitable for a type of a head used to thereby generate image data; and an interface board physically separated from the image board and receiving the image data and transmitting the image data to a plurality of heads through a plurality of channels.

[0009] An aspect of the substrate processing apparatus of the present invention for solving another technical problem described above includes a pattern computer providing original image data and setting data, and a jet driver controlling a plurality of heads based on the original image data and the setting data, wherein the jet driver includes an image board and an interface board physically separated from each other, the image board includes an FPGA (Field Programmable Gate Array) that converts the original image data into a form suitable for a type of the heads used to generate image data based on the original image data, and the interface board includes a plurality of differential line transmitters for communication with the plurality of heads, an image controller that receives the image data and provides the image data to the plurality of differential line transmitters, a heater controller that provides a heater control signal for controlling a heater provided in the head to the plurality of differential line transmitters, and a voltage controller that provides a voltage control signal for specifying a voltage level to be used by the plurality of heads to the plurality of differential line transmitters.

[0010] An aspect of the substrate processing method of the present invention for solving still another technical problem described above includes the steps of providing a jet driver including an image board and an interface board physically separated from each other, the image board including an FPGA; the image board receiving first original image data and converting the first original image data into a form suitable for a first type of first heads to generate first image data, and the interface board receiving the first image data and transmitting the first image data to a plurality of the first heads through a plurality of channels; replacing the plurality of first heads with a plurality of second heads, and the second heads being a second type different from the first type; reprogramming the FPGA of the image board to be suitable for the second type; and the image board receiving second original image data and converting the second original image data into a form suitable for the second heads of the second type to generate second image data, and the interface board receiving the second image data and transmitting the second image data to a plurality of the second heads through a plurality of the channels.

[0011] Particulars of other embodiments are included in the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram for explaining a jet driver according to some embodiments of the present invention.

[0013] Figure 2 is a block diagram for explaining Figure 1 an image board of

[0014] Figure 3 is a block diagram for explaining Figure 1a block diagram of an interface board.

[0015] Figure 4 is a block diagram of an exemplary structure of a head. Figure 1

[0016] Figure 5 and Figure 6 is a diagram for explaining a substrate processing apparatus according to some embodiments of the present application.

[0017] Figure 7 is a block diagram of a spray driver according to another embodiment of the present application.

[0018] Figure 8 is a flowchart for explaining a substrate processing method according to some embodiments of the present application.

[0019] Explanation of Reference Numerals

[0020] 10: Spray driver 100: Image board

[0021] 110: Processor 120: FPGA

[0022] 200: Interface board 210: Image controller

[0023] 220: Voltage controller 230: Heater controller DETAILED DESCRIPTION

[0024] Hereinafter, preferred embodiments of the present application will be described in detail with reference to the accompanying drawings. Advantages and features of the present application and methods of achieving the advantages and features will become apparent by referring to the following detailed description of the embodiments taken in conjunction with the accompanying drawings, which Figure 1 illustrate the embodiments. However, the present application is not limited to the disclosed embodiments but can be implemented in various forms, and the embodiments are provided only to completely disclose the present application and to completely inform the scope of the present application to those skilled in the art. Throughout the specification, the same reference numerals refer to the same components.

[0025] ​To easily describe a relative relationship between one element or constituent and another element or constituent as shown in the drawings, spatial relative terms "below", "beneath", "lower", "above", "upper" and the like can be used. It will be understood that the spatial relative terms are terms of convenience and are not necessarily limited to the positions of the elements shown in the drawings. Accordingly, the exemplary term "below" can include both the below and above directions. Elements can also be oriented in other directions, and the spatial relative terms can be interpreted accordingly.

[0026] Although the terms "first", "second", and the like are used to describe various elements, constituents, and / or portions, the elements, constituents, and / or portions are obviously not limited by these terms. These terms are used only to distinguish one element, constituent, and / or portion from another element, constituent, and / or portion. Therefore, a first element, a first constituent, or a first portion mentioned below can obviously be a second element, a second constituent, or a second portion within the technical idea of the present application.

[0027] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. In describing the embodiments with reference to the drawings, the same or corresponding constituents are given the same reference numerals regardless of the drawings, and repetitive explanations thereof will be omitted.

[0028] Figure 1 is a block diagram for explaining a head according to some embodiments of the present application. Figure 2 is a block diagram for explaining Figure 1 an image board. Figure 3 is a block diagram for explaining Figure 1 an interface board. Figure 4 is a block diagram for explaining Figure 1 an exemplary structure of the head shown in

[0029] First, referring to Figure 1 a head 10 according to some embodiments of the present application includes an image board 100 and an interface board 200.

[0030] The image board 100 receives setting data SD and raw image data RID.

[0031] The setting data SD can be information related to basic settings required for the operation of the heads H1 to H8. For example, the setting data SD can include information on a waveform of a voltage used to control a piezo element provided inside the heads H1 to H8 (e.g., a rising time, a falling time, a maintenance time of a high level, a maintenance time of a low level, etc.), information on a voltage level used (e.g., 3V, 5V, 10V, 15V, etc.), a target temperature that the heads H1 to H8 need to maintain, etc.

[0032] The image board 100 generates a first setting signal SD1 for controlling the temperature of the heads H1 to H8 and a second setting signal SD2 for controlling a voltage to be used by the heads H1 to H8, using the setting data SD.

[0033] The original image data RID can be information related to an image that the heads H1 to H8 need to eject onto a substrate. That is, it can be information on a form (e.g., a quadrangle, a triangle, a circle, a zigzag, etc.) in which the heads H1 to H8 need to eject a chemical liquid onto a substrate.

[0034] The image board 100 receives the original image data RID and converts the original image data RID into a form suitable for the type of the heads used, thereby generating image data ID. As to the conversion into a form "suitable for the type of the heads", the interface can be different depending on the maker, or even if it is the same maker, depending on the type of the heads. That is, since the interface is not standardized, the transfer sequence can be different depending on the maker / type of the heads. Therefore, the image board 100 generates the image data ID in a form suitable for the maker / type of the heads (e.g., a transfer sequence determined according to the maker of the heads).

[0035] Here, referring to Figure 2 , the image board 100 includes an input terminal that receives the setting data SD and the original image data RID and an output terminal that outputs the first setting signal SD1, the second setting signal SD2, and the image data ID. In addition, the image board 100 includes a processor 110 and an FPGA (Field Programmable Gate Array) 120.

[0036] As described above, the processor 110 can generate and provide the first setting signal SD1 and the second setting signal SD2 using the setting data SD. In addition, the processor 110 can receive the original image data RID and the setting data SD from the pattern computer 60 (refer to Figure 5 ) and the operation computer 50 (refer to Figure 5) and the encoder manager 52 (refer to Figure 5 ) and the like.

[0037] The FPGA 120 is a semiconductor element including a designable logic element and / or a programmable internal circuit. The FPGA 120 can be reprogrammed by a user (or a consumer, a designer) in the field even after manufacturing. Through such field programming, the FPGA 120 can perform various logic functions. Thus, when the head is replaced / changed, the user can reprogram the FPGA 120 according to the type of the replaced head (i.e., in a manner capable of performing operations suitable for the replaced head). The FPGA 120 converts the raw image data RID into a form suitable for the type of the replaced head, thereby generating the image data ID. Thus, even in the case of replacement / change of the head, since the FPGA 120 can be reprogrammed, there is no need to change the image board 100.

[0038] Referring again to Figure 1 , the interface board 200 performs an interface operation between the image board 100 and the plurality of heads H1 to H8.

[0039] For example, the interface board 200 receives the first setting signal SD1, the second setting signal SD2, the image data ID, and the like from the image board 100, and provides the first setting signal SD1, the second setting signal SD2, the image data ID, and the like to the plurality of heads H1 to H8. In addition, the interface board 200 can receive state information of the heads H1 to H8 (for example, temperature information of the heads H1 to H8) from the plurality of heads H1 to H8, and can control the heads H1 to H8 in response to the state information or provide the state information to the image board 100. Such state information of the heads H1 to H8 can be transmitted to the operation computer 50 (refer to Figure 5 ) through the image board 100.

[0040] In addition, the image board 100 and the interface board 200 are physically separated from each other. The image board 100 and the interface board 200 can be connected by a board to board connector and communicate with each other through the board to board connector.

[0041] Here, referring to Figure 3 , the interface board 200 can include an image controller 210, a voltage controller 220, a heater controller 230, a plurality of differential line transmitters DLT1 to DLT8.

[0042] The image controller 210 transmits the image data ID provided by the FPGA 120 to the plurality of heads H1 to H8 through a plurality of channels. In the drawing, only 8 channels are exemplarily shown, but it is not limited thereto. The number of channels can be 2, 4, 16, 64, etc.

[0043] The transmitted image data ID is converted into a form of a differential signal by the plurality of differential line transmitters DLT1 to DLT8 and transmitted to the plurality of heads H1 to H8. The reason for conversion into a differential signal for transmission is to minimize the influence of interference that can occur in the process of transmission from the jet driver 10 to the plurality of heads H1 to H8.

[0044] In addition, the heater controller 230 receives the first set signal SD1 and provides a heater control signal HCS for controlling the heaters 320 (refer to Figure 4 ) provided within the heads H1 to H8 to enable the heads H1 to H8 to reach a target temperature. As shown in the drawing, the heater control signal HCS is transmitted to the plurality of heads H1 to H8 through a plurality of channels.

[0045] The voltage controller 220 can receive the second set signal SD2 and can provide a voltage control signal VCS for specifying a plurality of voltage levels to be used by the heads H1 to H8. As shown in the drawing, the voltage control signal VCS is transmitted to the plurality of heads H1 to H8 through a plurality of channels.

[0046] On the other hand, the plurality of differential line transmitters DLT1 to DLT8 provide the image data ID, the heater control signal HCS, and the voltage control signal VCS in the form of a differential signal. Accordingly, the plurality of line receivers receive the differential signal from the corresponding differential line transmitters DLT1 to DLT8 and convert the differential signal into a form of a single end signal and provide it to the corresponding heads H1 to H8.

[0047] The heater controller 230, the voltage controller 220, and the image controller 210 can be implemented as one or more MCUs (Micro Control Units).

[0048] Here, referring to Figure 4 , the head H1 can include a logic chip 310, a heater 320, a control voltage generator 330, an amplifier 340, a plurality of piezoelectric elements P1 to Pn (n is a natural number), a plurality of nozzles N1 to Nn (n is a natural number).

[0049] The logic chip 310 can receive the image data ID, the heater control signal HCS, and the voltage control signal VCS and control a plurality of functional blocks (for example, 320, 330, P1 to Pn, etc.) within the head H1.

[0050] The logic chip 310 can cause the temperature of the heater 320 to reach a target temperature according to an indication of the heater control signal HCS. According to the temperature of the heater 320, the viscosity of the medicine liquid changes. If the viscosity of the medicine liquid changes, even if a preset voltage is applied to the piezoelectric elements P1 to Pn, a preset amount of medicine liquid is not ejected. Therefore, the temperature of the heater 320 needs to be continuously managed.

[0051] The logic chip 310 controls the control voltage generator 330 according to a plurality of voltage levels and a voltage waveform designated by the voltage control signal VCS according to a timing operation.

[0052] An amplifier 340 is provided inside the control voltage generator 330. The amplifier 340 can increase a low-level voltage to a preset voltage level even if a high-level voltage is not received through a power supply line.

[0053] The plurality of piezoelectric elements P1 to Pn receive a control voltage from the control voltage generator 330 and cause the nozzles N1 to Nn to eject the medicine liquid. Although not shown separately, the nozzles N1 to Nn are connected to a reservoir storing the medicine liquid to receive the medicine liquid from the reservoir and eject the medicine liquid according to the control voltage.

[0054] In summary, the ejection driver 10 according to some embodiments of the present application includes a physically separated image board 100 and an interface board 200. Even if the heads H1 to H8 to be used are changed / replaced, the FPGA 120 using the image board 100 can be reprogrammed (refer to Figure 2 ). Therefore, it is not necessary to replace the entire ejection driver 10. If necessary, only the interface board 200 can be replaced, or the interface board 200 can be modified with a minimum amount and reused.

[0055] Figure 5 and Figure 6 are diagrams for explaining a substrate processing apparatus according to some embodiments of the present application. Features different from those explained with reference to Figures 1 to 4 are mainly explained.

[0056] First, with reference to Figure 5 and Figure 6 , the substrate processing apparatus can include the ejection driver 10, the operation computer 50, the pattern computer 60, and the encoder manager 52.

[0057] The pattern computer 60 provides the ejection driver 10 with setting data SD and raw image data RID. As described above, the setting data SD can be information related to basic settings required for the operation of the heads H1 to H8, and can be information about a voltage waveform, a voltage level, a target temperature that the heads H1 to H8 need to maintain, etc. The raw image data RID is information related to an image that the heads H1 to H8 need to eject onto a substrate.

[0058] The operation computer 50 can communicate with Figure 6 the motion controller 55, and can control Figure 6 the equipment shown in FIG. 1 through the motion controller 55.

[0059] The equipment includes a process area PT and a maintenance area MT. A gantry 410 is disposed across the process area PT and the maintenance area MT. A plurality of heads 420 are provided on the gantry 410, and the heads 420 can move along the extension direction (left-right direction in the figure) of the gantry 410. That is, the heads 420 can eject chemical liquid in both the process area PT and the maintenance area MT.

[0060] A stage 430 is positioned on the process area PT, and the stage 430 can move along the length direction (up-down direction in the figure) of the process area PT. A glass substrate is placed on the stage 430, and during the stage 430 is moved in the up-down direction under the gantry 410 multiple times, the plurality of heads 420 eject chemical liquid onto the glass substrate.

[0061] The maintenance area MT is an area in which the state of the maintenance heads H1 to H8 or the inspection heads H1 to H8 is inspected. Although not shown otherwise, a test film that rotates in a roll-to-roll manner is disposed in the maintenance area MT, and the plurality of heads 420 eject chemical liquid onto the test film. Thereby, the amount, density, etc. of the chemical liquid ejected from each nozzle of the heads 420 can be inspected, or whether the nozzles are clogged, whether an amount much larger than a preset amount is ejected, etc. can be inspected.

[0062] Here, referring to Figure 5 , the encoder manager 52 provides a trigger signal to the plurality of ejection drivers 10 using an encoder signal that indicates the position of the stage 430. As described above, during the stage 430 is moved up and down, the heads H1 to H8 eject chemical liquid. Therefore, only if the accurate position of the stage 430 is known, the heads H1 to H8 can eject chemical liquid to the accurate position. The ejection drivers 10 control the chemical liquid ejection start point of the heads H1 to H8 based on such a trigger signal.

[0063] The operation computer 50 can receive the trigger signal from the encoder manager 52, and compare the position of the stage 430 with the trigger signal to check whether the trigger signal is abnormal.

[0064] On the other hand, the jet drive 10 (i.e., the image board 100) is connected with the operation computer 50 through a real-time Ethernet (EtherCAT) as an industrial network. The image board 100 provides the state of the jet drive 10 to the operation computer 50 to enable the operation computer 50 to monitor the jet drive 10. Since the jet drive 10 is connected with the operation computer 50 through the real-time Ethernet, the operation computer 50 can quickly know the state of the jet drive 10 in real time.

[0065] Further, the operation computer 50 can receive the state information of the heads H1 to H8 through the interface board 200 and the image board 100 to grasp the states of the heads H1 to H8. According to the grasped states of the heads H1 to H8, the operation computer 50 can request the pattern computer 60 to change the setting data SD. For example, if the operation computer 50 considers that the actual temperature of the heads H1 to H8 is high, it can request the pattern computer 60 to further lower the target temperature. The pattern computer 60 can modify the target temperature included in the setting data SD according to the request of the operation computer 50.

[0066] Further, the jet drive 10 and the encoder manager 52 can also be connected through the real-time Ethernet. The encoder manager 52 and the operation computer 50 can also be connected through the real-time Ethernet. The operation computer 50 can quickly check the trigger signal provided by the encoder manager 52 in real time. Thus, the operation computer 50 can function as a monitoring function to pre-sense the state of non-ejection, pattern accumulation, etc. that can occur in the mass production process.

[0067] Figure 7 is a block diagram for explaining a jet drive according to another embodiment of the present application. Hereinafter, the description of the contents substantially the same as those explained with reference to Figure 3 will be omitted for convenience of explanation.

[0068] Reference Figure 7 The interface board 200 of the jet drive 10 includes an image controller 210, a voltage controller 220, a heater controller 230, a plurality of differential line transmitters, etc.

[0069] In particular, the voltage controller 220 can further include an amplifier 222 for generating a voltage for driving a nozzle provided at the head H1 to H8, and the voltage controller 220 can determine whether to use the amplifier 222 according to the type of the head H1 to H8.

[0070] For example, the heads H1 to H8 can be a DPH (Drive Per Head) type including the amplifier 340 (refer to FIG. 4). In this case, the voltage controller 220 can determine not to use the amplifier 222. Figure 4). The heads H1 to H8 of the DPH type are controlled by the jet driver 10 in units of heads, not in units of nozzles. In this case, the amplifiers 222 of the voltage controller 220 are not used. Even if the voltage controller 220 only provides the voltage control signal VCS and the image data ID, the control voltage generators 330 of the heads H1 to H8 can provide the control voltages to the piezoelectric elements P1 to Pn according to preset voltage levels.

[0071] On the other hand, the heads H1 to H8 can be of the DPN (Drive Per Nozzle) type which does not include amplifiers. The heads H1 to H8 of the DPN type are controlled by the jet driver 10 in units of nozzles. In this case, the amplifiers 222 of the voltage controller 220 are used. The voltage controller 220 needs to provide not only the voltage control signal VCS and the image data ID to the heads H1 to H8, but also the voltages to control the piezoelectric elements P1 to Pn having preset voltage levels to the heads H1 to H8 together.

[0072] The jet driver 10 according to some embodiments of the present application includes the image board 100 and the interface board 200 which are physically separated. Even if the heads H1 to H8 to be used are changed / replaced, the FPGA 120 using the image board 100 can be reprogrammed (refer to Figure 2 ).

[0073] Furthermore, for example, even if the heads H1 to H8 of the DPH type are changed to the heads H1 to H8 of the DPN type, only the settings of the interface board 200 can be changed and used without changing the interface board 200. That is, one interface board 200 can be applicable to both the heads H1 to H8 of the DPH type and the heads H1 to H8 of the DPN type.

[0074] Figure 8 is a flowchart for explaining a substrate processing method according to some embodiments of the present application.

[0075] Referring to Figure 8 , a jet driver 10 (S505) is provided using Figures 1 to 6 explanation. That is, the jet driver 10 can include the image board 100 and the interface board 200 which are physically separated from each other, and the image board 100 can include a FPGA (Field Programmable Gate Array).

[0076] Next, a first head of a first type is controlled using the jet driver 10 which is set in advance (S510). Specifically, the image board 100 receives first original image data, and converts the first original image data into a form suitable for the first head of the first type to generate first image data. The interface board 200 receives the first image data, and transmits the first image data to a plurality of first heads through a plurality of channels.

[0077] Next, the first head of the first type is replaced with a second head of a second type (S520) due to the type of the liquid medicine, precision, and the like. The first type and the second type are different types from each other. For example, the first type can be a DPH type, and the second type can be a DPN type.

[0078] Next, the FPGA 120 of the image board 100 is reprogrammed to be suitable for the second type (S530). Additionally, the setting of the interface board 200 can be changed. For example, whether to use the amplifier 222 within the voltage controller 220 of the interface board 200 can be changed. Alternatively, the interface board 200 can be replaced with one suitable for the second type.

[0079] Next, the second head of the second type is controlled using the reprogrammed jet driver 10 (S540). Specifically, the image board 100 receives second original image data, and converts the second original image data into a form suitable for the second head of the second type to generate second image data. Further, the interface board 200 receives the second image data, and transmits the second image data to the plurality of second heads through the plurality of channels.

[0080] The embodiments of the present application have been described above with reference to the accompanying drawings, but it will be appreciated by those skilled in the art that the present application can be implemented in other specific forms without changing the technical idea or essential characteristics thereof. Therefore, it should be understood that the above-described embodiments are exemplary in all aspects and are not restrictive.

Claims

1. A jet drive comprising: an image board that receives raw image data and converts the raw image data into image data; an interface board that is physically separated from the image board and receives the image data and transmits the image data to a plurality of heads through a plurality of channels; wherein the image board comprises an FPGA, and the FPGA is reprogrammed to convert the raw image data into a form suitable for the type of head being used to generate image data, depending on the type of head being used.

2. The ejection driver of claim 1, wherein, the interface board further comprises: a plurality of differential line transmitters for communicating with the plurality of heads.

3. The jet drive of claim 2, wherein the image data is transmitted in the form of differential signals through the differential line transmitters.

4. The jet drive of claim 1, wherein the interface board further comprises a heater controller, and the heater controller controls a heater disposed within the head to enable the head to reach a target temperature.

5. The jet drive of claim 1, wherein the interface board further comprises a voltage controller, and the voltage controller specifies a plurality of voltage levels to be used by the head.

6. The jet drive of claim 1, wherein the interface board further comprises a voltage controller, and the voltage controller further comprises an amplifier for generating a voltage for driving a nozzle disposed in the head, and the voltage controller determines whether to use the amplifier depending on the type of head.

7. The jet drive of claim 6, wherein in the case where the head is a DPN type, the amplifier is used, and in the case where the head is a DPH type, the amplifier is not used.

8. The jet drive of claim 1, wherein the image board is connected to an operation computer through real-time Ethernet, and the image board provides a status of the jet drive to the operation computer to enable the operation computer to monitor the jet drive.

9. The jet drive of claim 1, wherein the image board and the interface board are connected through a board-to-board connector.

10. A substrate processing apparatus comprising Pattern computer, provides original image data and setting data; and a jet drive that controls a plurality of heads based on the raw image data and the setting data, wherein the jet drive comprises an image board and an interface board that are physically separated from each other, the image board comprises an FPGA that is configured to be reprogrammed to convert the raw image data into a form suitable for the type of head being used to generate image data, depending on the type of head being used, and the interface board comprises: a plurality of differential line transmitters for communicating with the plurality of heads; an image controller that receives the image data and provides the image data to the plurality of differential line transmitters; a heater controller that provides a heater control signal for controlling a heater disposed within the head to the plurality of differential line transmitters; and a voltage controller that provides a voltage control signal for specifying a voltage level to be used by the plurality of heads to the plurality of differential line transmitters.

11. The substrate processing apparatus of claim 10, wherein, the image board is connected to an operation computer through a real-time Ethernet, and the image board provides a state of the jet driver to the operation computer to enable the operation computer to monitor the jet driver.

12. The substrate processing apparatus of claim 10, wherein, the image board and the interface board are connected through a board-to-board connector.

13. The substrate processing apparatus of claim 10, wherein, the voltage controller further includes an amplifier for generating a voltage for driving a nozzle provided to the head, and the voltage controller determines whether to use the amplifier according to a type of the head.

14. The substrate processing apparatus of claim 13, wherein, in a case where the head is a DPN type, the amplifier is used, and in a case where the head is a DPH type, the amplifier is not used.

15. A substrate processing method, comprising the steps of: providing a jet driver including an image board and an interface board physically separated from each other, the image board including an FPGA; the image board receiving first raw image data and converting the first raw image data into a form suitable for a first head of a first type to generate first image data, and the interface board receiving the first image data and transmitting the first image data to a plurality of the first heads through a plurality of channels; replacing the plurality of the first heads with a plurality of second heads, and the second heads being of a second type different from the first type; reprogramming the FPGA of the image board to be suitable for the second type; and the image board receiving second raw image data and converting the second raw image data into a form suitable for the second heads of the second type to generate second image data, and the interface board receiving the second image data and transmitting the second image data to a plurality of the second heads through the plurality of channels.

16. The substrate processing method of claim 15, wherein, the image board and the interface board are connected through a board-to-board connector.

17. The substrate processing method of claim 15, wherein, the interface board further includes a voltage controller, and the voltage controller further includes an amplifier for generating a voltage for driving a nozzle provided to a head including the first head and the second head, and the voltage controller determines whether to use the amplifier according to a type of the head.

18. The substrate processing method of claim 17, wherein, in a case where the head is a DPN type, the amplifier is used, and in a case where the head is a DPH type, the amplifier is not used.

Images