A voltage reduction line real-time detection circuit and method

Abstract

The application discloses a real-time detection circuit and method for a voltage reduction circuit, and relates to the technical field of power supplies.The real-time detection circuit for the voltage reduction circuit comprises a voltage reduction module, a logic control module, a voltage sampling module, a differential amplification module, a digital-analog conversion module and a storage module.The application can monitor the output voltage in a starting state in real time without damaging a mainboard PCB and without destroying the whole system, so as to timely analyze and locate the power consumption of a later-stage chip, and the output current in the starting state can be obtained through calculation based on the voltage of the monitoring sampling port position, the current size can be detected without lifting one end of the inductor, the mainboard PCB and electronic components are not damaged, and the operation is convenient;the power supply current size of a certain component or chip can be detected remotely without disassembling the machine, and the application has good operability;the application can be monitored in real time, and has good timeliness.

Description

Technical Field

[0001] This invention relates to the field of current detection technology, and in particular to a real-time detection circuit and method for step-down circuits. Background Technology

[0002] With the rapid development of server performance, servers have become more diverse and complex in structure. The power supply components of server motherboards have also become more intricate.

[0003] As we all know, the most commonly used power supply circuit in server motherboards is the step-down circuit, also known as a DC-DC regulator. This circuit steps down a high-voltage DC input to a stable low-voltage DC output, for example, stepping down 12V to 1V. In most server power supply topologies, there are generally two types: STBY power and Core power. STBY power provides voltage output even in AC mode, powering the entire board in standby mode. Core power, on the other hand, typically only provides voltage output during power-on. Core power usually supplies power to a specific component or chip, and its current is generally higher, making its status more closely monitored. Therefore, how to monitor the current of critical chips in real time is a crucial issue worth considering.

[0004] like Figure 1 As shown, taking the MPQ8633B, a common DC-DC chip on the market, as an example, after EN is enabled, there will be an LC filter after SW to convert the square wave of SW into a stable voltage output Vout.

[0005] In existing technologies, to determine the real-time current of the power supply chip (Vout), one end of inductor L1 needs to be tilted up, and the tilted end of the inductor needs to be soldered to the PAD on the PCB using a wire. Then, a current clamp is used to detect the current flowing through the wire. Therefore, existing technologies have the following drawbacks: tilting up one end of the inductor to detect the output current is cumbersome and can easily damage the motherboard; it is very difficult to monitor the output current of a specific power supply chip within the overall system; and existing technologies are generally only used when there is a problem with the equipment and you want to pinpoint the output current of a specific power supply chip, and cannot achieve real-time current monitoring or remote operation capabilities. Summary of the Invention

[0006] This invention provides a real-time detection circuit and method for step-down circuits, which can monitor the output voltage in the power-on state in real time without damaging the motherboard PCB or the entire system, so as to analyze and locate the power consumption of downstream chips in a timely manner.

[0007] To solve one or more of the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] In a first aspect, a real-time detection circuit for a step-down line is provided, comprising: a step-down module, a logic control module, a voltage sampling module, a differential amplifier module, a digital-to-analog converter module, and a storage module;

[0009] An enable signal is input to the input terminal of the buck module, and the output terminal of the buck module is connected to the input terminal of the voltage sampling module.

[0010] The logic control module includes a power supply branch and a discharge branch; the power supply branch is connected to the input terminal of the voltage sampling module, and is used to conduct and input a constant current to the voltage sampling module when the enable signal is low, and to disconnect when the enable signal is high; the discharge branch is connected to the output terminal of the voltage sampling module, and is used to conduct and discharge when the enable signal is low, and to disconnect when the enable signal is high.

[0011] The voltage sampling module has an input terminal, a ground terminal, an output terminal, a first sampling port, and a second sampling port. The input terminal and the output terminal of the voltage sampling module are connected in parallel to a branch consisting of an output inductor and a DC resistor connected in series, and a branch consisting of a first resistor and a first capacitor connected in series. The two ends of the first capacitor are respectively connected to the first sampling port and the second sampling port. The output terminal of the voltage sampling module is connected to its ground terminal and grounded through the second capacitor.

[0012] The storage module includes a first register and a second register. The first register acquires the inverted voltage of the enable signal in real time, and the second register acquires the voltage of the enable signal in real time.

[0013] The first sampling port and the second sampling port of the voltage sampling module are both connected to the differential amplifier module, and the differential amplifier module is connected to the first register and the second register of the storage module through the digital-to-analog converter module.

[0014] In this embodiment, the buck module is configured to not operate when the enable signal is low and to operate when the enable signal is high; the first register is readable and writable when the enable signal is low, and the second register is readable and writable when the enable signal is high.

[0015] When the enable signal is low, the logic control module inputs a constant current to the voltage sampling module. The differential amplifier module obtains the first voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register.

[0016] When the enable signal is high, the enable signal is stepped down by the step-down module and then input to the voltage sampling module. The differential amplifier module obtains the second voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register.

[0017] In this embodiment, the real-time detection circuit for a step-down line further includes:

[0018] A power management bus interface is connected to the storage module, and the power management bus interface can be connected to the baseboard management controller.

[0019] In this embodiment, the power management bus interface is an I2C interface, which includes the corresponding address protocol; the power management bus interface outputs communication signals and data signals to the baseboard management controller.

[0020] In this embodiment, the power supply branch includes a first switch and a constant current source; the constant current source is connected to the input terminal of the voltage sampling module through the first switch; the first switch is used to turn on when the enable signal is low and to turn off when the enable signal is high.

[0021] In this embodiment, the discharge branch includes a second switch, and the output terminal of the voltage sampling module is grounded through the second switch; the second switch is used to turn on when the enable signal is low and to turn off when the enable signal is high.

[0022] In this embodiment, the enable signal is input to the first register through a NOT gate, and the enable signal is directly input to the second register.

[0023] On the other hand, this application also provides a real-time detection method for step-down lines, employing the aforementioned real-time detection circuit for step-down lines, the method comprising:

[0024] A low-level enable signal is sent to the real-time detection circuit of the step-down line; the step-down module is controlled to be inactive; the logic control module is controlled to be turned on and input a constant current to the voltage sampling module; the differential amplifier module obtains the first voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register.

[0025] A high-level enable signal is sent to the real-time detection circuit of the step-down line; the step-down module is controlled to work, and the logic control module is controlled to be disconnected. The enable signal is stepped down by the step-down module and then input to the voltage sampling module. The differential amplifier module obtains the second voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register.

[0026] In this embodiment, the first register is readable and writable when the enable signal is low, and the second register is locked and can only be read when the enable signal is low; the first register is locked and can only be read when the enable signal is high, and the second register is readable and writable when the enable signal is high; when the first register is in a readable and writable state for the first time, it directly reads and writes the first voltage; when the first register is in a readable and writable state again, it releases the data first and then reads and writes the first voltage; when the second register is in a readable and writable state for the first time, it directly reads and writes the second voltage; when the second register is in a readable and writable state again, it releases the data first and then reads and writes the second voltage.

[0027] In this embodiment, the method further includes:

[0028] Real-time acquisition of digital data stored in the first register and the second register;

[0029] The value of the first voltage V1 is calculated by back-calculating the digital value in the first register according to the predetermined amplification factor and quantization ratio.

[0030] The value of the second voltage V2 is calculated by back-calculating the digital value in the second register according to the predetermined amplification factor and quantization ratio.

[0031] Obtain the value of the constant current Iref, and calculate the output current value when the enable signal is high using the formula Iout = V2 / V1 * Iref.

[0032] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: By implementing the real-time detection circuit and method for step-down circuits disclosed in the embodiments of the present invention, the output voltage in the power-on state can be monitored in real time without damaging the motherboard PCB or the entire system. This allows for timely analysis and location of the power consumption of downstream chips. Moreover, the output current in the power-on state can be calculated based on the voltage at the monitoring sampling port location. The current magnitude can be detected without tilting one end of the inductor, without damaging the motherboard PCB or electronic components, making the operation convenient. The power supply current of a certain component or chip can be remotely detected without disassembling the entire system, providing excellent operability. There is no need to wait for a problem to be reproduced before taking action; real-time monitoring is possible, providing excellent timeliness. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the MPQ8633B DC-DC chip circuit in the prior art;

[0035] Figure 2 This is a schematic diagram of a real-time detection circuit for a step-down line provided in an embodiment of the present invention;

[0036] Figure 3 yes Figure 2 Enlarged view of a portion of the structure;

[0037] Figure 4 This is a schematic diagram of a real-time detection method for a step-down line provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] For the component symbols involved in this application specification, the circuit diagram indicates the type of component and distinguishes each component, such as R1, R2, C, etc.; in the corresponding formula, the magnitude of the corresponding physical quantity of the component is indicated by italics, for example: the resistance value corresponding to the first resistor R1 is R1.

[0041] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0042] Example 1

[0043] like Figure 2 , Figure 3 As shown, in Embodiment 1, a real-time detection circuit for a step-down line is provided, including: a step-down module Buck1, a logic control module 2, a voltage sampling module 3, a differential amplifier module 4, a digital-to-analog converter module 5, and a storage module 6.

[0044] The input terminal of the buck module Buck1 receives an enable signal ENABL, and the output terminal of the buck module Buck1 is connected to the input terminal of the voltage sampling module 3.

[0045] The logic control module 2 includes a power supply branch and a discharge branch; the power supply branch is connected to the input terminal of the voltage sampling module 3, and is used to conduct and input a constant current Iref to the voltage sampling module 3 when the enable signal ENABL is low, and to disconnect when the enable signal ENABL is high; the discharge branch is connected to the output terminal of the voltage sampling module 3, and is used to conduct and discharge when the enable signal ENABL is low, and to disconnect when the enable signal ENABL is high.

[0046] In this embodiment, the power supply branch includes a first switch SW1 and a constant current source Source1; the constant current source Source1 is connected to the input terminal of the voltage sampling module 3 through the first switch SW1; the first switch SW1 is used to turn on when the enable signal ENABL is low and to turn off when the enable signal ENABL is high.

[0047] In this embodiment, the discharge branch includes a second switch SW2, and the output terminal of the voltage sampling module 3 is grounded through the second switch SW2; the second switch SW2 is used to turn on when the enable signal ENABL is low and to turn off when the enable signal ENABL is high.

[0048] The voltage sampling module 3 has an input terminal, a ground terminal, an output terminal, a first sampling port Sense+, and a second sampling port Sense-. The input terminal and the output terminal of the voltage sampling module 3 are connected in parallel to a branch consisting of an output inductor L and a DC resistor DCR connected in series, and a branch consisting of a first resistor R1 and a first capacitor C1 connected in series. The two ends of the first capacitor C1 are respectively connected to the first sampling port Sense+ and the second sampling port Sense-. The output terminal of the voltage sampling module 3 is connected to its ground terminal and grounded through the second capacitor C.

[0049] The storage module 6 includes a first register 61 and a second register 62. The first register 61 acquires the inverted voltage of the enable signal ENABL in real time, and the second register 62 acquires the voltage of the enable signal ENABL in real time.

[0050] In this embodiment, the enable signal ENABL is input to the first register 61 through the NOT gate Q1, and the enable signal ENABL is directly input to the second register 62.

[0051] The first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3 are both connected to the differential amplifier module 4. The differential amplifier module 4 is connected to the first register 61 and the second register 62 of the storage module 6 through the digital-to-analog converter module 5.

[0052] In this embodiment, the buck module Buck1 is configured to not operate when the enable signal ENABL is low and to operate when the enable signal ENABL is high; the first register 61 is readable and writable when the enable signal ENABL is low, and the second register 62 is readable and writable when the enable signal ENABL is high.

[0053] When the enable signal ENABL is low, the logic control module 2 inputs a constant current Iref to the voltage sampling module 3. The differential amplifier module 4 obtains the first voltage V1 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register 61.

[0054] When the enable signal ENABL is high, the enable signal ENABL is stepped down by the buck module Buck1 and then input to the voltage sampling module 3. The differential amplifier module 4 obtains the second voltage V2 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register 62.

[0055] like Figure 2 The diagram shown is a schematic diagram of the specific circuit structure proposed in this invention.

[0056] In the voltage sampling module 3, select appropriate C1 and R1 to satisfy L / DCR=R1*C1, and detect that the voltage on C1 is proportional to the current passing through DCR.

[0057] The logic control modules 2SW1 and SW2 are both active low-level switches. When ENABLE is low, both switches are turned on (SW1 and SW2 can be replaced by MOSFETs). Q1 is a NOT gate circuit, which completes the logic level toggling.

[0058] The constant current source Source1 is a constant current source with a constant current output Iref (1mA for example). Under STBY mode, ENABLE is low, that is, when SW1 and SW2 are closed, the voltage on C1 in the buck circuit is sampled through a pair of differential lines Sense+ and sense-. At this time, only a stable current of 1mA flows through the inductor. When powered on, ENABLE is high, that is, when SW1 and SW2 are off, Sense+ and sense- sample the voltage on C1 connected in parallel with the output inductor L in the buck circuit.

[0059] like Figure 3As shown, the differential amplifier module 4 includes an amplifier, and the digital-to-analog conversion module 5 includes an analog-to-digital converter (ADC). The amplifier amplifies the sampled voltage by a fixed factor and sends it to the ADC. The ADC can quantize the amplified analog voltage into a 4-bit hexadecimal digital value and write it into the storage module 6, with a maximum value of FFFF.

[0060] Storage module 6 has different registers used to store different digital values. The first register 61 and the second register 62 are latched when the register enable is low, and can only be read but not written. When the enable is high, they are released and can be read and written.

[0061] An external BMC management chip can read this address via I2C and complete communication to obtain hexadecimal digital values ​​from different registers.

[0062] Example 2

[0063] like Figure 2 , Figure 3 As shown, in Embodiment 2, a real-time detection circuit for a step-down line is provided, including: a step-down module Buck1, a logic control module 2, a voltage sampling module 3, a differential amplifier module 4, a digital-to-analog converter module 5, and a storage module 6.

[0064] The input terminal of the buck module Buck1 receives an enable signal ENABL, and the output terminal of the buck module Buck1 is connected to the input terminal of the voltage sampling module 3.

[0065] The logic control module 2 includes a power supply branch and a discharge branch; the power supply branch is connected to the input terminal of the voltage sampling module 3, and is used to conduct and input a constant current Iref to the voltage sampling module 3 when the enable signal ENABL is low, and to disconnect when the enable signal ENABL is high; the discharge branch is connected to the output terminal of the voltage sampling module 3, and is used to conduct and discharge when the enable signal ENABL is low, and to disconnect when the enable signal ENABL is high.

[0066] In this embodiment, the power supply branch includes a first switch SW1 and a constant current source Source1; the constant current source Source1 is connected to the input terminal of the voltage sampling module 3 through the first switch SW1; the first switch SW1 is used to turn on when the enable signal ENABL is low and to turn off when the enable signal ENABL is high.

[0067] In this embodiment, the discharge branch includes a second switch SW2, and the output terminal of the voltage sampling module 3 is grounded through the second switch SW2; the second switch SW2 is used to turn on when the enable signal ENABL is low and to turn off when the enable signal ENABL is high.

[0068] The voltage sampling module 3 has an input terminal, a ground terminal, an output terminal, a first sampling port Sense+, and a second sampling port Sense-. The input terminal and the output terminal of the voltage sampling module 3 are connected in parallel to a branch consisting of an output inductor L and a DC resistor DCR connected in series, and a branch consisting of a first resistor R1 and a first capacitor C1 connected in series. The two ends of the first capacitor C1 are respectively connected to the first sampling port Sense+ and the second sampling port Sense-. The output terminal of the voltage sampling module 3 is connected to its ground terminal and grounded through the second capacitor C.

[0069] The storage module 6 includes a first register 61 and a second register 62. The first register 61 acquires the inverted voltage of the enable signal ENABL in real time, and the second register 62 acquires the voltage of the enable signal ENABL in real time.

[0070] In this embodiment, the enable signal ENABL is input to the first register 61 through the NOT gate Q1, and the enable signal ENABL is directly input to the second register 62.

[0071] The first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3 are both connected to the differential amplifier module 4. The differential amplifier module 4 is connected to the first register 61 and the second register 62 of the storage module 6 through the digital-to-analog converter module 5.

[0072] In this embodiment, the buck module Buck1 is configured to not operate when the enable signal ENABL is low and to operate when the enable signal ENABL is high; the first register 61 is readable and writable when the enable signal ENABL is low, and the second register 62 is readable and writable when the enable signal ENABL is high.

[0073] When the enable signal ENABL is low, the logic control module 2 inputs a constant current Iref to the voltage sampling module 3. The differential amplifier module 4 obtains the first voltage V1 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register 61.

[0074] When the enable signal ENABL is high, the enable signal ENABL is stepped down by the buck module Buck1 and then input to the voltage sampling module 3. The differential amplifier module 4 obtains the second voltage V2 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register 62.

[0075] In this embodiment, the real-time detection circuit for a step-down line further includes a power management bus interface 7 (SMBUS Interface). The power management bus interface 7 is connected to the storage module 6 and can be connected to the baseboard management controller (BMC).

[0076] In this embodiment, the power management bus interface 7 is an I2C interface, which includes the corresponding address protocol; the power management bus interface 7 outputs communication signal SCL and data signal SDA to the baseboard management controller (BMC).

[0077] like Figure 2 The diagram shown is a schematic diagram of the specific circuit structure proposed in this invention.

[0078] In the voltage sampling module 3, select appropriate C1 and R1 to satisfy L / DCR=R1*C1, and detect that the voltage on C1 is proportional to the current passing through DCR.

[0079] Both SW1 and SW2 of the logic control module 2 are active low-level switches. When ENABLE is low, both switches are turned on (SW1 and SW2 can be replaced by MOSFETs). Q1 is a NOT gate circuit, which completes the logic level flipping.

[0080] The constant current source Source1 is a constant current source with a constant current output Iref (1mA for example). Under STBY mode, ENABLE is low, that is, when SW1 and SW2 are closed, the voltage on C1 in the buck circuit is sampled through a pair of differential lines Sense+ and sense-. At this time, only a stable current of 1mA flows through the inductor. When powered on, ENABLE is high, that is, when SW1 and SW2 are off, Sense+ and sense- sample the voltage on C1 connected in parallel with the output inductor L in the buck circuit. At this time, the current flowing through the inductor is the actual load current.

[0081] This application detects a reference voltage Vref by providing a known stable current output Iref (1mA in this example) in standby mode. Then, upon power-on, the constant current source is turned off, and the real-time inductor voltage V is detected. The ratio between the real-time voltage V and Vref, multiplied by Iref, yields the desired real-time current information. After amplification and analog-to-digital conversion, the voltage information is stored in a register as a hexadecimal number. An I2C interface is added to allow the BMC to access this register information.

[0082] like Figure 3 As shown, the differential amplifier module 4 includes an amplifier, and the digital-to-analog conversion module 5 includes an analog-to-digital converter (ADC). The amplifier amplifies the sampled voltage by a fixed factor and sends it to the ADC. The ADC can quantize the amplified analog voltage into a 4-bit hexadecimal digital value and write it into the storage module 6, with a maximum value of FFFF.

[0083] Storage module 6 has different registers used to store different digital values. The first register 61 and the second register 62 are latched when the register enable is low, and can only be read but not written. When the enable is high, they are released and can be read and written.

[0084] An external BMC management chip can read this address via I2C and complete communication to obtain hexadecimal digital values ​​from different registers.

[0085] To clearly explain how BMC calculates the output current value when the enable signal ENABL is high using the formula Iout=V2 / V1*Iref, the implementation steps are explained in conjunction with the technical solution.

[0086] (1) When the device is powered on by AC, in standby (STBY) mode, ENABLE is low. At this time, the buck module Buck1 is not working, SW1 and SW2 are closed, and a 1mA current flows through the output inductor L. The amplifier will obtain a voltage V1, amplify it, and perform ADC conversion and quantization before sending it to the first register 61. The enable of the first register 61 is high after being inverted by Q1, so it is readable and writable. Therefore, the signal amplified by the amplifier can be written into the first register. The external BMC can obtain the digital value in the first register through the I2C of SMBUS. We calculate the value of V1 by working backwards according to the predetermined amplification factor and quantization ratio.

[0087] (2) When the power button is pressed and the device is powered on, ENABLE is high. At this time, the buck module Buck1 starts to step down, and the subsequent circuit starts to have current demand, with Iout passing through inductor L. When ENABLE is high, SW1 and SW2 are disconnected, and the enable of the first register is low after being inverted by Q1. The value of the first register can only be read but not written. The enable of the second register 62 is high, and it can be written and read. The amplifier will get a voltage V2 at this time, amplify it, and perform ADC conversion and quantization before sending it to the second register 62. The external BMC can get the digital value in the second register 62 through the I2C of SMBUS. We calculate the size of V2 according to the predetermined amplification factor and quantization ratio, and then V2 / V1*1mA=Iout.

[0088] This embodiment calculates the output current in the power-on state by monitoring the voltage at the sampling port location. It can detect the current magnitude without tilting one end of the inductor, without damaging the motherboard PCB or electronic components, making it convenient to operate. It can remotely detect the power supply current of a component or chip without disassembling the entire system, which has excellent operability. There is no need to wait for a problem to be reproduced before taking action, as it can be monitored in real time, which has excellent timeliness.

[0089] Example 3

[0090] like Figure 4 As shown, Embodiment 3 of this application provides a real-time detection method for a step-down line, employing the real-time detection circuit for a step-down line described above. The method includes:

[0091] Step S1: Send a low-level enable signal ENABL to the real-time detection circuit of the step-down line; control the step-down module Buck1 to not work, control the logic control module 2 to turn on and input a constant current Iref to the voltage sampling module 3; the differential amplifier module 4 obtains the first voltage V1 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register 61;

[0092] Step S2: Send a high-level enable signal ENABL to the real-time detection circuit of the step-down line; control the buck module Buck1 to work and control the logic control module 2 to disconnect. The enable signal ENABL is input to the voltage sampling module 3 after being stepped down by the buck module Buck1. The differential amplifier module 4 obtains the second voltage V2 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register 62.

[0093] In this embodiment, the first register 61 is readable and writable when the enable signal ENABL is low, and the second register 62 is locked and can only be read, not written, when the enable signal ENABL is low; the first register 61 is locked and can only be read, not written, when the enable signal ENABL is high, and the second register 62 is readable and writable when the enable signal ENABL is high; when the first register 61 is in a readable and writable state for the first time, it directly reads and writes the first voltage V1; when the first register 61 is in a readable and writable state again, it releases the data first and then reads and writes the first voltage V1; when the second register 62 is in a readable and writable state for the first time, it directly reads and writes the second voltage V2; when the second register 62 is in a readable and writable state again, it releases the data first and then reads and writes the second voltage V2.

[0094] Example 4

[0095] like Figure 4 As shown, Embodiment 4 of this application provides a real-time detection method for a step-down line, employing the real-time detection circuit for a step-down line described above. The method includes:

[0096] Step S1: Send a low-level enable signal ENABL to the real-time detection circuit of the step-down line; control the step-down module Buck1 to not work, control the logic control module 2 to turn on and input a constant current Iref to the voltage sampling module 3; the differential amplifier module 4 obtains the first voltage V1 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register 61;

[0097] Step S2: Send a high-level enable signal ENABL to the real-time detection circuit of the step-down line; control the buck module Buck1 to work and control the logic control module 2 to disconnect. The enable signal ENABL is input to the voltage sampling module 3 after being stepped down by the buck module Buck1. The differential amplifier module 4 obtains the second voltage V2 between the first sampling port Sense+ and the second sampling port Sense- of the voltage sampling module 3, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register 62.

[0098] In this embodiment, the first register 61 is readable and writable when the enable signal ENABL is low, and the second register 62 is locked and can only be read, not written, when the enable signal ENABL is low; the first register 61 is locked and can only be read, not written, when the enable signal ENABL is high, and the second register 62 is readable and writable when the enable signal ENABL is high; when the first register 61 is in a readable and writable state for the first time, it directly reads and writes the first voltage V1; when the first register 61 is in a readable and writable state again, it releases the data first and then reads and writes the first voltage V1; when the second register 62 is in a readable and writable state for the first time, it directly reads and writes the second voltage V2; when the second register 62 is in a readable and writable state again, it releases the data first and then reads and writes the second voltage V2.

[0099] like Figure 4 As shown, in this embodiment, the method further includes:

[0100] Step S3: Real-time acquisition of digital data stored in the first register 61 and the second register 62;

[0101] Step S4: Calculate the value V1 of the first voltage by back-calculating the digital value of the first register 61 according to the predetermined amplification factor and quantization ratio;

[0102] Step S5: Calculate the value V2 of the second voltage by reverse engineering the digital value of the second register 62 according to the predetermined amplification factor and quantization ratio;

[0103] Step S6: Obtain the value of the constant current Iref, and calculate the output current value when the enable signal ENABL is high using the formula Iout=V2 / V1*Iref.

[0104] To clearly illustrate the implementation of this method, the implementation steps will be explained in conjunction with the technical solution.

[0105] (1) When the device is powered on by AC, in standby (STBY) mode, ENABLE is low. At this time, the buck module Buck1 is not working, SW1 and SW2 are closed, and a 1mA current flows through the output inductor L. The amplifier will obtain a voltage V1, amplify it, and perform ADC conversion and quantization before sending it to the first register 61. The enable of the first register 61 is high after being inverted by Q1, so it is readable and writable. Therefore, the signal amplified by the amplifier can be written into the first register. The external BMC can obtain the digital value in the first register through the I2C of SMBUS. We calculate the value of V1 by working backwards according to the predetermined amplification factor and quantization ratio.

[0106] (2) When the power button is pressed and the device is powered on, ENABLE is high. At this time, the buck module Buck1 starts to step down, and the subsequent circuit starts to have current demand, with Iout passing through inductor L. When ENABLE is high, SW1 and SW2 are disconnected, and the enable of the first register is low after being inverted by Q1. The value of the first register can only be read but not written. The enable of the second register 62 is high, and it can be written and read. The amplifier will get a voltage V2 at this time, amplify it, and perform ADC conversion and quantization before sending it to the second register 62. The external BMC can get the digital value in the second register 62 through the I2C of SMBUS. We calculate the size of V2 according to the predetermined amplification factor and quantization ratio, and then V2 / V1*1mA=Iout.

[0107] (3) After pressing the power off button, ENABLE is low. At this time, the enable of the first register is flipped to high, and it can be read and written. The second register 62 is locked. Since Buck is no longer working, BMC has no need to read the second register 62.

[0108] (4) When the power button is pressed again, ENABLE will be high, the second register 62 will be released, and normal reading and writing can be performed again.

[0109] This application detects a reference voltage Vref by providing a known constant current output Iref (1mA in this example) in standby mode. Then, upon power-on, the constant current source is turned off, and the real-time inductor voltage V is detected. The ratio between the real-time voltage V and Vref, multiplied by Iref, yields the desired real-time current information. After amplification and analog-to-digital conversion, the voltage information is stored in a register as a hexadecimal number. An I2C interface is added to allow the BMC to access this register information.

[0110] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: By implementing the real-time detection circuit and method for step-down circuits disclosed in the embodiments of the present invention, the output voltage in the power-on state can be monitored in real time without damaging the motherboard PCB or the entire system. This allows for timely analysis and location of the power consumption of downstream chips. Moreover, the output current in the power-on state can be calculated based on the voltage at the monitoring sampling port location. The current magnitude can be detected without tilting one end of the inductor, without damaging the motherboard PCB or electronic components, making the operation convenient. The power supply current of a certain component or chip can be remotely detected without disassembling the entire system, providing excellent operability. There is no need to wait for a problem to be reproduced before taking action; real-time monitoring is possible, providing excellent timeliness.

[0111] Furthermore, the technical solution of this application can also be integrated into a multi-channel design, by configuring different addresses to select and access different power chips, thereby realizing a design method to monitor multiple power outputs.

[0112] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program loaded on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from memory, or installed from ROM. When the computer program is executed by an external processor, it performs the functions defined in the methods of embodiments of this application.

[0113] It should be noted that the computer-readable medium in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the embodiments of this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.

[0114] The aforementioned computer-readable medium may be included in the aforementioned server; or it may exist independently and not assembled into the server. The aforementioned computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the peripheral mode of the terminal is not activated, acquire the frame rate of the application on the terminal; when the frame rate meets the screen-off condition, determine whether the user is acquiring the terminal's screen information; and in response to the determination that the user is not acquiring the terminal's screen information, control the screen to enter an immediate dimming mode.

[0115] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0116] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0117] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A real-time detection circuit for a step-down circuit, characterized in that, include: The module includes a step-down module, a logic control module, a voltage sampling module, a differential amplifier module, a digital-to-analog converter module, and a storage module. An enable signal is input to the input terminal of the buck module, and the output terminal of the buck module is connected to the input terminal of the voltage sampling module. The logic control module includes a power supply branch and a discharge branch; the power supply branch is connected to the input terminal of the voltage sampling module, and is used to conduct and input a constant current to the voltage sampling module when the enable signal is low, and to disconnect when the enable signal is high; the discharge branch is connected to the output terminal of the voltage sampling module, and is used to conduct and discharge when the enable signal is low, and to disconnect when the enable signal is high. The voltage sampling module has an input terminal, a ground terminal, an output terminal, a first sampling port, and a second sampling port. The input terminal and the output terminal of the voltage sampling module are connected in parallel to a branch consisting of an output inductor and a DC resistor connected in series, and a branch consisting of a first resistor and a first capacitor connected in series. The two ends of the first capacitor are respectively connected to the first sampling port and the second sampling port. The output terminal of the voltage sampling module is connected to its ground terminal and grounded through the second capacitor. The storage module includes a first register and a second register. The first register acquires the inverted voltage of the enable signal in real time, and the second register acquires the voltage of the enable signal in real time. The first sampling port and the second sampling port of the voltage sampling module are both connected to the differential amplifier module, and the differential amplifier module is connected to the first register and the second register of the storage module through the digital-to-analog converter module; The step-down module is configured to not operate when the enable signal is low and to operate when the enable signal is high; the first register is readable and writable when the enable signal is low, and the second register is readable and writable when the enable signal is high. When the enable signal is low, the logic control module inputs a constant current to the voltage sampling module. The differential amplifier module obtains the first voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register. When the enable signal is high, the enable signal is stepped down by the step-down module and then input to the voltage sampling module. The differential amplifier module obtains the second voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register.

2. The real-time detection circuit for a step-down line according to claim 1, characterized in that, Also includes: A power management bus interface is connected to the storage module, and the power management bus interface can be connected to the baseboard management controller.

3. The real-time detection circuit for a step-down line according to claim 2, characterized in that, The power management bus interface is an I2C interface, which includes the corresponding address protocol; the power management bus interface outputs communication signals and data signals to the baseboard management controller.

4. The real-time detection circuit for a step-down line according to claim 1, characterized in that, The power supply branch includes a first switch and a constant current source; the constant current source is connected to the input terminal of the voltage sampling module through the first switch; the first switch is used to turn on when the enable signal is low and to turn off when the enable signal is high.

5. The real-time detection circuit for a step-down line according to claim 4, characterized in that, The discharge branch includes a second switch, and the output terminal of the voltage sampling module is grounded through the second switch; the second switch is used to turn on when the enable signal is low and to turn off when the enable signal is high.

6. The real-time detection circuit for a step-down line according to claim 1, characterized in that, The enable signal is input to the first register through a NOT gate, and the enable signal is directly input to the second register.

7. A method for real-time detection of a step-down line, employing the real-time detection circuit for a step-down line as described in any one of claims 1-6, characterized in that, The method includes: A low-level enable signal is sent to the real-time detection circuit of the step-down line; the step-down module is controlled to be inactive; the logic control module is controlled to be turned on and input a constant current to the voltage sampling module; the differential amplifier module obtains the first voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the first register. A high-level enable signal is sent to the real-time detection circuit of the step-down line; the step-down module is controlled to work, and the logic control module is controlled to be disconnected. The enable signal is stepped down by the step-down module and then input to the voltage sampling module. The differential amplifier module obtains the second voltage between the first sampling port and the second sampling port of the voltage sampling module, amplifies it, performs digital-to-analog conversion and quantization, and then writes it into the second register.

8. The real-time detection method for a step-down line according to claim 7, characterized in that, The first register is readable and writable when the enable signal is low, and the second register is locked and can only be read when the enable signal is low; the first register is locked and can only be read when the enable signal is high, and the second register is readable and writable when the enable signal is high; when the first register is initially in a readable and writable state, it directly reads and writes the first voltage; when the first register is in a readable and writable state again, it releases the data first and then reads and writes the first voltage; when the second register is initially in a readable and writable state, it directly reads and writes the second voltage; when the second register is in a readable and writable state again, it releases the data first and then reads and writes the second voltage.

9. The real-time detection method for a step-down line according to claim 8, characterized in that, The method further includes: Real-time acquisition of digital data stored in the first register and the second register; The value of the first voltage V1 is calculated by back-calculating the digital value in the first register according to the predetermined amplification factor and quantization ratio. The value of the second voltage V2 is calculated by back-calculating the digital value in the second register according to the predetermined amplification factor and quantization ratio. Obtain the value of the constant current Iref, and calculate the output current value when the enable signal is high using the formula Iout=V2 / V1*Iref.

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