Display panel driving circuit, display panel, and display device

Abstract

The present application discloses a driving circuit for a display panel. The driving circuit includes a source driving module, a level conversion module and a timing control module. The timing control module is connected to the source driving module and the level conversion module respectively. The timing control module is used to control the level conversion module to output a preset gate control signal according to the first abnormal feedback signal of the source driving module to turn off the display panel; and is used to control the source driving module to drive the display panel to display preset grayscale pixels according to the second abnormal feedback signal of the level conversion module. The timing control module in the driving circuit of the present application controls the source driving module to drive the display panel to display preset grayscale pixels according to the abnormal situation of the level conversion module, thereby reducing the poor sensitivity of the display panel. In addition, the timing control module can also control the level conversion module to output a preset gate control signal according to the abnormal situation of the source driving module to turn off the display panel, thereby avoiding the abnormal display of the display panel screen.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel driving circuit, a display panel, and a display device. Background Art

[0002] Power-on and power-off testing of LCD monitors is a crucial component of reliability testing. This is due to the unstable power supply and signal during the startup phase, which can easily lead to startup anomalies. For example, the occasional red flash and abnormal startup screen display errors that occur at the customer end can cause high visibility and negatively impact both the customer end and the end market. Reducing or eliminating these issues has become a pressing technical challenge. Summary of the Invention

[0003] In view of this, the present application aims to solve at least one of the problems in the related art to a certain extent. To this end, the purpose of the present application is to provide a display panel driving circuit, a display panel and a display device.

[0004] The present invention provides a driving circuit for a display panel. The driving circuit includes a source driver module, a level conversion module, and a timing control module, wherein the timing control module is connected to the level conversion module and the source driver module, respectively. The timing control module is configured to control the level conversion module to output a preset gate control signal to turn off the display panel based on a first abnormal feedback signal from the source driver module, and to control the source driver module to drive the display panel to display preset grayscale pixels based on a second abnormal feedback signal from the level conversion module.

[0005] In this manner, the timing control module in the driver circuit of the present application controls the source driver module to drive the display panel to display predetermined grayscale pixels based on the abnormality of the level conversion module, thereby reducing the display panel's sensitivity to defects. Furthermore, the timing control module can also control the level conversion module to output a predetermined gate control signal based on the abnormality of the source driver module, thereby shutting down the display panel and preventing abnormal display of the display panel image.

[0006] In some embodiments, the source driver module includes a plurality of source driver chips, each of which is provided with a signal transmission node, and the first abnormal feedback signal is transmitted between every two source driver chips through the signal transmission node.

[0007] In this way, the timing control module can receive the first abnormal feedback signal transmitted by the source driving module through the signal transmission node.

[0008] In some embodiments, the timing control module includes a power control circuit, and the power control circuit is used to control the startup and shutdown of the timing control module according to the first abnormal feedback signal and / or the second abnormal feedback signal.

[0009] In this way, the present application can control the startup and shutdown of the timing control module according to the first abnormal feedback signal or the second abnormal feedback signal through the power control circuit, complete the restart of the display panel, and then restore the normal display of the display panel in time when the display panel has a display abnormality.

[0010] In some embodiments, the power control circuit includes a power supply voltage, a startup unit, a control unit and a power management unit, the startup unit is connected to the power supply voltage and the control unit respectively; the control unit is connected to the power supply voltage and the power management unit respectively; the power management unit is used to control the startup and shutdown of the timing control module according to the voltage signal output by the control unit.

[0011] In this way, the present application can add a power control circuit in the timing control module, and control the timing control module to restart through the power control circuit to complete the restart of the display panel, so that the normal display of the display panel can be restored in time when the display abnormality occurs.

[0012] In some embodiments, the startup unit includes an input and output pin, a first transistor, a first resistor, and a second resistor, the input and output pin is connected to the gate of the first transistor, the first end of the first resistor is connected to the power supply voltage, and the second end of the first resistor is connected to the first end of the second resistor and the gate of the first transistor; the timing control module controls the voltage of the input and output pin according to the first abnormal feedback signal and / or the second abnormal feedback signal, and the drain of the first transistor is connected to the control unit.

[0013] In this way, the timing control module of the present application can control the voltage of the input and output pins according to the received first abnormal feedback signal or the second abnormal feedback signal, thereby completing the automatic restart of the timing control module, and then completing the automatic restart of the display panel, and then being able to restore the normal display of the display panel in time when the display panel has a display abnormality.

[0014] In some embodiments, the control unit includes a third resistor, a fourth resistor and a second transistor, the first end of the third resistor is connected to the drain of the first transistor, the second end of the third resistor is connected to the gate of the second transistor, the first end of the fourth resistor is connected to the gate of the second transistor, the second end of the fourth resistor is connected to the power supply voltage and the source of the second transistor, and the drain of the second transistor is connected to the power management unit.

[0015] In this way, the timing control module of the present application can control the voltage of the input and output pins according to the received first abnormal feedback signal or the second abnormal feedback signal, thereby completing the automatic restart of the timing control module, and then completing the automatic restart of the display panel, and then being able to restore the normal display of the display panel in time when the display panel has a display abnormality.

[0016] In some embodiments, the timing control module is further configured to generate a data stop signal according to the first abnormal feedback signal, and control the level conversion module to be turned off according to the data stop signal.

[0017] In this way, the timing control module can directly control the level conversion module to shut down according to the first abnormal feedback signal, thereby avoiding the undesirable phenomenon that the display area corresponding to some source driver chips displays abnormally when an abnormality occurs in the source driver module, and avoiding the undesirable phenomenon that the display panel displays red flashes.

[0018] In some embodiments, the driving circuit includes a power management unit, which is used to supply power to the timing control module, the source driving module and the level conversion module. The timing control module sends an enable signal to the power management unit based on the first abnormal feedback signal and the second abnormal feedback signal, so that the power management unit supplies power to the timing control module, the source driving module and the level conversion module.

[0019] In this way, when the timing control module receives the first feedback signal and the second feedback signal, the present application sends an enable signal to the power management unit. The power management unit can directly control the shutdown of the timing control module, the source driver module, and the level conversion module. After that, the power management unit can directly control the startup of the timing control module, the source driver module, and the level conversion module, thereby completing the automatic restart of the display panel to restore the normal display of the display panel.

[0020] The present application also provides a display panel, wherein the display panel includes the driving circuit according to any one of the above embodiments.

[0021] The display panel of the present application utilizes the timing control module in the aforementioned driver circuit to control the source driver module to drive the display panel to display predetermined grayscale pixels based on abnormalities in the level conversion module, thereby reducing the display panel's sensitivity to defects. Furthermore, the timing control module can also control the level conversion module to output a predetermined gate control signal based on abnormalities in the source driver module, thereby shutting down the display panel and preventing abnormal display on the display panel.

[0022] The present application also provides a display device, which includes the display panel described in the above embodiment.

[0023] The display panel of the display device of the present application utilizes the timing control module in the aforementioned driver circuit to control the source driver module to drive the display panel to display predetermined grayscale pixels based on abnormalities in the level conversion module, thereby reducing the display panel's sensitivity to defects. Furthermore, the timing control module can also control the level conversion module to output a predetermined gate control signal based on abnormalities in the source driver module, thereby shutting down the display panel and preventing abnormal display on the display panel.

[0024] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0026] Figure 1 This is a schematic diagram of the structure of the driving circuit of a current LCD display when the display flashes red when turned on;

[0027] Figure 2 This is a schematic diagram of the structure of the current LCD display's drive circuit when it is probabilistically turned on and displayed differently;

[0028] Figure 3 is a schematic structural diagram of a driving circuit in some embodiments of the present application;

[0029] Figure 4 is a schematic structural diagram of a power control circuit in a timing control module of certain embodiments of the present application;

[0030] Figure 5 is a schematic structural diagram of a driving circuit in some embodiments of the present application;

[0031] Figure 6 It is a schematic structural diagram of a driving circuit of certain embodiments of the present application. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application.

[0033] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise expressly and specifically defined.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that can communicate with each other; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connectivity between two components or interactions between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0035] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, these are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application.

[0037] Power-on and power-off testing of LCD monitors is a crucial component of reliability testing. This is due to the unstable power supply and signal during the startup phase, which can easily lead to startup anomalies. For example, recent incidents of occasional red flashing and abnormal startup images at client terminals have had a significant impact on both the client and the end market due to their high visibility.

[0038] LCD monitors exhibit a distinct pattern when experiencing probabilistic issues like red flashing on startup and abnormal screen display during startup: they occur rarely and can be corrected by restarting the device. Due to this low probability, these issues are difficult to detect during abnormality testing. Therefore, addressing these display issues requires addressing their root causes.

[0039] Therefore, this application aims to combine the probabilistic red flashing and abnormal startup image defects that occur on the client side, improve the circuit design solution to reduce or eliminate the occurrence of such defects, and improve the product's impression on end customers.

[0040] Understandably, see Figure 1 The mechanism for the probabilistic red flashing during startup of an LCD is as follows: When the LCD is powered on, some source driver ICs (S-ICs) in the source driver module of the display's driver circuit malfunction, causing the peer-to-peer (P2P) signal transmission node in the source driver IC to transmit an abnormal "Unlock" signal. After the timing control register (TCON) detects the abnormal "Unlock" signal, it continuously sends a training pattern signal to the source driver module. Some S-ICs mistakenly identify the training pattern signal as color grayscale pixel data (RGB data) and send it to the display area, thereby driving the display area to display color grayscale pixels. At this time, the level shifter (L / S) module normally outputs the gate on array (GOA) signal, also known as the gate signal. As a result, the display area corresponding to some source driver ICs (S-ICs) will experience display abnormalities, such as the undesirable phenomenon of flashing red. This undesirable phenomenon automatically disappears when the display is powered on again, and the display returns to normal display.

[0041] See also Figure 2 The mechanism of probabilistic startup image anomalies in LCDs is as follows: When the LCD is turned on, residual charge in the GOA unit or abnormal L / S output can cause the GOA unit's multi-output gate control (GOA) signal to trigger the L / S overcurrent protection (OCP). At this point, the L / S output is in a high-impedance (Hi-Z) state, preventing the display area's gate channel from shutting down properly. At this point, the source driver chip (S-IC) is outputting color pixel data normally, leading to a full-screen defect similar to mischarging. This defect disappears automatically after the display is powered on again, and the display returns to normal display.

[0042] The commonality between these two issues is that they can be recovered after a reboot. In both cases, one chip is malfunctioning while the other is still outputting data normally, leading to display issues. For example, the red flashing phenomenon during startup is caused by abnormal grayscale pixel data (RGBData) signal output while the gate control (Gate) signal is still outputting normally; the abnormal startup image phenomenon is caused by abnormal Gate signal output while the RGB Data signal is still outputting normally.

[0043] In view of this, please see Figure 3 The present application provides a driving circuit 10 for a display panel. The driving circuit 100 includes a source driver module 11, a level conversion module 12, and a timing control module 13. The timing control module 13 is connected to the source driver module 11 and the level conversion module 12, respectively. The timing control module 13 is configured to control the level conversion module 12 to output a preset gate control signal to turn off the display panel based on a first abnormal feedback signal from the source driver module 11, and to control the source driver module 11 to drive the display panel to display preset grayscale pixels based on a second abnormal feedback signal from the level conversion module 12.

[0044] Among them, the first abnormal feedback signal can be Figure 3 The second abnormal feedback signal can be Figure 3 FB signal in.

[0045] The preset gate control signal is a preset GOA signal. The preset gate control signal can be, for example, a low-voltage signal. When the timing control module 13 controls the level conversion module 12 to output the low-voltage signal based on the first abnormal feedback signal from the source driver module 11, the display panel can be promptly turned off, thereby avoiding abnormal display on the display panel.

[0046] When the level conversion module 12 is abnormal, the timing control module 13 can control the source driver module to drive the display panel to display black pixels according to the second abnormal feedback signal sent by the level conversion module 12, thereby reducing the sensitivity of the display panel.

[0047] In this manner, the timing control module 13 in the driver circuit 10 of the present application controls the source driver module 11 to drive the display panel to display predetermined grayscale pixels based on the abnormality of the level conversion module 12, thereby reducing the display panel's sensitivity to defects. Furthermore, the timing control module 13 can also control the level conversion module 12 to output a predetermined gate control signal based on the abnormality of the source driver module 11, thereby shutting down the display panel and preventing abnormal display of the display panel image.

[0048] The source driver module 11 includes a plurality of source driver chips S-IC. A signal transmission node P is provided on each source driver chip S-IC. The first abnormal feedback signal Unlock is transmitted between every two source driver chips S-IC via the signal transmission node P.

[0049] The number of signal transmission nodes P is the same as the number of source driver chips S-IC. Figure 3 As shown, the number of source driver chips S-IC is 4, and the number of signal transmission nodes P is also 4. At this time, since the timing control module 13 is connected to the source driver module 11, the timing control module 13 can receive the first abnormal feedback signal Unlock sent by the source driver module 11.

[0050] In this way, the timing control module 13 can receive the first abnormal feedback signal transmitted by the source driving module 11 through the signal transmission node P.

[0051] The foregoing describes how to reduce the poor sensitivity of the display panel and avoid abnormal display of the display panel image when the first abnormal feedback signal and the second abnormal feedback signal appear. The following describes a specific solution for how to automatically restart the display panel through the driving circuit 10 to restore normal display of the display panel after the first abnormal feedback signal and the second abnormal feedback signal appear.

[0052] In one embodiment, see Figure 4 , the timing control module 13 includes a power control circuit 131. The power control circuit 131 is used to control the startup and shutdown of the timing control module 13 according to the first abnormal feedback signal and / or the second abnormal feedback signal. That is, the present application can add a power control circuit 131 to the timing control module 13, and can control the startup and shutdown of the timing control module 13 through the power control circuit 131 when the timing control module 13 receives the first abnormal feedback signal or the second abnormal feedback signal, complete the restart of the display panel, and then restore the normal display of the display panel in time when the display panel has a display abnormality. Or when the timing control module 13 receives the first abnormal feedback signal and the second abnormal feedback signal, it can control the startup and shutdown of the timing control module 13 through the power control circuit 131, complete the restart of the display panel, and then restore the normal display of the display panel in time when the display panel has a display abnormality.

[0053] In this way, the present application can control the timing control module 13 to start and shut down according to the first abnormal feedback signal or the second abnormal feedback signal through the power control circuit 131, complete the restart of the display panel, and then restore the normal display of the display panel in time when the display panel has a display abnormality.

[0054] The power control circuit 131 includes a power supply voltage Vin, a startup unit 1311, a control unit 1312, and a power management unit PMIC1. The startup unit 1311 is connected to the power supply voltage Vin and the control unit 1312, respectively. The control unit 1312 is connected to the power supply voltage Vin and the power management unit PMIC1, respectively. The power management unit PMIC1 is used to control the startup and shutdown of the timing control module 13 based on the voltage signal output by the control unit 1312. The power supply voltage Vin can be 12V or other values, without limitation.

[0055] Specifically, when the power management unit PMIC1 is in the power on state, the power management unit PMIC1 can control the timing control module 13 to start, that is, control the timing control module 13 to work normally; when the power management unit PMIC1 is in the power off state, the power management unit PMIC1 can control the timing control module 13 to shut down, that is, control the timing control module 13 to stop working.

[0056] In this way, the present application can add a power control circuit 131 in the timing control module 13, and control the timing control module 13 to restart through the power control circuit 131 to complete the restart of the display panel, so that the normal display of the display panel can be restored in time when the display abnormality occurs.

[0057] The startup unit 1311 includes an input / output pin GPIO, a first transistor M1, a first resistor R1, and a second resistor R2. The input / output pin GPIO is connected to the gate G of the first transistor M1. A first end of the first resistor R1 is connected to the power supply voltage Vin, and a second end of the first resistor R1 is connected to the first end of the second resistor R2 and the gate G of the first transistor M1. The timing control module 13 controls the voltage of the input / output pin GPIO based on the first abnormal feedback signal and / or the second abnormal feedback signal. The drain D1 of the first transistor M1 is connected to the control unit 1312.

[0058] The control unit 1312 includes a third resistor R3, a fourth resistor R4, and a second transistor M2. A first end of the third resistor R3 is connected to the drain D of the first transistor M1, and a second end of the third resistor R3 is connected to the gate G of the second transistor M2. A first end of the fourth resistor R3 is connected to the gate G of the second transistor M2, and a second end of the fourth resistor R4 is connected to the power supply voltage Vin and the source S of the second transistor M2. The drain D of the second transistor M2 is connected to the power management unit PMIC1.

[0059] It can be understood that when the power management unit PMIC1 is powered on and the timing control module is operating normally, the voltage divided at point B is approximately 3V. At this time, the startup voltage Vgs2 of the first transistor M1 is greater than the threshold voltage Vth2 of the first transistor M1, and the first transistor M1 is in the on state. At this time, the voltage divided at point A causes the startup voltage Vgs1 of the second transistor M2 to be less than the threshold voltage Vth1 of the second transistor M2, causing the second transistor M2 to be in the on state. Since both the first transistor M1 and the second transistor M2 are in the on state, the voltage of the power supply voltage Vin can be normally input to the power management unit PMIC1, that is, the power management unit PMIC1 is in the power-on (P) state, and the timing control module 13 can be controlled to operate normally.

[0060] When the timing control module 13 receives one of the first abnormal feedback signal or the second abnormal feedback signal, or receives both abnormal feedback signals, it can control the voltage of the input / output pin GPIO to a low voltage, so that the startup voltage Vgs of the first transistor M1 is less than the threshold voltage Vth2 of the first transistor M1, and the first transistor M1 is in the off state. At this time, the voltage at point A is equal to the power supply voltage Vin, which is 12V, so that the second transistor M2 is in the off state. Since both the first transistor M1 and the second transistor M2 are in the off state, the voltage of the power supply voltage Vin cannot be normally input to the power management unit PMIC1, that is, the power management unit PMIC1 is in the off state. When the output voltage DVDD / Vcore of the power management unit PMIC1 drops to close to 0V, the timing control module 13 will stop working.

[0061] Within a preset time after the timing control module 13 stops working, the input and output pin GPIO returns to a floating state. The preset time is 1S, 2S or other values, which are not limited here. At this time, the voltage divided by point B is about 3V, the voltage divided by the second resistor R2, the starting voltage Vgs2 of the first transistor M1 is greater than the threshold voltage Vth2 of the first transistor M1, and the first transistor M1 is in the on state. At this time, point A has a voltage divided, which will make the starting voltage Vgs1 of the second transistor M2 less than the threshold voltage Vth1 of the second transistor M2, so that the second transistor M2 is in the on state. Since both the first transistor M1 and the second transistor M2 are in the on state, the voltage of the power supply voltage Vin can be normally input to the power management unit PMIC1, that is, the power management unit PMIC1 is in the power-on (P) state, which can control the timing control module 13 to operate normally.

[0062] Through the above process, the timing control module 13 of the present application can control the voltage of the input and output pin GPIO according to the received first abnormal feedback signal or the second abnormal feedback signal, thereby completing the automatic restart of the timing control module 13, and then completing the automatic restart of the display panel, and then being able to restore the normal display of the display panel in time when the display panel has a display abnormality.

[0063] In another embodiment, see Figure 5 The timing control module 13 is further configured to generate a data stop signal according to the first abnormal feedback signal, and control the level conversion module 12 to be closed according to the data stop signal. Figure 5 The XON signal in.

[0064] Specifically, when the timing control module 13 receives the first abnormal feedback signal from the source driver module 11, the chip of the timing control module 13 generates an XON signal according to the first abnormal feedback signal, so that the level conversion module 12 enters the shutdown mode, thereby avoiding the undesirable phenomenon that the display area corresponding to some source driver chips (S-ICs) displays abnormally when an abnormality occurs in the source driver module 11, and avoiding the undesirable phenomenon that the display panel displays red flashes.

[0065] In this way, the timing control module 13 can directly control the level conversion module 12 to shut down according to the first abnormal feedback signal, thereby avoiding the undesirable phenomenon that the display area corresponding to some source driver chips (S-ICs) displays abnormally when an abnormality occurs in the source driver module 11, and avoiding the undesirable phenomenon that the display panel displays red flashes.

[0066] Another specific solution is described below on how to automatically restart the display panel to restore normal display of the display panel through the driving circuit 100 after the first abnormal feedback signal and the second abnormal feedback signal appear.

[0067] See also Figure 6 The driving circuit 10 includes a power management unit PMIC2, which is used to supply power to the timing control module 13, the source driver module 11 and the level conversion module 12. The timing control module 13 sends an enable signal to the power management unit PMIC2 according to the first abnormal feedback signal and the second abnormal feedback signal, so that the power management unit PMIC2 supplies power to the timing control module 13, the source driver module 11 and the level conversion module 12.

[0068] That is, in this embodiment, the power management unit PMIC2 has the function of directly controlling the start and stop of the timing control module 13 , the source driving module 11 and the level conversion module 12 according to the enable signal.

[0069] Specifically, when an abnormality occurs in some source driver chips S-IC of the source driver module 11, the first abnormal feedback signal Unlock signal can be fed back to the timing control module 13. The timing control module 13 sends an enable signal EN signal to the power management unit PMIC2 according to the first abnormal feedback signal. After receiving the EN enable signal, the power management unit PMIC2 provides a low voltage to the timing control module 13 and the level conversion module 12, so that the timing control module 13, the source driver module 11, and the level conversion module 12 all stop working. Within a preset time after the timing control module 13 stops working, the power management unit PMIC2 resumes providing a high voltage, so that the timing control module 13, the source driver module 11, and the level conversion module 12 are all powered on and start working again, thereby completing the automatic restart of the display panel to restore the normal display of the display panel. The preset time is 1S, 2S or other values, which are not limited here.

[0070] Alternatively, when the level conversion module 12 triggers the overcurrent protection function and feeds back the second abnormal feedback signal Fault to the timing control module 13, the timing control module 13 sends an enable signal EN to the power management unit PMIC2 according to the second abnormal feedback signal. After receiving the EN enable signal, the power management unit PMIC2 provides a low voltage to the timing control module 13, the source driver module 11, and the level conversion module 12, so that the timing control module 13, the source driver module 11, and the level conversion module 12 all stop working. Within a preset time after the timing control module 13 stops working, the power management unit PMIC2 resumes providing a high voltage, so that the timing control module 13, the source driver module 11, and the level conversion module 12 are all powered on and start working again, thereby completing the automatic restart of the display panel to restore the normal display of the display panel. The preset time is 1S, 2S or other values, which are not limited here.

[0071] In this way, when the timing control module 13 receives the first feedback signal and the second feedback signal, the present application sends an enable signal to the power management unit PMIC2. The power management unit PMIC2 can directly control the shutdown of the timing control module 13, the source driver module 11, and the level conversion module 12. After that, the power management unit PMIC2 can directly control the startup of the timing control module 13, the source driver module 11, and the level conversion module 12, thereby completing the automatic restart of the display panel to restore the normal display of the display panel.

[0072] The present application also provides a display panel. The display panel includes the aforementioned driving circuit 10. The internal structure of the driving circuit 10 and other specific contents are not repeated here.

[0073] The display panel of this application utilizes the timing control module 13 in the aforementioned driver circuit 10, which controls the source driver module 11 to drive the display panel to display predetermined grayscale pixels based on abnormalities in the level conversion module 12, thereby reducing the display panel's sensitivity to defects. Furthermore, the timing control module 13 can also control the level conversion module 12 to output a predetermined gate control signal based on abnormalities in the source driver module 11, thereby shutting down the display panel and preventing abnormal display on the display panel.

[0074] The present application also provides a display device. The display device includes the display panel 10 described above. The display panel includes the drive circuit 10 described above. The internal structure of the drive circuit 10 and other specific contents are not repeated here.

[0075] The display panel of the display device of the present application utilizes the timing control module 13 in the aforementioned driver circuit 10 to control the source driver module 11 to drive the display panel to display predetermined grayscale pixels based on abnormalities in the level conversion module 12, thereby reducing the display panel's sensitivity to defects. Furthermore, the timing control module 13 can also control the level conversion module 12 to output a predetermined gate control signal based on abnormalities in the source driver module 11, thereby shutting down the display panel and preventing abnormal display on the display panel.

[0076] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A driving circuit for a display panel, characterized in that: The driving circuit includes a source driving module, a level conversion module and a timing control module, and the timing control module is connected to the level conversion module and the source driving module respectively; The timing control module is used to control the level conversion module to output a preset gate control signal according to the first abnormal feedback signal of the source driver module to turn off the display panel, and to control the source driver module to drive the display panel to display preset grayscale pixels according to the second abnormal feedback signal of the level conversion module.

2. The driving circuit according to claim 1, wherein: The source driver module includes a plurality of source driver chips. A signal transmission node is provided on the source driver chip. The first abnormal feedback signal is transmitted between every two source driver chips through the signal transmission node.

3. The driving circuit according to claim 1, wherein: The timing control module includes a power control circuit, and the power control circuit is used to control the timing control module to start and stop according to the first abnormal feedback signal and / or the second abnormal feedback signal.

4. The driving circuit according to claim 3, wherein: The power control circuit includes a power supply voltage, a startup unit, a control unit and a power management unit, wherein the startup unit is connected to the power supply voltage and the control unit respectively; the control unit is connected to the power supply voltage and the power management unit respectively; the power management unit is used to control the startup and shutdown of the timing control module according to the voltage signal output by the control unit.

5. The driving circuit according to claim 4, wherein: The startup unit includes an input / output pin, a first transistor, a first resistor, and a second resistor, wherein the input / output pin is connected to the gate of the first transistor, a first end of the first resistor is connected to the power supply voltage, and a second end of the first resistor is connected to the first end of the second resistor and the gate of the first transistor; The timing control module controls the voltage of the input and output pins according to the first abnormal feedback signal and / or the second abnormal feedback signal, and the drain of the first transistor is connected to the control unit.

6. The driving circuit according to claim 5, wherein: The control unit includes a third resistor, a fourth resistor and a second transistor, the first end of the third resistor is connected to the drain of the first transistor, the second end of the third resistor is connected to the gate of the second transistor, the first end of the fourth resistor is connected to the gate of the second transistor, the second end of the fourth resistor is connected to the power supply voltage and the source of the second transistor, and the drain of the second transistor is connected to the power management unit.

7. The driving circuit according to claim 1, wherein: The timing control module is further configured to generate a data stop signal according to the first abnormal feedback signal, and control the level conversion module to be turned off according to the data stop signal.

8. The driving circuit according to claim 7, wherein: The driving circuit includes a power management unit, which is used to supply power to the timing control module, the source driver module and the level conversion module. The timing control module sends an enable signal to the power management unit according to the first abnormal feedback signal and the second abnormal feedback signal, so that the power management unit supplies power to the timing control module, the source driver module and the level conversion module.

9. A display panel, characterized in that: The driving circuit comprises the driving circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: The display panel comprises the display panel according to claim 9.

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