A ring gate transistor and a method of manufacturing the same

Abstract

This invention discloses a gate-around transistor and its manufacturing method, relating to the field of semiconductor technology. It is used to improve the conduction uniformity between nanowire / sheet layers in the channel region, thereby enhancing the driving performance of the gate-around transistor. The gate-around transistor includes a semiconductor substrate, an active structure, and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions. Along the height direction of the active structure, the channel region includes at least two spaced nanowire / sheet layers. In the channel region, at least one nanowire / sheet layer is made of a different material than the remaining nanowire / sheet layers. The gate stack structure is formed on the semiconductor substrate. The gate stack structure includes at least two gate stack layers, each gate stack layer surrounding the outer periphery of a corresponding nanowire / sheet layer. The thickness and / or material of the different gate stack layers located around the outer periphery of nanowires / sheets made of different materials are different.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gate-ring transistor and its manufacturing method. Background Technology

[0002] The gate stack structure of the gate ring transistor can be formed not only on the top of the channel region and the sidewalls along the width direction, but also on the bottom of the channel region. Therefore, the gate ring transistor has advantages such as higher gate control capability compared with planar transistors and fin field-effect transistors, which can improve the operating performance of semiconductor devices including the gate ring transistor.

[0003] However, when the channel region of a gate-around transistor has multiple nanowires / sheets, the conduction uniformity between the nanowires / sheets in the channel region is poor, which leads to low driving performance of the gate-around transistor. Summary of the Invention

[0004] The purpose of this invention is to provide a gate-around transistor and its manufacturing method to improve the conduction uniformity between nanowires / sheets in the channel region, thereby improving the driving performance of the gate-around transistor.

[0005] To achieve the above objectives, the present invention provides a gate ring transistor, which includes a semiconductor substrate, an active structure, and a gate stack structure.

[0006] The aforementioned active structure is formed on a semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions. Along the thickness direction of the semiconductor substrate, the channel region includes at least two spaced-apart nanowires / sheets. In the channel region, at least one nanowire / sheet is made of a different material than the remaining nanowires / sheets. A gate stack structure is formed on the semiconductor substrate. The gate stack structure includes at least two gate stacks, each gate stack surrounding the outer periphery of a corresponding nanowire / sheet. The thickness and / or material of the different gate stacks located around the outer periphery of nanowires / sheets made of different materials are different.

[0007] Compared with the prior art, the gate-ring transistor provided by the present invention includes at least two layers of spaced nanowires / sheets in the channel region along the thickness direction of the semiconductor substrate. Furthermore, in the channel region, at least one layer of nanowires / sheets is made of a different material than the remaining nanowires / sheets. Therefore, in practical applications, manufacturing all nanowires / sheets in the channel region requires at least two different types of semiconductor materials. Based on this, since nanowires / sheets formed from different semiconductor materials have different carrier mobilities and conductivity, when at least one layer of nanowires / sheets is made of a different material than the remaining nanowires / sheets, at least one of the at least two types of semiconductor materials used to manufacture all nanowires / sheets can be set to a high-mobility material such as germanium-silicon or germanium, which has a higher carrier mobility than the other at least one type of semiconductor material; or, at least one type of semiconductor material can be set to a channel material such as silicon, which has a lower carrier mobility than the other at least one type of semiconductor material, thereby enabling the control of the driving capability of the corresponding nanowire / sheet layer.

[0008] Furthermore, gate stacks with different thicknesses and / or materials have different threshold control capabilities. Therefore, when the thickness and / or material of different gate stacks located on the periphery of nanowires / sheets of different materials are different, it is convenient to set the thickness and / or material of the gate stacks on the periphery of the nanowires / sheets according to the threshold control requirements corresponding to the nanowires / sheets of different materials in practical applications. This facilitates the same or approximately the same conduction characteristics between the nanowires / sheets when the gate ring transistor is in the on state, improves the conduction uniformity between the nanowires / sheets in the channel region, and ultimately improves the driving performance of the gate ring transistor.

[0009] The present invention also provides a method for manufacturing a gate-around transistor, the method comprising:

[0010] Provide a semiconductor substrate.

[0011] An active structure is formed on a semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions. Along the thickness direction of the semiconductor substrate, the channel region includes at least two spaced nanowires / sheets. In the channel region, at least one nanowire / sheet is made of a material different from the materials of the remaining nanowires / sheets.

[0012] A gate stack structure is formed on a semiconductor substrate. The gate stack structure includes at least two gate stack layers, each gate stack layer surrounding the outer periphery of a corresponding nanowire / sheet. The thickness and / or material of the different gate stack layers located on the outer periphery of nanowires / sheets of different materials are different.

[0013] Compared with the prior art, the beneficial effects of the manufacturing method of the ring gate transistor provided by the present invention are the same as those of the ring gate transistor provided by the present invention, and will not be repeated here. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0015] Figure 1 This is a schematic diagram of the first structure after forming a fin-like structure on a semiconductor substrate in an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of the second structure after forming a fin-like structure on a semiconductor substrate in an embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram of the third structure after forming a fin-like structure on a semiconductor substrate in an embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of a structure after the sacrificial gate is formed in an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of a structure after the gate sidewall is formed in an embodiment of the present invention;

[0020] Figure 6 This is a longitudinal cross-sectional view of a structure after the gate sidewall is formed in an embodiment of the present invention, along the length of the fin-like structure.

[0021] Figure 7 This is a longitudinal cross-sectional view along the length of the fin structure in an embodiment of the present invention after removing the portions of the fin structure located in the first and second regions.

[0022] Figure 8 This is a longitudinal cross-sectional view of a structure after the source region and drain region are formed in an embodiment of the present invention, along the length of the fin-like structure.

[0023] Figure 9 This is a schematic diagram of a longitudinal cross-section along the length of the fin-like structure after the dielectric layer is formed in an embodiment of the present invention.

[0024] Figure 10 This is a schematic diagram of a longitudinal section along the length of the channel region after the formation of the channel region in an embodiment of the present invention.

[0025] Figure 11 This is a schematic longitudinal cross-sectional view of a structure after the formation of the grid stack material in an embodiment of the present invention, along the width direction of the channel region.

[0026] Figure 12This is a schematic diagram of a longitudinal section along the width direction of the channel region of a structure after the gate stack material has been etched back in an embodiment of the present invention.

[0027] Figure 13 Part (1) is a longitudinal cross-sectional view of the gate ring transistor along the length of the channel region provided in the embodiment of the present invention; Figure 13 Part (2) is a longitudinal cross-sectional view of the gate ring transistor along the width direction of the channel region provided in the embodiment of the present invention;

[0028] Figure 14 This is a flowchart illustrating a method for manufacturing a gate-ring transistor according to an embodiment of the present invention.

[0029] Reference numerals: 11 is semiconductor substrate, 12 is shallow trench isolation structure, 13 is fin structure, 131 is stacked layer, 1311 is sacrificial layer, 1312 is channel layer, 14 is first region, 15 is second region, 16 is third region, 17 is sacrificial gate, 18 is gate sidewall, 19 is source region, 20 is drain region, 21 is dielectric layer, 22 is channel region, 221 is nanowire / sheet, 23 is gate stacking material, 24 is gate stacking structure, 241 is gate stacking portion. Detailed Implementation

[0030] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0031] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] The gate stack structure of the gate ring transistor can be formed not only on the top of the channel region and the sidewalls along the width direction, but also on the bottom of the channel region. Therefore, the gate ring transistor has advantages such as higher gate control capability compared with planar transistors and fin field-effect transistors, which can improve the operating performance of semiconductor devices including the gate ring transistor.

[0036] However, when the channel region of a gate-around transistor (GMT) comprises multiple nanowires / sheets spaced apart along the thickness direction of the semiconductor substrate, the driving performance of the GMT is poor. Specifically, in a GMT, the source electrically connected to the source region is formed at the top of the source region, and the drain electrically connected to the drain region is formed at the top of the drain region. Therefore, along the thickness direction close to the semiconductor substrate, the spacing between each nanowire / sheet and the source and drain, respectively, is greater than the spacing between the other nanowire / sheet above it and the source and drain, respectively. Correspondingly, when the GMT is in the on state, the transmission path between the source and drain through the upper nanowire / sheet is shorter, while the transmission path through the lower nanowire / sheet is longer. Since the transmission path is proportional to the on-resistance, the on-resistance of each nanowire / sheet is greater than the on-resistance of the other nanowire / sheet above it. Under the influence of the on-resistance, the conduction uniformity between the nanowires / sheets is poor, which in turn leads to a deterioration in the driving performance of the GMT.

[0037] To address the aforementioned technical problems, embodiments of the present invention provide a gate-around transistor and a method for manufacturing the same. In the gate-around transistor provided by the present invention, the material of at least one layer of nanowires / sheets in the channel region is different from the materials of the remaining nanowires / sheets, and the thickness and / or material of different gate stack portions located on the outer periphery of the nanowires / sheets of different materials are different, thereby improving the conduction uniformity among the nanowires / sheets in the channel region and ultimately enhancing the driving performance of the gate-around transistor.

[0038] like Figure 13 As shown in sections (1) and (2) of this embodiment, the gate-ring transistor provided by this invention includes: a semiconductor substrate 11, an active structure, and a gate stack structure 24. The active structure is formed on the semiconductor substrate 11. The active structure includes a source region 19, a drain region 20, and a channel region 22 located between the source region 19 and the drain region 20. Along the thickness direction of the semiconductor substrate 11, the channel region 22 includes at least two layers of spaced nanowires / sheets 221. In the channel region 22, at least one layer of nanowires / sheets 221 is made of a material different from the other nanowires / sheets 221. The gate stack structure 24 is formed on the semiconductor substrate 11. The gate stack structure 24 includes at least two layers of gate stack portions 241, each layer of gate stack portion 241 surrounding the outer periphery of a corresponding layer of nanowires / sheets 221. The thickness and / or material of the different gate stack portions 241 located around the outer periphery of nanowires / sheets 221 made of different materials are different.

[0039] Specifically, the specific structure of the aforementioned semiconductor substrate can be set according to the actual application scenario. For example, the semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates on which no other structures are formed. As another example, if the gate-around transistor provided in this embodiment is applied to a second or higher layer gate-around transistor in an integrated circuit, the semiconductor substrate can at least include a semiconductor substrate, a first device structure formed on the semiconductor substrate, and a dielectric layer covering the first device structure. In this case, the materials of each part of the semiconductor substrate can be set according to actual needs, as long as they can be applied to the gate-around transistor provided in this embodiment.

[0040] For the aforementioned active structure, structurally, the channel region is located between the source and drain regions and contacts both regions. The channel region may consist of only two nanowire / sheet layers, or it may consist of three or more nanowire / sheet layers. The specific number of nanowire / sheet layers in the channel region can be set according to actual needs and is not specifically limited here. There are gaps between the bottom nanowire / sheet and the semiconductor substrate, as well as between adjacent nanowire / sheet layers. Each gate stack surrounds the outer periphery of its corresponding nanowire / sheet layer through these gaps; therefore, the height of each gap can be determined based on the specifications of the corresponding gate stack.

[0041] From a materials perspective, the active structure, including the source, drain, and channel regions, can be made of semiconductor materials such as silicon, silicon-germanium, germanium, or group III-V compounds. Specifically, the source and drain regions can be made of the same or different materials. When the source and drain regions are made of the same material, they can be formed simultaneously in a unified operation, simplifying the manufacturing process of the gate-around transistor.

[0042] Furthermore, the specific material of each nanowire / sheet in the channel region can be set according to actual needs, as long as the material of at least one nanowire / sheet in the channel region is different from the materials of the other nanowires / sheets. Specifically, when the channel region includes at least three nanowires / sheets, the materials of different nanowires / sheets can be completely different from each other, or at least two nanowires / sheets can be made of the same material. In this embodiment of the invention, there is no specific limitation on the number of types of semiconductor materials used to manufacture all nanowires / sheets in the channel region, or the number of nanowire / sheet layers under the same type of semiconductor material. In addition, when the channel region includes at least three nanowires / sheets, the distribution of nanowires / sheets with different materials can also be set according to actual needs, and is not specifically limited here.

[0043] It is worth noting that, as mentioned earlier, in the channel region, at least one layer of nanowires / sheets is made of a different material than the rest. Therefore, in practical applications, manufacturing all nanowires / sheets in the channel region requires at least two different types of semiconductor materials. Based on this, since nanowires / sheets made from different semiconductor materials have different carrier mobilities and conductivity, when at least one layer of nanowires / sheets is made of a different material than the rest, at least one of the two types of semiconductor materials used to manufacture all nanowires / sheets can be set to a high-mobility material such as germanium-silicon or germanium, which has a higher carrier mobility than the other at least one type of semiconductor material; or, at least one type of semiconductor material can be set to a channel material such as silicon, which has a lower carrier mobility than the other at least one type of semiconductor material, thereby enabling the control of the driving capability of the corresponding nanowire / sheet layer.

[0044] For example, if the channel region includes two layers of nanowires / sheets, and one layer of nanowires / sheets is made of silicon, the other layer of nanowires / sheets can be made of high-mobility materials such as germanium-silicon or germanium to improve the carrier mobility of the other layer of nanowires / sheets, thereby improving the driving capability of the other layer of nanowires / sheets.

[0045] For the above-mentioned gate stack structure, such as Figure 13 As shown in sections (1) and (2), the number of gate stack portions 241 included in the gate stack structure 24 is equal to the number of nanowire / sheet 221 included in the channel region 22. Each gate stack portion 241 surrounds the outer periphery of the corresponding nanowire / sheet 221. Furthermore, each gate stack portion 241 includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. Each gate dielectric layer surrounds the outer periphery of the corresponding channel region 22. Additionally, as... Figure 13 As shown in sections (1) and (2), a gate dielectric layer can also be formed between the gate at the bottom layer and the semiconductor substrate 11. Specifically, the material of the gate dielectric layer can be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate can be a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0046] It should be noted that the difference in thickness and / or material of different gate stacks located on the periphery of nanowires / sheets of different materials can mean that only the thickness and / or material of the gate dielectric layer is different in the different gate stacks located on the periphery of nanowires / sheets of different materials.

[0047] It can also refer to the fact that in different gate stacks located on the periphery of nanowires / sheets of different materials, only the thickness and / or material of the gate is different.

[0048] It can also refer to the following: the thickness and / or material of the gate dielectric layer in different gate stacks located on the periphery of nanowires / sheets of different materials are different, and the thickness and / or material of the gate electrode in different gate stacks located on the periphery of nanowires / sheets of different materials are also different.

[0049] Furthermore, in practical applications, all other things being equal, gate-around transistors with channel regions made of different materials exhibit different threshold voltages. Also, all other things being equal, gate-around transistors with gate dielectric layers of different materials and / or thicknesses exhibit different threshold voltages. And, all other things being equal, gate-around transistors with gates of different materials and / or thicknesses also exhibit different threshold voltages. Therefore, the threshold voltage of a gate-around transistor can be controlled by changing the material and / or thickness of the gate dielectric layer in the gate stack structure; and / or by changing the material and / or thickness of the gate in the gate stack structure.

[0050] In the above-described scenario, when the material of at least one nanowire / sheet in the channel region is different from that of the remaining nanowires / sheets, and the thickness and / or material of different gate stacks located around the nanowires / sheets of different materials are different, the different gate stacks located around the nanowires / sheets of different materials can be modified by changing the material and / or thickness of the gate dielectric layer in the different gate stacks located around the nanowires / sheets of different materials, or by changing the material and / or thickness of the gate in the different gate stacks located around the nanowires / sheets of different materials, or by simultaneously changing the material and / or thickness of the gate dielectric layer and the gate in the different gate stacks located around the nanowires / sheets of different materials. This allows the different gate stacks located around the nanowires / sheets of different materials to have different threshold modulation capabilities. This facilitates the formation of identical or substantially identical conduction characteristics among the nanowires / sheets in the channel region when the gate-around transistor is in the on state, improving the conduction uniformity among the nanowires / sheets in the channel region, and ultimately enhancing the driving performance of the gate-around transistor.

[0051] For example, when the channel region includes two nanowires / sheets, the gate materials and thicknesses of the two gate stacks formed on the outer peripheries of these two nanowires / sheets are the same. In this case, the gate dielectric layers of the two gate stacks are made of the same material but have different thicknesses; or, the gate dielectric layers of the two gate stacks are made of different materials but have the same thickness; or, the gate dielectric layers of the two gate stacks are made of different materials and have different thicknesses.

[0052] For example, when the channel region includes two nanowires / sheets, the gate dielectric layers of the two gate stacks formed on the outer peripheries of these two nanowires / sheets are made of the same material and have the same thickness. In this case, the gate materials of the two gate stacks are the same but their thicknesses are different; or, the gate materials of the two gate stacks are different but their thicknesses are the same; or, the gate materials and thicknesses of the two gate stacks are both different.

[0053] Preferably, the threshold voltages of different gate stacks are equal. In this case, all nanowires / sheets in the channel region can be in the conducting state at the same threshold voltage, that is, each nanowire / sheet has the same conduction characteristics, further improving the conduction uniformity between each nanowire / sheet, thereby ensuring that the gate-around transistor has good electrical conduction characteristics.

[0054] In one example, such as Figure 1 ,as well as Figure 13 As shown in parts (1) and (2), in the channel region 22, different layers of nanowires / sheets 221 of the same material are arranged adjacently. It is understood that the gate stack portions 241 on the periphery of the different layers of nanowires / sheets 221 of the same material are made of the same material. Based on this, when different layers of nanowires / sheets 221 of the same material are arranged adjacently, the different layers of gate stack portions 241 of the same material are also arranged adjacently. At this time, the positions of the different layers of gate stack portions 241 of the same material are relatively concentrated. When actually manufacturing the gate stack structure 24 included in the ring-gate transistor provided in this embodiment of the invention, as follows... Figure 11 and Figure 12 As shown, at least two layers of gate stack 241 made of the same material can be formed simultaneously in the same operation, without the need to form each layer of gate stack 241 separately in different operation steps, thereby simplifying the manufacturing process of the gate stack structure 24 and reducing the manufacturing cost of the gate stack structure 24.

[0055] In one example, such as Figure 2 and Figure 3 As shown, in the channel region, there is at least one additional layer of nanowires / sheets of a different material between two layers of nanowires / sheets of the same material. In this case, the distribution position of nanowires / sheets of different materials along the thickness direction of the semiconductor substrate 11 in the channel region is more flexible, which can improve the applicability of the embodiments of the present invention in different application scenarios.

[0056] Specifically, the number of nanowires / sheets of different materials between two layers of nanowires / sheets made of the same material can be set according to actual needs, and no specific limit is made here. For example: Figure 2 As shown, the number of nanowires / sheets is ordered from bottom to top and from smallest to largest. In the active structure fabricated with this fin structure 13, the first and fourth nanowire / sheet layers are made of the same material. The second and third nanowire / sheet layers are made of the same material. There are two nanowire / sheet layers between the first and fourth nanowire / sheet layers that are made of different materials. For example: Figure 3 As shown, in the active structure fabricated with this fin structure 13, the first and third layers of nanowires / sheets are made of the same material. The second and fourth layers of nanowires / sheets are made of the same material. There is a layer of nanowires / sheets made of a different material between the first and third layers of nanowires / sheets.

[0057] In addition, when there are at least two other nanowires / sheets of different materials between two layers of nanowires / sheets of the same material, the materials of the at least two nanowires / sheets in the middle can be the same or different.

[0058] It should also be noted that when the channel portion comprises at least three layers of nanowires / sheets, and at least two layers of nanowires / sheets are made of the same material, the thicknesses of the different gate stacks located on the periphery of the nanowires / sheets of the same material can be the same or different. Furthermore, the materials of the different gate stacks located on the periphery of the nanosheets / sheets of the same material can be the same or different. Specifically, the relationship between the thickness and material of the different gate stacks located on the periphery of the nanowires / sheets of the same material can be set according to the distribution relationship between the different nanowires / sheets of the same material and actual requirements; no specific limitations are imposed here.

[0059] For example: Figure 13 As shown in parts (1) and (2), when different nanowires / sheets 221 of the same material are adjacent and the conduction characteristics of different nanowires / sheets 221 of the same material meet the requirements of the actual application scenario, the material and thickness of different gate stacks 241 located on the periphery of the nanowires / sheets 221 of the same material can be the same.

[0060] For example: Figure 2 As shown, in the active structure manufactured with the fin structure 13, the first layer and the fourth layer of nanowires / sheets are made of the same material, but the spacing between the first layer and the fourth layer of nanowires / sheets is large. Therefore, when the conduction uniformity between the first layer and the fourth layer of nanowires / sheets does not meet the requirements of the actual application scenario, the materials and / or thicknesses of the two gate stacks located on the outer periphery of the first layer and the fourth layer of nanowires / sheets are different.

[0061] In one example, such as Figure 13 As shown in sections (1) and (2), the channel region 22 has at least two first-type nanowire / sheet groups distributed along the thickness direction of the semiconductor substrate 11, each first-type nanowire / sheet group including at least one layer of nanowire / sheet 221. Furthermore, different nanowires / sheets 221 within the same first-type nanowire / sheet group are made of the same material, while any two layers of nanowires / sheets 221 belonging to different first-type nanowire / sheet groups are made of different materials. In this case, the carrier mobility corresponding to each first-type nanowire / sheet group is greater than the carrier mobility corresponding to the other first-type nanowire / sheet group located above it.

[0062] Understandably, in practical applications, the source, electrically connected to the source region, is formed at the top of the source region, and the drain, electrically connected to the drain region, is formed at the top of the drain region. Therefore, along the thickness direction of the semiconductor substrate, in the at least two nanowire / sheet layers included in the channel region, the distance between the lower nanowire / sheet and the source and drain is larger, respectively. Correspondingly, when the gate-around transistor is in the on state, the transmission path between the source and drain through the lower nanowire / sheet is longer, resulting in a larger on-resistance in the lower nanowire / sheet. Based on this, when the carrier mobility corresponding to each first type of nanowire / sheet group is greater than the carrier mobility corresponding to the other first type of nanowire / sheet group above it, the carrier mobility of the lower first type of nanowire / sheet group is higher along the direction closer to the semiconductor substrate. This can increase the current in the lower nanowire / sheet, improve the driving capability of the lower nanowire / sheet, and further enhance the electrical performance of the gate-around transistor.

[0063] As can be seen from the above, the number of first-class nanowire / sheet groups included in the channel region, the number of nanowire / sheet layers included in each first-class nanowire / sheet group, and the specific materials of nanowires / sheets in each first-class nanowire / sheet group can be set according to the requirements of the driving capability of each layer of nanowires / sheets in the actual application scenario. No specific settings are made here.

[0064] For example, such as Figure 13 As shown in sections (1) and (2), when each layer of nanowire / sheet 221 contains germanium, the germanium content in each first-type nanowire / sheet group is greater than the germanium content in the other first-type nanowire / sheet group located above it. The difference in germanium content between adjacent first-type nanowire / sheet groups can be set according to actual needs. For example: Figure 13 As shown in sections (1) and (2), the channel region 22 includes two first-type nanowire / sheet groups, wherein the nanowire / sheet 221 included in the upper first-type nanowire / sheet group can be made of Si. 0.8 Ge 0.2 The first type of nanowire / sheet group located at the bottom includes nanowires / sheets 221 made of Si. 0.5 Ge 0.5 .

[0065] In one example, such as Figure 13As shown in sections (1) and (2), the aforementioned gate-around transistor further includes a shallow trench isolation structure 12, a gate sidewall 18, and a dielectric layer 21. The shallow trench isolation structure 12 is formed on the semiconductor substrate 11 to isolate different active regions of the semiconductor substrate 11, preventing leakage. The thickness of the shallow trench isolation structure 12 can be set according to actual conditions. The material of the shallow trench isolation structure 12 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. The gate sidewall 18 is formed at least on both sides of the gate stack structure 24 along its length to isolate the gate included in the gate stack structure 24 from other subsequently formed conductive structures, improving the electrical characteristics of the gate-around transistor. The material of the gate sidewall 18 can be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 21 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 24. In actual manufacturing, the presence of the dielectric layer 21 can protect the source region 19 and the drain region 20 from subsequent operations such as removing the portion of the sacrificial layer located in the third region, thereby improving the yield of the gate-around transistor. The dielectric layer 21 can be made of insulating materials such as silicon oxide or silicon nitride.

[0066] In one example, the aforementioned gate-ring transistor may further include an inner sidewall (not shown in the figure). This inner sidewall is formed between the gate stack structure and the source region, and between the gate stack structure and the drain region, to define the length of the gate stack structure. The material of the inner sidewall may be an insulating material such as silicon oxide or silicon nitride.

[0067] like Figure 14 As shown, this embodiment of the invention provides a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 1 to 13 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes:

[0068] First, a semiconductor substrate is provided. The structure and materials of this semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0069] like Figure 10 As shown, an active structure is formed on a semiconductor substrate 11. The active structure includes a source region 19, a drain region 20, and a channel region 22 located between the source region 19 and the drain region 20. Along the thickness direction of the semiconductor substrate 11, the channel region 22 includes at least two layers of spaced nanowires / sheets 221. In the channel region 22, the material of at least one nanowire / sheet 221 is different from the material of the remaining nanowires / sheets 221.

[0070] Specifically, the details of the source region, drain region, and channel region of the active structure mentioned above, including their specific structures and materials, can be found in the previous text and will not be repeated here.

[0071] In practical applications, forming an active structure on a semiconductor substrate may include the following steps:

[0072] like Figures 1 to 3 As shown, a fin structure 13 is formed on a semiconductor substrate 11. The fin structure 13 includes at least two stacked layers 131 distributed along the thickness direction of the semiconductor substrate 11. Each stacked layer 131 includes a sacrificial layer 1311 and a channel layer 1312 located on the sacrificial layer 1311. Among all the channel layers 1312, at least one channel layer 1312 is made of a material different from the materials of the other channel layers 1312. The material of each sacrificial layer 1311 is different from the materials of all the channel layers 1312.

[0073] Specifically, in the aforementioned fin structure, the channel layer is a film layer used to fabricate the nanowires / sheets included in the channel region. Therefore, the number of layers in the stacked fin structure, as well as the material and thickness of each channel layer, can be determined based on the number of nanowires / sheets included in the channel region and information such as the material and thickness of each nanowire / sheet. The aforementioned sacrificial layer is used to form the gaps between two adjacent nanowires / sheets and the gaps between the bottom nanowires / sheets and the semiconductor substrate. Therefore, the thickness of the sacrificial layer can be determined based on the specifications of each gate stack. Furthermore, the material of each sacrificial layer can be any semiconductor material different from the materials of all the channel layers. For example, when the channel region includes two nanowires / sheets, the fin structure includes two stacked layers. Specifically, one channel layer is made of Si, and the other channel layer is made of Si. 0.7 Ge 0.3 In this case, both sacrificial layers can be made of Si. 0.4 Ge 0.6 wait.

[0074] For example, epitaxial growth or similar processes can be used to first form at least two stacked material layers covering a semiconductor substrate. These stacked material layers are film layers used to fabricate the at least two stacked layers comprising the aforementioned fin structure. Next, photolithography and etching processes can be used to pattern the at least two stacked material layers and a portion of the semiconductor substrate to form fins on the semiconductor substrate. The etching depth of the semiconductor substrate can be determined based on the height of the subsequently formed shallow trench isolation structure, and is not specifically limited here. Finally, as... Figures 1 to 3 As shown, a shallow trench isolation structure 12 can be formed on a semiconductor substrate 11 using processes such as chemical vapor deposition and etching. The top height of the shallow trench isolation structure 12 is less than the bottom height of the sacrificial layer 1311 located at the bottom. The portion of the fin exposed outside the shallow trench isolation structure 12 is a fin structure 13. Along the length direction of the fin structure 13, the fin structure 13 has a first region 14, a second region 15, and a third region 16 located between the first region 14 and the second region 15.

[0075] like Figure 10 As shown, an active structure is formed based on a fin-like structure.

[0076] In practical applications, the manufacturing process of active structures varies depending on the order in which the source and drain regions of the active structure are formed, as well as the order in which the gate stack structure is formed.

[0077] For example, when using a gate-first process, the portion of the fin structure located in the third region can be processed first, under the masking effect of the corresponding mask layer, so that the portion of each channel layer located in the third region forms a corresponding nanowire / sheet. Then, a corresponding gate stack is formed on the outer periphery of each nanowire / sheet. Finally, the mask layer is removed, and the portions of the fin structure located in the first and second regions are processed to form the source and drain regions, thus obtaining the active structure.

[0078] For example, when using a back-gate process, the above-mentioned formation of an active structure based on a fin structure may include the following steps:

[0079] like Figures 4 to 6 As shown, processes such as chemical vapor deposition and etching can be used to form a sacrificial gate 17 and a gate sidewall 18 spanning the portion of the fin structure 13 corresponding to the third region 16. The gate sidewall 18 is located at least on both sides of the sacrificial gate 17 along its length. The material of the sacrificial gate 17 can be polysilicon or similar materials. The material and specifications of the gate sidewall 18 can be referred to the previous text and will not be repeated here.

[0080] like Figure 7 and Figure 8 As shown, the portions of the fin-like structure located in the first and second regions are processed to form the source region 19 and the drain region 20.

[0081] In practical applications, under the masking effect of the sacrificial gate and gate sidewalls, ion implantation can be used to directly process the portions of the fin structure located in the first and second regions to form the source and drain regions. Alternatively, as... Figure 7 As shown, under the masking effect of the sacrificial gate 17 and the gate sidewall 18, dry etching or wet etching processes can be used to remove the portion of the fin structure located in the first and second regions. Figure 8 As shown, source region 19 and drain region 20 can then be formed on both sides of the length of the portion corresponding to the third region of the fin structure using a source-drain epitaxy method.

[0082] like Figure 9 As shown, a dielectric layer 21 covering the semiconductor substrate 11 can be formed using processes such as chemical vapor deposition and chemical mechanical polishing. The top of the dielectric layer 21 is flush with the top of the sacrificial gate 17. The material of the dielectric layer 21 can be referred to the previous text and will not be repeated here.

[0083] like Figure 10 As shown, dry etching or wet etching processes can be used to remove the sacrificial gate; and the portion of each sacrificial layer located in the third region can be removed so that each channel layer forms a corresponding nanowire / sheet 221 to obtain an active structure.

[0084] like Figure 13 As shown in sections (1) and (2), after forming the channel region 22, a gate stack structure 24 is formed on the semiconductor substrate 11. This gate stack structure 24 includes at least two gate stack portions 241, each gate stack portion 241 surrounding the outer periphery of a corresponding nanowire / sheet 221. The thickness and / or material of the different gate stack portions 241 located around nanowires / sheets 221 of different materials are different. The structure and material of each gate stack portion 241 can be referred to the preceding text and will not be repeated here.

[0085] In practical applications, atomic layer deposition and etching processes can be used to form a gate stack around the periphery of each nanowire / sheet layer by layer in a bottom-up direction.

[0086] For example, such as Figure 10 As shown, the channel region 22 has at least two second-type nanowire / sheet groups distributed along the thickness direction of the semiconductor substrate 11, each second-type nanowire / sheet group including at least one layer of nanowire / sheet 221. Different nanowires / sheets 221 in the same second-type nanowire / sheet group are made of the same material, and any two layers of nanowires / sheets 221 in different second-type nanowire / sheet groups are made of different materials.

[0087] Specifically, the number of groups of the second type of nanowire / sheet in the channel region, and the number of layers of nanowires / sheets included in each group of the second type of nanowire / sheet, can be determined according to the actual application scenario. For example: Figure 13 As shown in sections (1) and (2), the channel region 22 includes the same material for the first and second layers of nanowires / sheets 221. The third and fourth layers of nanowires / sheets 221 are also made of the same material. However, the materials of the first and second layers of nanowires / sheets 221 are different from the materials of the third and fourth layers of nanowires / sheets 221. In this case, the channel region 22 includes two groups of second-type nanowires / sheets. Each group of second-type nanowires / sheets includes two layers of nanowires / sheets 221.

[0088] In the above-described case, forming a gate stack structure on a semiconductor substrate may include the following steps:

[0089] like Figure 11As shown, a gate stack material 23 can be formed around all the currently exposed second-type nanowires / sheets using processes such as atomic layer deposition. Among all the currently exposed second-type nanowires / sheets, the second-type nanowires / sheets located at the bottom layer are the target-type nanowires / sheets.

[0090] For example: Figure 10 As shown, after the formation of the channel region 22, both of the second-type nanowire / sheet groups included in the channel region 22 are exposed. At this time, the target nanowire / sheet group is the first layer of the second-type nanowire / sheet group.

[0091] like Figure 12 As shown, dry etching or wet etching processes can be used to etch back the gate stack material so that the remaining part of the gate stack material is only located on the outer periphery of the target nanowire / sheet group.

[0092] like Figure 13 As shown in parts (1) and (2) above, the above operation is repeated until a corresponding layer gate stack 241 is formed on the outer periphery of each nanowire / sheet 221, thereby obtaining a gate stack structure 24. Specifically, the number of times the above operation is repeated can be determined according to the number of groups of the second type of nanowire / sheet group in the channel region 22, and no specific limitation is made here.

[0093] Compared with the prior art, the beneficial effects of the manufacturing method of the ring gate transistor provided in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the ring gate transistor described above, and will not be repeated here.

[0094] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0095] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A gate-ring transistor, characterized in that, include: Semiconductor substrate, An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; along the thickness direction of the semiconductor substrate, the channel region includes at least two spaced nanowires / sheets; in the channel region of the same gate-around transistor, at least one nanowire / sheet is made of a material different from the other nanowires / sheets. A gate stack structure is formed on the semiconductor substrate; The gate stack structure includes at least two gate stacks, each of which surrounds the outer periphery of the corresponding layer of nanowires / sheets; in the same ring gate transistor, the thickness and / or material of the different gate stacks located on the outer periphery of nanowires / sheets of different materials are different, so that each layer of nanowires / sheets has the same conduction characteristics.

2. The gate-ring transistor according to claim 1, characterized in that, In the channel region, different layers of the nanowires / sheets of the same material are arranged adjacent to each other.

3. The gate-ring transistor according to claim 1, characterized in that, In the channel region, there is at least one additional layer of nanowires / sheets of different material between the two layers of nanowires / sheets of the same material.

4. The gate-ring transistor according to claim 1, characterized in that, The channel region has at least two first-type nanowire / sheet groups distributed along the thickness direction of the semiconductor substrate, each first-type nanowire / sheet group including at least one layer of nanowire / sheet; different nanowires / sheets in the same first-type nanowire / sheet group are made of the same material, and any two layers of nanowires / sheets in different first-type nanowire / sheet groups are made of different materials. The carrier mobility of each of the first type of nanowires / sheets is greater than that of the other first type of nanowires / sheets located above it.

5. The gate-ring transistor according to claim 4, characterized in that, When the material of each layer of the nanowires / sheets contains germanium, the germanium content in each of the first type of nanowires / sheets is greater than the germanium content in the other first type of nanowires / sheets located above it.

6. The gate-to-ring transistor according to any one of claims 1 to 5, characterized in that, The gates in different gate stacks located on the periphery of the nanowires / sheets of different materials have different materials and / or thicknesses.

7. A method for manufacturing a gate-ring transistor, characterized in that, include: Provide a semiconductor substrate; An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; along the thickness direction of the semiconductor substrate, the channel region includes at least two spaced nanowires / sheets; in the channel region, at least one nanowire / sheet is made of a material different from the material of the remaining nanowires / sheets. A gate stack structure is formed on the semiconductor substrate; the gate stack structure includes at least two gate stacks, each gate stack surrounding the outer periphery of the corresponding layer of nanowires / sheets; the thickness and / or material of the different gate stacks located on the outer periphery of nanowires / sheets of different materials are different, so that each layer of nanowires / sheets has the same conduction characteristics.

8. The method for manufacturing a gate-to-ring transistor according to claim 7, characterized in that, The formation of an active structure on the semiconductor substrate includes: A fin-like structure is formed on the semiconductor substrate; the fin-like structure includes at least two stacked layers distributed along the thickness direction of the semiconductor substrate; each stacked layer includes a sacrificial layer and a channel layer located on the sacrificial layer; of all the channel layers, at least one of the channel layers is made of a material different from the materials of the remaining channel layers; the material of each sacrificial layer is different from the materials of all the channel layers; The active structure is formed based on the fin-like structure.

9. The method for manufacturing a gate-to-ring transistor according to claim 8, characterized in that, Along the length of the fin-like structure, the fin-like structure has a first region, a second region, and a third region located between the first region and the second region; The formation of the active structure based on the fin-like structure includes: A sacrificial gate and a gate sidewall are formed across the portion of the fin structure corresponding to the third region; the gate sidewall is located at least on both sides of the sacrificial gate along its length. The portions of the fin-like structure located in the first and second regions are processed to form the source region and the drain region; A dielectric layer is formed covering the semiconductor substrate; the top of the dielectric layer is flush with the top of the sacrificial gate; Remove the sacrificial gate; and remove the portion of each sacrificial layer located in the third region, so that each channel layer forms the corresponding nanowire / sheet, thereby obtaining the active structure.

10. A method for manufacturing a gate-to-ring transistor according to any one of claims 7 to 9, characterized in that, The channel region has at least two second-type nanowire / sheet groups distributed along the thickness direction of the semiconductor substrate, each second-type nanowire / sheet group including at least one layer of nanowire / sheet; different nanowires / sheets in the same second-type nanowire / sheet group are made of the same material, and any two layers of nanowire / sheets in different second-type nanowire / sheet groups are made of different materials; The formation of the gate stack structure on the semiconductor substrate includes: A gate stack material is formed on the periphery of all currently exposed second-type nanowires / sheets; wherein, among all currently exposed second-type nanowires / sheets, the second-type nanowires / sheets located at the bottom layer are the target-type nanowires / sheets. The gate stack material is etched back so that the remaining portion of the gate stack material is located only on the outer periphery of the target nanowire / sheet assembly; Repeat the above operation until the corresponding gate stack portion is formed on the outer periphery of each layer of nanowires / sheets to obtain the gate stack structure.

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