Pixel Circuit and Display Device Including the Same

Abstract

A pixel circuit and a display device including the pixel circuit. The pixel circuit of the present disclosure includes: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate connected to a second node, and a second electrode connected to a third node, and configured to provide a current to a light-emitting element; a first switching element configured to provide a data voltage of pixel data to a fourth node in response to a scan pulse; a second switching element configured to provide an initialization voltage to the second node in response to a first initialization pulse; a third switching element configured to provide a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switching element configured to provide a reference voltage to the fourth node in response to a second initialization pulse; a fifth switching element configured to connect the third node to an anode of the light-emitting element in response to a light emission control pulse; a first capacitor; a second capacitor; and a third capacitor.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Art

[0002] According to the material of the light-emitting layer, an electroluminescent display device can be classified into an inorganic light-emitting display device and an organic light-emitting display. An active matrix organic light-emitting display device includes an organic light-emitting diode (OLED), and the organic light-emitting diode (OLED) generates light by itself and has advantages in terms of high response speed, high luminous efficiency, high brightness, and wide viewing angle. In an organic light-emitting display device, an OLED is formed at each pixel. The organic light-emitting display device has high response speed, high luminous efficiency, high brightness, and wide viewing angle, and can represent black grayscale with complete black, thereby achieving high contrast and high color reproducibility.

[0003] In the case of an internal compensation circuit using a source follower circuit, the change in the source node voltage is as much as the threshold voltage of the driving element, and the amount of change in the source node voltage can be transmitted to the gate node. However, when the amount of change in the source node voltage is transmitted to the gate node, loss may occur due to the parasitic capacitance of the gate node. Due to the difference in the transmission rate of the amount of change in the source node voltage to the gate node, an error may occur when sensing the threshold voltage of the driving element. Summary of the Invention

[0004] An object of the present disclosure is to solve the above necessity and / or problems.

[0005] The present disclosure provides a pixel circuit and a display device including the pixel circuit, which can improve image quality by overcoming the compensation limitation of the pixel circuit by using a source follower circuit.

[0006] The problems of the present disclosure are not limited to the above problems, and those skilled in the art will clearly understand other problems not mentioned from the following description.

[0007] A pixel circuit according to an embodiment of the present disclosure may include: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate connected to a second node, and a second electrode connected to a third node, and configured to provide a current to a light-emitting element; a first switching element configured to provide a data voltage of pixel data to a fourth node in response to a scan pulse; a second switching element configured to provide an initialization voltage to the second node in response to a first initialization pulse; a third switching element configured to provide a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switching element configured to provide the reference voltage to the fourth node in response to a second initialization pulse; a fifth switching element configured to connect the third node to an anode of the light-emitting element in response to a light emission control pulse; a first capacitor connected between the second node and the fourth node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the first node and the third node.

[0008] The display device of the present disclosure includes a pixel circuit.

[0009] In the present disclosure, by using the source follower method and using the first to third capacitors added to the pixel circuit, the threshold voltage compensation performance of the driving element can be improved, and the compensation range can be increased.

[0010] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0012] Figure 1 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0013] Figure 2 is showing the application to Figure 1 the gate signal waveform diagram of the pixel circuit shown in;

[0014] Figure 3 is showing Figure 1 the waveform diagram of the voltage change of the main node of the pixel circuit shown in;

[0015] Figures 4A to 4F is showing at Figure 1The operation circuit diagram of the pixel circuit shown in sub-steps;

[0016] Figure 5 The simulation results showing the threshold voltage compensation effect of the driving element in the pixel circuit of the present disclosure are shown;

[0017] Figure 6 It is a block diagram showing a display device according to an embodiment of the present disclosure;

[0018] Figure 7 It shows Figure 6 A cross-sectional view showing the cross-sectional structure of the display panel shown. Detailed implementation manners

[0019] According to the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the method for implementing the present disclosure will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only defined within the scope of the appended claims.

[0020] The shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. In addition, when describing the present disclosure, the detailed description of known prior art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0021] Terms such as "comprising", "including", "having", and "consisting of" used herein generally mean allowing the addition of other components, unless the term "only" is used when using the term. Unless otherwise expressly stated, any singular reference may include the plural.

[0022] Even if not explicitly stated, components are interpreted to include a normal error range.

[0023] When using terms such as "on", "above", "below", and "adjacent to" to describe the positional relationship between two components, unless the terms "immediately" or "directly" are used when using these terms, one or more components may be located between the two components.

[0024] Terms such as "first", "second", etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by the serial numbers or component names in front of the components.

[0025] Throughout the present disclosure, the same reference numerals may refer to substantially the same elements.

[0026] The following embodiments can be combined or combined partially or completely with each other, and can be connected and operated in technically different ways. These embodiments can be executed independently or in association with each other.

[0027] Each pixel may include a plurality of sub-pixels having different colors in order to reproduce the color of an image on the screen of the display panel. Each sub-pixel includes a transistor that serves as a switching element or a driving element. Such a transistor can be implemented as a TFT (Thin Film Transistor).

[0028] The driving circuit of the display device writes the pixel data of the input image to the pixels on the display panel. For this purpose, the driving circuit of the display device may include a data driving circuit configured to provide a data signal to a data line, a gate driving circuit configured to provide a gate signal to a gate line, and the like.

[0029] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors can be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polycrystalline silicon (LTPS) TFTs including low temperature polycrystalline silicon, and the like. In an embodiment, a description will be given based on an example in which the transistors of the pixel circuit and the gate driving circuit are implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0030] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode from which carriers leave the transistor. In the transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of the current is from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0031] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0032] The transistor turns on in response to a gate-on voltage and turns off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a strobe high voltage and the gate-off voltage may be a strobe low voltage.

[0033] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be mainly described with respect to an organic light-emitting display device, but the present invention is not limited thereto. The present disclosure is not limited to the names of elements or signals in the following examples and claims.

[0034] Figure 1 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure. Figure 2 is a waveform diagram showing a strobe signal applied to Figure 1 the pixel circuit shown in. Figure 3 is a waveform diagram showing Figure 1 the voltage change of the main nodes of the pixel circuit shown in. In Figure 3 the solid line waveforms of the main nodes DTG, DTS, and DTS2 represent the initial state in which the threshold voltage Vth of the driving element DT has not shifted, and the dotted line waveforms thereof represent an example in which the threshold voltage Vth of the driving element DT shifts due to the accumulation of the driving time of the pixel due to the deterioration of the driving element DT. Figures 4A to 4F is a circuit diagram showing the operation of the pixel circuit shown step by step in Figure 1 .

[0035] Referring to Figures 1 to 4F , the pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements T1 to T5, and a first capacitor Cst1, a second capacitor Cst2, and a third capacitor C2. The driving element DT and the switching elements T1 to T5 may be implemented by n-channel oxide TFTs.

[0036] The pixel circuit is connected to a VDD line to which a pixel driving voltage EVDD is applied, a VSS line to which a low-potential pixel reference voltage EVSS is applied, an INIT line to which an initialization voltage Vinit is applied, a REF line RL to which a reference voltage Vref is applied, a data line DL to which a data voltage Vdata is applied, and a strobe line to which strobe signals INIT, INIT2, SENSE, SCAN, and EM are applied.

[0037] The pixel driving voltage EVDD is higher than the data voltage Vdata and is a voltage at which the driving element DT can operate in the saturation region. The pixel driving voltage EVDD is set to a voltage of EVSS + Vel + Vgs + Virmargin. "Vel" is the anode voltage of the light-emitting element EL that drives the light-emitting element EL at maximum brightness. "Vgs" is the gate-source voltage of the driving element DT. "Virmargin" is a margin voltage for compensating the IR drop of the pixel driving voltage EVDD caused by the wiring resistance R on the display panel and the current I flowing through the pixel.

[0038] The initialization voltage Vinit can be set to a voltage obtained by adding a margin voltage considering the threshold voltage compensation range of the driving element DT to the reference voltage Vref. The initialization voltage Vinit is higher than the reference voltage Vref. The reference voltage Vref is set to a low-potential voltage close to the low-potential pixel reference voltage EVSS. The reference voltage Vref can be lower than the low-potential pixel reference voltage EVSS.

[0039] The gate-on voltages VGH and VEH of the gate signals INIT, INIT2, SENSE, SCAN, and EM can be higher than the pixel driving voltage EVDD and can be set to the minimum gate-on voltage at which the data voltage Vdata can vary within the expressible gray-scale range to reduce power consumption. The gate-off voltages VGL and VEL of the gate signals INIT, INIT2, SENSE, SCAN, and EM can be lower than the low-potential pixel reference voltage EVSS and the reference voltage Vref and can be set to a voltage within the EVSS tolerance.

[0040] As Figure 2 and Figure 3 shown, the driving period of the pixel circuit can be divided into an initialization step Pi, a sensing step Ps, a first transfer step Ptr1, a data writing step Pwr, a second transfer step Ptr2, a boosting step Pboost, and a light-emitting step Pem. In Figure 3 this, "ΔVth" described in the second node DTG, the third node DTS, and the fourth node DTS2 is the voltage change amount of the threshold voltage in the driving element DT.

[0041] In the initialization step Pi, a first initialization pulse INIT, a sensing pulse SENSE, and a second initialization pulse IINIT2 are generated as the gate-on voltage VGH. In the initialization step Pi, the scan pulse SCAN and the light-emitting control pulse (hereinafter referred to as the "EM pulse") EM are the gate-off voltages VGL and VEL.

[0042] In the sensing step Ps, a first initialization pulse INIT is generated as the gate-on voltage VGH. The sensing pulse SENSE, the second initialization pulse INIT2, the scan pulse SCAN, and the EM pulse EM are the gate-off voltages VGL and VEL in the sensing step Ps.

[0043] In the first transfer step Ptr1, a second initialization pulse INIT2 is generated as the gate-on voltage VGH. The first initialization pulse INIT, the sensing pulse SENSE, the scan pulse SCAN, and the EM pulse EM are the gate-off voltages VGL and VEL in the first transfer step Ptr1.

[0044] In the data writing step Pwr, a scan pulse SCAN is generated as the gate-on voltage VGH synchronized with the data voltage Vdata of the pixel data. In the data writing step Pwr, the first initialization pulse INIT, the sensing pulse SENSE, the second initialization pulse INIT2, and the EM pulse EM are generated as the gate-off voltages VGL and VEL.

[0045] In the second transfer step Ptr2, a sensing pulse SENSE is generated as the gate-on voltage VGH. The first initialization pulse INIT, the second initialization pulse INIT2, the scan pulse SCAN, and the EM pulse EM are the gate-off voltages VGL and VEL in the second transfer step Ptr2.

[0046] In the boosting step Pboost, an EM pulse EM is generated as the gate-on voltage VEH, and the strobe signals INIT, SENSE, INIT2, and SCAN other than the EM pulse EM are generated as the gate-off voltage VGL. In the light emitting step Pem, the EM pulse EM maintains the gate-on voltage VEH, while the other strobe signals INIT, SENSE, INIT2, and SCAN maintain the gate-off voltage VGL.

[0047] The light-emitting element EL can be implemented using an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons. In this case, visible light is emitted from the emission layer EML. The OLED used as the light-emitting element EL may have a tandem structure in which a plurality of emission layers are stacked. The OLED having the tandem structure can improve the brightness and lifetime of the pixel. The anode of the light-emitting element EL is connected to the second electrode of the fifth switching element T5. When the fifth switching element T5 is turned on in response to the gate conduction voltage VEH of the EM pulse EM, the anode of the light-emitting element EL is connected to the third node DTS. The low-potential pixel reference voltage EVSS is applied to the cathode of the light-emitting element EL. The light-emitting element EL includes a capacitor connected between the anode and the cathode. The capacitor of the light-emitting element EL is omitted in the drawings.

[0048] The driving element DT generates a current according to the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a first electrode connected to the first node DRD, a gate connected to the second node DTG, and a second electrode connected to the third node DTS. The first node DRD may be connected to the VDD line, and the pixel driving voltage EVDD is applied through the VDD line. An EM switching element may be added between the first node DRD and the VDD line. The EM switching element may be turned on / off in response to a second EM pulse to switch the current path between the VDD line and the first node DRD.

[0049] The first capacitor Cst1 is connected between the second node DTG and the fourth node DTS2. The second capacitor Cst2 is connected between the third node DTS and the fourth node DTS2. The third capacitor C2 is connected between the first node DRD and the third node DTS. In the first transfer step Ptr1, the first capacitor Cst1 stores a primary transfer value for transferring the voltage of the third node DTS to the second node DTG, and transfers the data voltage Vdata of the pixel data to the second node DTG. The secondary transfer value is stored in the sum of the capacitances of the first capacitor and the second capacitor (Cst1 + Cst2). The third capacitor C2 controls the primary transfer rate and the secondary transfer rate. The first capacitor Cst1 and the second capacitor Cst2 may be set to have a capacitance larger than that of the third capacitor C2. The second capacitor Cst2 may be set to have the same capacitance as the first capacitor Cst1, or may be set to have a capacitance different from that of the first capacitor Cst1.

[0050] In the present disclosure, the primary transmittance and the secondary transmittance are adjusted by the ratios of the capacitors Cst1, Cst2, and C2 of the pixel circuit. When the voltage of the third node DTS set in the sensing step Ps is transmitted to the second node DTG, considering the transmission loss of the parasitic capacitance Cgpara of the second node DTG, the capacitors Cst1, Cst2, and C2 allow 100% of the threshold voltage Vth of the driving element DT to be transmitted to the second node DTG.

[0051] The switching elements T1 to T5 of the pixel circuit include a first switching element T1 for supplying the data voltage Vdata of the pixel data to the fourth node DTS2 in response to the scan pulse SCAN, a second switching element T2 for supplying the initialization voltage Vinit to the second node DTG in response to the first initialization pulse INIT, a third switching element T3 for supplying a reference voltage Vref lower than the initialization voltage Vinit to the third node DTS in response to the sensing pulse SENSE, a fourth switching element T4 for supplying the reference voltage Vref to the fourth node DTS2 in response to the second initialization pulse INIT2, and a fifth switching element T5 for connecting the third node DTS to the anode of the light-emitting element EL in response to the EM pulse EM.

[0052] In the data writing step Pwr, the first switching element T1 is turned on in response to the gate conduction voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata of the pixel data, so as to connect the data line DL to the fourth node DTS2. The data voltage Vdata is applied to the fourth node DTS2 in the data writing step Pwr. The first switching element T1 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate connected to the first gate line to which the scan pulse SCAN is applied, and a second electrode connected to the fourth node DTS2.

[0053] In the initialization step Pi and the sensing step Ps, the second switching element T2 is turned on in response to the gate conduction voltage VGH of the first initialization pulse INIT, so as to supply the initialization voltage Vinit to the second node DTG. The second switching element T2 includes a first electrode connected to the INIT line to which the initialization voltage Vinit is applied, a gate connected to the second gate line to which the first initialization pulse INIT is applied, and a second electrode connected to the second node DTG.

[0054] In the initialization step Pi, the third switching element T3 is turned on in response to the gate conduction voltage VGH of the sense pulse SENSE to supply the reference voltage Vref to the third node DTS. The third switching element T3 includes a first electrode connected to the third node DTS, a gate connected to the third gate line to which the sense pulse SENSE is applied, and a second electrode connected to the REF line RL to which the reference voltage Vref is applied.

[0055] In the initialization step Pi, the fourth switching element T4 is turned on in response to the gate conduction voltage VGH of the second initialization pulse INIT2 to supply the reference voltage Vref to the fourth node DTS2. The fourth switching element T4 includes a first electrode connected to the fourth node DTS2, a gate connected to the fourth gate line to which the second initialization pulse INIT2 is applied, and a second electrode connected to the REF line RL to which the reference voltage Vref is applied.

[0056] In the boosting step Pboost and the light-emitting step Pem, the fifth switching element T5 is turned on in response to the gate conduction voltage VEH of the EM pulse EM to connect the third node DTS to the anode of the light-emitting element EL. The fifth switching element T5 includes a first electrode connected to the third node DTS, a gate connected to the fifth gate line to which the EM pulse EM is applied, and a second electrode connected to the anode of the light-emitting element EL.

[0057] In the initialization step Pi, as Figure 4A shown, the second switching element T2, the third switching element T3, and the fourth switching element T4 and the driving element DT are turned on, and the first switching element T1 and the fifth switching element T5 are turned off. In this case, the light-emitting element EL is not turned on. In the initialization step Pi, the main nodes of the pixel circuit are initialized. In the initialization step Pi, the voltage of the second node DTG is initialized to the initialization voltage Vinit, and the voltages of the third node DTS and the fourth node DTS2 are initialized to the reference voltage Vref. In the initialization step Pi, as Figure 3 shown, the voltage of the third node DTS increases from the reference voltage Vref by the current flowing through the driving element DT, and the voltages of the third node DTS and the fourth node DTS2 of the coupling capacitor also increase.

[0058] As Figure 3 shown, the threshold voltage of the driving element DT may shift due to stress accumulation (e.g., positive bias temperature stress (PBTS)) of the driving element DT. In the Figure 3 example, for example, "ΔVth" in the initial state of the threshold voltage Vth represents the change in the threshold voltage of the driving element DT. In the sensing step Ps, the threshold voltage Vth of the driving element DT is sampled for each pixel.

[0059] In the sensing step Ps, as Figure 4B shown, the second switching element T2 is turned on, while the other switching elements T1, T3, T4, and T5 except for the second switching element T2 are turned off. In the sensing step Ps, when the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the increase in the voltages of the third node DTS and the fourth node DTS2 stops. In the sensing step Ps, the voltage of the second node DTG is maintained at the initialization voltage Vinit. At the end point of the sensing step Ps, the voltage of the third node DTS reaches the value Vinit - Vth, and the voltage of the fourth node DTS2 is the value A(Vinit - Vth - Vref). Here, "A" is the ratio of the first capacitor Cst1 and the second capacitor Cst2, and

[0060] In the first transfer step Ptr1, as Figure 4C shown, the fourth switching element T4 is turned on, while the other switching elements T1, T2, T3, and T5 except for the fourth switching element T4 are turned off. In the first transfer step Ptr1, the voltage of the fourth node DTS2 is reduced to the reference voltage Vref, and the voltage of the third node DTS is reduced to the value Vinit - Vth - AC(Vinit - Vth - Vref). In the first transfer step Ptr1, the voltage of the third node DTS is transferred to the second node DTG as a voltage multiplied by the capacitor ratio including the parasitic capacitance Cgpara of the second node DTG. At the end point of the first transfer step Ptr1, the voltage of the second node DTG is the value Vinit - AB(Vinit - Vth - Vref). Among the voltages of the second node DTG and the third node DTS,

[0061] In the data writing step Pwr, as Figure 4D shown, the first switching element T1 is turned on, while the other switching elements T2, T3, T4, and T5 except for the first switching element T1 are turned off. In this case, the data voltage Vdata of the pixel data is applied to the second node DTG, such that the voltage of the second node DTG rises, and the voltages of the third node DTS and the fourth node DTS2 capacitively coupled to the second node DTG also rise. In the data writing step Pwr, the voltage of the fourth node DTS2 changes to the data voltage Vdata. At the end point of the data writing step Pwr, the voltage of the second node DTG is the value Vinit - AB(Vinit - Vth - Vref) + B(Vdata - Vref), and the voltage of the third node DTS is the value Vinit - Vth - AC(Vinit - Vth - Vref) + C(Vdata - Vref).

[0062] In the second transfer step Ptr2, as Figure 4E shown, the third switching element T3 is turned on, while the other switching elements T1, T2, T4, and T5 except for the third switching element T3 are turned off. In the second transfer step Ptr2, the voltage of the third node DTS is reduced to the reference voltage Vref, and the voltage of the fourth node DTS2 connected to the third node DTS through a capacitor is also reduced. At the end point of the second transfer step Ptr2, the voltage of the second node DTG is the value of (1 - AB - D + ACD)Vinit + (AB + D - ACD)Vth + (B - CD)Vdata - (AB - B - ACD + DC + D)Vref. Here,

[0063] During the boosting step Pboost, as Figure 4F shown, the fifth switching element T5 is turned on, and the other switching elements T1, T2, T3, and T4 except for the fifth switching element T5 are turned off. During the boosting step Pboost, the voltage of the third node DTS rises, and the voltages of the second node DTG and the fourth node DTS2 that have been floating also rise. In the boosting step Pboost, the capacitor of the light-emitting element EL is charged. In the light-emitting step Pem, as Figure 4F shown, the current generated according to the gate-source voltage Vgs of the driving element DT flows through the light-emitting element EL, enabling the light-emitting element EL to emit light.

[0064] The strobe signals INIT, INIT2, SENSE, and SCAN other than the EM pulse EM are the gate cut-off voltage VGL. During the boosting step Pboost, the voltages of the second node DTG, the third node DTS, and the fourth node DTS2 that have been floating rise.

[0065] In the light-emitting step Pem, as Figure 4F shown, the fifth switching element T5 remains in the on state, and the first to fourth switching elements T1 to T4 remain in the off state. In this case, the current generated according to the gate-source voltage Vgs of the driving element DT (i.e., the voltage between the second node and the third node) can be supplied to the light-emitting element EL to allow the light-emitting element EL to emit light.

[0066] In the present disclosure, considering the parasitic capacitance Cgpara of the second node DTG, the voltage of the third node DTS is transferred to the second node DTG in the first transfer step Ptr1 and the second transfer step Ptr2, thereby improving the threshold voltage compensation performance of the device DT and increasing the compensation range.

[0067] Figure 5These are the simulation results for verifying the threshold voltage compensation effect of the driving element DT in the pixel circuit of the present disclosure. In this simulation, the capacitors Cst1, Cst2, and C2 are respectively set to 100 [f], 100 [f], and 40 [f]. In Figure 5 the horizontal axis represents the change ΔVth in the threshold voltage of the driving element DT, and the vertical axis represents the change ΔIOLED in the current flowing through the light-emitting element EL. As can be seen from Figure 5 the simulation results show that even when the threshold voltage Vth of the driving element DT in the pixel circuit of the present disclosure changes greatly, the amount of current flowing through the light-emitting element EL is constant. Therefore, the threshold voltage Vth of the driving element DT can be compensated within a relatively large compensation range.

[0068] Figure 6 This is a block diagram showing a display device according to an embodiment of the present disclosure. Figure 7 This is a diagram showing Figure 6 the cross-sectional structure of the display panel shown.

[0069] Referring to Figure 6 and Figure 7 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to the pixels of the display panel 100, and a power supply unit 140 for generating the power required to drive the pixels and the display panel driver.

[0070] The display panel 100 may be a display panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array for displaying an input image on the screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the plurality of data lines 102, and pixels arranged in a matrix. The display panel 100 may further include a power supply line commonly connected to the pixels. The power supply line supplies a constant voltage or a DC voltage required to drive the pixels 101 to the pixels 101. The power supply line may include a VDD line for applying a pixel driving voltage EVDD, an INIT line for applying an initialization voltage Vinit, a REF line for applying a reference voltage Vref, and a VSS line for applying a low-potential power supply voltage ELVSS.

[0071] The cross-sectional structure of the display panel 100 includes a circuit layer 12, a light-emitting element layer 14, and a packaging layer 16 stacked on a substrate 10, as shown in Figure 7 .

[0072] The circuit layer 12 may include a thin film transistor (TFT) array, a demultiplexer array 112, a gate driver 120, etc. The thin film transistor (TFT) array includes pixel circuits connected to interconnections such as data lines, gate lines, power supply lines, etc. The interconnections and circuit elements of the circuit layer 12 may include multiple insulating layers, two or more metal layers separated from each other, and an active layer including a semiconductor material, and the insulating layers are located between the two or more metal layers. All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs.

[0073] The light-emitting element layer 14 may include light-emitting elements EL driven by the pixel circuits. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. In another embodiment, the light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a multilayer protective layer including an organic film and an inorganic film.

[0074] The encapsulation layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 may be a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film prevents the penetration of moisture or oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so the penetration of moisture and oxygen that may affect the light-emitting element layer 14 can be effectively prevented.

[0075] Although not shown, a touch sensor layer is formed on the encapsulation layer 16, and a polarizing plate or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on capacitance changes before and after an input touch input. The touch sensor layer may include metal interconnection patterns and insulating films that form the capacitance of the touch sensor. The insulating film may insulate the cross-sectional portions of the metal interconnection patterns and planarize the surface of the touch sensor layer. The polarizing plate may convert the polarization of external light reflected from the metals of the touch sensor layer and the circuit layer to improve visibility and contrast. The polarizing plate may be implemented as a linear polarizing plate or a circular polarizing plate in which a linear polarizing plate and a phase retardation film are bonded to each other. A cover glass may be adhered to the polarizing plate. The color filter layer may include a red color filter, a green color filter, and a blue color filter. The color filter layer may further include a black matrix pattern. The color filter layer may absorb some light reflected from the circuit layer and the touch sensor layer rather than the polarizing plate, and increase the color purity of the image reproduced on the pixel array.

[0076] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes pixels in the first row arranged in the row direction (X-axis direction) on the pixel array of the display panel 100. The pixels arranged in the first pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing the first frame period by the total number of the pixel rows L1 to Ln.

[0077] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel is suitable for a transparent display device that displays an image on the screen and allows the real background to be seen. The display panel 100 can be manufactured as a flexible display panel.

[0078] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color reproduction. Each pixel can also include a white sub-pixel. Each sub-pixel can include Figures 2 to 4F the pixel circuit shown. Hereinafter, a pixel can be interpreted to have the same meaning as a sub-pixel. Each pixel circuit is connected to a data line, a gate line, and a power supply line.

[0079] Pixels can be arranged as true color pixels and pentile pixels. By driving two sub-pixels with different colors as one pixel 101 using a preset pixel rendering algorithm, the pentile pixels can achieve a higher resolution than the true color pixels. The pixel rendering algorithm can utilize the color of the light emitted from adjacent pixels to compensate for the insufficient color representation in each pixel.

[0080] The power supply unit 140 generates the DC voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driver by using a DC-DC converter. The DC-DC converter can include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 can adjust the level of the DC input voltage applied from a host system (not shown) to generate constant voltages such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, a low-potential pixel reference voltage EVSS, an initialization voltage Vinit, and a reference voltage Vref. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and VEH and the gate-off voltage VGL and VEL are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage EVDD, the low-potential pixel reference voltage EVSS, the initialization voltage Vinit, and the reference voltage Vref are supplied to the pixel 101 through the power supply line commonly connected to the pixel 101.

[0081] The display panel driver writes the pixel data of the input image to the pixels of the display panel 100 under the control of the timing controller 130.

[0082] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0083] The demultiplexer array 112 sequentially supplies the data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers DEMUX. The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the data lines 102 and the output terminals of the data driver 110, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0084] The display panel driver may further include a touch sensor driver for driving a touch sensor. Figure 6 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into one driving integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, etc. may be integrated into one driving IC.

[0085] The display panel driver may operate in a low-speed driving mode under the control of the timing controller 130. The low-speed driving mode may be set to reduce the power consumption of the display device when the input image has not changed a preset number of frames as a result of analyzing the input image. In the low-speed driving mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by reducing the refresh rate of the pixels. The low-speed driving mode is not limited to when a still image is input. For example, when the display device is operating in a standby mode, or when a user command or an input image has not been input to the display panel driver for a predetermined time or longer, the display panel driver may operate in the low-speed driving mode.

[0086] The data driver 110 receives the pixel data of the input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC) during each frame period to generate a data voltage Vdata. The gamma reference voltage VGMA is divided into gamma-compensated voltages for each gray level by a voltage divider circuit. The gamma-compensated voltage for each gray level is supplied to the DAC of the data driver 110. The data voltage Vdata is output from each channel of the data driver 110 through an output buffer.

[0087] The gate driver 120 may be implemented as an in-panel gate (GIP) circuit formed in the circuit layer 12 on the display panel 100 together with the wiring of the pixel array and the TFT array. The gate driver 120 may be disposed in the bezel BZ, which is a non-display area of the display panel 100, or may be disposed distributively in the pixel array for reproducing the input image. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may shift the gate signals by using a shift register to sequentially supply the signals to the gate lines 103. The gate signals may include various gate signals such as a scan pulse, a sense pulse, a first initialization pulse, a second initialization pulse, and an EM pulse.

[0088] To drive Figure 1 the pixel circuit shown, the gate driver 120 may include a first shift register that sequentially outputs a scan pulse SCAN, a second shift register that sequentially outputs a sense pulse SENSE, a third shift register that sequentially outputs a first initialization pulse INIT, a fourth shift register that sequentially outputs a second initialization pulse INIT2, and a fifth shift register that sequentially outputs an EM pulse EM.

[0089] The timing controller 130 receives digital video data DATA of the input image and a timing signal synchronized with the digital video data DATA from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period 1H.

[0090] The host system may be any one of a television (TV) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale the image signal from the video source to fit the resolution of the display panel 100 and send it to the timing controller 130 together with the timing signal.

[0091] In the normal driving mode, the timing controller 130 may multiply the input frame frequency by i (i is a natural number) times to control the operation timing of the display panel driver with a frame frequency of input frame frequency × i Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase Alternating Line (PAL) method.

[0092] The timing controller 130 reduces the frequency of the frame rate at which pixel data is written to the pixels in the low-speed driving mode compared to the normal driving mode. For example, a data refresh frame rate at which pixel data is written to the pixels in the normal driving mode can be generated at a frequency of 60 Hz or higher (e.g., a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz), and the data refresh frame DRF in the low-speed driving mode can be generated at a refresh rate lower than the refresh rate of the normal driving mode. The timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame rate to a frequency between 1 Hz and 30 Hz so as to reduce the refresh rate of the pixels in the low-speed driving mode.

[0093] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0094] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter can receive the gate timing control signal to generate a start pulse and a shift clock and supply them to the shift register of the gate driver 120.

[0095] The objects to be achieved by the present disclosure, the means for achieving these objects, and the effects of the present disclosure described above do not specify the basic features of the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0096] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

[0097] Cross-reference to related applications

[0098] This application claims the priority and benefit of Korean Patent Application No. 10-2021-0117533, filed on September 3, 2021, and Korean Patent Application No. 10-2021-0176373, filed on December 10, 2021, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A pixel circuit, the pixel circuit comprising: A driving element, the driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate connected to a second node, and a second electrode connected to a third node, and configured to provide current to a light-emitting element; A first switching element, the first switching element configured to provide a data voltage of pixel data to a fourth node in response to a scan pulse; A second switching element, the second switching element configured to provide an initialization voltage to the second node in response to a first initialization pulse; A third switching element, the third switching element configured to provide a reference voltage lower than the initialization voltage to the third node in response to a sense pulse; A fourth switching element, the fourth switching element configured to provide the reference voltage to the fourth node in response to a second initialization pulse; A fifth switching element, the fifth switching element configured to connect the third node to an anode of the light-emitting element in response to a light emission control pulse; A first capacitor, the first capacitor connected between the second node and the fourth node; A second capacitor, the second capacitor connected between the third node and the fourth node; And A third capacitor, the third capacitor connected between the first node and the third node, Wherein, a driving period of the pixel circuit includes an initialization step, a sensing step, a first transfer step, a data writing step, a second transfer step, a boosting step, and a light emission step, In the first transfer step, the second initialization pulse is generated as a gate conduction voltage, and the first initialization pulse, the sense pulse, the scan pulse, and the light emission control pulse are generated as gate cut-off voltages, In the data writing step, the scan pulse is generated as a gate conduction voltage synchronized with the data voltage, and the first initialization pulse, the sense pulse, the second initialization pulse, and the light emission control pulse are generated as the gate cut-off voltages, In the second transfer step, the sense pulse is generated as the gate conduction voltage, and the first initialization pulse, the second initialization pulse, the scan pulse, and the light emission control pulse are generated as the gate cut-off voltages, and Each of the first switching element, the second switching element, the third switching element, the fourth switching element, and the fifth switching element is turned on in response to the gate conduction voltage and turned off in response to the gate cut-off voltage.

2. The pixel circuit according to claim 1, wherein The capacitance of each of the first capacitor and the second capacitor is greater than the capacitance of the third capacitor.

3. The pixel circuit according to claim 1, wherein, The pixel driving voltage is higher than the data voltage and the initialization voltage, The gate conduction voltage of each of the scan pulse, the first initialization pulse, the sense pulse, the second initialization pulse, and the light emission control pulse is higher than the pixel driving voltage, and The gate cut-off voltage of each of the scan pulse, the first initialization pulse, the sense pulse, the second initialization pulse, and the light emission control pulse is lower than the reference voltage.

4. The pixel circuit according to claim 3, wherein, The anode of the light-emitting element is connected to the fifth switching element, and the light-emitting element further includes: An anode connected to the fifth switching element; and A cathode to which a low-potential pixel reference voltage lower than the reference voltage is applied.

5. The pixel circuit according to claim 1, wherein, The first switching element includes a first electrode to which the data voltage is applied, a gate to which the scan pulse is applied, and a second electrode connected to the fourth node. The second switching element includes a first electrode to which the initialization voltage is applied, a gate to which the first initialization pulse is applied, and a second electrode connected to the second node. The third switching element includes a first electrode connected to the third node, a gate to which the sense pulse is applied, and a second electrode to which the reference voltage is applied. The fourth switching element includes a first electrode connected to the fourth node, a gate to which the second initialization pulse is applied, and a second electrode to which the reference voltage is applied, and The fifth switching element includes a first electrode connected to the third node, a gate to which the light-emission control pulse is applied, and a second electrode connected to the anode of the light-emitting element.

6. The pixel circuit according to claim 1, wherein, In the initialization step, the first initialization pulse, the sense pulse, and the second initialization pulse are generated as gate-on voltages, and the scan pulse and the light-emission control pulse are generated as gate-off voltages. In the sensing step, the first initialization pulse is generated as the gate-on voltage, and the sense pulse, the second initialization pulse, the scan pulse, and the light-emission control pulse are generated as the gate-off voltages. In the boosting step and the light-emission step, the light-emission control pulse is generated as the gate-on voltage, and the first initialization pulse, the sense pulse, the second initialization pulse, and the scan pulse are generated as the gate-off voltages.

7. A display device, the display device including: A display panel on which a plurality of pixel circuits are provided; A data driver configured to generate a data voltage of pixel data; And A gate driver configured to generate a first initialization pulse, a sense pulse, a second initialization pulse, a scan pulse, and a light-emission control pulse to be applied to a gate line, wherein Each pixel circuit in the pixel circuits includes: A driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate connected to a second node, and a second electrode connected to a third node, and configured to provide a current to the light-emitting element; A first switching element configured to provide the data voltage of the pixel data to a fourth node in response to the scan pulse; A second switching element configured to provide an initialization voltage to the second node in response to the first initialization pulse; A third switching element configured to provide a reference voltage lower than the initialization voltage to the third node in response to the sense pulse. A fourth switching element configured to supply the reference voltage to the fourth node in response to the second initialization pulse; A fifth switching element configured to connect the third node to the anode of the light-emitting element in response to the light emission control pulse; A first capacitor connected between the second node and the fourth node; A second capacitor connected between the third node and the fourth node; and A third capacitor connected between the first node and the third node, wherein a driving period of the pixel circuit includes an initialization step, a sensing step, a first transfer step, a data writing step, a second transfer step, a boosting step, and a light emission step, in the first transfer step, the second initialization pulse is generated as a gate-on voltage, and the first initialization pulse, the sensing pulse, the scan pulse, and the light emission control pulse are generated as gate-off voltages, in the data writing step, the scan pulse is generated as a gate-on voltage synchronized with the data voltage, and the first initialization pulse, the sensing pulse, the second initialization pulse, and the light emission control pulse are generated as the gate-off voltages, in the second transfer step, the sensing pulse is generated as the gate-on voltage, and the first initialization pulse, the second initialization pulse, the scan pulse, and the light emission control pulse are generated as the gate-off voltages, and each of the first switching element, the second switching element, the third switching element, the fourth switching element, and the fifth switching element is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage.

8. The display device according to claim 7, wherein, The capacitance of each of the first capacitor and the second capacitor is greater than the capacitance of the third capacitor.

9. The display device according to claim 7, wherein, The pixel driving voltage is higher than the data voltage and the initialization voltage, the gate-on voltage of each of the scan pulse, the first initialization pulse, the sensing pulse, the second initialization pulse, and the light emission control pulse is higher than the pixel driving voltage, and the gate-off voltage of each of the scan pulse, the first initialization pulse, the sensing pulse, the second initialization pulse, and the light emission control pulse is lower than the reference voltage.

10. The display device according to claim 9, wherein, The anode of the light-emitting element is connected to the fifth switching element, and the light-emitting element further includes: An anode connected to the fifth switching element; and A cathode to which a low-potential pixel reference voltage lower than the reference voltage is applied.

11. The display device according to claim 7, wherein, In the initialization step, the first initialization pulse, the sensing pulse, and the second initialization pulse are generated as gate-on voltages, and the scan pulse and the light emission control pulse are generated as gate-off voltages, in the sensing step, the first initialization pulse is generated as the gate-on voltage, and the sensing pulse, the second initialization pulse, the scan pulse, and the light emission control pulse are generated as the gate-off voltages, During the boosting step and the light-emitting step, the light-emitting control pulse is generated as the gate-on voltage, and the first initialization pulse, the sensing pulse, the second initialization pulse, and the scanning pulse are generated as the gate-off voltage.

12. The display device according to claim 7, wherein, The driving element of the pixel circuit and each of the first switching element, the second switching element, the third switching element, the fourth switching element, and the fifth switching element include transistors, and wherein the display panel includes a circuit layer formed with the pixel circuit and the gate driver, and a light-emitting element layer disposed on the circuit layer and including the light-emitting element.

13. The display device according to claim 12, wherein, All the transistors in the circuit layer are n-channel oxide transistors.

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