Method and apparatus for arbitrary sampling rate conversion for a communication receiver

Abstract

The application provides a method and device for arbitrary sampling rate conversion of a communication receiver, comprising: performing down-rounding operation according to a sampling frequency of a sampling signal and a sampling frequency of the sampling signal required by a signal processor to determine an integral result; performing integral times down-sampling on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral times down-sampling; performing curve fitting based on the sampling result corresponding to the integral times down-sampling to obtain a continuous signal; calculating a sampling time interval after decimal times decimation according to the sampling frequency of the sampling signal required by the signal processor; and performing decimal times decimation on the continuous signal based on the sampling time interval after the decimal times decimation to complete the arbitrary sampling rate conversion. The application has good decimation effect on any decimal times sampling frequency, has wide application range, and is more suitable for practical application.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, and in particular to a method and device for converting arbitrary sampling rate for a communication receiver. BACKGROUND

[0002] In actual broadband communication receiver product design, the sampling clock of the AD (analog-to-digital) sampling device and the signal processor is often inconsistent, so in order to ensure that the received signal in the AD can be effectively extracted, the sampling rate of the AD sampling signal needs to be converted to the sampling clock of the signal processor.

[0003] However, the technical solution of the conventional non-integer multiple sampling is as follows: first, the non-integer multiple needs to be converted into a fraction with a very large numerator and denominator, and then the numerator multiple interpolation and the denominator multiple decimation are performed. This method is theoretically feasible, but in practice it is limited by the very large amount of calculation, and the device requirements are harsh, which cannot be used in engineering.

[0004] The existing non-integer multiple decimation method, such as decimation based on the transpose FARROW form, mainly has the following three shortcomings: 1. The transpose FARROW form fractional decimation does not have universal good effect for all fractional sampling rates; 2. The signal-to-noise ratio of the original signal after decimation is relatively lower than that of the theoretical fractional decimation; 3. The implementation process is not simple and clear enough. SUMMARY

[0005] In view of the problems in the prior art, the embodiments of the present application provide a method and device for converting arbitrary sampling rate for a communication receiver.

[0006] In a first aspect, the embodiments of the present application provide a method for converting arbitrary sampling rate for a communication receiver, comprising:

[0007] obtaining a sampling signal from a received signal through an analog-to-digital converter, and determining a sampling frequency of the sampling signal;

[0008] obtaining a sampling frequency of a sampling signal required by a signal processor;

[0009] performing a floor operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor to determine an integer result;

[0010] performing integer multiple down-sampling on the sampling signal according to the integer result to obtain a sampling result corresponding to the integer multiple down-sampling; wherein the sampling result corresponding to the integer multiple down-sampling is a plurality of discrete points, and the discrete points represent discrete signals;

[0011] performing curve fitting based on the sampling result corresponding to the integer multiple down-sampling to obtain a continuous signal;

[0012] calculating a fractional decimation sampling time interval according to a sampling frequency of the sampling signal required by the signal processor;

[0013] performing fractional decimation on the continuous signal based on the fractional decimation sampling time interval to complete arbitrary sampling rate conversion.

[0014] Further, the method further comprises:

[0015] determining the fitting result by using a Horner polynomial calculation method;

[0016] Correspondingly, the performing fractional decimation on the continuous signal based on the fractional decimation sampling time interval to complete arbitrary sampling rate conversion specifically comprises:

[0017] performing fractional decimation on the continuous signal based on the fitting result and the fractional decimation sampling time interval to complete arbitrary sampling rate conversion.

[0018] Further, the method further comprises:

[0019] calculating a pre-fractional decimation sampling time interval according to the sampling frequency of the sampling signal;

[0020] Correspondingly, the performing fractional decimation on the continuous signal based on the fitting result and the fractional decimation sampling time interval to complete arbitrary sampling rate conversion specifically comprises:

[0021] performing fractional decimation on the continuous signal based on the fitting result, the fractional decimation sampling time interval and the pre-fractional decimation sampling time interval to complete arbitrary sampling rate conversion.

[0022] Further, the performing integer times decimation on the sampling signal according to the integer result to obtain a sampling result corresponding to the integer times decimation specifically comprises:

[0023] decomposing the integer result into a form of m·2 n ; wherein, m represents a number of times of performing half-band decimation, and n represents a number of times of performing non-half-band decimation;

[0024] if m>1, performing m times decimation on the sampling signal;

[0025] if m=1 and n>1, performing preset times decimation on the sampling signal and performing half-band filtering.

[0026] In a second aspect, an embodiment of the present application provides an arbitrary sampling rate conversion device for a communication receiver, comprising:

[0027] The first obtaining module is configured to obtain a sampling signal obtained by converting a received signal by an analog-to-digital converter, and determine a sampling frequency of the sampling signal.

[0028] The second obtaining module is configured to obtain a sampling frequency of a sampling signal required by the signal processor.

[0029] The first determining module is configured to perform a down-round operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor, and determine an integral result.

[0030] The first sampling module is configured to perform an integral multiple down-sampling on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral multiple down-sampling; wherein the sampling result corresponding to the integral multiple down-sampling is a plurality of discrete points, and the discrete points represent discrete signals.

[0031] The fitting module is configured to perform curve fitting on the sampling result corresponding to the integral multiple down-sampling to obtain a continuous signal.

[0032] The second determining module is configured to calculate a sampling time interval after decimal multiple extraction according to the sampling frequency of the sampling signal required by the signal processor.

[0033] The second sampling module is configured to perform decimal multiple extraction on the continuous signal based on the sampling time interval after decimal multiple extraction to complete arbitrary sampling rate conversion.

[0034] Further, the method further comprises:

[0035] The first calculating module is configured to determine a fitting result by using a Horner polynomial calculation method.

[0036] Correspondingly, the second sampling module is specifically configured to:

[0037] perform decimal multiple extraction on the continuous signal based on the fitting result and the sampling time interval after decimal multiple extraction to complete arbitrary sampling rate conversion.

[0038] Further, the method further comprises:

[0039] The second calculating module is configured to calculate a sampling time interval before decimal multiple extraction based on the sampling frequency of the sampling signal.

[0040] Correspondingly, when performing the decimal multiple extraction on the continuous signal based on the fitting result and the sampling time interval after decimal multiple extraction to complete the arbitrary sampling rate conversion, the second sampling module is specifically configured to:

[0041] The continuous signal is decimated based on the sampling time interval after the fractional decimation, the fitting result and the sampling time interval after the fractional decimation to complete the arbitrary sampling rate conversion.

[0042] Further, the first sampling module is specifically configured to:

[0043] The sampling signal is decomposed according to the integer result into the form of m·2 n ; wherein m represents the number of times of half-band decimation; and n represents the number of times of non-half-band decimation.

[0044] If m>1, the sampling signal is m times decimated.

[0045] If m=1 and n>1, the sampling signal is preset times decimated and half-band filtered.

[0046] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the arbitrary sampling rate conversion method for a communication receiver according to the first aspect.

[0047] In a fourth aspect, a non-transitory computer readable storage medium is provided, which stores a computer program, and the computer program is executable on a processor to implement the steps of the arbitrary sampling rate conversion method for a communication receiver according to the first aspect.

[0048] According to the above technical solution, the arbitrary sampling rate conversion method and device for a communication receiver provided by the embodiments of the present application obtain a sampling signal from a received signal through an analog-to-digital converter, determine a sampling frequency of the sampling signal, obtain a sampling frequency of a sampling signal required by a signal processor, perform a down-rounding operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor to determine an integer result, perform integer times decimation on the sampling signal according to the integer result to obtain a sampling result corresponding to the integer times decimation, wherein the sampling result corresponding to the integer times decimation is a plurality of discrete points, and the discrete points represent discrete signals, perform curve fitting on the sampling result corresponding to the integer times decimation to obtain a continuous signal, calculate a sampling time interval after fractional decimation based on the sampling frequency of the sampling signal required by the signal processor, and perform fractional decimation on the continuous signal based on the sampling time interval after the fractional decimation to complete the arbitrary sampling rate conversion. The present application has good decimation effect on any fractional sampling frequency, has wide application range, and is thus more suitable for practical application. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0050] Figure 1 The flowchart of the arbitrary sampling rate conversion method for the communication receiver provided by an embodiment of the present application is shown in the figure.

[0051] Figure 2 The frequency spectrum simulation effect diagram of the AD sampling signal before fractional decimation provided by an embodiment of the present application is shown in the figure.

[0052] Figure 3 The frequency spectrum simulation effect diagram of the AD sampling signal before fractional decimation provided by an embodiment of the present application is shown in the figure.

[0053] Figure 4 The timing simulation effect diagram of the AD sampling signal before fractional decimation provided by an embodiment of the present application is shown in the figure.

[0054] Figure 5 The timing simulation effect diagram of the AD sampling signal after fractional decimation provided by an embodiment of the present application is shown in the figure.

[0055] Figure 6 The flowchart of the segmented parallel processing provided by an embodiment of the present application is shown in the figure.

[0056] Figure 7 The structure diagram of the arbitrary sampling rate conversion device for the communication receiver provided by an embodiment of the present application is shown in the figure.

[0057] Figure 8 The entity structure diagram of the electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0058] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings. The arbitrary sampling rate conversion method for the communication receiver provided by the present application will be explained and described in detail through specific embodiments.

[0059] Figure 1A flowchart of a method for arbitrary sampling rate conversion for a communication receiver is provided in an embodiment of the present application. As shown in FIG. 1, the method comprises: Figure 1

[0060] Step 101: obtaining a sampling signal from a received signal through an analog-to-digital converter, and determining a sampling frequency of the sampling signal.

[0061] Step 102: obtaining a sampling frequency of a sampling signal required by a signal processor.

[0062] Step 103: performing a floor operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor, and determining an integer result.

[0063] Step 104: performing an integer times decimation on the sampling signal according to the integer result to obtain a sampling result corresponding to the integer times decimation; wherein the sampling result corresponding to the integer times decimation is a plurality of discrete points, and the discrete points represent discrete signals.

[0064] Step 105: performing curve fitting based on the sampling result corresponding to the integer times decimation to obtain a continuous signal.

[0065] Step 106: calculating a sampling time interval after fractional times decimation according to the sampling frequency of the sampling signal required by the signal processor.

[0066] Step 107: performing fractional times decimation on the continuous signal based on the sampling time interval after fractional times decimation to complete the arbitrary sampling rate conversion.

[0067] In the embodiment, it is to be noted that the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor are known and can be directly determined. For example, the sampling rate of the signal Sig AD (AD sampled signal, i.e. the sampling signal obtained from the received signal through the analog-to-digital converter) is f AD (AD sampling frequency, i.e. the sampling frequency of the sampling signal), and the sampling rate required by the signal processor (such as FPGA, a high-speed parallel signal processor) is f FPGA (FPGA sampling rate, i.e. the sampling frequency of the sampling signal required by the signal processor).

[0068] In the embodiment, for the floor operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor, for example: for the sampling frequency of the sampling signal f (k is a number less than or equal to ​an integer), k represents the rounding result, that is, the quotient of the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor is rounded (that is, the integer part, such as 3.12, the rounding result is 3; 4.56, the rounding result is 4); represents rounding down.

[0069] In this embodiment, it can be understood that after the rounding result is obtained, the integer multiple down-sampling of the sampling signal is performed by using the rounding result, so that the sampling result corresponding to the integer multiple down-sampling is obtained, that is, the integer multiple down-sampling is completed; then, after the integer multiple down-sampling is completed, a plurality of discrete points are obtained, and the discrete points represent discrete signals; then, the plurality of discrete signals are curve-fitted to obtain a continuous signal; then, the sampling time interval T2 after the decimal multiple extraction is calculated according to the sampling frequency of the sampling signal required by the signal processor, such as After T2 is determined, the continuous signal is extracted by the decimal multiple based on the sampling time interval after the decimal multiple extraction, so that the arbitrary sampling rate conversion is completed, and the sampling signal of the sampling clock required by the signal processing is obtained.

[0070] In this embodiment, it should be noted that the rate conversion of the embodiment of the present application refers to the process that the digital signal of the received signal of the radio frequency device of the wideband communication receiver after AD sampling is firstly integer multiple down-sampled (that is, the integer multiple down-sampling of the sampling signal is performed according to the rounding result to obtain the sampling result corresponding to the integer multiple down-sampling), and then the sampling rate of the decimal multiple extraction is quickly converted according to the sampling clock of the signal processor (that is, the sampling time interval after the decimal multiple extraction is calculated according to the sampling frequency of the sampling signal required by the signal processor), and the extracted signal can be subjected to subsequent signal processing.

[0071] According to the technical scheme, the method for converting an arbitrary sampling rate of a communication receiver provided by the embodiment of the application comprises the following steps: obtaining a sampling signal by acquiring a received signal that has passed through an analog-to-digital converter and determining a sampling frequency of the sampling signal; obtaining a sampling frequency of a sampling signal required by a signal processor; performing a down-rounding operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor to determine an integral result; performing integral multiple down-sampling on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral multiple down-sampling; wherein the sampling result corresponding to the integral multiple down-sampling is a plurality of discrete points, and the discrete points represent discrete signals; performing curve fitting on the sampling result corresponding to the integral multiple down-sampling to obtain a continuous signal; calculating a sampling time interval after decimal multiple extraction according to the sampling frequency of the sampling signal required by the signal processor; and performing decimal multiple extraction on the continuous signal based on the sampling time interval after the decimal multiple extraction to complete the conversion of the arbitrary sampling rate. The method has good extraction effect on an arbitrary decimal multiple sampling frequency, has wide application range, and is thus more suitable for practical application.

[0072] In the embodiment, the following steps are further included:

[0073] The fitting result is determined by using a Horner polynomial calculation method.

[0074] Correspondingly, the decimal multiple extraction on the continuous signal based on the sampling time interval after the decimal multiple extraction to complete the conversion of the arbitrary sampling rate specifically comprises the following steps:

[0075] The decimal multiple extraction on the continuous signal based on the fitting result and the sampling time interval after the decimal multiple extraction to complete the conversion of the arbitrary sampling rate.

[0076] In the embodiment, it should be noted that the Horner polynomial calculation method is a fast algorithm for evaluating a polynomial named after William George Horner, a British mathematician. The Horner polynomial calculation method has the advantage of time complexity, and the greater the polynomial degree is, the more obvious the speed-up effect is, thereby helping to quickly complete the conversion of the arbitrary sampling rate.

[0077] In the embodiment, the following steps are further included:

[0078] The sampling time interval before the decimal multiple extraction is calculated based on the sampling frequency of the sampling signal.

[0079] Correspondingly, the decimal multiple extraction on the continuous signal based on the fitting result and the sampling time interval after the decimal multiple extraction to complete the conversion of the arbitrary sampling rate specifically comprises the following steps:

[0080] Based on the sampling time interval after fractional decimation, the fitting result, and the sampling time interval after fractional decimation, the continuous signal is fractionally decimated to complete the arbitrary sampling rate conversion.

[0081] In this embodiment, the sampling time interval before fractional decimation is calculated based on the sampling frequency of the sampled signal. This can be understood as using a first relational model to obtain the sampling time interval T1 before fractional decimation; wherein the first relational model is:

[0082]

[0083] Among them, m·2 n This indicates that the sampling frequency of the sampled signal is determined by rounding down based on the sampling frequency of the sampled signal and the sampling frequency required by the signal processor. The rounded result indicates that the sampling frequency of the sampled signal is f. AD .

[0084] Based on the above embodiments, in this embodiment, the step of performing integer-multiple downsampling on the sampled signal according to the rounding result to obtain the sampling result corresponding to the integer-multiple downsampling specifically includes:

[0085] The rounding result is decomposed into m·2. n The form is: m represents the number of half-band extractions; n represents the number of extractions when performing non-half-band extractions.

[0086] If m > 1, then the sampled signal is decimated by a factor of m;

[0087] If m = 1 and n > 1, then the sampled signal is decimated by a preset multiple and subjected to half-band filtering.

[0088] In this embodiment, it should be noted that m and n are positive integers or zero.

[0089] In this embodiment, it should be noted that the signal Sig after AD sampling is assumed to be... AD The sampling rate of the signal after AD sampling is f AD (AD sampling frequency), the required sampling rate for an FPGA (a high-speed parallel signal processor) is f. FPGA (FPGA sampling rate), perform arbitrary rate conversion according to the following process:

[0090] (1): The integer result is k, for (k is a value less than or equal to) (integers) (For floor function) it is decomposed into m·2 as follows: n The form of (a power of 2 multiplied by a power other than 2):

[0091] make S is a 1×l vector, and each element in S is:

[0092] S(i) = k / 2 i (1≤i≤l),

[0093] Find the vector The number of zeros in the middle ( This refers to rounding down each element of vector S, and the number of rounds is n. From n, we can obtain...

[0094] (2): If m > 1, then for Sig AD Perform m-fold decimation, followed by 3 to 5 CIC (integral-comb filter) filtering. Otherwise, proceed directly to the next step (3).

[0095] (3): If n>1, the output sequence of the CIC filter is decimated by a preset multiple and then half-band filtered.

[0096] In this embodiment, for example, if the rounding result is 8, it is decomposed into m·2. n If m = 1 and n = 3, then the sampled signal is extracted by a preset multiple (2 times or 3 times, etc., set according to actual needs) and half-band filtering is performed.

[0097] Similarly, if the integer result is 9, it can be decomposed into m·2. n Then m = 9, n = 0; if the integer result is 10, it can be decomposed into m·2 n Then m = 5, n = 1; if the integer result is 12, it can be decomposed into m·2. n Then m = 3, n = 2.

[0098] To better understand the present invention, the following embodiments further illustrate the content of the present invention, but the present invention is not limited to the following embodiments.

[0099] For example, see Figures 2 to 6 ,in, Figure 2 and Figure 3 These are schematic diagrams showing the simulated spectrum effects of the AD sampled signal before and after fractional decimation. Figure 4 and Figure 5 These diagrams illustrate the timing simulation effects of the AD sampling signal before and after fractional decimation. Figure 6 This is a schematic diagram illustrating the process of segmenting and parallel processing of the received signal.

[0100] Assume the signal Sig after AD sampling AD The sampling rate of the signal after AD sampling is f AD(AD sampling frequency), the required sampling rate for an FPGA (a high-speed parallel signal processor) is f. FPGA (FPGA sampling rate), perform arbitrary rate conversion according to the following process:

[0101] (1): The integer result is k, for (k is a value less than or equal to) (integers) (For floor function) it is decomposed into m·2 as follows: n The form of (a power of 2 multiplied by a power other than 2):

[0102] make S is a 1×l vector, and each element in S is:

[0103] S(i) = k / 2 i (1≤i≤l),

[0104] Find the vector The number of zeros in the middle ( This refers to rounding down each element of vector S, and the number of rounds is n. From n, we can obtain...

[0105] (2): If m > 1, then for Sig AD Perform m-fold decimation, followed by 3 to 5 CIC (integral-comb filter) filtering. Otherwise, proceed directly to the next step (3).

[0106] (3): If n>1, the output sequence of the CIC filter is decimated by 2 times and half-band filtered, and the CIC filter decimation is repeated n times. The signal after CIC decimation is denoted as y, and the length N of y is recorded. Otherwise, proceed directly to the next step (4).

[0107] (4) Calculate the sampling time interval T1 before fractional sampling:

[0108]

[0109] And the sampling time interval T2 after fractional extraction:

[0110]

[0111] (5): Symmetric matrix

[0112]

[0113] Perform LU decomposition (LU decomposes a matrix into the product of a unit lower triangular matrix and an upper triangular matrix) (i.e., H = LU), and the forms of L and U are as follows:

[0114]

[0115] The matrix L, U, l = [l1,..., ln] and U = [u1,..., un] are calculated according to the following formula: N-3 N-2

[0116] l i-1 = 1 / u i-1 , u i = 4-l i-1 , u1 = 4;

[0117] (6) M = [m1,..., m N-2 ] is calculated according to the following formula:

[0118]

[0119] (b i = 6f1·(y(i+2)-2y(i+1)+y(i)), i = 1, 2,..., N-2, f1 = 1 / T1). The calculation method of M is as follows:

[0120] Let z1 = b1,

[0121] First, the vector z = [z1,..., zn] is calculated according to the following formula: That is:

[0122] z i = b i -l i-1 z i-1 (i = 2,..., N-2),

[0123] Then, the vector m = [m1,..., m i ] is calculated according to the following formula: That is

[0124] m i = (z i -m i-1 ) / u i (i = N-2, N-1,..., 1),

[0125] The effective closed loop of the above formula depends on two virtual values m0 = 0. Let the vector M' = [m'1,..., m'N] be:

[0126]

[0127] (7) Let the time sequence corresponding to the signal y after CIC decimation be t1 = 0: T1: (N-1)T1, then the fitting function on the time interval [t k-1 , t k ] (t k = (k-1)T1) is:

[0128] ​​

[0129] To avoid division, the above equation can be implemented in the implementation process as follows:

[0130] 6·S k (t) = -f1·M'(k-1)·(t-t k ) 3 +f1·M'(k)·(t-t k-1 ) 3 -6y k-1 f1·(t-t k )+M'(k-1)T1·(t-t k )+6y k f1·(t-t k-1 )-M'(k)T1·(t-t k-1 )

[0131] Let Q1 = -f1·M'(k-1), Q2 = -6y k-1 f1+M'(k-1)T1, H1 = f1·M'(k), H2 = 6y k f1-M'(k)T1, then:

[0132] 6·S k (t) = Q1·(t-t k ) 3 +Q2·(t-t k )+H1·(t-t k-1 ) 3 +H2·(t-t k-1 ),

[0133] The above equations Q1(t-t k ) 3 +Q2(t-t k ) and H1(t-t k-1 ) 3 +H2(t-t k-1 ) can be calculated using the Horner algorithm (a fast polynomial calculation method named after Horner) to obtain S k (t) (i.e. the fitting result). Taking Q1(t-t k ) 3 +Q2(t-t k ) as an example,

[0134] Q1(t-t k ) 3 +Q2(t-t k ) = (Q1(t-t k ) 2 +Q2)·(t-t k ).

[0135] determining the time period of t1 corresponding to each time point of time sequence t2=0:T2:(N-1)T2 k-1 ,t k ] to determine the segment S k (t) corresponding to each time point of t2, and substituting each time point of t2 into the function value obtained from the corresponding S k (t) is the output after decimal decimation.

[0136] (8):Referring to Figure 6 Due to the excellent characteristics of the matrix H, if the data of the input signal is long, the received signal can be segmented and processed in parallel according to the processing capacity of the signal processor, and each segment performs the processes of steps 1 to 8.

[0137] The embodiment of the present application has low calculation complexity and good decimation effect for any decimal, and is very suitable for implementation on FPGA. Actual engineering tests show that it has good performance.

[0138] Figure 7 The structural schematic diagram of the arbitrary sampling rate conversion device for a communication receiver provided by an embodiment of the present application is shown in FIG. 1, and the device comprises a first acquisition module 201, a second acquisition module 202, a first determination module 203, a first sampling module 204, a fitting module 205, a second determination module 206 and a second sampling module 207. Figure 7

[0139] The first acquisition module 201 is configured to acquire a sampling signal obtained by converting a received signal through an analog-to-digital converter, and determine a sampling frequency of the sampling signal.

[0140] The second acquisition module 202 is configured to acquire a sampling frequency of a sampling signal required by a signal processor.

[0141] The first determination module 203 is configured to perform a floor operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor, and determine a floor result.

[0142] The first sampling module 204 is configured to perform integer multiple down-sampling on the sampling signal according to the floor result to obtain a sampling result corresponding to the integer multiple down-sampling. The sampling result corresponding to the integer multiple down-sampling is a plurality of discrete points, and the discrete points represent discrete signals.

[0143] The fitting module 205 is configured to perform curve fitting on the sampling result corresponding to the integer multiple down-sampling to obtain a continuous signal.

[0144] ​The second determining module 206 is configured to calculate a sampling time interval after decimal times extraction according to a sampling frequency of the sampling signal required by the signal processor.

[0145] The second sampling module 207 is configured to complete arbitrary sampling rate conversion by performing decimal times extraction on the continuous signal based on the sampling time interval after decimal times extraction.

[0146] The arbitrary sampling rate conversion device for the communication receiver provided by the embodiment of the present application can be specifically used for executing the arbitrary sampling rate conversion method for the communication receiver of the above embodiment, and has similar technical principles and beneficial effects. For details, refer to the above embodiment, which will not be described here again.

[0147] Based on the same inventive concept, the embodiment of the present application provides an electronic device, which is described below with reference to Figure 8 The electronic device specifically includes the following contents: a processor 301, a communication interface 303, a memory 302 and a communication bus 304.

[0148] The processor 301, the communication interface 303 and the memory 302 complete mutual communication through the communication bus 304; the communication interface 303 is configured to realize information transmission between the modeling software, the intelligent manufacturing equipment module library and other related devices; the processor 301 is configured to call a computer program in the memory 302, and the processor realizes the method provided by each method embodiment described above when executing the computer program, for example, the processor realizes the following steps when executing the computer program: obtaining a sampling signal obtained by converting a received signal through an analog-to-digital converter, and determining a sampling frequency of the sampling signal; obtaining a sampling frequency of the sampling signal required by a signal processor; performing a down rounding operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor, and determining a rounding result; performing integer times down sampling on the sampling signal according to the rounding result to obtain a sampling result corresponding to the integer times down sampling; wherein the sampling result corresponding to the integer times down sampling is a plurality of discrete points, and the discrete points represent discrete signals; performing curve fitting based on the sampling result corresponding to the integer times down sampling to obtain a continuous signal; calculating a sampling time interval after decimal times extraction according to a sampling frequency of the sampling signal required by the signal processor; and performing decimal times extraction on the continuous signal based on the sampling time interval after decimal times extraction to complete arbitrary sampling rate conversion.

[0149] Based on the same inventive concept, another embodiment of the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method provided by the above method embodiments, for example, obtaining a sampling signal obtained by an analog-to-digital converter from a received signal, and determining a sampling frequency of the sampling signal; obtaining a sampling frequency of the sampling signal required by a signal processor; performing a down rounding operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor, and determining an integral result; performing integral multiple down sampling on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral multiple down sampling; wherein the sampling result corresponding to the integral multiple down sampling is a plurality of discrete points, and the discrete points represent discrete signals; performing curve fitting on the sampling result corresponding to the integral multiple down sampling to obtain a continuous signal; calculating a sampling time interval after decimal multiple decimation according to the sampling frequency of the sampling signal required by the signal processor; and performing decimal multiple decimation on the continuous signal based on the sampling time interval after the decimal multiple decimation to complete arbitrary sampling rate conversion.

[0150] The device embodiments described above are merely illustrative, wherein the units illustrated as separate components can or can not be physically separated, and the components illustrated as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0151] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and the necessary general hardware platform, and of course, it can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the method of each embodiment or some part of the embodiment.

[0152] In addition, in the present application, such as "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0153] Moreover, in the subject specification, the term "engaged" simply means to be coupled with or to come in contact with. Additionally, the term "first," "second," "third," etc. as used in the subject specification, is used only to differentiate one element from another, and does not imply a physical or logical relationship or order of such elements. Furthermore, the use of terminology such as "including" should not be interpreted as incorporating only that which follows the comma after such term. "Including" means "comprising" or "consisting of" and not "consisting exclusively of" or "consisting only of." In addition, the term "coupled" and variations thereof, as used in the subject specification, means connected, whether directly or indirectly, for example, through one or more intervening elements.

[0154] In addition, throughout the specification, and in the claims, the term "comprises" and variations thereof, such as "comprising" and "comprise," mean "including but not limited to," and are not intended to exclude, for example, other additives, components, integers or steps. Throughout the specification, and in the claims, the expression "at least one of A and B" means "A or B or both A and B." Throughout the specification, and in the claims, the expression "at least one of A, B and C" means "A or B or C or any combination of these." Throughout the specification, and in the claims, the expression "at least one of A, B, C and D" means "A or B or C or D or any combination of these." Throughout the specification, and in the claims, the expression "at least one of A, B, C, D and E" means "A or B or C or D or E or any combination of these." Throughout the specification, and in the claims, the expression "at least one of A, B, C, D, E and F" means "A or B or C or D or E or F or any combination of these." Throughout the specification, and in the claims, the expression "at least one of A, B, C, D, E, F and G" means "A or B or C or D or E or F or G or any combination of these." Throughout the specification, and in the claims, the expression "at least one of A, B, C, D, E, F, G and H" means "A or B or C or D or E or F or G or H or any combination of these."

[0155] Finally, it should be noted that the above-mentioned embodiments merely illustrate the technical solutions of the present application, rather than limit the scope of the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still make modifications to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for arbitrary sampling rate conversion for a communications receiver, characterized by, The method comprises the following steps: obtaining a sampling signal obtained by analog-to-digital conversion of a received signal, and determining a sampling frequency of the sampling signal; obtaining a sampling frequency of the sampling signal required by a signal processor; performing a down-round operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor to determine an integral result; performing integral times decimation on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral times decimation; wherein the sampling result corresponding to the integral times decimation is a plurality of discrete points, and the discrete points represent discrete signals; performing curve fitting based on the sampling result corresponding to the integral times decimation to obtain a continuous signal; calculating a decimal times decimation sampling time interval based on the sampling frequency of the sampling signal required by the signal processor; performing decimal times decimation on the continuous signal based on the decimal times decimation sampling time interval to complete arbitrary sampling rate conversion.

2. The arbitrary sample rate conversion method for a communications receiver of claim 1, wherein, Further comprising: determining a fitting result by using a Horner polynomial calculation method; Correspondingly, the step of performing decimal times decimation on the continuous signal based on the decimal times decimation sampling time interval to complete arbitrary sampling rate conversion specifically comprises: performing decimal times decimation on the continuous signal based on the fitting result and the decimal times decimation sampling time interval to complete arbitrary sampling rate conversion.

3. The arbitrary sampling rate conversion method for a communication receiver according to claim 2, further comprising: calculating a sampling time interval before decimal times decimation based on the sampling frequency of the sampling signal; Correspondingly, the step of performing decimal times decimation on the continuous signal based on the fitting result and the decimal times decimation sampling time interval to complete arbitrary sampling rate conversion specifically comprises: performing decimal times decimation on the continuous signal based on the fitting result, the decimal times decimation sampling time interval and the fitting result to complete arbitrary sampling rate conversion.

4. The method for arbitrary sample rate conversion for a communications receiver of claim 1, wherein, The step of performing integral times decimation on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral times decimation specifically comprises: According to the rounding result, the signal is decomposed into m·2 n forms; where m represents the number of times of half-band extraction; n represents the number of times of non-half-band extraction. if m>1, performing m times decimation on the sampling signal; if m=1 and n>1, performing a preset times decimation on the sampling signal and performing half-band filtering.

5. An arbitrary sample rate conversion device for a communications receiver, characterized by, The method comprises the following steps: a first obtaining module is configured to obtain a sampling signal obtained by analog-to-digital conversion of a received signal, and determine a sampling frequency of the sampling signal; a second obtaining module is configured to obtain a sampling frequency of the sampling signal required by a signal processor; a first determining module is configured to perform a down-round operation according to the sampling frequency of the sampling signal and the sampling frequency of the sampling signal required by the signal processor to determine an integral result; a first sampling module is configured to perform integral times decimation on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral times decimation; wherein the sampling result corresponding to the integral times decimation is a plurality of discrete points, and the discrete points represent discrete signals; a fitting module is configured to perform curve fitting based on the sampling result corresponding to the integral times decimation to obtain a continuous signal; The second determining module is configured to calculate a sampling time interval after decimal extraction according to a sampling frequency of the sampling signal required by the signal processor. The second sampling module is configured to perform decimal extraction on the continuous signal based on the sampling time interval after decimal extraction to complete arbitrary sampling rate conversion.

6. The arbitrary sample rate conversion device for a communications receiver of claim 5, wherein, Further comprising: The first calculating module is configured to determine a fitting result by using a Horner polynomial calculation method. Correspondingly, the second sampling module is specifically configured to: perform decimal extraction on the continuous signal based on the fitting result and the sampling time interval after decimal extraction to complete arbitrary sampling rate conversion.

7. The arbitrary sample rate conversion device for a communications receiver of claim 6, wherein, Further comprising: The second calculating module is configured to calculate a sampling time interval before decimal extraction based on the sampling frequency of the sampling signal. Correspondingly, when performing decimal extraction on the continuous signal based on the fitting result and the sampling time interval after decimal extraction to complete arbitrary sampling rate conversion, the second sampling module is specifically configured to: perform decimal extraction on the continuous signal based on the sampling time interval after decimal extraction, the fitting result and the sampling time interval after decimal extraction to complete arbitrary sampling rate conversion.

8. The arbitrary sample rate conversion apparatus for a communications receiver of claim 5, wherein, The first sampling module is specifically configured to: According to the rounding result, the signal is decomposed into m·2 n forms; where m represents the number of times of half-band extraction; n represents the number of times of non-half-band extraction. if m>1, perform m times extraction on the sampling signal; if m=1 and n>1, perform preset times extraction on the sampling signal and perform half-band filtering.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the arbitrary sampling rate conversion method for a communication receiver according to any one of claims 1-4.

10. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the arbitrary sampling rate conversion method for a communication receiver according to any one of claims 1-4.

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