A design method for comprehensive diagnosis system of SRIO bus of radar processor

Abstract

This application provides a design method for a comprehensive diagnostic system for the SRIO bus of a radar processor, belonging to the technical field of SRIO bus communication systems for airborne radar processing units. Specifically, it includes implementing a real-time fault reporting mechanism for the SRIO bus; an error detection mechanism based on the SRIO bus to analyze real-time reported faults; drawing the bus topology using dynamic enumeration technology based on the SRIO bus; a BIT-based SRIO bus system maintenance technology to enable communication using BIT links when SRIO bus links are abnormal; and implementing QT GraphicView human-computer interaction technology. This application's solution improves the development and debugging efficiency of radar signal processing systems.

Description

Technical Field

[0001] The present application relates to the field of SRIO bus communication system of airborne radar processing unit, and in particular to a design method of SRIO bus comprehensive diagnosis system of radar processing unit. Background Art

[0002] As modern warfare places increasingly stringent demands on the performance, weight, and volume of radar processing units, radar processing units have introduced three high-speed buses: PCIe, SRIO, and Ethernet, for data transmission, function debugging, and other tasks. The introduction of high-speed buses has improved the data transmission performance of the processor, reduced device and wiring costs, simplified the overall system design, and met the needs of integration and miniaturization of radar processing units. In response to the needs of high-bandwidth communications for big data, a fully switched network based on the SRIO bus was designed in the radar processing unit, realizing flexible communication methods between multiple modules and between multiple chips such as FPGA, CPU, and DSP processors within the module. The SRIO bus system of the radar processing unit is as follows: Figure 1 At present, SRIO high-speed serial bus and its fully switched network are widely used in radar processing units, but when problems or abnormalities occur, the bus system is complex, positioning is difficult, and development and debugging efficiency is low. Summary of the invention

[0003] In view of this, the present application provides a design method for a radar processor SRIO bus comprehensive diagnostic system, which solves the problems in the prior art and improves the development and debugging efficiency of the radar signal processing system.

[0004] The design method of a radar processor SRIO bus comprehensive diagnosis system provided in this application adopts the following technical solution:

[0005] A design method for a radar processor SRIO bus comprehensive diagnosis system includes the following steps:

[0006] Realize the real-time fault reporting mechanism of SRIO bus;

[0007] Based on the error detection mechanism of SRIO bus, analyze the faults reported in real time;

[0008] Draw bus topology based on dynamic enumeration technology of SRIO bus;

[0009] BIT-based SRIO bus system maintenance technology enables communication using BIT links when SRIO bus links are abnormal;

[0010] Implement human-computer interaction technology of QT GraphicView.

[0011] Optionally, the real-time reporting mechanism for SRIO bus faults specifically includes:

[0012] The radar processor module is integrated with an SRIO bus switching chip. The modules are interconnected and communicated using the SRIO switching chip ports to form an SRIO full-switching communication system formed by cascading multiple switching chips. According to the specific design of the module, the interrupt pin function or PortWrite function of the SRIO switching chip is selected to inform the processor. After the processor in the module senses the fault or abnormality in real time, it sends an abnormal message to the main control processor of the main control module. The main control processor software reports the fault information of the SRIO bus to the host computer SRIO bus comprehensive diagnostic interface in real time through Ethernet.

[0013] Optional, based on the SRIO bus error detection mechanism, analyze the real-time reported faults, including:

[0014] After receiving the SRIO bus abnormality message or user control instruction, the host computer SRIO bus comprehensive diagnosis interface accesses and maintains the SRIO bus system through the Ethernet interface or hardware BIT system link, and diagnoses and analyzes the SRIO bus fault from three aspects: physical layer, logical layer, and transaction layer. The host computer SRIO bus comprehensive diagnosis interface adds online testing and switching chip flow control functions between SRIO end devices for further positioning and diagnosis of faults.

[0015] Optional, BIT-based SRIO bus system maintenance technology, which uses the BIT link for communication when the SRIO bus link is abnormal, specifically includes:

[0016] The radar processing unit modules are all designed with board control processors, which are interconnected through RS485 bus to form the hardware BIT system of the radar processing unit. The STM32F103 processor accesses and controls the SRIO switch chip of this module through the I2C interface. The host computer SRIO bus comprehensive diagnostic interface uses the hardware BIT system link to monitor the port status and performance of each module SRIO bus switch chip in real time and configure the port mode, so that the SRIO bus system can be dynamically maintained when the SRIO bus is abnormal.

[0017] Optionally, the bus topology is drawn based on the dynamic enumeration technology of the SRIO bus, specifically including: the host computer SRIO bus comprehensive diagnostic interface is developed based on the QT IDE software, including QGraphicView graphics drawing and display technology, QJsonDocument reading and writing Json file technology; during the initialization of the diagnostic interface, the user policy is read from the user-customized JSON file, and the depth-first traversal enumeration algorithm is used according to the policy to realize the real-time acquisition of the SRIO bus topology; the diagnostic interface uses QGraphicView technology to realize the drawing and display of the SRIO topology and interact with the user; the user can use the diagnostic interface to access and configure different levels of terminal devices, switching chips, ports and links.

[0018] In summary, this application includes the following beneficial technical effects:

[0019] High efficiency: The real-time fault reporting mechanism can realize rapid fault detection, and the host computer implements the diagnosis strategy determined by the fault tree to realize rapid fault location.

[0020] Reliable diagnostic system: Based on the redundant diagnostic method of SRIO bus and BIT bus, the reliability of the diagnostic link is improved.

[0021] Good usability: The strategy and interface configuration based on JSON files can meet the needs of different models; the GUI interface developed based on QT software realizes graphic control and control, which is convenient for debugging the SRIO bus system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 The block diagram of the SRIO bus communication system for the radar processing unit is shown below;

[0024] Figure 2 This is a schematic diagram of the host computer interface of the SRIO bus comprehensive diagnosis and debugging system;

[0025] Figure 3 Initialize the flow chart of the SRIO bus comprehensive diagnostic debugging interface;

[0026] Figure 4 This is a real-time processing flow chart of SRIO bus comprehensive diagnosis and debugging interface faults;

[0027] Figure 5This is the instruction control flow chart of the SRIO bus comprehensive diagnostic debugging interface. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0029] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0030] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0032] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0033] The embodiment of the present application provides a design method for a radar processor SRIO bus comprehensive diagnostic system.

[0034] like Figure 1The figure shows the block diagram of the radar processing unit SRIO bus communication system. A high-speed bus (SRIO) and a BIT link (RS485) are designed between the radar processing unit modules.

[0035] The SRIO bus is used to transmit business data with a large amount of data. The radar processing unit includes a main control data processing module and multiple signal processing modules. The main control data processing module has 1 or 2 CPU processors; the signal processing module generally uses 4 DSP chips to form a chip array. The SRIO bus communication system adopts a full switching communication model, and each terminal device (node) is connected to the switching chip in a peer-to-peer manner to achieve interconnection and interoperability of all nodes. Each terminal device has an independent destID, but it can receive 1 or more IDs when receiving, and compare the destination ID in the received data packet with each element in the ID set. When the two match, it is considered that the packet is sent to itself and continues to implement the unpacking operation, otherwise the data packet is discarded. The DSP processor includes 1 unicast ID and 8 multicast IDs 0xF0~0xF7; and the CPU processor is configured with the AcceptAll function to receive all data packets.

[0036] The BIT link is used to transmit the module hardware BIT information, and the data volume is small. The radar processor hardware BIT system is composed of the module's MCU connected in series through the RS485 bus. The I2C interface of the SRIO bus switch chip in the module is connected to the module's MCU. Therefore, the diagnostic interface can use the hardware BIT system link to maintain the core device switch chip in the SRIO bus system. Especially when the SRIO bus system fails, maintaining the SRIO bus system based on the hardware BIT system is a more reliable way.

[0037] A design method for a radar processor SRIO bus comprehensive diagnosis system includes the following steps:

[0038] Implement a real-time fault reporting mechanism for the SRIO bus.

[0039] Based on the error detection mechanism of the SRIO bus, analyze the faults reported in real time.

[0040] Draw the bus topology based on the dynamic enumeration technology of SRIO bus.

[0041] The SRIO bus system maintenance technology based on BIT can realize communication using BIT link when the SRIO bus link is abnormal.

[0042] Implement human-computer interaction technology of QT GraphicView.

[0043] The virtual channel technology based on SRIO bus improves the reliability of data transmission between nodes.

[0044] The real-time fault reporting mechanism for the SRIO bus includes:

[0045] The radar processor module is integrated with an SRIO bus switching chip. The modules are interconnected and communicated using the SRIO switching chip ports to form an SRIO full-switching communication system formed by cascading multiple switching chips. According to the specific design of the module, the interrupt pin function or PortWrite function of the SRIO switching chip is selected to inform the processor. After the processor in the module senses the fault or abnormality in real time, it sends an abnormal message to the main control processor of the main control module. The main control processor software reports the fault information of the SRIO bus to the host computer SRIO bus comprehensive diagnostic interface in real time through Ethernet.

[0046] Based on the error detection mechanism of the SRIO bus, the real-time reported faults are analyzed and specifically include:

[0047] After receiving the SRIO bus abnormality message or user control instruction, the host computer SRIO bus comprehensive diagnosis interface accesses and maintains the SRIO bus system through the Ethernet interface or hardware BIT system link, and diagnoses and analyzes the SRIO bus fault from three aspects: physical layer, logical layer, and transaction layer. The host computer SRIO bus comprehensive diagnosis interface adds online testing and switching chip flow control functions between SRIO end devices for further positioning and diagnosis of faults.

[0048] The SRIO bus system maintenance technology based on BIT implements the use of BIT link for communication when the SRIO bus link is abnormal, including:

[0049] The radar processing unit modules are all designed with board control processors, which are interconnected through RS485 bus to form the hardware BIT system of the radar processing unit. The STM32F103 processor accesses and controls the SRIO switch chip of this module through the I2C interface. The host computer SRIO bus comprehensive diagnostic interface uses the hardware BIT system link to monitor the port status and performance of each module SRIO bus switch chip in real time and configure the port mode, so that the SRIO bus system can be dynamically maintained when the SRIO bus is abnormal.

[0050] Drawing the bus topology based on the dynamic enumeration technology of the SRIO bus specifically includes: the host computer SRIO bus comprehensive diagnostic interface is developed based on the QT IDE software, including QGraphicView graphics drawing and display technology, QJsonDocument reading and writing Json file technology. During the initialization of the diagnostic interface, the user policy is read from the user-customized JSON file, and the depth-first traversal enumeration algorithm is used according to the policy to realize the real-time acquisition of the SRIO bus topology. The diagnostic interface uses QGraphicView technology to realize the drawing and display of the SRIO topology and interact with the user. The user can use the diagnostic interface to access and configure different levels of terminal devices, switching chips, ports and links.

[0051] The radar processing unit uses hardware circuit design technology based on the CPS1848 switch chip. An SRIO bus switch chip CPS1848 is designed on each module that uses SRIO bus communication, forming an SRIO full-switching communication system composed of multiple switch chips cascaded.

[0052] The internal modules of the radar processing unit are all designed with the board control chip STM32F103 processor. The STM32F103 processor is interconnected through the RS485 bus to form the health management system of the radar processing unit. The STM32F103 processor accesses and controls the SRIO switch chip of this module through the I2C interface. The radar processing unit health management system BIT can realize real-time monitoring of the port status and performance of each module SRIO bus switch chip and configuration update of the port mode based on user strategies, so as to achieve the purpose of dynamic maintenance of the SRIO bus.

[0053] The host computer is developed using QT GraphicView technology, and uses depth-first traversal enumeration algorithm dynamic enumeration technology to achieve real-time drawing of SRIO bus topology. The interface has good interactivity and can achieve access and configuration of different levels of end devices, switching chips, ports, and links.

[0054] This application designs two fault diagnosis methods for the SRIO bus full-switching communication system, active access and interrupt monitoring. In the active access mode, the host computer diagnostic system accesses and maintains the SRIO bus system through the Ethernet interface or with the help of the BIT bus; in the interrupt monitoring mode, the real-time fault reporting mechanism and hot-swap mechanism based on the SRIO bus are used to achieve real-time monitoring and rapid positioning of errors or anomalies. In addition, the diagnostic debugging system also supports testing between SRIO end devices, flow control of switching chips, and virtual channel control.

[0055] like Figure 2 and Figure 3 As shown, the SRIO bus comprehensive diagnosis and debugging system interface supports the following functions:

[0056] 1. Real-time display of SRIO bus system topology;

[0057] 2. Query the status of the SRIO bus system switch chip port and the terminal device port;

[0058] 3.SRIO bus system switch chip routing clearing, configuration and query;

[0059] 4. Packet count of the SRIO bus system switch chip port;

[0060] 5. SRIO bus system switch chip port and terminal device register level query and configuration;

[0061] 6.Inter-node communication test of SRIO bus system.

[0062] The SRIO bus comprehensive diagnosis and debugging system interface is developed based on QT, and its key technologies include QGraphicView graphics drawing and display technology, QJsonDocument reading and writing Json file technology, etc. During the initialization of the interface operation, the user policy is read from the user-customized JSON file, and then the real-time drawing of the SRIO bus topology is realized by using the depth-first traversal enumeration algorithm dynamic enumeration technology according to the policy. The interface uses QGraphicView technology to draw and display, which has good interactivity with the user and can realize the access and configuration of different levels of terminal devices, switching chips, ports, and links.

[0063] The SRIO bus comprehensive diagnosis and debugging system supports two fault query modes, including the upper computer active access mode and the lower computer reporting mode. The upper computer active access refers to the upper computer interface sending command packets to the main control module processor through Ethernet, which are converted into SRIO maintenance packets to query the status of the devices and switching chips at each end of the SRIO bus system; when some devices in the SRIO bus system are blocked due to abnormalities and cannot be accessed through the SRIO bus maintenance package, it can automatically switch to the BIT system link to indirectly maintain the SRIO bus. In the lower computer reporting mode, the processors of each module of the radar processor or the FPGA device are responsible for the configuration of the PortWrite function or the interrupt pin function of the switching chip. Once an abnormality or hot-swap event occurs at the switching chip port, the module processor or FPGA device will receive an interrupt event or PortWrite event in real time. The module processor or FPGA device analyzes the event to complete preliminary fault diagnosis, reports it to the main control module processor, and then forwards it to the upper computer SRIO bus diagnostic interface. The upper computer SRIO bus diagnostic interface is as follows Figure 4 The fault information is processed as shown. The host computer SRIO bus diagnostic interface is as follows Figure 4 The fault information is processed as shown.

[0064] like Figure 5 As shown in the figure, after the user issues a control command through the interface control, the processing flow of the diagnostic interface. The SRIO diagnostic interface first determines the validity of the command, and then enters the status query configuration sub-process, routing table configuration query sub-process, statistics count configuration query sub-process and test-related sub-process according to the type of command.

[0065] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A design method for a radar processor SRIO bus comprehensive diagnostic system, characterized in that: The steps include: Implement the real-time fault reporting mechanism of SRIO bus; Based on the error detection mechanism of SRIO bus, analyze the faults reported in real time; Draw bus topology based on the dynamic enumeration method of SRIO bus; The SRIO bus system maintenance method based on the built-in test BIT realizes communication using the built-in test BIT link when the SRIO bus link is abnormal; Execute the human-computer interaction method of QT GraphicView; The real-time fault reporting mechanism for the SRIO bus specifically includes: The radar processor module is integrated with an SRIO bus switching chip. The modules are interconnected and communicated using the SRIO bus switching chip ports, forming an SRIO full-switching communication system formed by cascading multiple switching chips. According to the specific design of the module, the interrupt pin function or PortWrite function of the SRIO bus switching chip is selected to inform the processor. After the processor in the module senses the fault or abnormality in real time, it sends an abnormal message to the main control processor of the main control module. The main control processor software reports the fault information of the SRIO bus to the host computer SRIO bus comprehensive diagnosis interface in real time through Ethernet. The SRIO bus system maintenance method based on the built-in test BIT implements communication using the built-in test BIT link when the SRIO bus link is abnormal, specifically including: The radar processing unit modules are all designed with board control processors, which are interconnected through RS485 bus to form the hardware built-in test BIT system of the radar processing unit. The STM32F103 processor accesses and controls the SRIO bus switching chip of this module through the I2C interface. The host computer SRIO bus comprehensive diagnostic interface uses the hardware built-in test BIT system link to monitor the port status and performance of each module SRIO bus switching chip in real time and configure the port mode, so that the SRIO bus system can be dynamically maintained when the SRIO bus is abnormal; The SRIO bus comprehensive diagnosis and debugging system supports two fault query modes, including the host computer active access mode and the slave computer reporting mode.

2. The design method of the radar processor SRIO bus comprehensive diagnosis system according to claim 1 is characterized in that: Based on the error detection mechanism of the SRIO bus, the faults reported in real time are analyzed and specifically include: After receiving the SRIO bus abnormality message or user control instruction, the host computer SRIO bus comprehensive diagnosis interface accesses and maintains the SRIO bus system through the Ethernet interface or the hardware built-in test BIT system link, and diagnoses and analyzes the SRIO bus fault from three aspects: physical layer, logical layer, and transaction layer. The host computer SRIO bus comprehensive diagnosis interface adds online testing between SRIO end devices and SRIO bus switching chip flow control functions for further positioning and diagnosis of faults.

3. The design method of the radar processor SRIO bus comprehensive diagnosis system according to claim 1 is characterized in that: Drawing the bus topology based on the dynamic enumeration method of SRIO bus specifically includes: the host computer SRIO bus comprehensive diagnostic interface is developed based on QT IDE software, including QT GraphicView graphics drawing and display method, QJsonDocument reading and writing Json file method; during the initialization of the diagnostic interface, the user policy is read from the user-customized JSON file, and the depth-first traversal enumeration algorithm is used according to the policy to realize the real-time acquisition of the SRIO bus topology; the diagnostic interface uses the QTGraphicView method to realize the drawing and display of the SRIO topology and interact with the user; the user uses the diagnostic interface to realize the access and configuration of different levels of terminal devices, SRIO bus switching chips, ports and links.

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