Display substrate and display device

Abstract

The display substrate and the display device provided by the present disclosure comprise a substrate, which comprises a display area and a frame area on at least one side of the display area; a first electrode on the substrate, the first electrode extending from the display area to the frame area; a first power bus between the layer where the first electrode is located and the substrate, the first power bus being located in the frame area and electrically connected with the first electrode; and a first power line between the layer where the first electrode is located and the substrate, the first power line being located in the display area, the first power line being in a mesh structure and electrically connected with the first power bus.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] In recent years, organic light-emitting diode (OLED) displays have gradually attracted more attention as a new type of flat panel display. They have excellent characteristics such as active light emission, high brightness, high resolution, wide viewing angle, fast response speed, small thickness, low power consumption, flexibility, wide operating temperature range, and relatively simple structure and manufacturing process, and have broad application prospects. Summary of the Invention

[0003] The display substrate and display device provided in this disclosure are specifically designed as follows:

[0004] On one hand, embodiments of this disclosure provide a display substrate, including:

[0005] A substrate, the substrate including a display area and a border area located on at least one side of the display area;

[0006] A first electrode is located on the substrate and extends from the display area to the border area;

[0007] A first power bus is located between the layer containing the first electrode and the substrate, and the first power bus is located in the border area and is electrically connected to the first electrode.

[0008] A first power line is located between the layer containing the first electrode and the substrate. The first power line is located in the display area and has a mesh structure and is electrically connected to the first power bus.

[0009] In some embodiments, in the display substrate provided in the present disclosure, the first power line includes a plurality of first sub-power lines extending along a first direction and arranged along a second direction, and a plurality of second sub-power lines extending along the second direction and arranged along the first direction. The first sub-power lines and the second sub-power lines are electrically connected to each other on the same or different layers, and the first direction and the second direction are intersected.

[0010] In some embodiments, in the display substrate provided in the present disclosure, the display area includes a plurality of pixel columns extending along the first direction and arranged along the second direction and a plurality of dummy sub-pixel columns, with one dummy sub-pixel column disposed between each adjacent at least one of the pixel columns, and the first sub-power line located in the dummy sub-pixel column.

[0011] In some embodiments, in the display substrate provided in the present disclosure, the display area includes a plurality of sub-pixel columns extending along the first direction and arranged along the second direction, and the first sub-power line is located in at least a portion of the sub-pixel columns.

[0012] In some embodiments, in the display substrate provided in the present disclosure, the display area includes a plurality of sub-pixel rows extending along the second direction and arranged along the first direction and a plurality of dummy sub-pixel rows, wherein a dummy sub-pixel row is provided between each adjacent at least one of the sub-pixel rows, and the second sub-power line is located in the dummy sub-pixel row.

[0013] In some embodiments, in the display substrate provided in the present disclosure, the display area includes a plurality of sub-pixel rows extending along the second direction and arranged along the first direction, and the second sub-power line is located in at least a portion of the sub-pixel rows.

[0014] In some embodiments, in the display substrate provided in the present disclosure, the border area includes a first border area and a second border area disposed opposite to each other on both sides of the display area, and both the first border area and the second border area extend along the second direction.

[0015] The first power bus includes a first sub-power bus located in the first frame area and / or the second frame area, and the first sub-power bus is electrically connected to the first sub-power line and the first electrode, respectively.

[0016] In some embodiments, in the display substrate provided in the present disclosure, the first sub-power bus includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion; wherein the first portion is disposed adjacent to the display area and electrically connected to the first sub-power line, and the second portion is located on the side of the first portion away from the display area and electrically connected to the first electrode.

[0017] In some embodiments, in the display substrate provided in the present disclosure, the line width of the third portion is greater than the line width of the first portion and less than the line width of the second portion.

[0018] In some embodiments, the display substrate provided in this disclosure further includes a transition electrode located between the layer where the first power bus is located and the layer where the first electrode is located, the transition electrode connecting the second portion and the first electrode.

[0019] In some embodiments, the display substrate provided in the present disclosure further includes a second electrode located between the first power bus layer and the first electrode layer, wherein the transition electrode is disposed on the same layer and made of the same material as the second electrode.

[0020] In some embodiments, the display substrate provided in the present disclosure further includes a second power bus located in the first border area and / or the second border area. The second power bus includes a main body extending along the second direction, and the main body is located in the area enclosed by the first portion, the second portion and the third portion.

[0021] In some embodiments, in the display substrate provided in the present disclosure, the second power bus further includes at least one lead-out portion located on the side of the main body away from the display area, and the second portion is disconnected at the position of the lead-out portion.

[0022] In some embodiments, in the display substrate provided in the present disclosure, the second power bus and the first sub-power bus are disposed in a different layer of insulation.

[0023] In some embodiments, in the display substrate provided in the present disclosure, the border area includes a third border area and a fourth border area disposed opposite to each other on both sides of the display area, and both the third border area and the fourth border area extend along the first direction;

[0024] The first power bus includes a second sub-power bus located in the third border area and / or the fourth border area, and the second sub-power bus is electrically connected to the second sub-power line.

[0025] In some embodiments, the display substrate provided in the present disclosure further includes a connecting line located in the third border area and / or the fourth border area, the connecting line being connected between the second sub-power bus and the second sub-power line.

[0026] In some embodiments, in the display substrate provided in the present disclosure, the connecting line, the second sub-power bus, and the second sub-power line are disposed on different layers.

[0027] In some embodiments, the display substrate provided in the present disclosure further includes a gate driving circuit located in the third border area and / or the fourth border area. The gate driving circuit is disposed on a different layer from the second sub-power bus, and the orthogonal projection of the gate driving circuit on the substrate is located within the orthogonal projection of the second sub-power bus on the substrate.

[0028] In some embodiments, the display substrate provided in the present disclosure further includes: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer sequentially disposed on the substrate and insulated from each other; the first sub-power line and the second sub-power line are disposed on at least one of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0029] On the other hand, this disclosure provides a display device including the display substrate described above. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0031] Figure 2 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0032] Figure 3 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0033] Figure 4 for Figure 3 A schematic diagram of the structure of the first and second power lines in region M;

[0034] Figure 5 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0035] Figure 6 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0036] Figure 7 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0037] Figure 8 for Figure 7 A schematic diagram of the structure of the first power line in region N;

[0038] Figure 9 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0039] Figure 10 for Figure 1 and Figure 3 A schematic diagram of the structure of the first power line, the first power bus, and the second power bus in region O;

[0040] Figure 11 for Figure 1 and Figure 3 A schematic diagram of the structure of the second sub-power bus, connecting lines, and first power line in the P region. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0042] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0043] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0044] As used in this disclosure, “approximately” or “roughly” includes the stated value and means within an acceptable range of deviation from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “roughly” may mean a difference relative to the stated value within one or more standard deviations (e.g., ±10%).

[0045] With the increasing prevalence of active-matrix organic light-emitting diode (AMOLED) displays in small-sized applications, the demand for AMOLED displays in medium-to-large-sized automotive displays, laptops, and tablets is growing rapidly due to their rich color gamut and high contrast. Related technologies typically place a first power bus (VSS) in the bezel area, and connect it to a planar cathode extending from the display area to the bezel area via perforations. Because the current density on the first power bus is relatively high, it is generally wide, which is not conducive to achieving a narrow bezel. Furthermore, as the size of AMOLED displays increases, the wiring length and resistance of the first power bus also increase, resulting in a larger load on the first power bus and a correspondingly larger IR drop. This causes delays in power signal transmission on the first power bus, affecting display uniformity.

[0046] To address the aforementioned technical problems in related technologies, this disclosure provides a display substrate, such as... Figure 1 As shown, it includes:

[0047] The substrate 101 includes a display area AA and a border area BB located on at least one side of the display area AA.

[0048] The first electrode 102 is located on the substrate 101 and extends from the display area AA to the frame area BB; optionally, the first electrode 102 is the cathode of the light-emitting device.

[0049] The first power bus 103 is located between the layer where the first electrode 102 is located and the substrate 101. The first power bus 103 is located in the border area BB and is electrically connected to the first electrode 102. Optionally, the first power bus 103 is a low-level power line VSS.

[0050] The first power line 104 is located between the layer where the first electrode 102 is located and the substrate 101. The first power line 104 is located in the display area AA. The first power line 104 has a mesh structure and is electrically connected to the first power bus 103.

[0051] In the display substrate provided in the embodiments of this disclosure, by adding a mesh structure first power line 104 in the display area AA and electrically connecting the first power line 104 to the first power bus 103 in the bezel area BB, the current can be distributed by the mesh structure first power line 104, thereby effectively alleviating the large current density on the first power bus 103, making the first power bus 103 narrower, which is beneficial for narrow bezel design; and the power signal provided by the first power bus 103 is distributed and transmitted through the mesh structure first power line 104, which can effectively reduce the voltage drop of the power signal on the transmission path and improve the uniformity of the power signal, thereby effectively improving the display uniformity.

[0052] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 As shown, the first power line 104 includes multiple first sub-power lines 1041 extending along the first direction Y and arranged along the second direction X, and multiple second sub-power lines 1042 extending along the second direction X and arranged along the first direction Y. The first sub-power lines 1041 and second sub-power lines 1042 can be electrically connected in the same layer or in different layers, and the first direction Y and the second direction X are intersected. Optionally, when the first sub-power lines 1041 and second sub-power lines 1042 are electrically connected in the same layer, they can be integrally arranged; when the first sub-power lines 1041 and second sub-power lines 1042 are electrically connected in different layers, they can be electrically connected by drilling holes or by other conductive parts, which is not limited here.

[0053] Considering that the display substrate itself has multiple conductive layers, to reduce the number of film layers, one or more of these conductive layers can be used to fabricate the first sub-power line 1041 and the second sub-power line 1042; for example, the display substrate can be a low-temperature polycrystalline oxide (LTPO) substrate, such as... Figure 2As shown, the substrate 101 includes a first active layer (Poly), a first gate metal layer (Gate1), a second gate metal layer (Gate2), a second active layer (not shown), a third gate metal layer (Gate3, not shown), a first source / drain metal layer (SD1), a second source / drain metal layer (SD2), and a third source / drain metal layer (SD3, not shown), which are sequentially disposed on the substrate 101 and insulated from each other. Optionally, a first sub-power line 1041 and a second sub-power line 1042 are disposed in at least one of the first gate metal layer (Gate1), the second gate metal layer (Gate2), the third gate metal layer (Gate3), the first source / drain metal layer (SD1), the second source / drain metal layer (SD2), and the third source / drain metal layer (SD3). For example, the first sub-power line 1041 is disposed in the first source-drain metal layer (SD1), the second source-drain metal layer (SD2), or the third source-drain metal layer (SD3), and the second sub-power line 1042 is disposed in the second gate metal layer (Gate2), the third gate metal layer (Gate3), the first source-drain metal layer (SD1), the second source-drain metal layer (SD2), or the third source-drain metal layer (SD3), without limitation.

[0054] In some embodiments, such as Figure 2 As shown, the structure of the display substrate provided in this disclosure, from bottom to top, may sequentially include a substrate 101, a buffer layer, a first active layer (Poly), a first gate insulating layer (GI1), a first gate metal layer (Gate1), a second gate insulating layer (GI2), a second gate metal layer (Gate2), an insulating layer (not shown in the figure), a second active layer (not shown in the figure), a third gate insulating layer (GI3, not shown in the figure), a third gate metal layer (Gate3, not shown in the figure), an interlayer dielectric layer (ILD), a first source / drain metal layer (SD1), a first planarization layer (PLN1), a second source / drain metal layer (SD2), a second planarization layer (PLN1), a third source / drain metal layer (SD3, not shown in the figure), a third planarization layer (PLN3), an anode (AND), a light-emitting functional layer (EL), a cathode (e.g., a first electrode 102), a first inorganic encapsulation layer (CVD1), an organic encapsulation layer (IJP), and a second inorganic encapsulation layer (CVD2).

[0055] The substrate 101 can be a flexible substrate, such as a plastic substrate with excellent heat resistance and durability made of polyvinyl ether phthalate, polyaryl compounds, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), cyclic olefin polymer (COP), cellulose acetate propionate (CAP), polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallyl ester, cellulose triacetate (TAC), etc.; or it can be a rigid substrate, such as a glass substrate, which is not limited here.

[0056] The materials of the buffer layer, the first gate insulating layer (GI1), the second gate insulating layer (GI2), the insulating layer (not shown in the figure), the third gate insulating layer (GI3), and the interlayer dielectric layer (ILD) may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. The film structure can be a single-layer structure or a multilayer structure, which is not limited here.

[0057] The materials of the first planarization layer (PLN1), the second planarization layer (PLN2), the third planarization layer (PLN3), and the pixel defining layer (PDL) can be organic insulating materials such as polyacrylic resin, polyepoxyacrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin, and are not limited here.

[0058] The materials of the first gate metal layer (Gate1), the second gate metal layer (Gate2), the third gate metal layer (Gate3, not shown in the figure), the first source / drain metal layer (SD1), the second source / drain metal layer (SD2), and the third source / drain metal layer (SD3, not shown in the figure) can be materials suitable for dry etching, such as molybdenum (Mo), aluminum (Al), and titanium (Ti). Optionally, these metal films can be single-layer metals or multilayer metals. For example, the gate metal layer is a single-layer molybdenum metal, and the source / drain metal layer is a triple layer composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0059] The light-emitting functional layer (EL) includes, but is not limited to, a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The light-emitting material layer can be a red light-emitting material layer, a green light-emitting material layer, a blue light-emitting material layer, a yellow light-emitting material layer, a white light-emitting material layer, etc.; and the light-emitting material layer can include small molecule organic materials or polymer molecules, and can be fluorescent light-emitting materials, phosphorescent light-emitting materials, etc.

[0060] The anode (AND) material may include at least one transparent conductive oxide material, including inert tin oxide (ITO), inert zinc oxide (IZO), zinc oxide (ZnO), etc.; in addition, the anode may include a metal with high reflectivity as a reflective layer, such as silver (Ag). The cathode (e.g., the first electrode 102) material may include metallic materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag).

[0061] The materials of the first inorganic encapsulation layer (CVD1) and the second inorganic encapsulation layer (CVD2) may include inorganic materials with high density, such as silicon nitride, silicon oxide, and silicon oxynitride, which can prevent the intrusion of water, oxygen, etc.; the materials of the organic encapsulation layer (IJP) may be polymer materials containing desiccants or polymer materials that can block water vapor, such as polymer resins, to planarize the surface of the display substrate and relieve the stress of the first and second inorganic encapsulation layers. They may also include water-absorbing materials such as desiccants to absorb water, oxygen, and other substances that have intruded into the interior.

[0062] Low-temperature polycrystalline oxide (LTPO) substrates include two types of thin-film transistors: low-temperature polycrystalline silicon (LTPS) thin-film transistors and oxide thin-film transistors, as well as components such as capacitors (C). Among them, LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors on a single display substrate can take advantage of both to achieve low-frequency driving while reducing power consumption, thereby improving display quality. In some embodiments, the first active layer may be the active layer of a low-temperature polycrystalline silicon thin-film transistor, such as low-temperature polycrystalline silicon; the second active layer may be the active layer of an oxide thin-film transistor, such as indium gallium zinc oxide; the first gate metal layer (Gate1) can be used to form the gate of the low-temperature polycrystalline silicon thin-film transistor and the first electrode plate of the capacitor; the second gate metal layer (Gate2) can be used to form the bottom gate of the oxide thin-film transistor and the second electrode plate of the capacitor; the third gate metal layer (Gate3) can be used to form the top gate of the oxide thin-film transistor; the first source-drain metal layer (SD1) can be used to form the source-drain of the low-temperature polycrystalline silicon thin-film transistor and the source-drain of the oxide thin-film transistor; the second source-drain metal layer (SD2) and the third source-drain metal layer (SD3) are used to form signal lines such as data lines. It can be seen that these conductive layers of the display substrate itself typically form thin-film transistors, capacitors, and other components of the pixel driving circuit in the display area AA. Therefore, to simplify the wiring design of a single conductive layer, this disclosure preferably places the first sub-power line 1041 and the second sub-power line 1042 on different film layers.

[0063] In some embodiments, in the display substrate provided in the present disclosure, the first sub-power line 1041 can be configured using the following two wiring methods, one of which is as follows: Figures 3 to 5 As shown, the display area AA includes multiple pixel columns PCs extending along the first direction Y and arranged along the second direction X, and multiple dummy sub-pixel columns DSPCs. A dummy sub-pixel column DSPC is set between each adjacent pixel column PC. To avoid affecting the normal display function of the pixel column PCs, the first sub-power line 1041 can be placed in the dummy sub-pixel column DSPC; another wiring method is as follows... Figure 6 As shown, the display area AA includes multiple sub-pixel columns SPCs extending along the first direction Y and arranged along the second direction X, without setting up a dummy sub-pixel column DSPC. In this case, the first sub-power line 1041 can be set at least some of the sub-pixel columns SPCs. For example, a first sub-power line 1041 can be set at each sub-pixel column SPC. Since it is only necessary to add the first sub-power line 1041 at at least some of the sub-pixel columns SPCs without adding a dummy sub-pixel column DSPC, the solution is relatively simple.

[0064] In some embodiments, in the display substrate provided in the present disclosure, the second sub-power line 1042 can be configured using the following two wiring methods, one of which is as follows: Figure 5 and Figure 7 As shown, the display area AA includes multiple sub-pixel rows SPRs extending along the second direction X and arranged along the first direction Y, and multiple dummy sub-pixel rows DSPRs. A dummy sub-pixel row DSPR is set between each adjacent sub-pixel row SPR. To avoid interfering with the normal display function of the sub-pixel rows SPRs, the second sub-power line 1042 can be placed in the dummy sub-pixel row DSPR; another wiring method is as follows... Figure 6 As shown, the display area AA includes multiple sub-pixel rows SPRs extending along the second direction X and arranged along the first direction Y, without setting up dummy sub-pixel rows DSPRs. In this case, the second sub-power line 1042 can be set at least some of the sub-pixel rows SPRs. For example, a second sub-power line 1042 can be set at each sub-pixel row SPR. Since it is only necessary to add the second sub-power line 1042 at at least some of the sub-pixel rows SPRs without adding dummy sub-pixel rows DSPRs, the solution is relatively simple.

[0065] In some embodiments, each pixel column (PC) may include multiple pixels, and each pixel includes multiple sub-pixels. Sub-pixels in the same column form a sub-pixel column (SPC), and sub-pixels in the same row form a sub-pixel row (SPR). Optionally, each pixel may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, so that color can be achieved by mixing red, green, and blue; or, a pixel may also include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, etc., so that color can be achieved by mixing red, green, blue, and white. Of course, in practical applications, the emission color of each sub-pixel in a pixel can be designed and determined according to the actual application environment, and is not limited here. In addition, the dummy subpixel column DSPC and dummy subpixel row DSPR can include multiple dummy subpixels D, which are the same as the red subpixel R, green subpixel G, blue subpixel B, etc. The dummy subpixel D can also include a pixel driving circuit and a light-emitting device. In order to ensure that each driving signal in the display area AA has the same load, the layout of the pixel driving circuit and the light-emitting device can be the same in the subpixel and the dummy subpixel D. The difference is that in the red subpixel R, green subpixel G, blue subpixel B, etc., the pixel driving circuit is electrically connected to the light-emitting device, and the light-emitting device can be driven to emit light through the pixel driving circuit. However, in the dummy subpixel D, the pixel driving circuit and the light-emitting device are not electrically connected. Therefore, the dummy subpixel D does not emit light.

[0066] See also Figure 4 As can be seen, the display substrate may further include a light-emitting control signal line (EM). Optionally, the light-emitting control signal line (EM) is located in the first gate metal layer (Gate 1). To avoid affecting the wiring space of the first gate metal layer (Gate 1), the second sub-power line 1042 may be located in the third gate metal layer (Gate 3). In some embodiments, the orthographic projection of the second sub-power line 1042 on the substrate 101 and the orthographic projection of the light-emitting control signal line (EM) on the substrate 101 may overlap. Since the layers on which they are located include a second gate insulating layer (GI2), an insulating layer (not shown in the figure), and a third gate insulating layer (GI3), even if their orthographic projections overlap, the coupling capacitance between them is small, and they will not cause significant interference. Of course, in some embodiments, the orthographic projection of the second sub-power line 1042 on the substrate 101 and the orthographic projection of the light-emitting control signal line (EM) on the substrate 101 may also be staggered, which is not limited here. See also Figure 8As can be seen, the display substrate may also include a second power line 106 that is substantially parallel to the second sub-power line 1042 (i.e. parallel or within the error range caused by factors such as manufacturing and measurement). In some embodiments, the second power line 106 is disposed on the same layer as the second sub-power line 1042, and the second power line 106 may be disposed in the sub-pixel row SPR and connected to a high-level power signal (VDD).

[0067] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 , Figure 9 and Figure 10 As shown, the bezel area BB includes a first bezel area BB1 and a second bezel area BB2 positioned opposite each other on both sides of the display area AA. Both the first bezel area BB1 and the second bezel area BB2 extend along the second direction X. The first power bus 103 includes a first sub-power bus 1031 located in the first bezel area BB1 and / or the second bezel area BB2. The first sub-power bus 1031 is electrically connected to the first sub-power line 1041 and the first electrode 102, respectively. When the first sub-power bus 1031 is provided in both the first bezel area BB1 and the second bezel area BB2, the impact of the voltage drop of the power signal on the transmission path on the display uniformity can be better reduced.

[0068] In some embodiments, in the display substrate provided in this disclosure, the first sub-power bus 1031 may be located in the first source / drain metal layer (SD1), and the first sub-power line 1041 may be located in the second source / drain metal layer (SD2). The first sub-power bus 1031 may be electrically connected to the first sub-power line 1041 by means of a hole. Furthermore, the first sub-power bus 1031 may be connected to the first electrode 102 (e.g., the cathode of a light-emitting device) through a transfer electrode that is disposed in the same layer and of the same material as the second electrode (e.g., the anode of a light-emitting device). Optionally, the transfer electrode may have a hollow structure, which can reduce the overlap area between the transfer electrode and the second power bus 105, thereby avoiding the overlap of large currents on the second power bus 105 and the first power bus 103.

[0069] It should be noted that, in this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes. The specific pattern in the formed layer structure can be continuous or discontinuous; these specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0070] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 , Figure 9 and Figure 10 As shown, the first sub-power bus 1031 may include a first portion 311 and a second portion 312 extending along the second direction X, and a third portion 313 connecting the first portion 311 and the second portion 312; wherein, the first portion 311 is disposed adjacent to the display area AA and electrically connected to the first sub-power line 1041, and the second portion 312 is located on the side of the first portion 311 away from the display area AA and electrically connected to the first electrode 102 and the bonding terminals (Pad) of the circuit board such as the chip-on-film (COF) film. Optionally, to minimize the border width, the line width of the first portion 311 electrically connected to the first sub-power line 1041 can be set to be slightly smaller, for example, the line width of the first portion 311 is smaller than the line width of the third portion 313; to enhance the electrical connection effect between the second portion 312 and the first electrode 102, the line width of the second portion 312 can be set to be slightly larger, for example, the line width of the second portion 312 is larger than the line width of the third portion 313; in other words, the line width of the third portion 313 can be larger than the line width of the first portion 311 and smaller than the line width of the second portion 312. Optionally, the line width of the second portion 312 is more than four times the line width of the first portion 311, so as to facilitate that the cathode (e.g., the first electrode 106) is only connected to the second portion 312, and not connected to the first portion 311.

[0071] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 , Figure 9 and Figure 10 As shown, it may also include a second power bus 105 located in the first border area BB1 and / or the second border area BB2. The second power bus 105 includes a main body 1051 extending along the second direction X. The main body 1051 is located within the area enclosed by the first portion 311, the second portion 312, and the third portion 313 to avoid the first sub-power bus 1031 and the second power bus 105 overlapping and interfering with each other. See also Figure 1 and Figure 9 As can be seen, the second power bus 105 may further include at least one lead-out portion 1052 located on the side of the main body 1051 away from the display area AA. This lead-out portion 1052 can be electrically connected to the bonding terminal (Pad) of a circuit board such as a chip-on-film (COF) film. The second portion 312 is disconnected at the position of the lead-out portion 1052 to avoid the first sub-power bus 1031 and the second power bus 105 overlapping and interfering with each other. Optionally, the second portions 312 on both sides of the disconnected position are electrically connected to the first electrode 102 to increase the overlap area between the second portion 312 and the first electrode 102, reduce the connection resistance between them, thereby reducing the voltage drop and saving energy.

[0072] In some embodiments, in the display substrate provided in this disclosure, the second power bus 105 can be electrically connected to the second power line 106 of the display area AA. Optionally, to avoid the second power line 105 being short-circuited with the first sub-power bus 1031 in the first bezel area BB1 and / or the second bezel area BB1, the second power bus 105 and the first sub-power bus 1031 can be disposed in a different layer with insulation. For example, the first power bus 103 is located in the first source-drain metal layer (SD1), and the second power bus 105 is located in the second source-drain metal layer (SD2). Optionally, the second power line 106 can be disposed in the same layer as the second power bus 105. For example, the second power line 106 is also disposed in the second source-drain metal layer (SD2).

[0073] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 , Figure 9 and Figure 11 As shown, the bezel area BB includes a third bezel area BB3 and a fourth bezel area BB4 positioned opposite each other on both sides of the display area AA. Both the third bezel area BB3 and the fourth bezel area BB4 extend along the first direction Y. The first power bus 103 includes a second sub-power bus 1032 located in the third bezel area BB3 and / or the fourth bezel area BB4. The second sub-power bus 1032 is electrically connected to a second sub-power line 1042, so that the current of the second sub-power bus 1032 can be shunted to the surface of the display area AA through the second sub-power line 1042. Optionally, a connecting line 107 can be provided in the third bezel area BB3 and / or the fourth bezel area BB4, which connects the second sub-power bus 1032 and the second sub-power line 1042. In some embodiments, to simplify single-layer wiring, the connecting line 107, the second sub-power bus 1032, and the second sub-power line 1042 can be arranged in different layers. For example, the connecting line 107 is located on the first source-drain metal layer (SD1), the second sub-power bus 1032 is located on the second source-drain metal layer (SD2), and the second sub-power line 1042 is located on the third gate metal layer (Gate3). Alternatively, as... Figure 11 As shown, the display area AA may include at least one signal line 1041' arranged substantially parallel to the first sub-power line 1041. In some embodiments, the signal line 1041' may be connected to a low-level power signal VSS, in which case the signal line 1041' may be connected in parallel with the first sub-power line 1041. In other embodiments, the signal line 1041' may be connected to a high-level power signal VDD, an initialization signal Vinit, etc., which are not limited here.

[0074] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 11As shown, it may also include a gate drive circuit GOA located in the third border area BB3 and / or the fourth border area BB4. The gate drive circuit GOA and the second sub-power bus 1042 are disposed on different layers. The orthographic projection of the gate drive circuit GOA on the substrate 101 can be located within the orthographic projection of the second sub-power bus 1042 on the substrate 101, so as to maximize the line width of the second sub-power line 1042, reduce the voltage drop, and improve the display uniformity while ensuring the narrow border effect.

[0075] Based on the same inventive concept, this disclosure provides a display device including the display substrate provided in the above-mentioned embodiments. Since the principle of the display device in solving the problem is similar to that of the display substrate in solving the problem, the implementation of the display device provided in this disclosure can refer to the implementation of the display substrate provided in the above-mentioned embodiments, and repeated details will not be described again.

[0076] In some embodiments, the display device can be any product or component with display functionality, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. The display device includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip can be a central processing unit, digital signal processor, or system-on-a-chip (SoC). For example, the control chip may also include memory and a power module, and power supply and signal input / output functions are implemented through additional wires and signal lines. For example, the control chip may also include hardware circuitry and computer-executable code. The hardware circuitry may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuitry may also include field-programmable gate arrays, programmable array logic, and programmable logic devices. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0077] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0078] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein, include: A substrate, the substrate including a display area and a border area located on at least one side of the display area; A first electrode is located on the substrate and extends from the display area to the border area; A first power bus is located between the layer containing the first electrode and the substrate, and the first power bus is located in the border area and is electrically connected to the first electrode. A first power line is located between the layer containing the first electrode and the substrate. The first power line is located in the display area. The first power line has a mesh structure and is electrically connected to the first power bus. The first electrode is a cathode; The first power line includes a plurality of first sub-power lines extending along a first direction and arranged along a second direction; The border area includes a first border area and a second border area that are positioned opposite each other on both sides of the display area, and both the first border area and the second border area extend along the second direction; The first power bus includes a first sub-power bus located in the first frame area and / or the second frame area, and the first sub-power bus is electrically connected to the first sub-power line and the first electrode, respectively.

2. The display substrate as claimed in claim 1, wherein, Multiple second sub-power lines extending along the second direction and arranged along the first direction, wherein the first sub-power lines and the second sub-power lines are electrically connected to each other on the same or different layers, and the first direction and the second direction are intersected.

3. The display substrate as described in claim 2, wherein, The display area includes a plurality of pixel columns extending along the first direction and arranged along the second direction and a plurality of dummy sub-pixel columns, with one dummy sub-pixel column provided between each adjacent at least one of the pixel columns, and the first sub-power line located in the dummy sub-pixel column.

4. The display substrate as claimed in claim 2, wherein, The display area includes a plurality of sub-pixel columns extending along the first direction and arranged along the second direction, wherein the first sub-power line is located in at least a portion of the sub-pixel columns.

5. The display substrate according to any one of claims 2 to 4, wherein, The display area includes a plurality of sub-pixel rows extending along the second direction and arranged along the first direction, and a plurality of dummy sub-pixel rows. A dummy sub-pixel row is provided between each adjacent at least one of the sub-pixel rows, and the second sub-power line is located in the dummy sub-pixel row.

6. The display substrate according to any one of claims 2 to 4, wherein, The display area includes a plurality of sub-pixel rows extending along the second direction and arranged along the first direction, wherein the second sub-power line is located at least a portion of the sub-pixel rows.

7. The display substrate as claimed in claim 1, wherein, The first sub-power bus includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion; wherein the first portion is disposed adjacent to the display area and electrically connected to the first sub-power line, and the second portion is located on the side of the first portion away from the display area and electrically connected to the first electrode.

8. The display substrate as claimed in claim 7, wherein, The line width of the third section is greater than that of the first section and less than that of the second section.

9. The display substrate as claimed in claim 7 or 8, wherein, It also includes a transition electrode located between the layer where the first power bus is located and the layer where the first electrode is located, the transition electrode connecting the second part and the first electrode.

10. The display substrate as claimed in claim 9, wherein, It also includes a second electrode located between the first power bus layer and the first electrode layer, wherein the transition electrode is disposed on the same layer and made of the same material as the second electrode.

11. The display substrate as claimed in claim 7, wherein, It also includes a second power bus located in the first border area and / or the second border area, the second power bus including a main body extending along the second direction, the main body being located in the area enclosed by the first portion, the second portion and the third portion.

12. The display substrate as claimed in claim 11, wherein, The second power bus also includes at least one lead-out portion located on the side of the main body away from the display area, and the second portion is disconnected at the location of the lead-out portion.

13. The display substrate as claimed in claim 11 or 12, wherein, The second power bus and the first sub-power bus are separated by a different layer of insulation.

14. The display substrate according to any one of claims 2 to 4, 7, 8, 11, and 12, wherein, The border area includes a third border area and a fourth border area positioned opposite each other on both sides of the display area, and both the third border area and the fourth border area extend along the first direction; The first power bus includes a second sub-power bus located in the third border area and / or the fourth border area, and the second sub-power bus is electrically connected to the second sub-power line.

15. The display substrate as claimed in claim 14, wherein, It also includes a connecting line located in the third border area and / or the fourth border area, the connecting line being connected between the second sub-power bus and the second sub-power line.

16. The display substrate as claimed in claim 15, wherein, The connecting line, the second sub-power bus, and the second sub-power line are arranged in different layers.

17. The display substrate as claimed in claim 14, wherein, It also includes a gate driving circuit located in the third border area and / or the fourth border area, the gate driving circuit being disposed on a different layer from the second sub-power bus, and the orthogonal projection of the gate driving circuit on the substrate being located within the orthogonal projection of the second sub-power bus on the substrate.

18. The display substrate according to any one of claims 2 to 4, 7, 8, 11, and 12, wherein, Also includes: A first active layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer are sequentially disposed on the substrate and are mutually insulated from each other; the first sub-power line and the second sub-power line are disposed on at least one of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

19. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 18.

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