Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate, a first signal line extending along a first direction as a whole, a second signal line extending along a second direction intersecting the first direction as a whole, and a sub-pixel arranged on the substrate; the first signal line transmits a first scanning signal, and the second signal line transmits a data signal; the sub-pixel comprises a pixel circuit, and the pixel circuit comprises: a light emitting device, a driving transistor, and a data writing transistor; the data writing transistor is configured to transmit the data signal to the driving transistor under the control of the first scanning signal; the driving transistor is configured to control the size of a driving current flowing through the light emitting device according to the data signal; the driving transistor comprises an active pattern and a gate electrode; the active pattern comprises a channel region; the orthographic projection of the channel region on the substrate at least partially overlaps the orthographic projection of the gate electrode on the substrate; the planar shape of the channel region of the driving transistor is a strip shape extending along the second direction as a whole; and the light emitting device is configured to receive the driving current and is driven by the driving current to emit light.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] In the display field, organic light-emitting diode (OLED) display panels have the advantages of self-illumination, high contrast, low power consumption, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and simple manufacturing, and have broad development prospects. To enrich the functionality of display panels, components with other functions are usually integrated, such as imaging elements with photosensitive functions, to realize functions such as camera and fingerprint recognition. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate, the display substrate including a substrate and sub-pixels disposed on the substrate; each sub-pixel includes a pixel circuit, the pixel circuit including: a first signal line and a second signal line, a light-emitting device, a driving transistor, a data writing transistor, and a storage capacitor. The data writing transistor is configured to transmit a data signal to the driving transistor under the control of a first scan signal, the first scan signal being transmitted on the first signal line and the data signal being transmitted on the second signal line; the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to the data signal, the light-emitting device being configured to receive the driving current and be driven by the driving current to emit light; the driving transistor includes an active pattern and a gate, the active pattern of the driving transistor including a channel region, the orthographic projection of the channel region on the substrate being at least partially overlapping with the orthographic projection of the gate on the substrate; the storage capacitor includes: a first electrode and a second electrode. The first electrode is electrically connected to the gate of the driving transistor; the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate, and does not overlap with the orthographic projection of the channel region of the driving transistor on the substrate.

[0004] For example, in at least one embodiment of the display substrate provided in this disclosure, the first electrode plate includes a first portion and a second portion. The orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate; the second portion is connected to the first portion and protrudes from the first portion, and the orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit further includes a first connection structure, which is electrically connected to the gate of the driving transistor and the first electrode plate. The orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate, and at least partially overlaps with the orthographic projection of the first portion on the substrate.

[0006] For example, in at least one embodiment of the display substrate provided in this disclosure, the first connection structure is disposed on the same layer as the first electrode of the driving transistor and is electrically connected to the first electrode plate through a first via; the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first portion of the first electrode plate on the substrate.

[0007] For example, in at least one embodiment of the display substrate provided in this disclosure, the first electrode plate and the gate of the driving transistor are disposed on the same layer and are an integral structure.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the first signal line is connected to the gate of the data writing transistor and configured to provide the first scan control signal to the gate of the data writing transistor; the first signal line includes a first lateral portion extending generally along a first direction and a first longitudinal portion extending generally along a second direction, the first lateral portion being connected to the first longitudinal portion, and the first direction intersecting the second direction; the data writing transistor includes an active pattern, and the orthographic projection of the active pattern of the data writing transistor on the substrate at least partially overlaps with the orthographic projection of the first longitudinal portion on the substrate.

[0009] For example, in at least one embodiment of the display substrate provided in this disclosure, the pixel circuit further includes a first light-emitting control transistor and a first light-emitting control line. The first light-emitting control transistor is connected to a first terminal and a first voltage terminal of the driving transistor, and is configured to apply a first power supply voltage of the first voltage terminal to the gate of the driving transistor under the control of a first light-emitting control signal; the first light-emitting control line is connected to the gate of the first light-emitting control transistor and is configured to provide the first light-emitting control signal to the gate of the first light-emitting control transistor; the first light-emitting control line includes a second lateral portion extending generally along the first direction and a second longitudinal portion extending generally along the second direction; the first light-emitting control transistor includes an active pattern, and the orthographic projection of the active pattern of the first light-emitting control transistor on the substrate at least partially overlaps with the orthographic projection of the second longitudinal portion on the substrate.

[0010] For example, in at least one embodiment of the display substrate provided in this disclosure, the pixel circuit further includes a second light-emitting control transistor and a second light-emitting control line. The second light-emitting control transistor is connected to a second light-emitting control terminal, the light-emitting device, and the second terminal of the driving transistor, and is configured to apply the driving current to the light-emitting device under the control of a second light-emitting control signal; the second light-emitting control line is connected to the gate of the second light-emitting control transistor and is configured to provide the second light-emitting control signal to the gate of the second light-emitting control transistor; the first light-emitting control line is multiplexed as the second light-emitting control line, and the second light-emitting control transistor includes an active pattern, the orthographic projection of the active pattern of the second light-emitting control transistor on the substrate at least partially overlapping the orthographic projection of the second vertical portion on the substrate.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the storage capacitor is located between the first vertical portion and the second vertical portion, and between the first horizontal portion and the second horizontal portion.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the active pattern of the first light-emitting control transistor includes a channel region, and the active pattern of the second light-emitting control transistor includes a channel region; in the first direction, the distance between the channel region of the first light-emitting control transistor and the channel region of the driving transistor is equal to the distance between the channel region of the second light-emitting control transistor and the channel region of the driving transistor; and in the second direction, the distance between the channel region of the first light-emitting control transistor and the channel region of the driving transistor is equal to the distance between the channel region of the second light-emitting control transistor and the channel region of the driving transistor.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the aspect ratio of the channel region of the first light-emitting control transistor is the same as the aspect ratio of the channel region of the second light-emitting control transistor.

[0014] For example, in at least one embodiment of the display substrate provided in this disclosure, the pixel circuit further includes a first power line. The first power line is connected to a first voltage terminal and configured to provide a first power supply voltage to the pixel circuit. It is disposed on the same layer as the first electrode of the driving transistor and includes a third vertical portion and a third horizontal portion. The third vertical portion extends generally along the second direction and is connected to the adjacent sub-pixel. The third horizontal portion is connected to the third vertical portion and extends from the third vertical portion toward the second electrode plate. The third horizontal portion is electrically connected to the second electrode plate through a second via.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the second signal line is disposed on the same layer as the first power line and includes a fourth lateral portion extending generally along the first direction and a fourth longitudinal portion extending generally along the second direction; in the second direction, the fourth lateral portion is at least partially opposite to the third lateral portion, and the orthographic projection of the fourth longitudinal portion on the substrate does not overlap with the orthographic projection of the third lateral portion on the substrate.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the third vertical portion is located on the first side of the storage capacitor in the first direction, and the orthographic projection of the fourth vertical portion on the substrate at least partially overlaps with the orthographic projection of the storage capacitor on the substrate, and does not overlap with the orthographic projection of the second via on the substrate.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit includes a semiconductor layer, the semiconductor layer includes a channel region of the driving transistor, and the orthographic projection of the third lateral portion on the substrate is located within the orthographic projection of the semiconductor layer on the substrate.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit further includes a compensation transistor configured to compensate the gate of the driving transistor in response to a second scan signal applied to the gate of the compensation transistor and the data signal; a first lateral portion of the first signal line providing the first scan signal to the data writing transistor is configured to provide the second scan signal to the compensation transistor; the compensation transistor includes an active pattern, the active pattern of the compensation transistor being disposed on the same layer as the active pattern of the driving transistor; the sub-pixel further includes a blocking portion. The blocking portion is located on the side of the active pattern of the compensation transistor away from the substrate, wherein the orthographic projection of the blocking portion on the substrate at least partially overlaps with the orthographic projection of the active pattern of the compensation transistor on the substrate; the pixel circuit further includes a reset signal line, and the blocking portion is electrically connected to the reset signal line.

[0019] For example, in at least one embodiment of the display substrate provided in this disclosure, the shielding portion and the reset signal line are disposed on the same layer and integrally formed.

[0020] For example, in at least one embodiment of the display substrate provided in this disclosure, the pixel circuit includes a semiconductor layer, the semiconductor layer including an active pattern of the driving transistor; the semiconductor layer includes a first portion and a second portion, the first portion and the second portion of the semiconductor layer are spaced apart by an opening, the orthographic projection of the opening on the substrate overlaps with the orthographic projection of the second lateral portion on the substrate, and the orthographic projections of the first portion and the second portion of the semiconductor layer on the substrate do not overlap with the orthographic projection of the second lateral portion on the substrate.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the planar shape of the channel region of the driving transistor is a strip that extends generally along the second direction.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the planar shape of the channel region of the driving transistor is a straight strip extending along the second direction.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, the sub-pixel includes a first electrode, which is electrically connected to one of the first and second electrodes of the driving transistor; the substrate includes a plurality of the sub-pixels, the plurality of sub-pixels including a first sub-pixel and two adjacent second sub-pixels, the two adjacent second sub-pixels being an upper second sub-pixel and a lower second sub-pixel, the orthographic projection of the first electrode of the upper second sub-pixel on the substrate and the orthographic projection of the first connection structure of the upper second sub-pixel on the substrate at least partially overlap, and the orthographic projection of the first electrode of the lower second sub-pixel on the substrate and the orthographic projection of the first connection structure of the lower second sub-pixel on the substrate at least partially overlap.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, the first sub-pixel emits red light and the second sub-pixel emits green light.

[0025] This disclosure provides at least one embodiment of a display device, which includes any of the display substrates provided in the embodiments of this disclosure. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0027] Figure 1 This is a schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0028] Figure 2AA schematic diagram of a pixel circuit provided in at least one embodiment of this disclosure;

[0029] Figure 2B for Figure 2A A circuit diagram of a specific example of a pixel circuit is shown;

[0030] Figure 2C A signal timing diagram of a driving method for a pixel circuit provided in at least one embodiment of this disclosure;

[0031] Figure 3A This is a schematic diagram of the structure of a sub-pixel of a display substrate according to an embodiment of the present disclosure;

[0032] Figure 3B for Figure 3A The diagram shows a planar schematic of the semiconductor layer in the display substrate.

[0033] Figure 3C for Figure 3A A schematic plan view of the first conductive layer in the display substrate shown;

[0034] Figure 3D for Figure 3A The diagram shows a planar schematic of the stacked semiconductor layer and first conductive layer in the display substrate.

[0035] Figure 3E for Figure 3A A schematic plan view of the second conductive layer in the display substrate shown;

[0036] Figure 3F for Figure 3A A planar schematic diagram showing the stacked semiconductor layer, first conductive layer, and second conductive layer in the display substrate;

[0037] Figure 3G for Figure 3A A schematic plan view of the third conductive layer in the display substrate shown;

[0038] Figure 3H A plan view of the first electrode provided in at least one embodiment of this disclosure;

[0039] Figure 3I for Figure 3A The semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of the display substrate shown are... Figure 3H A schematic diagram of the first electrode stack shown;

[0040] Figure 4A For along Figure 3A A cross-sectional view of line A-A' in the middle;

[0041] Figure 4B For along Figure 3AA cross-sectional view of line B-B' in the diagram;

[0042] Figure 4C For along Figure 3A A cross-sectional view of line C-C' in the middle;

[0043] Figure 4D For along Figure 3A A cross-sectional view of line D-D' in the middle;

[0044] Figure 4E For along Figure 3A A sectional view of line E-E' in the middle;

[0045] Figure 4F A plan view of the channel region of another driving transistor of a display substrate provided in at least one embodiment of the present disclosure;

[0046] Figure 4G for Figure 5A A magnified view of a sub-pixel;

[0047] Figure 5A A schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of this disclosure;

[0048] Figure 5B for Figure 5A The diagram shows a planar schematic of the semiconductor layer in the display substrate.

[0049] Figure 5C for Figure 5A A schematic plan view of the first conductive layer in the display substrate shown;

[0050] Figure 5D for Figure 5A The diagram shows a planar schematic of the stacked semiconductor layer and first conductive layer in the display substrate.

[0051] Figure 5E for Figure 5A A schematic plan view of the second conductive layer in the display substrate shown;

[0052] Figure 5F for Figure 5A A planar schematic diagram showing the stacked semiconductor layer, first conductive layer, and second conductive layer in the display substrate;

[0053] Figure 5G for Figure 5F The structure shown is illustrated in plan view along with each via.

[0054] Figure 5H for Figure 5A A schematic plan view of the third conductive layer in the display substrate shown;

[0055] Figure 5I A plan view of the first electrode provided in at least one embodiment of this disclosure;

[0056] Figure 5J for Figure 5A The semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of the display substrate shown are... Figure 5I A schematic diagram of the first electrode stack shown;

[0057] Figure 6A For along Figure 5A A cross-sectional view of line F-F' in the middle;

[0058] Figure 6B for Figure 5A A magnified view of a sub-pixel;

[0059] Figure 7A This is a schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure;

[0060] Figure 7B for Figure 7A The diagram shows a planar schematic of the semiconductor layer in the display substrate.

[0061] Figure 7C for Figure 7A A schematic plan view of the first conductive layer in the display substrate shown;

[0062] Figure 7D for Figure 7A The diagram shows a planar schematic of the stacked semiconductor layer and first conductive layer in the display substrate.

[0063] Figure 7E for Figure 7A A schematic plan view of the second conductive layer in the display substrate shown;

[0064] Figure 7F for Figure 7A A planar schematic diagram showing the stacked semiconductor layer, first conductive layer, and second conductive layer in the display substrate;

[0065] Figure 7G for Figure 7A A schematic plan view of the third conductive layer in the display substrate shown;

[0066] Figure 7H A plan view of the first electrode provided in at least one embodiment of this disclosure;

[0067] Figure 7I for Figure 7A The semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of the display substrate shown are... Figure 7H A schematic diagram of the first electrode stack shown;

[0068] Figure 8A For along Figure 7A A cross-sectional view of line G-G' in the middle;

[0069] Figure 8B For along Figure 7A A cross-sectional view of line H-H' in the middle;

[0070] Figure 8C For along Figure 7A A cross-sectional view of line I-I' in the middle;

[0071] Figure 8D Figure 7A A magnified view of a sub-pixel;

[0072] Figure 9A This is a schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure;

[0073] Figure 9B for Figure 9A The diagram shows a planar schematic of the semiconductor layer in the display substrate.

[0074] Figure 9C for Figure 9A A schematic plan view of the first conductive layer in the display substrate shown;

[0075] Figure 9D for Figure 9A The diagram shows a planar schematic of the stacked semiconductor layer and first conductive layer in the display substrate.

[0076] Figure 9E for Figure 9A A schematic plan view of the second conductive layer in the display substrate shown;

[0077] Figure 9F for Figure 9A A planar schematic diagram showing the stacked semiconductor layer, first conductive layer, and second conductive layer in the display substrate;

[0078] Figure 9G for Figure 9A A schematic plan view of the third conductive layer in the display substrate shown;

[0079] Figure 9H A plan view of the first electrode provided in at least one embodiment of this disclosure;

[0080] Figure 9I for Figure 9A The semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of the display substrate shown are... Figure 9H A schematic diagram of the first electrode stack shown;

[0081] Figure 9J for Figure 9A A magnified view of a sub-pixel;

[0082] Figure 10A For along Figure 9A A cross-sectional view of line J-J' in the middle;

[0083] Figure 10B For along Figure 9A A cross-sectional view of line K-K' in the middle;

[0084] Figure 10C For along Figure 9A A cross-sectional view of line L-L' in the diagram. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The embodiments described below are some, but not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0086] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0087] The scale of the figures in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure.

[0088] At least one embodiment of this disclosure provides a display substrate, the display substrate including a substrate, a first signal line generally extending along a first direction disposed on the substrate, and a second signal line generally extending along a second direction intersecting the first direction, the first signal line transmitting a first scan signal, and the second signal line transmitting a data signal; the sub-pixel includes a pixel circuit; the pixel circuit includes: a light-emitting device, a driving transistor, and a data writing transistor; the data writing transistor is configured to transmit a data signal to the driving transistor under the control of the first scan signal, the first scan signal being transmitted on the first signal line, and the data signal being transmitted on the second signal line; the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to the data signal, the driving transistor including an active pattern and a gate, the active pattern including a channel region, the orthographic projection of the channel region on the substrate overlapping with the orthographic projection of the gate on the substrate; the planar shape of the channel region of the driving transistor is a strip extending generally along the second direction; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. In the display substrate provided in this embodiment, the channel region of the driving transistor is a strip that extends along the second direction as a whole, which increases the aspect ratio of the channel region of the driving transistor and helps to save the layout space of the pixel circuit.

[0089] At least one embodiment of this disclosure provides a display substrate, which includes a substrate and sub-pixels disposed on the substrate. Each sub-pixel includes a pixel circuit, comprising a first signal line and a second signal line, a light-emitting device, a driving transistor, a data writing transistor, and a storage capacitor. The data writing transistor is configured to transmit a data signal to the driving transistor under the control of a first scan signal, wherein the first scan signal is transmitted on the first signal line and the data signal is transmitted on the second signal line. The driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The driving transistor includes an active pattern and a gate, the active pattern of which includes a channel region, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate. The storage capacitor includes a first electrode and a second electrode. The first electrode plate is electrically connected to the gate of the driving transistor; the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, but does not overlap with the orthographic projection of the channel region of the driving transistor on the substrate. In the display panel provided in this embodiment, since the second electrode plate is connected to a first power supply voltage for voltage regulation, the first power supply voltage signal will affect the channel region of the driving transistor. In order to reduce its impact on the channel region of the driving transistor, the second electrode plate is made to avoid the channel region of the driving transistor, so as to avoid affecting the performance of the driving transistor.

[0090] For example, Figure 1 This is a schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. Figure 1 As shown, for example, the display substrate 10 includes a plurality of pixels 100 arranged in an array. At least a portion of the pixels 100 include a plurality of sub-pixels, and at least a portion of the sub-pixels include a light-emitting device and a pixel circuit for driving the light-emitting device to emit light. For example, the pixel circuit may include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, a 5T1C, a 7T1C, or an nTmC (n and m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit may also include a compensation sub-circuit, which may include an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include transistors, capacitors, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc.

[0091] For example, such as Figure 1As shown, multiple pixels 100 are located in the display area. For example, in the display substrate 10 provided in some embodiments, some of the pixels among the multiple pixels 100 are dummy pixels 1000. The dummy pixels 1000 do not participate in the display operation. Each dummy pixel 1000 includes multiple dummy subpixels, but does not include subpixels that play a display driving role.

[0092] For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 may also include multiple scan lines and multiple data lines to provide scan signals (control signals) and data signals to the multiple sub-pixels, thereby driving the multiple sub-pixels. As needed, the display substrate 10 may further include power lines, detection lines, etc.

[0093] Figure 2A This is a schematic diagram of a pixel circuit provided in at least one embodiment of the present disclosure. Figure 2A As shown, the pixel circuit unit 100 includes a driving sub-circuit 122, a compensation sub-circuit 128, a data writing sub-circuit 126, a storage sub-circuit 127, a first light emission control sub-circuit 123, a second light emission control sub-circuit 124, a first reset sub-circuit 125, and a second reset sub-circuit 129.

[0094] For example, the driving sub-circuit 122 includes a control terminal 122a, a first terminal 122b, and a second terminal 122c, and is configured to be connected to the light-emitting device 121 and control the driving current flowing through the light-emitting device 121. The control terminal 122a of the driving sub-circuit 122 is connected to the first node N1, the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2 and configured to receive the first power supply voltage VDD, and the second terminal 122c of the driving sub-circuit 122 is connected to the third node N3.

[0095] For example, the data writing sub-circuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c. The control terminal 126a is configured to receive a first scan signal Ga1, the first terminal 126b is configured to receive a data signal Vd, and the second terminal 126c is connected to the first terminal 122b (i.e., the second node N2) of the driving sub-circuit 122. The data writing sub-circuit 126 is configured to write the data signal Vd to the first terminal 122b of the driving sub-circuit 122 in response to the first scan signal Ga1. For example, the first terminal 126b of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11, which serves as the scan line, to receive the first scan signal Ga1. For example, during the data writing and compensation phase, the data writing sub-circuit 126 can be turned on in response to the first scan signal Ga1, thereby writing the data signal to the first terminal 122b (second node N2) of the driving sub-circuit 122 and storing the data signal in the storage sub-circuit 127 so that, for example, during the light emission phase, a driving current for driving the light emission device 121 to emit light can be generated based on the data signal.

[0096] For example, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b, and a second terminal 128c. The control terminal 128a of the compensation sub-circuit 128 is configured to receive a second scan signal Ga2. The first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the drive sub-circuit 122, respectively. The compensation sub-circuit 128 is configured to perform threshold compensation on the drive sub-circuit 122 in response to the second scan signal Ga2.

[0097] For example, the first scan signal Ga1 can be the same as the second scan signal Ga2. Alternatively, the first scan signal Ga1 and the second scan signal Ga2 can be connected to the same signal output terminal. Or, the first scan signal Ga1 and the second scan signal Ga2 can be transmitted through the same scan line.

[0098] In other examples, the first scan signal Ga1 may also be different from the second scan signal Ga2. For example, the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals. For example, the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines.

[0099] For example, the storage sub-circuit 127 includes a first terminal 127a and a second terminal 127b. The first terminal 127a of the storage sub-circuit is configured to receive a first power supply voltage VDD, and the second terminal 127b of the storage sub-circuit is electrically connected to the control terminal 122a of the drive sub-circuit.

[0100] For example, the storage sub-circuit 127 is electrically connected to the control terminal 122a and the first voltage terminal vdd of the driving sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126. For example, during the data writing and compensation phase, the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, thereby storing the data signal written by the data writing sub-circuit 126 in the storage sub-circuit 127. For example, simultaneously during the data writing and compensation phase, the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, thereby storing the relevant information of the threshold voltage of the driving sub-circuit 122 in the storage sub-circuit accordingly. Thus, for example, during the light emission phase, the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122, thereby compensating the output of the driving sub-circuit 122.

[0101] For example, the first light-emitting control sub-circuit 123 is connected to the first terminal 122b (second node N2) and the first voltage terminal vdd of the driving sub-circuit 122, and is configured to apply the first power supply voltage VDD of the first voltage terminal vdd to the first terminal 122b of the driving sub-circuit 122 in response to the first light-emitting control signal EM1. For example, as Figure 2A As shown, the first light-emitting control sub-circuit 123 is connected to the first light-emitting control terminal EM1, the first voltage terminal vdd, and the second node N2.

[0102] For example, the second light-emitting control sub-circuit 124 is connected to the second light-emitting control terminal EM2, the first terminal 134 of the light-emitting device 121 and the second terminal 122c of the driving sub-circuit 122, and is configured to allow a driving current to be applied to the light-emitting device 121 in response to the second light-emitting control signal.

[0103] For example, during the light-emitting phase, the second light-emitting control sub-circuit 124 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving sub-circuit 122 can be electrically connected to the light-emitting device 121 through the second light-emitting control sub-circuit 124, thereby driving the light-emitting device 121 to emit light under the control of the driving current; while during the non-light-emitting phase, the second light-emitting control sub-circuit 124 is turned off in response to the second light-emitting control signal EM2, thereby preventing current from flowing through the light-emitting device 121 and causing it to emit light, which can improve the contrast of the corresponding display device.

[0104] For example, during the initialization phase, the second light-emitting control sub-circuit 124 can also be turned on in response to the second light-emitting control signal EM2, thereby enabling the reset sub-circuit to perform a reset operation on the drive sub-circuit 122 and the light-emitting device 121 in conjunction with the reset sub-circuit.

[0105] For example, the second light-emitting control signal EM2 can be the same as the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 can be connected to the same signal output terminal as the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 can be transmitted through the same light-emitting control line as the first light-emitting control signal EM1.

[0106] In other examples, the second light-emitting control signal EM2 may be different from the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be connected to different signal output terminals. For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be transmitted through different light-emitting control lines.

[0107] For example, the first reset sub-circuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the drive sub-circuit 122, and is configured to apply the first reset voltage Vinit1 to the control terminal 122a of the drive sub-circuit 122 in response to the first reset control signal Rst1.

[0108] For example, the second reset sub-circuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 134 (fourth node N4) of the light-emitting device 121, and is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light-emitting device 121 in response to the second reset control signal Rst2.

[0109] For example, the first reset sub-circuit 125 and the second reset sub-circuit 129 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively. This allows the second reset voltage Vinit2 to be applied to the first node N1 and the first reset voltage Vinit1 to be applied to the first terminal 134 of the light-emitting device 121, thereby resetting the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting device 121, eliminating the influence of the previous light-emitting stage.

[0110] For example, the second reset control signal Rst2 for each row of sub-pixels can be the same signal as the first scan signal Ga1 for that row of sub-pixels, and both can pass through the same gate line (e.g. Figure 3A The reset control line 220b in the middle is used for transmission. For example, the first reset control signal Rst1 of each row of sub-pixels can be transmitted through the same gate line (e.g., the first scan signal Ga1 of the previous row of sub-pixels). Figure 3A The reset control line 220a) is used for transmission.

[0111] For example, such as Figure 2AThe light-emitting device 121 includes a first terminal 134 and a second terminal 135. The first terminal 134 of the light-emitting device 121 is configured to be connected to the second terminal 122c of the driving sub-circuit 122, and the second terminal 135 of the light-emitting device 121 is configured to be connected to the second voltage terminal VSS. For example, in one example, as... Figure 2A As shown, the first terminal 134 of the light-emitting device 121 can be connected to the fourth node N4 through the second light-emitting control sub-circuit 124. Embodiments of this disclosure include, but are not limited to, this scenario.

[0112] It should be noted that in the description of the embodiments of this disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0113] It should be noted that, in the description of the embodiments of this disclosure, the symbol Vd can represent both a data signal terminal and the level of a data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal, or both the first scan signal terminal and the second scan signal terminal. The symbol Rst1 can represent both the first reset control terminal and the first reset control signal, and the symbol Rst2 can represent both the second reset control terminal and the second reset control signal. The symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal, or both the first reset voltage and the second reset voltage. The symbol VDD can represent both the first power supply voltage and the first power supply line, and the symbol VSS can represent both the common power supply voltage and the common power supply line. The following embodiments are the same and will not be described again.

[0114] Figure 2B for Figure 2A The circuit diagram shown is a specific implementation example of the pixel circuit. For example... Figure 2B As shown, the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, as well as a storage capacitor Cst. For example, the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

[0115] For example, such as Figure 2B As shown, the driving sub-circuit 122 can be implemented as a first transistor T1. The gate of the first transistor T1 serves as the control terminal 122a of the driving sub-circuit 122 and is connected to the first node N1; the first terminal of the first transistor T1 serves as the first terminal 122b of the driving sub-circuit 122 and is connected to the second node N2; the second terminal of the first transistor T1 serves as the second terminal 122c of the driving sub-circuit 122 and is connected to the third node N3.

[0116] For example, such as Figure 2BAs shown, the data writing sub-circuit 126 can be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first terminal of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second terminal of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.

[0117] For example, such as Figure 2B As shown, the compensation sub-circuit 128 can be implemented as a third transistor T3. The gate, first terminal, and second terminal of the third transistor T3 serve as the control terminal 128a, first terminal 128b, and second terminal 128c of the compensation sub-circuit, respectively. The gate of the third transistor T3 is configured to be connected to the second scan line (second scan signal terminal Ga2) to receive the second scan signal. The first terminal T3s of the third transistor T3 is connected to the second terminal T1d (third node N3) of the first transistor T1, and the second terminal T3d of the third transistor T3 is electrically connected to the gate T1g (first node N1) of the first transistor T1. For example, as... Figure 2B As shown, the storage sub-circuit 127 can be implemented as a storage capacitor Cst, which includes a first plate Cst1 and a second plate Cst2. The first plate Cst2 is electrically connected to the first voltage terminal vdd, and the second plate Cst1 is electrically connected to the gate T1g (first node N1) of the first transistor T1.

[0118] For example, such as Figure 2B As shown, the first light-emitting control sub-circuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, the first terminal of the fourth transistor T4 is connected to the first voltage terminal vdd to receive the first power supply voltage, and the second terminal of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.

[0119] For example, the light-emitting device 121 is specifically implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a micro LED or a micro OLED. For example, the light-emitting device 121 can be a top-emitting structure, a bottom-emitting structure, or a double-sided emitting structure. The light-emitting device 121 can emit red, green, blue, or white light, etc. The embodiments of this disclosure do not limit the specific structure of the light-emitting device.

[0120] For example, the first end of the light-emitting device 121 includes a first electrode (e.g., an anode), which is connected to the fourth node N4 and configured to be connected to the second end 122c of the driving sub-circuit 122 via the second light-emitting control sub-circuit 124. The second end of the light-emitting device 121 includes a second electrode (e.g., a cathode), which is configured to be connected to a common power supply voltage terminal VSS to receive the common power supply voltage VSS. The circuit flowing from the second end 122c of the driving sub-circuit 122 into the light-emitting device 121 determines the brightness of the light-emitting device. For example, the common power supply voltage terminal VSS can be grounded, i.e., VSS can be 0V. For example, the common power supply voltage VSS can be a negative voltage.

[0121] For example, the second light-emitting control sub-circuit 124 can be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light-emitting control line (second light-emitting control terminal EM2) to receive the second light-emitting control signal. The first terminal of the fifth transistor T5 is connected to the second terminal 122c (third node N3) of the driving sub-circuit 122, and the second terminal of the fifth transistor T5 is connected to the first terminal 134 (fourth node N4) of the light-emitting device 121.

[0122] For example, the first reset sub-circuit 125 can be implemented as a sixth transistor T6, and the second reset sub-circuit can be implemented as a seventh transistor T7. The gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1. The first terminal of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1. The second terminal of the sixth transistor T6 is configured to be connected to the first node N1. The gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2. The first terminal of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2. The second terminal of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0123] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal.

[0124] Furthermore, transistors can be classified into N-type and P-type transistors based on their characteristics. When a transistor is P-type, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage). For example, as... Figure 2B As shown, the first to seventh transistors T1-T7 are all P-type transistors, such as low-temperature polycrystalline silicon thin-film transistors. However, this embodiment does not limit the type of transistors; when the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0125] The following combination Figure 2C The signal timing diagram shown is for Figure 2B The working principle of the pixel circuit shown is explained. For example... Figure 2C As shown, the display process of each frame of the image includes three stages: initialization stage 1, data writing and compensation stage 2, and illumination stage 3.

[0126] like Figure 2C As shown, in this embodiment, the first scan signal Ga1 and the second scan signal Ga2 use the same signal, and the first light emission control signal EM1 and the second light emission control signal EM2 use the same signal; and the waveforms of the second reset control signal Rst2 and the first scan signal Ga1 / second scan signal Ga2 are the same, that is, the second reset control signal Rst2 and the first scan signal Ga1 / second scan signal Ga2 can use the same signal; the waveforms of the first reset signal Rst1 of the current row sub-pixel are the same as those of the first scan signal Ga1 / second scan signal Ga2 of the previous row sub-pixel, that is, the same signal is used. However, this is not intended to limit this disclosure. In other embodiments, different signals can be used as the first scan signal Ga1, the second scan signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first light emission control signal EM1 and the second light emission control signal EM2.

[0127] In initialization phase 1, the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.

[0128] In the data writing and compensation stage 2, the first scan signal Ga1, the second scan signal Ga2, and the data signal Vd are input. The second transistor T2 and the third transistor T3 are turned on. The data signal Vd is written to the second node N2 by the second transistor T2 and then charges the first node N1 through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd + Vth, at which point the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. This potential of the first node N1 is stored in the storage capacitor Cst and thus maintained. In other words, the voltage information containing the data signal and the threshold voltage Vth is stored in the storage capacitor Cst for use in the subsequent light-emitting stage to provide grayscale display data and compensate for the threshold voltage of the first transistor T1 itself.

[0129] In the data writing compensation stage 2, a second reset control signal Rst2 can also be input to turn on the seventh transistor T7, applying the second reset voltage Vinit2 to the fourth node N4, thereby resetting the fourth node N4. For example, the reset of the fourth node N4 can also be performed in the initialization stage 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 can be the same. This disclosure does not limit this aspect.

[0130] In the light-emitting stage 3, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5, and the first transistor T1. The fifth transistor T5 applies a driving current to the OLED to make it emit light. The value of the driving current Id flowing through the OLED can be obtained according to the following formula:

[0131] Id = K(VGS-Vth)2 = K[(Vd+Vth-VDD)-Vth]2 = K(Vd-VDD)2, where K is the conductivity coefficient of the first transistor.

[0132] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and source (here, the first electrode) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. As can be seen from the above formula for calculating Id, the driving current Id flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1. This allows for compensation of the pixel circuit, solving the problem of threshold voltage drift caused by the driving transistor (the first transistor T1 in this embodiment) due to process technology and long-term operation, eliminating its influence on the driving current Id, and thus improving the display effect of the display device using it.

[0133] Figure 3A This is a schematic diagram of the structure of a sub-pixel of a display substrate according to an embodiment of the present disclosure. Figure 3B-3I for Figure 3A The diagram shows a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first electrode of a display substrate. Figure 4A For along Figure 3A A sectional view of line A-A' in the middle. Figure 4B For along Figure 3A A cross-sectional view of line B-B' in the middle. Figure 4C For along Figure 3A A cross-sectional view of line C-C' in the middle. Figure 4D For along Figure 3A A cross-sectional view of line D-D' in the middle. Figure 4E For along Figure 3A A sectional view of line E-E' in the middle. Figure 4F This is a plan view of the channel region of another driving transistor in a display substrate provided in at least one embodiment of the present disclosure. Figure 4G for Figure 3A A magnified view of a sub-pixel. Below is a diagram showing a magnified view of a sub-pixel. Figure 2B Taking the pixel circuit shown as an example, and combining it with Figure 3B-3I and Figure 4A-4G The structure of a display substrate provided in at least one embodiment of the present disclosure will be described by way of example.

[0134] Combination Figure 3A , Figure 4B and Figure 4GThe display substrate 10 includes a substrate 200, a first signal line generally extending along a first direction D1 disposed on the substrate 200, and a second signal line generally extending along a second direction D2 intersecting the first direction D1. For example, the first signal line and the second signal line intersect to define a sub-pixel, such as defining multiple sub-pixels. It should be noted that the boundary of each of the multiple sub-pixels is not necessarily the first signal line and the second signal line. The intersection of the first signal line and the second signal line to define a sub-pixel means that the arrangement of the multiple sub-pixels is consistent with the arrangement of the multiple regions defined by the intersection of the first signal line and the second signal line, that is, the multiple sub-pixels correspond one-to-one with the region. For example, the first signal line is a gate line serving as a scan signal line, and the second signal line is a data line; or, in some other embodiments, the first signal line is a data line, and the second signal line is a gate line serving as a scan signal line. At least some of the multiple sub-pixels each include a pixel circuit 101, which includes the above-mentioned light-emitting device, a driving transistor T1, and a data writing transistor T2. For example, the "at least some sub-pixels" refers to sub-pixels that perform display functions, not dummy sub-pixels. The data writing transistor T2 is configured to transmit the data signal Vd to the driving transistor T1 under the control of the first scan signal Ga1. The first scan signal Ga1 is transmitted on the first signal line, and the data signal Vd is transmitted on the second signal line. The driving transistor T1 is configured to control the magnitude of the driving current flowing through the light-emitting device 121 according to the data signal Vd. The driving transistor T1 includes an active pattern T1a and a gate T1g. The active pattern T1a includes a channel region C1 (…). Figure 3A The dashed box in the plan view shown and Figure 4A As shown, the orthographic projection of the channel region C1 on the substrate 200 overlaps with the orthographic projection of the gate T1g on the substrate 200; the planar shape of the channel region C1 of the driving transistor T1 is a strip extending along the second direction D2; the light-emitting device is configured to receive driving current and be driven by driving current to emit light. In the display substrate 10 provided in the embodiments of this disclosure, the planar shape of the channel region C1 of the driving transistor T1 is a strip extending along the second direction D2. This feature can increase the length of the channel region of the driving transistor (the length along the second direction D2), thereby increasing the aspect ratio of the channel region of the driving transistor to ensure that the leakage current of the driving transistor T1 is small and the driving is stable in the black state; the larger the length of the channel region of the driving transistor T1, the closer the output curve of the driving transistor T1 is to the ideal linear situation in the saturation region, so that the display substrate, such as the OLED display substrate, operates in the saturation region of the driving transistor T1, so that the brightness of the display panel using this display substrate is better controlled by the driving transistor T1; and this feature is beneficial to saving the layout space of the pixel circuit. The channel area C1 is different from the existing zigzag or S-shaped channels that extend along the first direction D1 and have obvious bends.

[0135] It should be noted that the term "strip extending generally along the second direction D2" includes extending substantially along the second direction D2, or at least generally along the second direction D2. For example, in some examples, the strip extending generally along the second direction D2 may have a certain degree of curvature, such as... Figure 4F The shape shown is a wavy shape that extends generally along the second direction D2; or, in some examples, the edges of the strip that extends generally along the second direction D2 may not be smooth lines, for example, its edges may have burrs or jagged edges. In short, it is sufficient to satisfy the requirement that the strip extends generally along the second direction D2.

[0136] For example, such as Figure 3A and Figure 3B As shown, the planar shape of the channel region C1 of the driving transistor T1 is a straight strip extending along the second direction D2, so as to better increase the aspect ratio of the channel region C1 of the driving transistor T1, making the planar shape of the channel region C1 of the driving transistor T1 more regular, thereby facilitating manufacturing and better saving the layout space of the pixel circuit.

[0137] Combination Figure 3B-3G and Figures 4A-4D It is known that the display substrate 10 includes a semiconductor layer 107, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a third conductive layer 203, a fourth insulating layer 304, and a fourth conductive layer 204 sequentially disposed on the substrate 200.

[0138] For example, such as Figure 3B The semiconductor layer 107 shown includes active patterns T1a-T7a of the first to seventh transistors T1-T7, wherein... Figure 3B As shown, the active patterns T1a-T7a of the first to seventh transistors T1-T7 are interconnected as a single structure. For example, the semiconductor layers 107 in each column of sub-pixels are interconnected as a single structure, and the semiconductor layers in adjacent columns of sub-pixels are spaced apart from each other.

[0139] For example, such as Figure 3C-3D As shown, the first conductive layer 201 includes the gate of each transistor as well as some scan lines and control lines. Figure 3A The area where the pixel circuitry of each sub-pixel is located is shown in large dashed boxes. Figure 3D The gates T1g-T7g of the first to seventh transistors T1-T7 in a pixel circuit unit 100 are shown in small dashed boxes.

[0140] For example, such as Figure 3C-3DAs shown, the first conductive layer 201 includes the gates T1g-T7g of the first to seventh transistors T1-T7. For example, the display substrate 10 employs a self-aligned process, using the first conductive layer 201 as a mask to perform a conductor-enhancing treatment (e.g., doping) on ​​the semiconductor layer 107, so that the portion of the semiconductor layer 107 not covered by the first conductive layer 201 is conductor-enhanced. Consequently, the portions of the active patterns of each transistor located on both sides of the channel region are conductor-enhanced to form the first and second electrodes of the transistor, respectively.

[0141] For example, the first conductive layer 201 also includes multiple gate lines that are insulated from each other. These gate lines include, for example, multiple scan lines 210, multiple reset control lines 220a / 220b, and multiple light emission control lines 230. Here, a gate line refers to a signal line that is directly connected to the gate of a transistor to provide a scan signal or a control signal. For example, each row of sub-pixels is respectively connected to one scan line 210, two reset control lines, and one light emission control line 230, wherein the two reset control lines are the first reset control line 220a and the second reset control line 220b.

[0142] For example, such as Figure 3A and Figure 3D As shown, the gate T6g of the sixth transistor T6 in this row of pixel circuits is electrically connected to the first reset control line 220a corresponding to this row to receive the first reset control signal Rst1. The gate of the seventh transistor T7 in this row of pixel circuits is electrically connected to the second reset control line 220b corresponding to the next row of pixel circuits (i.e., the row of pixel circuits where the scan lines are sequentially turned on after the scan lines in this row, according to the scanning order of the scan lines) to receive the second reset control signal Rst2.

[0143] Scan line 210 is electrically connected (or integrated) to the gate of the second transistor T2 in the corresponding row of sub-pixels to provide a first scan signal Ga1. A reset control line 220 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1. Light emission control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light emission control signal EM1.

[0144] For example, such as Figure 3AAs shown, scan line 210 is also electrically connected to the gates T3g1 / T3g2 of the third transistor T3 to provide a second scan signal Ga2, meaning the first scan signal Ga1 and the second scan signal Ga2 can be the same signal; a portion of scan line 210 constitutes the first gate T3g1 and the second gate T3g2 of the third transistor T3. Light emission control line 230 is also electrically connected to the gate T5g of the fifth transistor T5 to provide a second light emission control signal EM2, meaning the first light emission control signal EM1 and the second light emission control signal EM2 are the same signal; a portion of light emission control line 230 constitutes the gate T5g of the fifth transistor T5.

[0145] For example, combining Figure 3A and Figure 4B The pixel circuit 101 also includes a storage capacitor Cst, which includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is electrically connected to the gate T1g of the driving transistor T1. The orthographic projection of the second plate Cst2 on the substrate 200 at least partially overlaps with the orthographic projection of the first plate Cst1 on the substrate 200, but does not overlap with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200. Since the second plate Cst2 is connected to the first power supply voltage VDD for voltage regulation, this first power supply voltage signal will affect the channel region C1 of the driving transistor T1. In order to reduce its impact on the channel region C1 of the driving transistor T1, the second plate Cst2 is made to avoid the channel region C1 of the driving transistor T1, so as to avoid affecting the performance of the driving transistor.

[0146] For example, the first electrode plate Cst1 includes a first portion Cst11 and a second portion Cst12. The first portion Cst11 of the first electrode plate Cst1 extends along a second direction D2. For example, the planar pattern of the first electrode plate Cst1 is L-shaped. The orthographic projection of the first portion Cst11 of the first electrode plate Cst1 on the substrate 200 overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200. The second portion Cst12 of the first electrode plate Cst1 is connected to the first portion Cst11 and extends from the first portion Cst11 of the first electrode plate Cst1 along a first direction D1, protruding beyond the first portion Cst11 of the first electrode plate Cst1. The orthographic projection of the second portion Cst12 of the first electrode plate Cst1 on the substrate 200 at least partially overlaps with the orthographic projection of the second electrode plate Cst2 on the substrate 200.

[0147] For example, such as Figure 4BAs shown, the first electrode plate Cst1 and the gate T1g of the driving transistor T1 are disposed on the same layer and are integrally structured, for example, both located in the first conductive layer 201, to simplify the structure of the display substrate 10. Furthermore, the first electrode plate Cst1 and the gate T1g of the driving transistor T1 can be formed by performing the same patterning process on the same film layer using the same mask, simplifying the fabrication process of the display substrate 10. In this case, the first part Cst11 of the first electrode plate Cst1 is the first part T1ga of the gate of the driving transistor T1, and the second part Cst12 is the second part T1gb of the gate of the driving transistor T1.

[0148] It should be noted that the term "same-layer configuration" in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different. The term "integrated structure" in this disclosure refers to a structure formed by two (or more) structures interconnected by patterning the same film layer through the same patterning process, and their materials may be the same or different.

[0149] For example, combining Figure 3A and Figure 4A The pixel circuit also includes a first connection structure P1, which is electrically connected to the gate T1g of the driving transistor T1 and the first electrode Cst1. The orthographic projection of the first connection structure on the substrate 200 does not overlap with the orthographic projection of the second electrode Cst2 on the substrate 200. For example, the second electrode Cst2 is located on the second conductive layer 202, which is located on the side of the first conductive layer 201 away from the substrate 200. There is a second insulating layer 302 between the second conductive layer 202 and the first conductive layer 201. Thus, the first connection structure P1 needs to be electrically connected to the first electrode Cst1 through a via. The first connection structure P1 will not pass through the second electrode Cst2 of the storage capacitor Cst, thereby increasing the area of ​​the second electrode Cst2 to increase the capacitance of the storage capacitor.

[0150] For example, such as Figure 3A , Figure 3G and Figure 4A As shown, the first connection structure P1 is disposed on the same layer as the first electrode T1s of the driving transistor T1, and is electrically connected to the first plate Cst1 (i.e., the gate T1g of the driving transistor T1) through the first via V1. The orthographic projection of the first via V1 on the substrate 200 overlaps with the orthographic projection of the second part Cst12 of the first plate Cst1 on the substrate 200, but does not overlap with the orthographic projection of the second plate Cst2 on the substrate 200. Therefore, the first via V1 does not pass through the second plate Cst2 of the storage capacitor Cst, thereby increasing the area of ​​the second plate Cst2 and increasing the capacitance of the storage capacitor.

[0151] For example, such as Figure 3A and Figure 4A The orthographic projection of the first connection structure P1 on the substrate 200 does not overlap with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200. The orthographic projection of the first connection structure P1 on the substrate 200 at least partially overlaps with the orthographic projection of the second part of the first electrode Cst1 on the substrate 200, so as to avoid the electrical signal on the first connection structure P1 from affecting the channel region C1 of the driving transistor T1.

[0152] For example, in Figure 3A In the embodiment shown, the first connection structure P1 is a straight strip extending along the second direction D2, which is beneficial for saving space and for arranging other structures of the pixel circuit in a reasonable way with limited space. This is very important for the pixel design of the display substrate and can solve the important technical problem of how to effectively improve PPI.

[0153] For example, such as Figure 3A , Figure 3G and Figure 4B As shown, the pixel circuit also includes a first power line VDD, which is connected to a first voltage terminal and configured to provide a first power supply voltage to the pixel circuit. It is disposed on the same layer as the first electrode T1s of the driving transistor T1, for example, both located in the third conductive layer 203. It also includes a first vertical portion VDD1 and a first horizontal portion VDD2. The first vertical portion VDD1 extends along the second direction D2 and is connected to an adjacent sub-pixel; the first horizontal portion VDD2 is connected to the vertical portion and extends from the vertical portion toward the second electrode plate Cst2; the first horizontal portion VDD2 is electrically connected to the second electrode plate Cst2 through a second via V2.

[0154] For example, the orthographic projection of the end of the first lateral portion VDD2 away from the first vertical portion VDD1 onto the substrate in the first direction D1 does not exceed the orthographic projection of the second electrode Cst2 onto the substrate.

[0155] For example, in Figure 3A In the illustrated embodiment, the first power line VDD and the data line Data are located on the same side of the storage capacitor Cst; in other embodiments, the first power line VDD and the data line Data may be located on different sides of the storage capacitor Cst.

[0156] For example, in Figure 3AIn the illustrated embodiment, the first power line VDD and the data line Data are located on the same layer, both in the third metal layer 203; in other embodiments, the first power line VDD and the data line Data may be located on different layers. For example, in at least one embodiment, the display substrate further includes a fourth metal layer located in the third metal layer 203, away from the substrate 200. For example, the first power line VDD is located in the third metal layer 203, and the data line Data is located in the fourth metal layer; or, the first power line VDD is located in the fourth metal layer, and the data line Data is located in the third metal layer 203.

[0157] For example, such as Figure 3A , Figure 3C and Figure 4G As shown, the first portion Cst11 of the first electrode plate Cst1 has a first end in the second direction D2, which, together with the second portion Cst12 of the first electrode plate Cst1, forms a blank notch H. Figure 4G (Within the dashed box indicated by the reference numeral H); the data writing transistor, namely the second transistor T2, provides a first signal line for the first scan signal, namely the scan line 210, which is arranged on the same layer as the first electrode plate Cst1 and spaced apart. The scan line 210 includes a main body 2101 and a protrusion 2102. The main body 2101 extends through the sub-pixel along the first direction D1, that is, it extends along the first direction D1 and connects from one sub-pixel to an adjacent sub-pixel, and the main body 2101 is located on the first side of the first electrode plate Cst1 in the second direction D2; the protrusion 2102 is connected to the main body 2101 and protrudes from the main body 2101 toward the first electrode plate Cst1, and the protrusion 2102 is at least partially located in the notch H. This design makes the arrangement compact and makes reasonable use of the limited space.

[0158] For example, a portion of the main body 2101 of the scan line 210 constitutes the first gate T3g1 of the third transistor T3, and the protrusion 2102 of the scan line 210 constitutes the second gate T3g2.

[0159] For example, the pixel circuit also includes a compensation transistor, namely a third transistor T3, which is configured to compensate the gate T1g of the driving transistor T1 in response to a second scan signal Ga2 and a data signal Vd applied to the gate T3g of the compensation transistor T3. Figure 3AAs shown, a first signal line 210, i.e., a scan line 210, provides a first scan signal Ga1 to the data writing transistor T2, and is also configured to provide a second scan signal Ga2 to the compensation transistor T3. The compensation transistor T3 includes a first gate T3g1 and a second gate T3g2; at least a portion of the protrusion 2102 of the scan line 210 constitutes the first gate T3g1 of the compensation transistor, and a portion of the main body 2101 of the scan line 210 constitutes the second gate T3g2 of the compensation transistor T3 and the gate T2g of the data writing transistor T2. The first gate T3g1 extends along a first direction D1, and the second gate T3g2 extends along a second direction D2.

[0160] For example, such as Figure 3B As shown, the compensation transistor T3 includes an active pattern T3a, and the active pattern T3a of the compensation transistor T3 is disposed on the same layer as the active pattern T1a of the driving transistor T1. Figure 4C As shown, the sub-pixel also includes a blocking portion 31, which is located on the side of the active pattern T3a of the compensation transistor T3 away from the substrate 200. The orthographic projection of the blocking portion 31 on the substrate 200 at least partially overlaps with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the substrate 200. The blocking portion 31 is electrically connected to the first connection structure P1. Thus, the blocking portion 31 blocks the active pattern T3a of the compensation transistor T3, for example, blocking the channel region of the compensation transistor T3, preventing light from affecting the performance of the channel region of the compensation transistor T3, and connecting the blocking portion 31 to the first connection structure P1. Figure 2B The electrical signal at node N1 is better stabilized to improve the potential of node N1. It should be noted that the active pattern T3a blocked by the blocking part 31 here is the conductive portion around the channel region of the compensation transistor T3, and does not include the channel region of the compensation transistor T3.

[0161] For example, such as Figure 4B and Figure 4C As shown, the shielding portion 31 and the second electrode plate Cst2 are disposed on the same layer, for example, both located on the second metal layer 202. Thus, both can be formed by performing a patterning process on the same film layer using the same mask, simplifying the structure and manufacturing process of the display substrate. For example, the orthographic projection of the first connection structure P1 on the substrate 200 at least partially overlaps with the orthographic projection of the shielding portion 31 on the substrate 200. The first connection structure P1 is electrically connected to the shielding portion 31 through the third via V3 to realize the electrical connection between the first connection structure P1 and the shielding portion 31.

[0162] For example, pixel circuit 101 also includes reset transistors, such as a first reset transistor, i.e., the sixth transistor T6, and a second reset transistor, i.e., the seventh transistor T7; Figure 3A and Figure 3EAs shown, the pixel circuit also includes a reset voltage line 240, which is on the same layer as the second electrode plate Cst2, for example, both located in the second conductive layer 202; and, as Figure 4D As shown, the reset voltage line 240 is electrically connected to the first terminal T6s of the first reset transistor T6 to provide the first reset voltage Vinit1 to the first reset transistor T6.

[0163] For example, such as Figure 3A and Figure 3E As shown, the second conductive layer 202 includes multiple reset voltage lines 240 extending along the first direction D1, each of which is connected to a corresponding row of sub-pixels. Each reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in a corresponding row of sub-pixels to provide a first reset voltage Vinit1 to the sixth transistor T6 in that row. The first electrode T7s of the seventh transistor T7 in the same row of sub-pixels is electrically connected to the reset voltage line 240 corresponding to the next row of sub-pixels to receive a second reset voltage Vinit2.

[0164] For example, such as Figure 3A , Figure 3G and Figure 4D As shown, the pixel circuit 101 also includes a second connection structure P2. The reset voltage line 240 is electrically connected to the first terminal T6s of the first reset transistor T6 through the second connection structure P2. For example, the second connection structure P2 is on the same layer as the first connection structure P1. The first end of the second connection structure P2 is electrically connected to the reset voltage line 240 through a fourth via V4, and the second end of the second connection structure P2 opposite to its first end is electrically connected to the first terminal T6s of the first reset transistor T6 through a fifth via V5.

[0165] For example, such as Figure 3A and Figure 4E As shown, the orthographic projection of the first power line VDD on the substrate 200 overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200. Thus, the first power line VDD blocks the channel region C1 of the driving transistor T1, thereby preventing the influence of light on the performance of the channel region C1 of the driving transistor T1 by utilizing the existing structure while saving layout space.

[0166] For example, such as Figure 4CAs shown, the light-emitting device 121 of the sub-pixel includes a first electrode 40, a second electrode (not shown), and a light-emitting layer (not shown) located between the first electrode 40 and the second electrode. The sub-pixel also includes a pixel defining layer 306 located on the side of the first electrode 40 of the light-emitting device away from the substrate 200. An opening is formed in the pixel defining layer 306 to expose at least a portion of the first electrode 40, thereby defining the opening region (i.e., the light-emitting region) 600 of each sub-pixel of the display substrate. The light-emitting layer of the light-emitting device is formed at least within the opening region 600 (the light-emitting layer may also cover a portion of the surface of the pixel defining layer away from the first electrode), and the second electrode is formed on the light-emitting layer to form the light-emitting device. For example, the second electrode is a common electrode, arranged across the entire surface of the display substrate 10. For example, the first electrode 40 is the anode of the light-emitting device, and the second electrode is the cathode of the light-emitting device.

[0167] For example, the light-emitting device 121 is a top-emitting structure, with the first electrode 40 being reflective and the second electrode being transmissive or semi-transmissive. For example, the first electrode 40 is made of a high work function material to act as the anode, such as an ITO / Ag / ITO stacked structure; the second electrode is made of a low work function material to act as the cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0168] In a sub-pixel, the first electrode 40 is electrically connected to one of the first electrode T1s and the second electrode T1d of the driving transistor T1. For example, as Figure 3H-3I As shown, the display substrate 10 has multiple sub-pixels, including a first sub-pixel, two adjacent second sub-pixels, and a third sub-pixel. The first, second, and third sub-pixels emit light of different colors. The first electrodes of the first, second, and third sub-pixels are first electrode 41, first electrode 42, and first electrode 43, respectively, as shown in the figure. The two adjacent second sub-pixels are upper second sub-pixel 100a and lower second sub-pixel 100b, respectively. Upper second sub-pixel 100a includes a first electrode 421, and lower second sub-pixel 100b includes a first electrode 422. For example, the display substrate includes multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels, thereby including multiple first electrodes 41, multiple first electrodes 42, and multiple first electrodes 43; the multiple first electrodes 42 include first electrodes 421 and first electrodes 422; the multiple first electrodes 41 include... Figure 3IThe first electrode 41a is the first electrode of the first sub-pixel adjacent to the upper second sub-pixel 100a. For example, the orthographic projection of the first connection structure P1-1 of the upper second sub-pixel 100a onto the substrate 200 and the orthographic projection of the first electrode 41a of the first sub-pixel adjacent to the upper second sub-pixel 100a onto the substrate 200 at least partially overlap. Furthermore, the orthographic projection of the first connection structure P1-2 of the lower second sub-pixel 100b onto the substrate 200 and the orthographic projection of the first electrode 422 of the lower second sub-pixel 100b onto the substrate 200 and the orthographic projection of the first electrode 421 of the upper second sub-pixel 100a onto the substrate 200 at least partially overlap. That is, the first connection structures P1 of two adjacent second sub-pixels (corresponding to node N1 in the circuit diagram) are blocked by the first electrode 41 of the adjacent first sub-pixel, the first electrode 421 of the upper second sub-pixel 100a, and the first electrode 422 of the lower second sub-pixel 100b, respectively. As a result, the first connection structures P1 of two adjacent second sub-pixels are basically blocked by the first electrode, making the light emission brightness of the two adjacent second sub-pixels tend to be consistent.

[0169] It should be noted that, in this application, the first electrode of a sub-pixel refers to the first electrode being connected to the pixel circuit of the sub-pixel through the ninth via V9, without requiring that the orthographic projection of the first electrode on the substrate be located within the orthographic projection of the pixel circuit (e.g., each thin-film transistor, each signal line, etc.) on the substrate.

[0170] like Figure 3I As shown, in each sub-pixel with a first electrode, taking the second sub-pixel 100a as an example, the first electrode 421 is electrically connected to the second terminal T1d of the driving transistor T1 through the ninth via V9.

[0171] For example, the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light.

[0172] For example, the upper second sub-pixel 100a and the lower second sub-pixel 100b are arranged along the second direction D2, and the upper second sub-pixel 100a and the first sub-pixel adjacent to it are arranged along the first direction D1. Of course, in other embodiments, the upper second sub-pixel 100a and the lower second sub-pixel 100b may also be arranged along the first direction D1, and the upper second sub-pixel 100a and the first sub-pixel adjacent to it may be arranged along the second direction D2. This disclosure does not limit the scope of the embodiments.

[0173] For example, such as Figure 3AAs shown, the first end of the first connection structure P1 is electrically connected to the semiconductor layer through the sixth via V6, and the second end of the first connection structure P1 opposite to its first end is electrically connected to the first plate Cst1 (i.e., the gate T1g of the driving transistor T1) through the first via V1; the data line Data is electrically connected to the semiconductor layer through the seventh via V7.

[0174] For example, refer to Figures 4A-4E The display substrate 10 also includes a buffer layer 200a located on the substrate 200, and a first semiconductor layer 107 located on the buffer layer 200a. The buffer layer 200a can prevent contamination and damage to the substrate 200 during the manufacturing process, making other structures formed thereon purer and flatter.

[0175] In the embodiments of this disclosure, the first terminal of the transistor is the source and the second terminal is the drain; or, the first terminal is the drain and the second terminal is the source.

[0176] In the display substrate 10 provided in the embodiments of this disclosure, for example, the substrate 200 can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP), and cyclic olefin copolymer (COC).

[0177] For example, the materials of the semiconductor layer 107 include, but are not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, polythiophene, etc.).

[0178] For example, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys composed of the above metals; or transparent conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0179] For example, the first insulating layer 301, the second insulating layer 302, the third insulating layer 303, and the fourth insulating layer 304 are inorganic insulating layers, and their materials include at least one of silicon oxides, silicon nitrides, silicon oxynitrides, etc., silicon oxides, silicon nitrides, or silicon oxynitrides, or include insulating materials including metal oxynitrides such as aluminum oxide and titanium nitride. For example, the pixel defining layer 306 and the fourth insulating layer 304 can be organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc. For example, the fourth insulating layer 304 is a planarization layer. This disclosure does not limit these aspects.

[0180] Figure 5A This is a schematic diagram of the structure of a sub-pixel of another display substrate provided in one embodiment of the present disclosure. Figure 5B-5J for Figure 5A The diagram shows the semiconductor layer, first conductive layer, second conductive layer, various vias, third conductive layer, and first electrode of the display substrate. Figure 6A For along Figure 5A A cross-sectional view of line F-F' in the middle. Figure 6B for Figure 5A A magnified view of a sub-pixel. Figure 5B-5J and Figures 6A-6B The pixel circuit of the display substrate provided in the illustrated embodiment is still as follows Figure 2B As shown, Figure 5B-5J and Figures 6A-6B The embodiment shown provides a display substrate and Figure 3A The display substrates provided in the illustrated embodiments have the following differences.

[0181] Figure 5A The routing design of the first signal line 210 in the illustrated embodiment is similar to... Figure 3A The differences. For example Figure 5A and Figure 5C As shown, the first portion Cst11 of the first electrode plate Cst1 has a first end in the first direction D1. The first signal line 210 (i.e., scan line 210) that provides the first scan signal Ga1 to the data writing transistor T2 is bent, including a bent portion 2103. The bent portion 2103 is disposed around the first end of the first portion Cst11 of the first electrode plate Cst1. The first end of the first portion Cst11 of the first electrode plate Cst1 in the second direction D2 and the second portion Cst12 of the first electrode plate Cst1 form a blanking gap H. The portion of the bent portion 2103 located on the first side of the first electrode plate Cst1 in the second direction D2 is at least partially located in the blanking gap H, so as to reasonably wire the circuit, utilize the limited space, and help improve the PPI and aperture ratio of the display panel using the display substrate.

[0182] like Figure 5A , Figure 5E and Figure 6A As shown, the sub-pixel includes a blocking portion 31, which is located on the side of the active pattern T3a of the compensation transistor T3 away from the substrate 200. The orthographic projection of the blocking portion 31 on the substrate 200 at least partially overlaps with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the substrate 200. The blocking portion 31 is electrically connected to the active pattern T3a of the compensation transistor T3 through an eighth via V8. Thus, the blocking portion 31 blocks the active pattern T3a of the compensation transistor T3, and the blocking portion 31 is connected to the first connection structure P1. Figure 2B The electrical signal of node N1 is used to better stabilize the potential of node N1.

[0183] For example, such as Figure 5A , Figure 5E and Figure 6A As shown, the shielding portion 31 and the second electrode plate Cst2 are disposed on the same layer, for example, both are located on the second metal layer 202, so that the two can be formed by performing a patterning process on the same film layer using the same mask, simplifying the structure and manufacturing process of the display substrate.

[0184] Figure 5B-5J and Figures 6A-6B Other unmentioned features and corresponding technical effects of the display substrate shown Figure 3A The display substrate shown is the same as the previous description, and will not be repeated here.

[0185] Figure 7A This is a schematic diagram of the structure of a sub-pixel of a display substrate according to an embodiment of the present disclosure. Figures 7B-7H for Figure 7A The diagram shows the semiconductor layer, first conductive layer, second conductive layer, various vias, third conductive layer, and first electrode of the display substrate. Figure 8A For along Figure 7A A cross-sectional view of line G-G' in the middle. Figure 8B For along Figure 7A A cross-sectional view of line H-H' in the middle. Figure 8C For along Figure 7A A cross-sectional view of line I-I' in the middle. Figure 8D for Figure 7A A magnified view of a sub-pixel. Figures 7B-7H and Figures 8A-8D The pixel circuit of the display substrate provided in the illustrated embodiment is still as follows Figure 2B As shown, Figures 7B-7H and Figures 8A-8D The embodiment shown provides a display substrate and Figure 3A The display substrates provided in the illustrated embodiments have the following differences.

[0186] like Figure 7A , Figure 5E and Figure 6A As shown, for example, the orthographic projection of the first connection structure P1 of the subpixel on the substrate 200 at least partially overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200, in order to save layout space, thereby improving the PPI and aperture ratio of the display panel using the display substrate.

[0187] For example, refer to Figure 7A , Figure 7G and Figure 8A The first connection structure P1 is disposed on the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third conductive layer 203; the first connection structure P1 is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst through the first via V1.

[0188] refer to Figure 7A The orthographic projection of the first via V1 on the substrate 200 overlaps with the orthographic projection of the first part Cst11 of the first electrode Cst1 on the substrate 200, and does not overlap with the orthographic projections of the second part Cst12 of the first electrode Cst1 and the second electrode Cst2 on the substrate 200.

[0189] Unlike Figure 3A In the illustrated embodiment, the first connecting structure P1 is a strip-shaped structure, such as a straight strip, that extends generally along the second direction. For example, refer to... Figure 7A and Figure 7G The first connection structure P1 includes a first inclined portion P1-3, which extends along a third direction that intersects the first direction D1 and the second direction D2. The orthographic projection of the first inclined portion P1-3 on the substrate 200 at least partially overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200.

[0190] For example, such as Figure 7A and Figures 7C-7D As shown, the first portion Cst11 of the first electrode plate Cst1 has a first end in the first direction D1, and the first signal line 210 that provides the first scan signal Ga1 to the data writing transistor T2 includes a bent portion 2103, which surrounds the first end of the first portion Cst11.

[0191] For example, the first signal line 210, i.e., the scan line 210, which provides the first scan signal Ga1 to the data writing transistor T2, is also configured to provide the second scan signal Ga2 to the compensation transistor T3. For example, the compensation transistor T3 includes an active pattern T3a, which is disposed in the same layer as the active pattern T1a of the driving transistor T1, for example, both located in the semiconductor layer. The sub-pixel also includes a blocking portion 31, located on the side of the active pattern T3a of the compensation transistor T3 away from the substrate 200. The orthographic projection of the blocking portion 31 on the substrate 200 at least partially overlaps with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the substrate 200, so that the blocking portion 31 blocks the active pattern T3a of the compensation transistor T3, for example, blocking the channel region of the blocking portion 31, to prevent light from affecting the performance of the channel region of the compensation transistor T3. For example, the blocking part 31 is electrically connected to the first power line to provide the blocking part 31 with the first power supply voltage VDD signal for voltage regulation, so as to prevent the voltage fluctuation on the blocking part 31 from affecting the stable operation of the pixel circuit.

[0192] For example, refer to Figure 7E The shielding portion 31 and the second electrode plate Cst2 are disposed on the same layer, for example, both located on the second metal layer 202. This allows the shielding portion 31 and the second electrode plate Cst2 to be formed using the same mask and the same patterning process on the same film layer, simplifying the fabrication process of the display substrate 10. For example, the orthographic projection of the first power line VDD on the substrate 200 at least partially overlaps with the orthographic projection of the shielding portion 31 on the substrate 200, and the first power line VDD is electrically connected to the shielding portion 31 through the second via V2.

[0193] For example, in Figure 7A In the display substrate 10 shown, the first power line VDD of the pixel circuit is connected to the first voltage terminal and configured to provide a first power supply voltage to the pixel circuit. It is disposed on the same layer as the first terminal T1s of the driving transistor T1, for example, both located in the third conductive layer 203. Combined with... Figure 7A , Figure 7G and Figure 8B The first power line VDD includes a second vertical portion VDD3 and a second inclined portion VDD4. The second vertical portion VDD3 extends along a second direction D2; the second inclined portion VDD4 extends along a fourth direction intersecting the first direction D1 and the second direction D2, and is electrically connected to the second electrode plate Cst2 through a second via V2. The second electrode plate Cst2 has a first side and a second side opposite to each other in the second direction D2. The second vertical portion VDD3 is located on the first side of the second electrode plate Cst2, and the second inclined portion VDD4 is connected to the first vertical portion VDD3 and extends along the fourth direction from the first side of the second electrode plate Cst2 to the second side of the second electrode plate Cst2.

[0194] exist Figure 7AIn the display substrate 10 shown, the first power line VDD and the data line Data are located on different sides of the storage capacitor Cst.

[0195] For example, in Figure 3A In the illustrated embodiment, the first power line VDD and the data line Data are located on the same layer, both in the third metal layer 203; in other embodiments, the first power line VDD and the data line Data may be located on different layers. For example, in at least one embodiment, the display substrate further includes a fourth metal layer located in the third metal layer 203, away from the substrate 200. For example, the first power line VDD is located in the third metal layer 203, and the data line Data is located in the fourth metal layer; or, the first power line VDD is located in the fourth metal layer, and the data line Data is located in the third metal layer 203.

[0196] Figure 7B-7I and Figures 8A-8D Other unmentioned features and corresponding technical effects of the display substrate shown Figure 3A The display substrate shown is the same as the previous description, and will not be repeated here.

[0197] Figure 9A This is a schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure; Figure 9B-9I for Figure 9A The diagram shows the semiconductor layer, first conductive layer, second conductive layer, various vias, third conductive layer and first electrode of the display substrate. Figure 9J Figure 9A A magnified view of a sub-pixel; Figure 10A For along Figure 9A A cross-sectional view of line J-J' in the middle; Figure 10B For along Figure 9A A cross-sectional view of line K-K' in the middle; Figure 10C For along Figure 9A A cross-sectional view of line L-L' in the diagram. Below is an example. Figure 2B Taking the pixel circuit shown as an example, and combining it with Figure 9B-9I and Figures 10A-10C The structure of a display substrate provided in at least one embodiment of the present disclosure will be described by way of example.

[0198] like Figure 9A and Figure 10BThe display substrate 10 includes a substrate 200 and sub-pixels disposed on the substrate 200. For example, a plurality of sub-pixels are disposed on the substrate 200 in an array. At least some of the sub-pixels each include a pixel circuit 101. For example, the "at least some" sub-pixels refer to sub-pixels that perform display functions, not dummy sub-pixels. For example, the pixel circuit 101 includes: a first signal line and a second signal line, a light-emitting device, a driving transistor T1, a data writing transistor T2, and a storage capacitor Cst. The data writing transistor T2 is configured to transmit a data signal, for example, transmitted on the second signal line 210, to the driving transistor T1 under the control of the first scan signal Ga1. The first scan signal Ga1 is transmitted on the first signal line 210. The driving transistor T1 is configured to control the magnitude of the driving current flowing through the light-emitting device 121 according to the data signal Vd. The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The driving transistor T1 includes an active pattern T1a and a gate T1g. The active pattern T1a of the driving transistor T1 includes a channel region C1. The orthographic projection of the channel region C1 on the substrate 200 at least partially overlaps with the orthographic projection of the gate on the substrate 200. The storage capacitor Cst includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is electrically connected to the gate of the driving transistor T1. The orthographic projection of the second plate Cst2 on the substrate 200 at least partially overlaps with the orthographic projection of the first plate Cst1 on the substrate 200, but does not overlap with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200. In the display substrate 10 provided in this embodiment, since the second electrode plate Cst2 is connected to the first power supply voltage VDD for voltage regulation, the first power supply voltage signal will affect the channel region C1 of the driving transistor T1. In order to reduce its influence on the channel region C1 of the driving transistor T1, the second electrode plate Cst2 is made to avoid the channel region C1 of the driving transistor T1, so as to avoid the performance of the driving transistor T1 being affected.

[0199] For example, the first signal line is a gate line serving as a scan signal line, and the second signal line is a data line; or, in some other embodiments, the first signal line is a data line, and the second signal line is a gate line serving as a scan signal line.

[0200] and Figure 3A The illustrated embodiments are similar, combined with Figure 9B-9G and Figures 10A-10C It is known that the display substrate 10 includes a semiconductor layer 107, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a third conductive layer 203, a fourth insulating layer 304, and a fourth conductive layer 204 sequentially disposed on the substrate 200.

[0201] For example, such as Figure 9BThe semiconductor layer 107 shown includes active patterns T1a-T7a of the first to seventh transistors T1-T7.

[0202] For example, such as Figure 9C-9D As shown, the first conductive layer 201 includes the gate of each transistor as well as some scan lines and control lines. Figure 9A The area where the pixel circuitry of each sub-pixel is located is shown in large dashed boxes. Figure 9B The gates T1g-T7g of the first to seventh transistors T1-T7 in a pixel circuit unit 100 are shown in small dashed boxes.

[0203] For example, such as Figure 9C-9D As shown, the first conductive layer 201 includes the gates T1g-T7g of the first to seventh transistors T1-T7. For example, the display substrate 10 employs a self-aligned process, using the first conductive layer 201 as a mask to perform a conductor-enhancing treatment (e.g., doping) on ​​the semiconductor layer 107, so that the portion of the semiconductor layer 107 not covered by the first conductive layer 201 is conductor-enhanced. Consequently, the portions of the active patterns of each transistor located on both sides of the channel region are conductor-enhanced to form the first and second electrodes of the transistor, respectively.

[0204] For example, such as Figure 9A As shown, the gate T6g of the sixth transistor T6 in this row of pixel circuits is electrically connected to the first reset control line 220a corresponding to this row to receive the first reset control signal Rst1. The gate of the seventh transistor T7 in this row of pixel circuits is electrically connected to the second reset control line 220b corresponding to the next row of pixel circuits (i.e., the row of pixel circuits where the scan lines are sequentially turned on after the scan lines in this row, according to the scanning order of the scan lines) to receive the second reset control signal Rst2.

[0205] Scan line 210 is electrically connected (or integrated) to the gate of the second transistor T2 in the corresponding row of sub-pixels to provide a first scan signal Ga1. A reset control line 220 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1. Light emission control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light emission control signal EM1.

[0206] For example, such as Figure 9A and Figure 9CAs shown, the planar shape of the channel region C1 of the driving transistor T1 is a strip extending along the second direction D2. This feature increases the length of the channel region of the driving transistor (the length along the second direction D2), thereby increasing the aspect ratio of the channel region of the driving transistor. This ensures that the leakage current of the driving transistor T1 is small and the driving is stable in the black state. The larger the length of the channel region of the driving transistor T1, the closer the output curve of the driving transistor T1 is to the ideal linear condition in the saturation region. This allows the display substrate, such as an OLED display substrate, to operate in the saturation region of the driving transistor T1, making the brightness of the display panel using this display substrate better controlled by the driving transistor T1. Furthermore, this feature helps to save layout space for pixel circuits. This channel region C1 is different from existing zigzag channels or S-shaped channels that extend along the first direction D1 and have obvious bends. The first direction D1 and the second direction D2 and Figure 3A The same as in [the previous sentence].

[0207] It should be noted that the phrase "a strip extending generally along the second direction D2" includes strips that extend substantially along the second direction D2, or at least generally along the second direction D2. For example, in some examples, the strip extending generally along the second direction D2 may have a certain degree of curvature, such as... Figure 4F The shape shown is a wavy shape that extends generally along the second direction D2; or, in some examples, the edges of the strip that extends generally along the second direction D2 may not be smooth lines, for example, its edges may have burrs or jagged edges. In short, it is sufficient to satisfy the requirement that the strip extends generally along the second direction D2.

[0208] For example, such as Figure 9A and Figure 9C As shown, the planar shape of the channel region C1 of the driving transistor T1 is a straight strip extending along the second direction D2, so as to better increase the aspect ratio of the channel region C1 of the driving transistor T1, making it more regular, thereby facilitating manufacturing and better saving the layout space of the pixel circuit.

[0209] For example, refer to Figures 9A-9D The first electrode Cst1 includes a first part Cst11 and a second part Cst12. The orthographic projection of the first part Cst11 of the storage capacitor Cst on the substrate 200 does not overlap with the orthographic projection of the first electrode Cst2 on the substrate 200. The second part Cst12 of the storage capacitor Cst is connected to the first part Cst11 and protrudes from the first part Cst11. The orthographic projection of the second part Cst12 on the substrate 200 overlaps with the orthographic projection of the first electrode Cst2 on the substrate 200.

[0210] For example, in Figure 9AIn the illustrated embodiment, the first electrode plate Cst1 and the gate T1g of the driving transistor T1 are disposed on the same layer and are an integral structure. For example, both are located in the first conductive layer 201 to simplify the structure of the display substrate 10. Furthermore, the first electrode plate Cst1 and the gate T1g of the driving transistor T1 can be formed by performing the same patterning process on the same film layer using the same mask, thus simplifying the fabrication process of the display substrate 10. For example, the first portion Cst11 of the first electrode plate Cst1 is a strip extending along the second direction D2, and the second portion Cst12 of the first electrode plate Cst1 protrudes from the first portion Cst11 along the first direction D1.

[0211] For example, such as Figure 9A and Figure 10B As shown, the pixel circuit 101 also includes a first connection structure P1, which is electrically connected to the gate T1g of the driving transistor T1 and the first electrode Cst1. The orthographic projection of the first connection structure P1 on the substrate 200 does not overlap with the orthographic projection of the first electrode Cst2 on the substrate 200. For example, the second electrode Cst2 is located on the second conductive layer 202, which is located on the side of the first conductive layer 201 away from the substrate 200. There is a second insulating layer 302 between the second conductive layer 202 and the first conductive layer 201. Thus, the first connection structure P1 needs to be electrically connected to the first electrode Cst1 through a via. The first connection structure P1 will not pass through the second electrode Cst2 of the storage capacitor Cst, thereby increasing the area of ​​the second electrode Cst2 to increase the capacitance of the storage capacitor.

[0212] For example, such as Figure 9A and Figure 10B As shown, the first connection structure P1 and the first part Cst11 are at least partially overlapped on the substrate 200, for example, they overlap with the channel region C1 of the driving transistor T1, in order to save space and facilitate the arrangement of other structures of the pixel circuit in the limited space. This is very important for the pixel design of the display substrate and can solve the important technical problem of how to effectively improve PPI.

[0213] For example, the first connection structure P1 and the first electrode T1s of the driving transistor T1 are disposed on the same layer, for example, both located in the third conductive layer 203. The first connection structure P1 is electrically connected to the first electrode Cst1 through the first via V1; the orthographic projection of the first via V1 on the substrate 200 overlaps with the orthographic projection of the first part Cst11 of the first electrode Cst1 on the substrate 200, that is, it does not overlap with the orthographic projection of the second electrode Cst2 on the substrate 200.

[0214] For example, the first conductive layer 201 also includes multiple gate lines that are insulated from each other. These gate lines include, for example, multiple scan lines 210, multiple reset control lines 220a / 220b, and multiple light emission control lines 230. Here, a gate line refers to a signal line that is directly connected to the gate of a transistor to provide a scan signal or a control signal. For example, each row of sub-pixels is respectively connected to one scan line 210, two reset control lines, and one light emission control line 230, wherein the two reset control lines are the first reset control line 220a and the second reset control line 220b.

[0215] For example, such as Figure 9A As shown in header 9C, the first signal line 210, i.e., the first scan signal line, is connected to the gate of the data write transistor T2 and configured to provide a first scan control signal Ga1 to the gate of the data write transistor T2. The first signal line 210 includes a first lateral portion 210a extending generally along a first direction D1 and a first longitudinal portion 210b extending generally along a second direction D2, with the first lateral portion 210a and the first longitudinal portion 210b connected. Figure 9B As shown, the data writing transistor T2 includes an active pattern T2a. The orthographic projection of the active pattern T2a on the substrate 200 at least partially overlaps with the orthographic projection of the first vertical portion 210b on the substrate 200, so that a portion of the first vertical portion 210b constitutes the gate T2g of the data writing transistor T2. Thus, the first scan control signal Ga1 enters the sub-pixel along the first direction D1 and is applied to the gate T2g of the data writing transistor T2 along the second direction D2, i.e., driving the data writing transistor T2 along the second direction D2. This allows for more stable driving of the data writing transistor T2, while also making reasonable use of the limited space of the sub-pixel for wiring arrangement.

[0216] For example, such as Figure 9A and Figure 9C As shown, the first light-emitting control transistor T4 of the pixel circuit 101 is connected to the first terminal T1s and the first voltage terminal Vdd of the driving transistor T1, and is configured to apply the first power supply voltage VDD of the first voltage terminal Vdd to the first terminal T1s of the driving transistor T1 under the control of the first light-emitting control signal EM1. Multiple light-emitting control lines 230 include a first light-emitting control line 231, which is connected to the gate of the first light-emitting control transistor T4 and configured to provide a first light-emitting control signal to the gate of the first light-emitting control transistor T4.

[0217] For example, such as Figures 9A-9CAs shown, the first light-emitting control line 231 includes a second transverse portion 231a extending generally along the first direction D1 and a second vertical portion 231b extending generally along the second direction D2. The first light-emitting control transistor T4 includes an active pattern T4a. The orthographic projection of the active pattern T4a of the first light-emitting control transistor T4 onto the substrate 200 at least partially overlaps with the orthographic projection of the second vertical portion 231b onto the substrate 200, so that a portion of the second vertical portion 231b constitutes the gate T4g of the first light-emitting control transistor T4. In this way, the first light-emitting control signal EM1 enters the sub-pixel along the first direction D1 and is applied to the gate T4g of the first light-emitting control transistor T4 along the second direction D2, that is, driving the first light-emitting control transistor T4 along the second direction D2. This can drive the first light-emitting control transistor T4 more stably, while also making reasonable use of the limited space of the sub-pixel to arrange the wiring.

[0218] For example, such as Figures 9A-9C As shown, the second light-emitting control transistor T5 of the pixel circuit 101 is connected to the second light-emitting control terminal VSS, the light-emitting device, and the second terminal T1d of the driving transistor T1, and is configured to apply a driving current to the light-emitting device under the control of the second light-emitting control signal EM2. The plurality of light-emitting control lines 230 also include a second light-emitting control line 232, which is connected to the gate T5g of the second light-emitting control transistor T5 and configured to provide the second light-emitting control signal EM2 to the gate T5g of the second light-emitting control transistor T5. The first light-emitting control line 231 is multiplexed as the second light-emitting control line 232, meaning that the first light-emitting control transistor T4 and the second light-emitting control transistor T5 share a single light-emitting control line. Furthermore, the second light-emitting control transistor T5 includes an active pattern, and the orthographic projection of the active pattern T5a of the second light-emitting control transistor T5 onto the substrate 200 at least partially overlaps with the orthographic projection of the second vertical portion 231b onto the substrate 200, so that a portion of the second vertical portion 231b constitutes the gate T5g of the second light-emitting control transistor T5. Thus, the second light-emitting control signal EM2 enters the sub-pixel along the first direction D1 and is applied to the gate T4g of the second light-emitting control transistor T5 along the second direction D2. This means that the second light-emitting control transistor T5 is driven along the second direction D2, enabling more stable driving of T5. Simultaneously, it makes efficient use of the limited space within the sub-pixel for wiring arrangement. The second vertical portion 231b is used to construct the gate T4g of the first light-emitting control transistor T4 and the gate T5g of the second light-emitting control transistor T5, simultaneously achieving driving (vertical driving) of both transistors along the second direction D2, simplifying the pixel circuit structure.

[0219] For example, the storage capacitor Cst is located between the first vertical portion 210b and the second vertical portion 231b, and between the first horizontal portion 210a and the second horizontal portion 210b, so as to make reasonable use of the limited space to arrange the first light-emitting control line and the second light-emitting control line, which have horizontal and vertical portions respectively, which is beneficial to improving the PPI and aperture ratio of the display panel using the display substrate.

[0220] For example, such as Figure 9B As shown, the active pattern of the first light-emitting control transistor T4 includes a channel region, and the active pattern of the second light-emitting control transistor T5 includes a channel region C5. In the first direction D1, the distance between the channel region C4 of the first light-emitting control transistor T4 and the channel region C1 of the driving transistor T1 is h1, and the distance between the channel region C5 of the second light-emitting control transistor T5 and the channel region C1 of the driving transistor T1 is h2. Furthermore, in the second direction D2, the distance between the channel region of the first light-emitting control transistor T4 and the channel region C1 of the driving transistor T1 is equal to the distance between the channel region of the second light-emitting control transistor T5 and the channel region C1 of the driving transistor T1.

[0221] It should be noted that distance h1 refers to the distance between the edge of channel area C4 closest to channel area C1 in the first direction D1 and the edge of channel area C1 closest to channel area C4 in the first direction D1; distance h2 refers to the distance between the edge of channel area C5 closest to channel area C1 in the first direction D1 and the edge of channel area C1 closest to channel area C5 in the first direction D1; distance h3 refers to the distance between the edge of channel area C4 closest to channel area C1 in the second direction D2 and the edge of channel area C1 closest to channel area C4 in the second direction D2; and distance h4 refers to the distance between the edge of channel area C5 closest to channel area C1 in the second direction D2 and the edge of channel area C1 closest to channel area C5 in the second direction D2.

[0222] For example, the aspect ratio of the channel region C4 of the first light-emitting transistor T4 is the same as that of the channel region C5 of the second light-emitting transistor T5. For example, the ratio of the length of the channel region C4 in the first direction D1 to its width in the second direction D2 is the same as the ratio of the length of the channel region C5 in the first direction D1 to its width in the second direction D2. This makes the driving effects of the first light-emitting transistor T4 and the second light-emitting transistor T5 more similar, resulting in a more stable display effect and reducing the difficulty of the manufacturing process.

[0223] For example, such as Figure 9A and Figure 9GAs shown, the pixel circuit 101 also includes a first power line VDD. The first power line VDD is connected to the first voltage terminal vdd and configured to provide a first power supply voltage to the pixel circuit. It is disposed on the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third metal layer 203. The first power line VDD includes a third vertical portion VDD1 and a third horizontal portion VDD2. The third vertical portion VDD1 extends generally along the second direction D2 and is connected to adjacent sub-pixels to provide a power supply voltage to multiple sub-pixels in the same column. The third horizontal portion VDD2 is connected to the third vertical portion VDD1 and extends from the third vertical portion VDD1 toward the second electrode plate Cst2. The third horizontal portion VDD2 is electrically connected to the second electrode plate Cst2 through the second via V2.

[0224] For example, such as Figure 9A and Figure 9G As shown, the second signal line, such as the data line Data, is disposed on the same layer as the first power line VDD, both located in the third metal layer 203; and includes a fourth horizontal portion Data1 extending generally along the first direction D1 and a fourth vertical portion Data2 extending generally along the second direction D2; in the second direction D2, the fourth horizontal portion Data1 of the data line Data and the third horizontal portion VDD2 of the first power line VDD are at least partially opposite each other, that is, their projections overlap in the second direction D2. The orthographic projection of the fourth vertical portion Data2 of the data line Data on the substrate 200 does not overlap with the orthographic projection of the third horizontal portion VDD2 of the first power line VDD on the substrate 200, so that when the data line Data and the first power line VDD are on the same layer, the data line Data avoids the first power line VDD, preventing short circuits or signal crosstalk between them.

[0225] For example, in Figure 9A In the illustrated embodiment, the first power line VDD and the data line Data are located on the same layer, both in the third metal layer 203; in other embodiments, the first power line VDD and the data line Data may be located on different layers. For example, in at least one embodiment, the display substrate further includes a fourth metal layer located in the third metal layer 203, away from the substrate 200. For example, the first power line VDD is located in the third metal layer 203, and the data line Data is located in the fourth metal layer; or, the first power line VDD is located in the fourth metal layer, and the data line Data is located in the third metal layer 203. When the first power line VDD and the data line Data may be located in different layers, their orthographic projections on the substrate may overlap.

[0226] For example, such as Figure 9A and Figure 10BAs shown, the third vertical portion VDD1 is located on the first side of the storage capacitor Cst in the first direction D1. The fourth vertical portion Data2 of the data line Data and its orthographic projection on the substrate 200 at least partially overlap with the orthographic projection of the storage capacitor Cst on the substrate 200, and do not overlap with the orthographic projection of the second via V2 on the substrate 200, so that the data line Data avoids the first power line VDD which is disposed on the same layer as it while saving space.

[0227] For example, such as Figure 9A As shown, the compensation transistor T3 of the pixel circuit 101 is configured to compensate the gate T1g of the driving transistor T1 in response to a second scan signal Ga2 and a data signal Vd applied to the gate T3g of the compensation transistor T3. The first lateral portion 210a of the first signal line 210, which provides the first scan signal Ga1 to the data writing transistor T2, is configured to provide the second scan signal to the compensation transistor T3. As... Figure 9B As shown, the compensation transistor T3 includes an active pattern T3a, which is disposed on the same layer as the active pattern T1a of the driving transistor T1, both located in the semiconductor layer 107. The sub-pixel also includes a blocking portion 31, which is located on the side of the active pattern T3a of the compensation transistor T3 away from the substrate 200. The orthographic projection of the blocking portion 31 on the substrate 200 at least partially overlaps with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the substrate 200, so as to block the active pattern T3a of the compensation transistor T3, for example, blocking the channel region of the compensation transistor T3, to prevent light from affecting the performance of the channel region of the compensation transistor T3. For example, the shielding portion 31 and the reset signal line 240 are disposed on the same layer, such as both located on the second metal layer 202. For instance, the shielding portion 31 and the reset signal line 240 are disposed on the same layer and integrally formed. Therefore, both can be formed using the same mask to perform a patterning process on the same film layer, simplifying the structure and manufacturing process of the display substrate. It should be noted that the active pattern T3a shielded by the shielding portion 31 here is the conductive portion around the channel region of the compensation transistor T3, and does not include the channel region of the compensation transistor T3.

[0228] For example, such as Figures 9A-9BAs shown, the semiconductor layer 107 includes an active pattern T1a for driving transistor T1; the semiconductor layer 107 includes a first portion 107a and a second portion 107b, the first portion 107a and the second portion 107b of the semiconductor layer are separated by an opening O, the orthographic projection of the opening O on the substrate 200 overlaps with the orthographic projection of the second lateral portion 231a of the first light-emitting control line 231 on the substrate 200, and the orthographic projections of the first portion 107a and the second portion 107b of the semiconductor layer on the substrate 200 do not overlap with the orthographic projection of the second lateral portion 231a of the first light-emitting control line 231 on the substrate 200.

[0229] Each sub-pixel performing a display function includes a first electrode 40, which is electrically connected to one of the first electrode T1s and the second electrode T1d of the driving transistor T1. The substrate 200 includes a plurality of sub-pixels, for example, such as... Figure 9H-9I As shown, the display substrate 10 has multiple sub-pixels, including a first sub-pixel, two adjacent second sub-pixels, and a third sub-pixel. The first, second, and third sub-pixels emit light of different colors and each includes a first electrode 41, a first electrode 42, and a first electrode 43. The two adjacent second sub-pixels are an upper second sub-pixel 101a and a lower second sub-pixel 101b. The upper second sub-pixel 101a includes a first electrode 421, and the lower second sub-pixel 101b includes a first electrode 422. For example, the display substrate includes multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels, thereby including multiple first electrodes 41, multiple first electrodes 42, and multiple first electrodes 43. For example, the multiple first electrodes 42 include... Figure 9I The first electrode 421 and the first electrode 422 in the middle. The orthographic projection of the first connection structure P1-1 of the upper second sub-pixel 101a on the substrate 200 and the orthographic projection of the first electrode 421 of the upper second sub-pixel 101a on the substrate 200 at least partially overlap, and the orthographic projection of the first connection structure P1-2 of the lower second sub-pixel 101b on the substrate 200 and the orthographic projection of the first electrode 422 of the lower second sub-pixel 101b on the substrate 200 at least partially overlap, so that the first connection structures of two adjacent second sub-pixels are basically blocked by the first electrode of the sub-pixel to which they belong, so that the light emission brightness of two adjacent second sub-pixels tends to be consistent.

[0230] like Figure 9I As shown, in each sub-pixel with a first electrode, taking the second sub-pixel 101a as an example, the first electrode 421 is electrically connected to the second terminal T1d of the driving transistor T1 through the ninth via V9.

[0231] For example, the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light.

[0232] For example, the upper second sub-pixel 101a and the lower second sub-pixel 101b are arranged along the second direction D2, and the upper second sub-pixel 101a and the first sub-pixel adjacent to it are arranged along the first direction D1. Of course, in other embodiments, the upper second sub-pixel 101a and the lower second sub-pixel 101b may also be arranged along the first direction D1, and the upper second sub-pixel 101a and the first sub-pixel adjacent to it may be arranged along the second direction D2. This disclosure does not limit the scope of the embodiments.

[0233] Figure 9A Other features and their technical effects not mentioned in the illustrated embodiments, such as the type of transistor, the material of each film layer, etc., are the same as the corresponding structures in the previous embodiments, and can be referred to the previous description.

[0234] This disclosure provides at least one embodiment of a display device, including any of the display substrates provided in the embodiments of this disclosure. The display device may be, for example, an organic light-emitting diode (OLED) display device, a quantum dot OLED display device, or other devices with display functions, or other types of devices. The embodiments of this disclosure are not limited in this regard.

[0235] The structure, function, and technical effects of the display device provided in this disclosure embodiment can be referred to the corresponding description in the display substrate 10 provided in the above disclosure embodiment, and will not be repeated here.

[0236] For example, the display device provided in at least one embodiment of this disclosure can be any product or component with display function, such as a display panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of this disclosure do not limit this.

[0237] The above are merely exemplary embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. The scope of protection of this disclosure is determined by the scope defined in the claims.

Claims

1. A display substrate, comprising: Substrate; The substrate has a first signal line extending generally along a first direction and a second signal line extending generally along a second direction intersecting the first direction. The first signal line transmits a first scan signal, and the second signal line transmits a data signal. Sub-pixels, wherein each sub-pixel includes pixel circuitry, and the pixel circuitry includes: Light-emitting devices, driving transistors, and data writing transistors, among which, The data writing transistor is configured to transmit the data signal to the driving transistor under the control of the first scan signal; The driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device according to the data signal. The driving transistor includes an active pattern and a gate. The active pattern includes a channel region. The orthographic projection of the channel region on the substrate overlaps at least partially with the orthographic projection of the gate on the substrate. The planar shape of the channel region of the driving transistor is a strip that extends generally along the second direction; The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; The pixel circuit further includes a storage capacitor, which includes: The first electrode plate is electrically connected to the gate of the driving transistor; and The second electrode plate has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the first electrode plate on the substrate. The pixel circuit also includes: A semiconductor layer, including the active pattern of the driving transistor; and A first connection structure, wherein a first end of the first connection structure is connected to the semiconductor layer, a second end of the first connection structure opposite to its first end is electrically connected to the gate of the driving transistor and the first electrode plate, and the orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate.

2. The display substrate according to claim 1, wherein, The planar shape of the channel region of the driving transistor is a straight strip extending along the second direction.

3. The display substrate according to claim 1, wherein, The second electrode plate and the channel region of the driving transistor do not overlap on the orthographic projection of the substrate.

4. The display substrate according to claim 3, wherein, The first electrode plate includes: The first portion extends along the second direction, and its orthographic projection on the substrate overlaps with the orthographic projection of the channel region of the driving transistor on the substrate; and The second part is connected to the first part and protrudes from the first part of the first electrode plate along the first direction, wherein the orthographic projection of the second part on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate.

5. The display substrate according to claim 4, wherein, The orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the channel region of the driving transistor on the substrate.

6. The display substrate according to claim 5, wherein, The orthographic projection of the first connection structure on the substrate at least partially overlaps with the orthographic projection of the second portion of the first electrode plate on the substrate.

7. The display substrate according to claim 5, wherein, The first connection structure is disposed on the same layer as the first electrode of the driving transistor and is electrically connected to the first electrode plate through the first via. The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the second portion of the first electrode plate on the substrate, but does not overlap with the orthographic projection of the second electrode plate on the substrate.

8. The display substrate according to claim 1, wherein, The pixel circuit also includes: A first power line, connected to a first voltage terminal and configured to provide a first power supply voltage to the pixel circuit, is disposed on the same layer as the first terminal of the driving transistor, and includes: A first vertical portion extends along the second direction and connects to the adjacent sub-pixel; and A first lateral portion is connected to the vertical portion and extends from the vertical portion toward the second electrode plate, wherein the first lateral portion is electrically connected to the second electrode plate through a second through hole.

9. The display substrate according to any one of claims 4-7, wherein, The first portion of the first electrode plate has a first end in the second direction, and the first end and the second portion form a blank gap; The first signal line is disposed on the same layer as the first electrode plate and at intervals therebetween, and includes: The main body extends through the sub-pixel along the first direction and is located on the first side of the first electrode plate in the second direction; and A protrusion, connected to the main body and protruding from the main body toward the first electrode plate, wherein the protrusion is at least partially located in the notch.

10. The display substrate according to claim 9, wherein, The pixel circuit also includes: A compensation transistor is configured to compensate the gate of the driving transistor in response to a second scan signal applied to the gate of the compensation transistor and the data signal, wherein, The first signal line that provides the first scan signal to the data writing transistor is also configured to provide the second scan signal to the compensation transistor; The compensation transistor includes a first gate and a second gate, at least a portion of the protrusion constitutes the first gate of the compensation transistor, and a portion of the main body constitutes the second gate of the compensation transistor and the gate of the data writing transistor.

11. The display substrate according to claim 10, wherein, The compensation transistor includes an active pattern, and the active pattern of the compensation transistor is disposed on the same layer as the active pattern of the driving transistor. The sub-pixel also includes: A shielding portion is located on the side of the active pattern of the compensation transistor away from the substrate, wherein the orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the active pattern of the compensation transistor on the substrate. The shielding part is electrically connected to the first connecting structure.

12. The display substrate according to claim 11, wherein, The shielding portion is disposed on the same layer as the second electrode plate. The orthographic projection of the first connecting structure on the substrate and the orthographic projection of the shielding portion on the substrate at least partially overlap. The first connecting structure is electrically connected to the shielding portion through a third via.

13. The display substrate according to claim 4, wherein, The orthographic projection of the first connection structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the driving transistor on the substrate.

14. The display substrate according to claim 13, wherein, The first connection structure is disposed on the same layer as the first electrode of the driving transistor and is electrically connected to the first electrode plate through the first via. The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the second portion of the first electrode plate on the substrate, but does not overlap with the orthographic projections of the second portion of the first electrode plate and the second electrode plate on the substrate.

15. The display substrate according to claim 13, wherein, The first connection structure includes a first inclined portion extending along a third direction intersecting the first direction and the second direction, and the orthographic projection of the first inclined portion on the substrate at least partially overlaps with the orthographic projection of the channel region of the driving transistor on the substrate.

16. The display substrate according to claim 4, wherein, The first electrode plate has an L-shaped planar pattern.

17. The display substrate according to claim 4, wherein, The first portion has a first end in the second direction, and the first signal line that provides the first scan signal to the data writing transistor includes a bent portion that surrounds the first end of the first portion.

18. The display substrate according to claim 17, wherein, The pixel circuit also includes: A compensation transistor is configured to compensate the gate of the driving transistor in response to a second scan signal applied to the gate of the compensation transistor and the data signal, wherein, The first signal line that provides the first scan signal to the data writing transistor is also configured to provide the second scan signal to the compensation transistor.

19. The display substrate according to claim 18, wherein, The compensation transistor includes an active pattern, and the active pattern of the compensation transistor is disposed on the same layer as the active pattern of the driving transistor. The sub-pixel also includes: A shielding portion is located on the side of the active pattern of the compensation transistor away from the substrate, wherein the orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the active pattern of the compensation transistor on the substrate. The shielding portion is electrically connected to a first power line, which is connected to a first voltage terminal and configured to provide a first power supply voltage to the pixel circuit.

20. The display substrate according to claim 19, wherein, The shielding portion is disposed on the same layer as the second electrode plate, and the orthographic projection of the first power line on the substrate overlaps at least partially with the orthographic projection of the shielding portion on the substrate. The first power line is electrically connected to the shielding portion through a second via.

21. The display substrate according to claim 1, wherein, The pixel circuit also includes: A first power line, connected to a first voltage terminal and configured to provide a first power supply voltage to the pixel circuit, is disposed on the same layer as the first terminal of the driving transistor, wherein the first power line includes: The second vertical portion extends along the second direction; and The second inclined portion extends along a fourth direction intersecting the first and second directions and is electrically connected to the second electrode plate through a second through hole. The second electrode plate has a first side and a second side opposite to each other in the second direction. The second vertical portion is located on the first side of the second electrode plate. The second inclined portion is connected to the second vertical portion and extends from the first side of the second electrode plate to the second side of the second electrode plate along the fourth direction.

22. The display substrate according to any one of claims 4-8 and 13-21, wherein, The sub-pixel includes a first electrode, which is electrically connected to one of the first and second electrodes of the driving transistor. The sub-pixel includes a first sub-pixel and two adjacent second sub-pixels, the two adjacent second sub-pixels being an upper second sub-pixel and a lower second sub-pixel, the orthographic projection of the first connection structure of the upper second sub-pixel on the substrate and the orthographic projection of the first electrode of the first sub-pixel adjacent to the upper second sub-pixel on the substrate at least partially overlap, the orthographic projection of the first electrode of the lower second sub-pixel on the substrate and the orthographic projection of the first connection structure of the lower second sub-pixel on the substrate at least partially overlap.

23. The display substrate according to claim 22, wherein, The first sub-pixel emits red light, and the second sub-pixel emits green light.

24. A display device comprising the display substrate according to any one of claims 1-23.

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