Test circuit, test system, test method and semiconductor chip

Abstract

The application provides a test circuit, a test system, a test method and a semiconductor chip. The test circuit comprises a ring oscillation module, a biasing module and a delay module. The ring oscillation module comprises an odd number of first reverse units, each of which comprises a transistor. The signal input end of the delay module is used to receive an enable signal. The delay module is used to output the received enable signal to the enable input end of the ring oscillation module through the signal output end of the delay module after delaying for a preset time. The signal input end of the biasing module is connected with the signal input end of the delay module. The biasing module is used to generate a bias pulse signal according to the received enable signal and output the bias pulse signal to the bias control end of the ring oscillation module through the bias output end. The bias pulse signal is used to adjust the threshold voltage of the transistor when the first reverse unit occurs level inversion. The application can improve the accuracy of the effective drive current test of the ring oscillation module.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a test circuit, test system, test method and semiconductor chip. Background Technology

[0002] Ring oscillators (ROs) are used in integrated circuits to provide high-frequency oscillations. They are characterized by simple circuitry, easy start-up, and convenient integration.

[0003] A ring oscillator consists of multiple NOT gates connected sequentially from end to end, forming a ring circuit. The number of NOT gates is typically odd. These NOT gates employ a CMOS (Complementary Metal-Oxide Semiconductor) structure, including N-type metal-oxide transistors (NMOS) and P-type metal-oxide transistors (PMOS). After a signal is input to the ring oscillator, it passes through multiple NOT gates, causing the signal to undergo multiple high-low level transitions, thus generating oscillation. Related technologies use testing the effective drive current and drive voltage (VDD) of the ring oscillator to determine its equivalent capacitance.

[0004] However, the accuracy of effective drive current testing in related technologies is low, which affects the accuracy of the determined equivalent capacitance of the ring oscillator. Summary of the Invention

[0005] The test circuit, test system, test method, and semiconductor chip provided in this application can improve the accuracy of the effective drive current test of the ring oscillator module, thereby helping to improve the accuracy of the determined equivalent capacitance of the ring oscillator.

[0006] To achieve the above objectives, in a first aspect, this application provides a test circuit, including a ring oscillation module, a bias module, and a delay module;

[0007] The ring oscillation module includes an enable input terminal and a bias control terminal. The ring oscillation module includes an odd number of first inverting units, which are cascaded in sequence. Each first inverting unit includes a transistor.

[0008] The delay module includes a signal input terminal and a signal output terminal. The signal input terminal of the delay module is used to receive an enable signal. The delay module is used to delay the received enable signal for a preset time and then output it to the enable input terminal of the ring oscillation module through the signal output terminal of the delay module.

[0009] The bias module includes a signal input terminal and a bias output terminal. The signal input terminal of the bias module is connected to the signal input terminal of the delay module and is used to receive an enable signal. The bias module is used to generate a bias pulse signal according to the received enable signal and output it to the bias control terminal of the ring oscillation module through the bias output terminal. The bias pulse signal is used to adjust the threshold voltage of the transistor when the level of the first inverting unit flips.

[0010] In the above test circuit, optionally, the bias module includes a ring oscillation unit and a pulse generation unit, and the pulse generation unit includes a bias output terminal;

[0011] The ring oscillation unit includes a signal input terminal, which is connected to the signal input terminal of the delay module. It is used to generate an oscillation signal when an enable signal is received. The ring oscillation unit is used to output a modulation signal to the pulse generation unit when generating the oscillation signal.

[0012] The pulse generation unit includes the bias output terminal. The pulse generation unit is used to generate a bias pulse signal according to the modulation signal, and output the bias pulse signal to the bias control terminal of the ring oscillation module through the bias output terminal. The body terminal of the transistor of the first inverting unit serves as the bias control terminal of the ring oscillation module.

[0013] In the above test circuit, optionally, the ring oscillation unit includes an odd number of second inverting units, which are cascaded in sequence, and each second inverting unit includes a transistor.

[0014] In the above test circuit, optionally, the odd number of second inverting units includes a second NAND gate and an even number of second NOT gates cascaded in sequence. The first signal input terminal of the second NAND gate serves as the signal input terminal of the ring oscillation unit. The signal output terminal of the second NAND gate is connected to the signal input terminal of the first stage second NOT gate. The second signal input terminal of the second NAND gate is connected to the signal output terminal of the last stage second NOT gate.

[0015] In the above test circuit, optionally, each second NOT gate includes a third transistor and a fourth transistor of different types, the first power supply terminal of the second NAND gate and the first terminal of the third transistor are both connected to the third voltage terminal, and the second power supply terminal of the second NAND gate and the first terminal of the fourth transistor are both connected to the fourth voltage terminal.

[0016] In the same second NOT gate, the second terminal of the third transistor is connected to the second terminal of the fourth transistor and serves as the signal output terminal of the corresponding second NOT gate. The control terminal of the third transistor is connected to the control terminal of the fourth transistor and serves as the signal input terminal of the corresponding second NOT gate.

[0017] In the above test circuit, optionally, the odd number of first inverting units includes a first NAND gate and an even number of first NOT gates cascaded in sequence. The first signal input terminal of the first NAND gate serves as the enable input terminal of the ring oscillation module. The signal output terminal of the first NAND gate is connected to the signal input terminal of the first stage first NOT gate, and the second signal input terminal of the first NAND gate is connected to the signal output terminal of the last stage first NOT gate.

[0018] Furthermore, the signal output terminal of the first NOT gate in the last stage serves as the signal output terminal of the ring oscillation module.

[0019] The number of first NOT gates is equal to the number of second NOT gates.

[0020] In the above test circuit, optionally, each first NOT gate includes a first transistor and a second transistor of different types, the first power supply terminal of the first NAND gate and the first terminal of the first transistor are both connected to the first voltage terminal, and the second power supply terminal of the first NAND gate and the first terminal of the second transistor are both connected to the second voltage terminal.

[0021] In the same first NOT gate, the second terminal of the first transistor is connected to the second terminal of the second transistor and serves as the signal output terminal of the corresponding first NOT gate; the control terminal of the first transistor is connected to the control terminal of the second transistor and serves as the signal input terminal of the corresponding first NOT gate.

[0022] In the above-described test circuit, optionally, the pulse generation unit includes an even number of pulse generation sub-units.

[0023] Each pulse generation subunit is connected to the second inverting unit and the first inverting unit respectively. Each pulse generation subunit is used to generate a corresponding bias pulse signal according to the modulation signal generated by the corresponding connected second inverting unit, and output it to the body terminal of the transistor of the corresponding connected first inverting unit.

[0024] The number of pulse generation subunits, the number of first NOT gates, and the number of second NOT gates are all equal.

[0025] In the above test circuit, optionally, each pulse generation sub-unit includes a pulse logic gate and a pulse NOT gate, the first power supply terminal of the pulse logic gate and the first power supply terminal of the pulse NOT gate are both connected to the third voltage terminal, and the second power supply terminal of the pulse logic gate and the second power supply terminal of the pulse NOT gate are both connected to the fourth voltage terminal.

[0026] The first signal input terminal of the pulse logic gate is connected to the signal input terminal of the second NOT gate corresponding to the pulse generation subunit, and the second signal input terminal of the pulse logic gate is connected to the signal output terminal of the second NOT gate corresponding to the pulse generation subunit.

[0027] The signal output terminal of the pulse logic gate is connected to the signal input terminal of the pulse NOT gate. The signal output terminal of the pulse NOT gate serves as the bias output terminal of the corresponding pulse generation sub-unit and is connected to the body terminal of the transistor of a first inverting unit corresponding to the pulse generation sub-unit.

[0028] In the above test circuit, optionally, the first and third transistors are PMOS transistors, and the second and fourth transistors are NMOS transistors.

[0029] In the above test circuit, optionally, the pulse logic gate is a NAND gate, and the bias output terminal is connected to the body terminal of the first transistor.

[0030] The voltage value of the first voltage terminal is a, the voltage value of the third voltage terminal is a1, and the voltage value of the fourth voltage terminal is a2. a, a1, and a2 satisfy the formula: a2 = a, a1 = 2a; the second voltage terminal is grounded.

[0031] In the above test circuit, optionally, the pulse logic gate is a NOR gate, and the bias output terminal is connected to the body terminal of the second transistor.

[0032] The voltage value of the first voltage terminal is b, and the voltage value of the fourth voltage terminal is b1. b and b1 satisfy the formula: b1 = -b, and b > 0; the second and third voltage terminals are both grounded.

[0033] In the above test circuit, optionally, the delay module includes at least two delay NOT gates, which are cascaded in sequence. The signal input terminal of the first-stage delay NOT gate is connected to the signal input terminal of the bias module to receive the enable signal.

[0034] The signal output of the last stage delay NOT gate is connected to the enable input of the ring oscillator module;

[0035] The delay module is used to generate an enable signal with a preset delay time according to the enable signal and output it to the enable input terminal. The enable signal with a preset delay time is used to control the oscillation signal generated by the ring oscillation module, which lags behind the oscillation signal generated by the ring oscillation unit, so that when the first inverting unit of the ring oscillation module undergoes a level flip, it receives the bias pulse signal.

[0036] In the above test circuit, optionally, the delay module also includes a delay capacitor, the first electrode of which is connected between any two delay NOT gates, and the second electrode of which is connected to the third voltage terminal.

[0037] Secondly, this application provides a test system, including a signal generation circuit, a test device, and the aforementioned test circuit. The enable signal output terminal of the signal generation circuit is connected to the signal input terminal of the bias module of the test circuit, and the enable signal output terminal is connected to the enable input terminal of the ring oscillation module of the test circuit through the delay module of the test circuit.

[0038] Optionally, the test system described above may also include a frequency divider element connected to the signal output terminal of the ring oscillation module of the test circuit.

[0039] Optionally, the test system described above may also include an output buffer element, which is connected to the signal output terminal of the frequency divider element.

[0040] Thirdly, this application provides a testing method for the aforementioned testing system, the testing method comprising:

[0041] Apply an enable signal to the test circuit;

[0042] Obtain the current value at the first voltage terminal of the ring oscillation module of the test circuit and the oscillation frequency of the oscillation signal generated by the ring oscillation module;

[0043] The effective drive current of the ring oscillation module is determined based on the current value at the first voltage terminal.

[0044] The equivalent capacitance and equivalent resistance of the transistor in the first inverting unit of the ring oscillation module are determined based on the effective drive current and oscillation frequency.

[0045] Fourthly, this application provides a semiconductor chip including the aforementioned testing system.

[0046] The test circuit, test system, test method, and semiconductor chip provided in this application utilize a bias module within the test circuit. This bias module generates a bias pulse signal based on an enable signal and outputs it to the body terminal of the transistor in the first inverting unit of the ring oscillation module via its bias output terminal. A delay module within the test circuit delays the enable signal of the bias module by a preset time before outputting it to the ring oscillation module. The timing of the bias pulse signal generated by the enabled bias module is earlier than the timing of the ring oscillation module generating its oscillation signal. By controlling the delay time of the enable signal, the arrival time of the bias pulse signal in the ring oscillation module can be controlled. Specifically, the bias pulse signal arrives at the transistor in the first inverting unit of the ring oscillation module when the level flips. The received bias pulse signal adjusts the threshold voltage of the transistor, preventing leakage current issues caused by simultaneous conduction of transistors in the first inverting unit during level flips. This avoids an excessively large effective drive current in the tested ring oscillation module, ensuring the accuracy of the test results and further guaranteeing the accuracy of the equivalent capacitance of the ring oscillation module determined based on the test results.

[0047] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the structure of the test system provided in the embodiments of this application;

[0050] Figure 2 A schematic diagram of the ring oscillation module and signal generation circuit of the test system provided in the embodiments of this application;

[0051] Figure 3 A schematic diagram of the structure of the first NOT gate of the ring oscillation module of the test system provided in the embodiment of this application;

[0052] Figure 4 A schematic diagram of a test circuit provided in an embodiment of this application;

[0053] Figure 5 This is a schematic diagram illustrating another circuit connection between the bias module and the first NOT gate in a test circuit provided in an embodiment of this application.

[0054] Figure 6 A schematic diagram of the structure of a bias module for a test circuit provided in an embodiment of this application;

[0055] Figure 7 A schematic diagram of the circuit connection of the first NOT gate in a test circuit provided in an embodiment of this application;

[0056] Figure 8 A circuit connection diagram of a pulse generation subunit of a test circuit provided in an embodiment of this application;

[0057] Figure 9 A timing diagram of a test circuit provided for an embodiment of this application;

[0058] Figure 10 A schematic diagram of the structure of a delay module of a test circuit provided in an embodiment of this application;

[0059] Figure 11 This is a schematic diagram of another test circuit provided in an embodiment of this application;

[0060] Figure 12 A schematic diagram of the bias module of another test circuit provided in an embodiment of this application;

[0061] Figure 13 A schematic diagram of the circuit connection of the first NOT gate in another test circuit provided in an embodiment of this application;

[0062] Figure 14 A schematic diagram of the circuit connection of the pulse generation subunit of another test circuit provided in an embodiment of this application;

[0063] Figure 15 A timing diagram of another test circuit provided in an embodiment of this application;

[0064] Figure 16 A schematic diagram of the oscillation signal output by the ring oscillation module provided in the embodiments of this application;

[0065] Figure 17 This is a flowchart illustrating the testing method provided in an embodiment of this application.

[0066] Explanation of reference numerals in the attached figures:

[0067] 100. Ring oscillation module; 101. First NAND gate; 102. First NOT gate; 102a. First transistor; 102b. Second transistor; 200. Bias module; 201. Ring oscillation unit; 2011. Second NAND gate; 2012. Second NOT gate; 202. Pulse generation unit; 2021. Pulse generation subunit; 2021a. Pulse logic gate; 2021b. Pulse NOT gate; 300. Delay module; 301. Delay NOT gate; 302. Delay capacitor; 302a. First electrode; 302b. Second electrode; A. First voltage terminal; B. Second voltage terminal; C. Third voltage terminal; D. Fourth voltage terminal; 400. Signal generation circuit; 500. Test device; 600. Frequency divider element; 700. Output buffer element; 800. Oscillation signal output terminal. Detailed Implementation

[0068] The inventors of this application discovered during their research that a ring oscillator comprises multiple NOT gate circuits connected end-to-end to form a ring circuit. The NOT gate circuits include NMOS and PMOS. In related technologies, an enable signal (EN signal) is generated through an address circuit, which is used to control the corresponding ring oscillator to oscillate. By measuring the first current flowing into the drive voltage terminal of the ring oscillator when it is in a static state and the second current flowing into the drive voltage terminal when oscillation occurs, the difference between the first and second currents is the effective drive current of the ring oscillator. The equivalent resistance of the ring oscillator is determined based on the effective drive current and the drive voltage value at the drive voltage terminal. Furthermore, the equivalent capacitance of the ring oscillator can be determined based on the drive current, the period of the oscillating AC signal, and the equivalent resistance. In some embodiments, the equivalent capacitance of the CMOS of a single NOT gate circuit in the ring oscillator can be analyzed based on the equivalent capacitance of the ring oscillator, thereby analyzing the relationship between the equivalent capacitance of the CMOS and the ion doping of the CMOS. This provides guidance for the actual fabrication of ring oscillators.

[0069] However, in the ring oscillators of related technologies, additional drive current flows through the transistors in the NOT gates during level transitions. Specifically, when the input level of the preceding NOT gate in a multi-stage NOT gate circuit changes from high to low, the PMOS in the preceding NOT gate circuit gradually turns on, and current flows through the PMOS. The current flowing through the PMOS drives the gate of the NMOS in the next NOT gate circuit, causing it to reach a high level. However, during the process of the input level of the preceding NOT gate circuit changing from high to low, while the PMOS in the preceding NOT gate circuit turns on, the NMOS is not completely turned off, resulting in some additional leakage current flowing through the not-turned-off NMOS and into the ground terminal GND. The current through the NMOS is superimposed on the effective drive current driving the next NOT gate circuit, causing the effective drive current detected at the VDD terminal to be higher than the actual effective drive current required to drive the next NOT gate circuit. The measured value of the effective drive current is too high, resulting in an underestimation of the equivalent resistance and an overestimation of the equivalent capacitance of the ring oscillator, making it impossible to accurately analyze the impact of CMOS ion doping on the equivalent capacitance based on the equivalent capacitance.

[0070] Alternatively, when the input level of the preceding NOT gate in a multi-stage NOT gate circuit changes from low to high, the NMOS in the preceding NOT gate circuit gradually turns on, and current flows through the NMOS. The current flowing through the NMOS drives the common-gate high level of the next NOT gate circuit to gradually decrease to zero. However, during the process of the input level of the preceding NOT gate circuit changing from low to high, while the NMOS in the preceding NOT gate circuit turns on, the PMOS is not completely turned off. Some additional leakage current will flow through the not-turn-off PMOS, through the NMOS, and into the ground terminal GND. The current through the PMOS will be superimposed on the effective drive current driving the next NOT gate circuit, resulting in the effective drive current detected at the VDD terminal being higher than the actual effective drive current required to drive the next NOT gate circuit. The measured value of the effective drive current is too large, resulting in an underestimation of the equivalent resistance and an overestimation of the equivalent capacitance of the ring oscillator, making it impossible to accurately analyze the impact of CMOS ion doping on the equivalent capacitance based on the equivalent capacitance.

[0071] In view of this, the test circuit, test system, test method, and semiconductor chip provided in the embodiments of this application, by setting a bias module in the test circuit, utilize the bias module to generate a bias pulse signal according to an enable signal, and output the bias pulse signal to the body terminal of the transistor of the first inverting unit of the ring oscillation module through the bias output terminal of the bias module. By setting a delay module in the test circuit, the enable signal of the bias module is delayed for a preset time before being output to the ring oscillation module. The bias pulse signal generated when the bias module is enabled must occur earlier than the oscillation signal generated by the ring oscillation module. By controlling the delay time of the enable signal, the arrival time of the bias pulse signal at the ring oscillation module can be controlled. Specifically, the bias pulse signal reaches the transistor of the first inverting unit of the ring oscillation module when the level flips. The threshold voltage of the transistor is adjusted by the received bias pulse signal to avoid leakage current caused by the simultaneous conduction of transistors in the first inverting unit during level flipping. This prevents the effective drive current of the tested ring oscillation module from being too high, ensuring the accuracy of the test results and further guaranteeing the accuracy of the equivalent capacitance test of the ring oscillation module determined based on the test results. In this way, the influence of CMOS ion doping on the equivalent capacitance can be determined based on the detected equivalent capacitance.

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0073] Figure 1 This is a schematic diagram of the structure of the testing system provided in the embodiments of this application. Figure 2 This is a schematic diagram of the ring oscillation module and signal generation circuit of the test system provided in the embodiments of this application. Figure 3 A schematic diagram of the first NOT gate of the ring oscillation module of the test system provided in this application embodiment. (Refer to...) Figures 1 to 3As shown, this application embodiment provides a test system, including an enable signal generation circuit 400, a test device 500, and a test circuit. The enable signal terminal of the signal generation circuit 400 is connected to the signal input terminal of the bias module 200 of the test circuit, and the enable signal terminal is connected to the enable input terminal of the ring oscillation module 100 of the test circuit through the delay module 300 of the test circuit. The test device 500 is connected to the first voltage terminal VDD of the test circuit.

[0074] It should be noted that the signal generation circuit 400 can be Figure 1 The address circuit shown acquires the address signal and generates an enable signal (ENSignal) based on it. The enable signal can be output to the test circuit through the enable signal terminal of the signal generation circuit 400. (Refer to...) Figure 2 As shown, the enable signal terminal is connected to the enable input terminal of the ring oscillation module 100 of the test circuit. In some embodiments, the signal generation circuit 400 may also be a command decoding module.

[0075] Figure 4 This is a schematic diagram of a test circuit provided in an embodiment of this application, with reference to... Figure 4 As shown, the enable signal terminal is connected to the signal input terminal of the bias module 200 of the test circuit. The enable signal terminal is also connected to the enable input terminal of the ring oscillation module 100 of the test circuit via the delay module 300. After a preset time delay by the delay module 300, the enable signal is output to the ring oscillation module 100. In the test circuit, the ring oscillation module 100 generates an oscillation signal based on the delayed enable signal.

[0076] The first voltage terminal VDD of the test circuit is connected to the test device 500, which can be a current measuring device, such as a current sensor. The test device 500 measures the current flowing through the first voltage terminal VDD, thereby determining the effective driving current of the ring oscillation module 100 in the test circuit during operation based on the current at the first voltage terminal VDD. The test device 500 can be a test device outside the test circuit, or it can be a current testing circuit integrated into the test circuit.

[0077] In some embodiments, the above-described test system may further include a frequency divider 600, which is connected to the signal output terminal of the ring oscillation module 100 of the test circuit. The signal output terminal of the ring oscillation module 100 outputs an oscillation signal, and the frequency divider 600 can be used to perform frequency division processing on the oscillation signal. The first power supply terminal of the frequency divider 600 is connected to the power supply terminal VCC.

[0078] In some embodiments, the test system described above may further include an output buffer element 700, which is connected to the signal output terminal of the frequency divider element 600. The output buffer element 700 can be used to adjust the waveform of the frequency-divided oscillation signal. Figure 16 This is a schematic diagram of the oscillation signal output by the ring oscillation module provided in the embodiments of this application. Figure 16 The waveform of an oscillation signal processed by a frequency divider element 600 and an output buffer element 700 according to this application is shown.

[0079] The output buffer element 700 may include two buffers connected in series with the signal output terminal of the frequency divider element 600. The first power supply terminal of both buffers is connected to the power supply terminal VCC, and the signal output terminal of the output buffer element 700 is connected to the oscillation signal output terminal 800 of the test system.

[0080] Furthermore, the oscillation frequency (oscillation period) of the oscillation signal output from the oscillation signal output terminal 800 can be tested. Based on the oscillation frequency (oscillation period) and the effective drive current, the equivalent capacitance and equivalent resistance of the transistors in the ring oscillation module 100 can be calculated and determined. The oscillation frequency (oscillation period) of this oscillation signal can also be obtained by testing with the testing device 500.

[0081] The test circuit in the above-described test system will be described in detail below through embodiments of this application.

[0082] This application provides a test circuit including a ring oscillation module 100, a bias module 200, and a delay module 300. The ring oscillation module 100 includes an enable input terminal and a bias control terminal. The ring oscillation module 100 includes an odd number of first inverting units, which are cascaded sequentially. Each first inverting unit includes a transistor.

[0083] The delay module 300 includes a signal input terminal and a signal output terminal. The signal input terminal of the delay module 300 is used to receive an enable signal. The delay module 300 is used to delay the received enable signal for a preset time and then output it to the enable input terminal of the ring oscillation module 100 through the signal output terminal of the delay module 300.

[0084] The bias module 200 includes a signal input terminal and a bias output terminal. The signal input terminal of the bias module 200 is connected to the signal input terminal of the delay module 300 and is used to receive an enable signal. The bias module 200 is used to generate a bias pulse signal according to the received enable signal and output it to the bias control terminal of the ring oscillation module 100 through the bias output terminal. The bias pulse signal is used to adjust the threshold voltage of the transistor when the level of the first inverting unit flips.

[0085] It should be noted that, in combination Figure 2 , Figure 3 and Figure 4 As shown, the odd-numbered first inverting units in the ring oscillation module 100 include a first NAND gate 101 (NAND2) and an even-numbered cascaded first NOT gates 102 (INV). The first signal input terminal 101c of the first NAND gate 101... Figure 4 (As shown) This is the enable input terminal of the ring oscillation module 100. This enable input terminal is connected to the signal output terminal of the delay module 300 and is used to receive the enable signal for the preset delay time processed by the delay module 300. The signal output terminal of the first NAND gate 101 is connected to the signal input terminal of the first-stage first NOT gate 102, and the signal output terminal of the last-stage first NOT gate 102 is connected to the second signal input terminal of the first NAND gate 101. This allows the oscillation signal output from the last-stage first NOT gate 102 to be output to the second signal input terminal of the first NAND gate 101, forming a ring loop of oscillation signal. It should be noted that the first NOT gate 102 can also be replaced with a controllable NOT gate or a NAND gate.

[0086] Furthermore, the signal output terminal of the last stage first NOT gate 102 serves as the signal output terminal of the ring oscillation module 100, used to output the oscillation signal of the ring oscillation module 100.

[0087] It needs to be explained that "first-level first NOT gate 102" refers to the first NOT gate 102 connected in the first position among multiple first NOT gates 102 in cascading order, and "last-level NOT gate" refers to the first NOT gate 102 connected in the last position among multiple first NOT gates 102 in cascading order. The explanations of "first level" and "last level" in the following text are similar and will not be repeated. An even number of first NOT gates 102 can be... Figure 2 The six shown in the image can also be... Figure 4 The four shown in the figure are not limited in the specific number of the first NOT gate 102 in this embodiment.

[0088] in, Figure 7 This is a schematic diagram of the circuit connection of the first NOT gate in a test circuit provided in an embodiment of this application. (Refer to...) Figure 4 and Figure 7 As shown, the structure of the first NOT gate 102 can be described as follows: Each first NOT gate 102 includes a first transistor 102a and a second transistor 102b of different types. The first power supply terminal 101a of the first NAND gate 101 and the first terminal 102aa of the first transistor 102a are both connected to the first voltage terminal A. The second power supply terminal 101b of the first NAND gate 101 and the first terminal 102bb of the second transistor 102b are both connected to the second voltage terminal B. In the test circuit, the voltage value of the first voltage terminal A can be VCC1.

[0089] Reference Figure 7 As shown, in the ring oscillation module 100, the first transistor 102a is a PMOS transistor, and the second transistor 102b is an NMOS transistor. In the same first NOT gate 102, the second terminal 102ab of the first transistor 102a (PMOS) is connected to the second terminal 102ba of the second transistor 102b (NMOS), and serves as the signal output terminal 102d of the corresponding first NOT gate 102. This signal output terminal 102d can be used to connect to the signal input terminal 102c of the next stage first NOT gate 102. Figure 4 (As shown), or connected to the second signal input terminal 101d of the first NAND gate 101, and serving as the signal output terminal of the ring oscillation module 100. The control terminal 102ac of the first transistor 102a is connected to the control terminal 102bc of the second transistor 102b, and serves as the signal input terminal 102c of the corresponding first NOT gate 102. This signal input terminal can be used to connect to the signal output terminal of the previous stage first NOT gate 102, or connected to the signal output terminal 101e of the first NAND gate 101.

[0090] For example, refer to Figure 4 As shown, this embodiment uses four cascaded first NOT gates 102 as an example. The four first NOT gates 102 are the first-stage first NOT gate 102-1, the second-stage first NOT gate 102-2, the third-stage first NOT gate 102-3, and the fourth-stage first NOT gate 102-4. The signal input terminal 102c of the first-stage first NOT gate 102-1 is connected to the signal output terminal 101e of the first NAND gate 101. The signal output terminal 102d of the first-stage first NOT gate 102-1 is connected to the signal input terminal 102c of the second-stage first NOT gate 102-2, and so on. The signal output terminal 102d of the fourth-stage first NOT gate 102-4 is connected to the second signal input terminal 101d of the first NAND gate 101 and serves as the signal output terminal of the ring oscillation module 100.

[0091] Reference Figure 4 As shown, the bias module 200 in this embodiment includes a bias output terminal. The signal input terminal of the bias module 200 is connected to the signal input terminal of the delay module 300, that is, connected to the enable signal terminal of the signal generation circuit 400. The signal input terminal of the bias module 200 is used to receive the enable signal. The signal output terminal of the bias module 200 is connected to the bias control terminal of the ring oscillation module 100. Since the ring oscillation module 100 has multiple levels of first NOT gates 102, each first NOT gate 102 can be provided with a bias control terminal.

[0092] In this embodiment, the connection between the signal output terminal of the bias module 200 and the bias control terminal of the multi-stage first NOT gate 102 can include the following two methods:

[0093] Reference Figure 4 As shown, in the first connection method, the signal output terminals of the bias module 200 can be configured to be multiple, and the signal output terminals of the multiple bias modules 200 are interconnected and then correspondingly connected to the bias control terminals of the multi-stage first NOT gate 102. The multi-stage first NOT gate 102 receives the bias pulse signal output by the bias module 200. In the first connection method, the signals of the signal output terminals of the multiple bias modules 200 are shared, and simultaneously control the multi-stage first NOT gate 102.

[0094] Figure 5 This is a schematic diagram illustrating another circuit connection between the bias module and the first NOT gate in a test circuit provided in an embodiment of this application. (Refer to...) Figure 5 As shown, as a second connection method, the signal output terminals of the bias module 200 can be configured to be multiple. The signal output terminals of the multiple bias modules 200 are connected one-to-one with the bias control terminals of the multi-stage first NOT gate 102, respectively receiving the bias pulse signals output by the bias module 200. In summary, in this second connection method, the signals of the signal output terminals of the multiple bias modules 200 are not shared, and each controls the multi-stage first NOT gate 102.

[0095] In this embodiment, the delay module 300 is connected between the signal generation circuit 400 and the ring oscillation module 100. It delays the enable signal output by the enable signal to generate an enable signal with a preset delay time, and outputs this delayed enable signal to the enable input terminal of the ring oscillation module 100. The preset-time delayed enable signal controls the oscillation signal generated by the ring oscillation module 100, lagging behind the oscillation signal generated by the ring oscillation unit 201, so that when the first inverting unit of the ring oscillation module 100 undergoes a level flip, it has already received the bias pulse signal.

[0096] When the test circuit is working, the enable input terminal of the ring oscillation module 100 receives an enable signal that has been delayed for a preset time after being processed by the delay module 300. The enable signal delayed for the preset time passes through the first NAND gate 101 and multiple stages of first NOT gates 102 to form an oscillation signal. During the generation of the oscillation signal, the first inverting unit undergoes multiple level flips. During each level flip, the multiple stages of first NOT gates 102 can not only receive the output signal of the previous stage first NOT gate 102 to ensure the completion of the level flip, but also receive the bias pulse signal of the bias unit through the bias control terminal. This bias pulse signal can be output to the bias control terminal of the first NOT gate 102 to adjust the threshold voltage of the transistor in the first NOT gate 102 during the time period when the level of the first NOT gate 102 flips.

[0097] The explanation is that during the level flipping process of the first NOT gate 102, one of the two transistors (e.g., NMOS) gradually turns on, while the other of the two transistors (e.g., PMOS) is turned off in advance due to the increase in threshold voltage, thereby avoiding the problem of leakage current caused by the simultaneous turn-on of the two transistors during the level flipping process.

[0098] Since both the first transistor 102a and the second transistor 102b are MOS transistors, in this embodiment, adjusting the threshold voltage of the transistor can be achieved by increasing the absolute value of the threshold voltage. When the bias pulse signal reaches the non-conducting transistor (the transistor that is gradually turned off during the level switching process), the absolute value of the threshold voltage of the non-conducting transistor increases. When the conducting transistor (the transistor that is gradually turned on during the level switching process) gradually turns on, the absolute value of the gate-source bias voltage Vgs of the non-conducting transistor is less than the absolute value of the increased threshold voltage, so it is in the off state in advance. There is no leakage current passing through the conducting transistor and the non-conducting transistor.

[0099] For example, such as Figure 7 As shown, during the transition of the first NOT gate 102 from 1 to 0, the first transistor 102a (PMOS) gradually turns on, and the second transistor 102b (NMOS) gradually turns off. When VCC1 is 2V, and the threshold voltages of both the first transistor 102a (PMOS) and the second transistor 102b (NMOS) are 0.7V, during the transition of the voltages at the control terminals 102ac of the first transistor 102a and 102bc of the second transistor 102b from high level 1 (2V) to low level 0 (0V), there is a moment when the first transistor 102a (PMOS) and the second transistor 102b (NMOS) are simultaneously turned on. Specifically, when the input voltage drops from 1.3V to between 0.7V, the absolute values ​​of the gate voltages of the first transistor 102a (PMOS) and the source bias voltage Vgs of the second transistor 102b (NMOS) are both greater than the threshold voltage of 0.7V. 102b is simultaneously turned on, resulting in leakage current.

[0100] According to this application, the bias pulse signal generated by the bias module 200 reaches the transistor at the level flipping moment. Specifically, when the level of the first NOT gate 102 flips from 1 to 0, the bias pulse signal below 0V reaches the body terminal of the second transistor 102b (NMOS) when the level starts to flip. The threshold voltage of the second transistor 102b (NMOS) gradually increases from 0.7V to 1.4V. During the process of the input level of the first NOT gate 102 flipping from 1 to 0, it can be ensured that when the first transistor 102a (PMOS) is turned on (input voltage is 1.3V), the second transistor 102b (NMOS) is already in the off state (input voltage is 1.3V, which is less than the adjusted threshold voltage of 1.4V).

[0101] In this application, the process of the level of the first NOT gate 102 switching from 0 to 1 is similar to the process of the level switching from 1 to 0 described above. Specifically, as follows... Figure 13 As shown, when the level of the first NOT gate 102 flips from 0 to 1, a bias pulse signal higher than 2V has already reached the body terminal of the first transistor 102a (PMOS) when the level begins to flip. The threshold voltage of the first transistor 102a (PMOS) gradually increases from 0.7V to 1.4V. When the input voltage rises to 0.7V and the second transistor 102b (NMOS) turns on, the first transistor 102a (PMOS) is already in the off state (the difference between the input voltage and the power supply voltage VCC1 is 1.3V, which is less than the threshold voltage of 1.4V).

[0102] Therefore, in some embodiments, the threshold voltage of the transistor can be adjusted according to the actual needs of level switching to ensure that current flows through the conducting transistor (e.g., PMOS) while no current flows through the non-conducting transistor (e.g., NMOS). This avoids leakage current in the non-conducting transistor (e.g., NMOS) of the first NOT gate 102 during level switching; this additional current is a short-circuit current. Furthermore, this embodiment can prevent leakage current from affecting the measurement of the effective drive current of the ring oscillation module 100, thus improving the accuracy of the effective drive current measurement of the ring oscillation module 100 and its first NOT gate 102.

[0103] Furthermore, the equivalent resistance of the ring oscillation module 100 can be determined based on the effective drive current and the drive voltage value of the first voltage terminal A. The equivalent capacitance of the ring oscillation module 100 can be determined based on the effective drive current, the period of the oscillation signal of the ring oscillation module 100, and the equivalent resistance. In this embodiment, the multiple first NOT gates 102 of the ring oscillation module 100 have identical structures, and the equivalent capacitance of a single first NOT gate 102 can be determined based on the equivalent capacitance of the ring oscillation module 100. The first transistor 102a and the second transistor 102b in the first NOT gate 102 form a CMOS structure, and ion doping in the CMOS structure affects the equivalent capacitance.

[0104] The term "ion doping" here may include, but is not limited to, parameters such as the type of dopant ions, doping dose, ion doping angle, and implantation temperature during the ion doping process. "Equivalent capacitance" may include, but is not limited to, the direct coupling capacitance (Cdo) between the source and drain and the gate in CMOS, and the junction capacitance (Cj) between the drain and the body of the transistor.

[0105] Therefore, accurately determining the equivalent capacitance of the first NOT gate 102 in this embodiment can be used to analyze the effect of ion doping of CMOS on the equivalent capacitance and improve the accuracy of the analysis results.

[0106] The structure of the bias module 200 and the delay module 300 in this embodiment will be described in detail below.

[0107] Figure 6 This is a schematic diagram of the bias module of a test circuit provided in an embodiment of this application. (Combined with...) Figure 4 and Figure 6 As shown, the bias module 200 includes a ring oscillation unit 201 and a pulse generation unit 202, and the pulse generation unit 202 includes a bias output terminal.

[0108] The body terminal of the transistor in the first inverting unit serves as the bias control terminal of the ring oscillation module 100.

[0109] The ring oscillation unit 201 includes a signal input terminal, which is connected to the signal input terminal of the delay module 300. It is used to generate an oscillation signal when an enable signal is received. The ring oscillation unit 201 is used to output a modulation signal to the pulse generation unit 202 when generating the oscillation signal.

[0110] The pulse generation unit 202 includes the bias output terminal. The pulse generation unit 202 is used to generate a bias pulse signal according to the modulation signal, and output the bias pulse signal to the bias control terminal of the ring oscillation module 100 through the bias output terminal. The body terminal of the transistor of the first inverting unit serves as the bias control terminal of the ring oscillation module 100.

[0111] It should be noted that the ring oscillation unit 201 includes an odd number of second inverting units, which are cascaded sequentially. Each second inverting unit includes a transistor. Specifically, the odd number of second inverting units includes a second NAND gate 2011 (NAND2) and an even number of second NOT gates 2012 (INV) cascaded sequentially. The first signal input terminal of the second NAND gate 2011 serves as the signal input terminal of the ring oscillation unit 201. The signal output terminal of the second NAND gate 2011 is connected to the signal input terminal of the first-stage second NOT gate 2012, and the signal output terminal of the last-stage second NOT gate 2012 is connected to the second signal input terminal of the second NAND gate 2011.

[0112] The ring oscillation unit 201 and the ring oscillation module 100 have identical structures, and the number of first NOT gates 102 is equal to the number of second NOT gates 2012. This reduces the difficulty of fabricating the test circuit. Furthermore, since the two oscillation circuits are structurally identical, when multiple second NOT gates 2012 in the second inverting unit can be connected one-to-one to their corresponding first NOT gates 102 via the pulse generation unit 202, controlling the delay time of the delay module 300 ensures that each first NOT gate 102 receives a stable bias pulse signal during level flipping.

[0113] Specifically, the structure of the second NOT gate 2012 can be described as follows: each second NOT gate 2012 includes a third transistor and a fourth transistor of different types. The first power supply terminal of the second NAND gate 2011 and the first terminal of the third transistor are both connected to the third voltage terminal C. The second power supply terminal of the second NAND gate 2011 and the first terminal of the fourth transistor are both connected to the fourth voltage terminal D.

[0114] In the same second NOT gate 2012, the second terminal of the third transistor is connected to the second terminal of the fourth transistor and serves as the signal output terminal of the corresponding second NOT gate 2012. The control terminal of the third transistor is connected to the control terminal of the fourth transistor and serves as the signal input terminal of the corresponding second NOT gate 2012. In the ring oscillation unit 201, the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor. The first terminals of the third transistor and the fourth transistor can be their respective source terminals, and the second terminals of the third transistor and the fourth transistor can be their respective drain terminals.

[0115] It should be noted that in this embodiment, the first transistor 102a has the same performance parameters as the third transistor, and the second transistor 102b has the same performance parameters as the fourth transistor. It should be explained that "performance parameters" here can refer to the transistor's channel size, the type of doped ions, doping process parameters, and doping concentration, etc. This ensures that the time required for the first and second inverting units to flip levels is the same. Therefore, it can be guaranteed that when the first NOT gate in the first inverting unit undergoes a level flip, the threshold voltage of the transistor in the first inverting unit is adjusted.

[0116] Wherein, the first terminal 102aa of the first transistor 102a and the first terminal 102bb of the second transistor 102b can be their respective source terminals, and the second terminal 102ab of the first transistor 102 and the second terminal 102ba of the second transistor 102b can be their respective drain terminals.

[0117] The pulse generation unit 202 includes an even number of pulse generation sub-units 2021. Each pulse generation sub-unit 2021 is connected to the second inverting unit and the first inverting unit respectively. Each pulse generation sub-unit 2021 is used to generate a corresponding bias pulse signal according to the modulation signal generated by the corresponding connected second inverting unit, and output it to the body terminal of the transistor of the corresponding connected first inverting unit.

[0118] The signal output terminal of a second inverting unit is connected to the body terminal of a transistor in a first inverting unit via a pulse generation subunit 2021. This pulse generation subunit 2021 can be used to generate a bias pulse signal based on the oscillation signal from the ring oscillation unit 201.

[0119] The number of pulse generation subunits 2021, the number of first NOT gates 102, and the number of second NOT gates 2012 are all equal. In this way, multiple second NOT gates 2012 can be connected one-to-one with multiple first NOT gates 102 through multiple pulse generation subunits 2021.

[0120] For example, refer to Figure 4 Figure 5 and Figure 6As shown, in this embodiment, there are four pulse generation subunits 2021: the first pulse generation subunit 2021-1, the second pulse generation subunit 2021-2, the third pulse generation subunit 2021-3, and the fourth pulse generation subunit 2021-4. There are also four second NOT gates 2012: the first-stage second NOT gate 2012-1, the second-stage second NOT gate 2012-2, the third-stage second NOT gate 2012-3, and the fourth-stage second NOT gate 2012-4. The first-stage second NOT gate 2012-1 is connected to the first-stage first NOT gate 102-1 through the first pulse generation subunit 2021-1, and so on. Further details are omitted.

[0121] Specifically, Figure 8 This is a circuit connection diagram of a pulse generation subunit of a test circuit provided in an embodiment of this application. (Combined with...) Figures 6 to 8 As shown, the pulse generation subunit 2021 includes a pulse logic gate 2021a and a pulse NOT gate 2021b. The first power supply terminal 2021aa of the pulse logic gate 2021a and the first power supply terminal 2021ba of the pulse NOT gate 2021b are both connected to the third voltage terminal C. The second power supply terminal 2021ab of the pulse logic gate 2021a and the second power supply terminal 2021bb of the pulse NOT gate 2021b are both connected to the fourth voltage terminal D.

[0122] The first signal input terminal 2021ac of pulse logic gate 2021a is connected to the signal input terminal of the second NOT gate 2012 corresponding to the pulse generation subunit 2021, and the second signal input terminal 2021ad of pulse logic gate 2021a is connected to the signal output terminal of the second NOT gate 2012 corresponding to the pulse generation subunit 2021. The signal output terminal 2021ae of pulse logic gate 2021a is connected to the signal input terminal of pulse NOT gate 2021b, and the signal output terminal of pulse NOT gate 2021b serves as the bias output terminal of the corresponding pulse generation subunit 2021 and is connected to the body terminal of the transistor of a first inverting unit corresponding to the pulse generation subunit 2021.

[0123] In this embodiment, the pulse generation subunit 2021 has two structures, which will be described below.

[0124] Figure 9 A timing diagram of a test circuit provided in an embodiment of this application, combined with Figures 4 to 9 As shown, in one feasible implementation, the pulse logic gate 2021a is a NOR gate, and its bias output terminal is connected to the body terminal of the second transistor 102b.

[0125] At this time, the voltage value at the first voltage terminal A is b, and the voltage value at the fourth voltage terminal D is b1. b and b1 satisfy the formula: b1 = -b, and b > 0; the second voltage terminal B and the third voltage terminal C are both grounded. The voltage value b at the first voltage terminal A is... Figure 4 VCC1 is shown in the figure.

[0126] During the operation of the test circuit, the body terminals of the second transistors 102b (NMOS) of all first NOT gates 102 in the first inverting unit are connected to the bias output terminals of the corresponding pulse generation subunits 2021. For the pulse logic gate 2021a, which is a NOR gate, when the Input terminal potential remains constant, the potential of its signal output terminal Vb is always low -VCC1. After passing through the pulse NOT gate 2021b, the Output terminal finally outputs a high potential of 0. At time t1, when the Input terminal level changes from high to low, the Va terminal needs a short delay before becoming high again (0). During the short delay of t1-t2, there is a brief moment when both the Input and Va terminals of the NOR gate are simultaneously low, meaning the signal output terminal Vb of the NOR gate will briefly increase from low -VCC1. During the time interval t2-t3, when the signal change at the Input terminal is fully output to the Va terminal, the signal output terminal Vb returns to a stable low potential of -VCC1. In this process, based on the pulse NOT gate 2021b connected to the signal output terminal Vb, after the pulse NOT gate 2021b receives the signal from the signal output terminal Vb, it outputs a bias pulse signal. When the input terminal changes from a high potential to a low potential -VCC1, the output terminal will briefly decrease from a high potential 0, and then return to a high potential 0.

[0127] The output terminal is the bias output terminal. Based on the delay module 300, the signal of the bias output terminal can be aligned in timing with the input signal of the first NOT gate 102 of each corresponding stage in the ring oscillation module 100. This ensures that when the level of each first NOT gate 102 is flipped, the body terminal of the second transistor 102b (NMOS) of the first NOT gate 102 can receive the output pulse signal output from the bias output terminal. The pulse signal increases the substrate voltage of the second transistor 102b (NMOS), thereby increasing the threshold voltage of the second transistor 102b (NMOS) and controlling the turn-off time of the second transistor 102b (NMOS) to be advanced.

[0128] Thus, when the signal input level of the first NOT gate 102 in each stage of the ring oscillation module 100 changes from high to low, the second transistor 102b (NMOS) turns off. At this time, the first transistor 102a (PMOS) gradually turns on, generating a switching current, which is output to the next stage's first NOT gate 102. During this process, the potential of the bias output terminal becomes a potential lower than 0. Since the body terminal of all the second transistors 102b (NMOS) has a certain resistance, the local body terminal potential of the second transistor 102b (NMOS) will become a potential value lower than 0, resulting in a negative potential difference between the body terminal and the source terminal of the second transistor 102b (NMOS). This significantly increases the turn-on voltage of the second transistor 102b (NMOS), thus greatly reducing the additional short-circuit current flowing through the second transistor 102b (NMOS) when the first transistor 102a (PMOS) undergoes a level switching.

[0129] Furthermore, in other timing sequences, the signal at the bias output terminal is at 0 potential. Therefore, the body terminal of the second transistor 102b (NMOS) of the first NOT gate 102 receives a 0 potential, which does not affect the switching current of the second transistor 102b (NMOS). This allows for a more accurate and effective drive current of the ring oscillation module 100 to be obtained from the first voltage terminal A.

[0130] Figure 11 This is a schematic diagram of another test circuit provided in an embodiment of this application. Figure 12 This is a schematic diagram of the bias module of another test circuit provided in an embodiment of this application. Figure 13 This is a schematic diagram of the circuit connection of the first NOT gate in another test circuit provided in an embodiment of this application. Figure 14 A schematic diagram of the circuit connection of the pulse generation subunit of another test circuit provided in an embodiment of this application. Figure 15 A timing diagram of another test circuit provided in an embodiment of this application.

[0131] Reference Figures 11 to 15 As shown, as another possible implementation, the pulse logic gate 2021a is a NAND gate, and its bias output terminal is connected to the body terminal of the first transistor 102a.

[0132] At this time, the voltage value of the first voltage terminal A is a, the voltage value of the third voltage terminal C is a1, and the voltage value of the fourth voltage terminal D is a2. a, a1, and a2 satisfy the formulas: a2 = a, a1 = 2a; the second voltage terminal B is grounded. In this embodiment, the voltage value a of the first voltage terminal A is... Figure 11 VCC1 in the middle.

[0133] During the operation of the test circuit, the body terminals of the first transistors 102a (PMOS) of all the first NOT gates 102 in the first inverting unit are connected to the bias output terminals of the corresponding pulse generation subunits 2021. For the pulse logic gate 2021a, which is a NAND gate, when the Input terminal potential remains constant, the potential of its signal output terminal Vb is always high at VCC3. After passing through the pulse NOT gate 2021b, the final Output terminal outputs a low potential VCC2. At time t1, when the Input terminal level changes from low to high, the Va terminal needs a short delay before it becomes low at VCC2. During the short delay of t1-t2, there is a brief moment when the Input terminal and Va terminal of the NAND gate are simultaneously high, meaning that the signal output terminal Vb of the NAND gate will briefly decrease from the high potential VCC3. During the time interval t2-t3, when the signal change at the Input terminal is fully output to the Va terminal, the signal output terminal Vb returns to a stable high potential VCC3. In this process, based on the pulse NOT gate 2021b connected to the signal output terminal Vb, after receiving the signal from the signal output terminal Vb, the pulse NOT gate 2021b outputs a bias pulse signal. When the input terminal changes from a low potential VCC2 to a high potential VCC3, the output terminal will briefly rise from a low potential VCC2 and then return to a low potential VCC2.

[0134] The output terminal serves as a bias output terminal. Based on the delay module 300, the signal of the bias output terminal can be aligned in timing with the input signal of the first NOT gate 102 of each corresponding stage in the ring oscillation module 100, so that when the level of each first NOT gate 102 undergoes a level flip, the body terminal of the first transistor 102a (PMOS) of the first NOT gate 102 can receive the signal of the bias output terminal.

[0135] Thus, when the signal input level of the first NOT gate 102 in each stage of the ring oscillation module 100 changes from low to high, the first transistor 102a (PMOS) turns off. At this time, the second transistor 102b (NMOS) gradually turns on, generating a switching current, which is output to the next stage's first NOT gate 102. During this process, the potential of the bias output terminal becomes higher than VCC2 (=VCC1). Since the body terminal of all the first transistors 102a (PMOS) has a certain resistance, the local body terminal potential of the first transistor 102a (PMOS) will become higher than VCC1, resulting in a positive potential difference between the body terminal and the source terminal of the first transistor 102a (PMOS). This significantly increases the turn-on voltage of the first transistor 102a (PMOS), thus greatly reducing the additional short-circuit current flowing through the first transistor 102a (PMOS) when the second transistor 102b (NMOS) undergoes a level switching.

[0136] Furthermore, in other timing sequences, the signal at the bias output terminal is VCC2 (=VCC1), and the body and source terminals of the first transistor 102a (PMOS) have the same potential, which does not affect the switching current of the first transistor 102a (PMOS). In this way, a more accurate effective drive current of the ring oscillation module 100 can be obtained from the first voltage terminal A.

[0137] Figure 10 This is a schematic diagram of the structure of a delay module of a test circuit provided in an embodiment of this application, combined with... Figure 4 and Figure 10 As shown, the delay module 300 includes an even number of delay NOT gates 301, which are cascaded sequentially. The signal input terminal of the first-stage delay NOT gate 301 is connected to the signal input terminal of the bias module 200 to receive an enable signal; the signal output terminal of the last-stage delay NOT gate 301 is connected to the enable input terminal of the ring oscillation module 100. This embodiment shows two delay NOT gates 301. In some embodiments, the number of delay NOT gates 301 can be adjusted according to the test circuit settings; this embodiment does not impose any limitations on this.

[0138] The delay module 300 also includes a delay capacitor 302. The first electrode 302a of the delay capacitor 302 is connected between any two delay NOT gates 301, and the second electrode 302b of the delay capacitor 302 is connected to the third voltage terminal C. By changing the capacitance value of the delay capacitor 302, the charging and discharging time of the delay circuit when the input enable signal changes can be controlled, thereby achieving precise control of the delay time of the delay module 300.

[0139] Based on the above-described testing system, this application provides a testing method for use in the above-described testing system. Figure 17 The flowchart of the testing method provided in the embodiments of this application is shown in the figure. Figure 17 As shown, the test method includes:

[0140] S100: Apply an enable signal to the test circuit.

[0141] It should be noted that, based on the connection between the signal generation circuit 400 and the test circuit, the signal generation circuit 400 can write an enable signal into the test circuit. This enable signal can be output to the bias module 200, causing it to generate a bias pulse signal. The bias pulse signal is then output to the body terminal of the transistor in the first inverting unit of the ring oscillation module 100. The enable signal can also be output to the delay circuit, causing it to generate an enable signal with a preset delay time, and then output to the ring oscillation module 100 to generate an oscillation signal.

[0142] S200: Obtain the current value at the first voltage terminal of the ring oscillation module of the test circuit and the oscillation frequency of the oscillation signal generated by the ring oscillation module.

[0143] It should be noted that the above process can be completed by the test device 500 connected to the first voltage terminal.

[0144] S300: Determine the effective drive current of the ring oscillation module based on the current value at the first voltage terminal.

[0145] It should be noted that, in this embodiment, during the level flipping process of the first inverting unit in the ring oscillation module 100, the threshold voltage of the transistor in the first inverting unit can be adjusted by the bias pulse signal generated by the bias module 200, thereby avoiding additional drive current in the non-conducting transistor in the first inverting unit during level flipping. Therefore, the current value obtained from the first voltage terminal is the effective drive current of the ring oscillation module 100.

[0146] S400: Determine the equivalent capacitance and equivalent resistance of the transistor in the first inverting unit of the ring oscillation module based on the effective drive current and oscillation frequency.

[0147] It should be noted that the equivalent resistance can be determined based on the effective drive current and oscillation frequency, and the equivalent capacitance can be determined based on the equivalent resistance and the delay of the ring oscillation module. In some embodiments, the equivalent capacitance of each stage of the first NOT gate 102 is equal. Therefore, by dividing the equivalent capacitance equally, the equivalent capacitance of the CMOS in a single first NOT gate 102 can be analyzed based on the equivalent capacitance of the ring oscillation module, thereby determining the relationship between the equivalent capacitance of the CMOS and the ion doping of the CMOS.

[0148] This application also provides a semiconductor chip, including the aforementioned testing system. The semiconductor chip further includes a substrate layer, which can be a PCB (Printed Circuit Board). The signal generation circuit 400, testing device 500, testing circuit, frequency divider element 600, and output buffer element 700 of the aforementioned testing system can all be disposed on this substrate layer. Other technical features in the testing circuit of the semiconductor chip of this application are the same as those in the aforementioned testing circuit embodiments and achieve the same technical effects, and will not be described in detail here.

[0149] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0150] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A test circuit, characterized in that, It includes a ring oscillation module, a bias module, and a delay module; The ring oscillation module includes an enable input terminal and a bias control terminal. The ring oscillation module includes an odd number of first inverting units, which are cascaded in sequence. Each first inverting unit includes a transistor. The delay module includes a signal input terminal and a signal output terminal. The signal input terminal of the delay module is used to receive an enable signal. The delay module is used to delay the received enable signal for a preset time and then output it to the enable input terminal of the ring oscillation module through the signal output terminal of the delay module. The bias module includes a signal input terminal and a bias output terminal. The signal input terminal of the bias module is connected to the signal input terminal of the delay module and is used to receive the enable signal. The bias module is used to generate a bias pulse signal according to the received enable signal, and output it to the bias control terminal of the ring oscillation module through the bias output terminal. The bias pulse signal is used to adjust the threshold voltage of the transistor when the first inverting unit undergoes a level flip. The bias module includes a ring oscillation unit and a pulse generation unit; The ring oscillation unit includes a signal input terminal, which is connected to the signal input terminal of the delay module. It is used to generate an oscillation signal when the enable signal is received. The ring oscillation unit is used to output a modulation signal to the pulse generation unit when generating the oscillation signal. The pulse generation unit includes the bias output terminal. The pulse generation unit is used to generate the bias pulse signal according to the modulation signal, and output the bias pulse signal to the bias control terminal of the ring oscillation module through the bias output terminal. The body terminal of the transistor of the first inverting unit serves as the bias control terminal of the ring oscillation module. The enable signal with a preset delay is used to control the oscillation signal generated by the ring oscillation module, which lags behind the oscillation signal generated by the ring oscillation unit, so that when the first inverting unit of the ring oscillation module undergoes a level flip, it receives the bias pulse signal.

2. The test circuit according to claim 1, characterized in that, An odd number of first inverting units include a first NAND gate and an even number of first NOT gates cascaded in sequence. The first signal input terminal of the first NAND gate serves as the enable input terminal of the ring oscillation module. The signal output terminal of the first NAND gate is connected to the signal input terminal of the first stage first NOT gate. The second signal input terminal of the first NAND gate is connected to the signal output terminal of the last stage first NOT gate. Furthermore, the signal output terminal of the first NOT gate in the last stage serves as the signal output terminal of the ring oscillation module.

3. The test circuit according to claim 2, characterized in that, The ring oscillation unit includes an odd number of second inverting units, which are cascaded in sequence, and each second inverting unit includes a transistor.

4. The test circuit according to claim 3, characterized in that, Each of the first NOT gates includes a first transistor and a second transistor of different types. The first power supply terminal of the first NAND gate and the first terminal of the first transistor are both connected to a first voltage terminal, and the second power supply terminal of the first NAND gate and the first terminal of the second transistor are both connected to a second voltage terminal. In the same first NOT gate, the second terminal of the first transistor is connected to the second terminal of the second transistor and serves as the signal output terminal of the corresponding first NOT gate; the control terminal of the first transistor is connected to the control terminal of the second transistor and serves as the signal input terminal of the corresponding first NOT gate.

5. The test circuit according to claim 4, characterized in that, An odd number of second inverting units include a second NAND gate and an even number of second NOT gates cascaded in sequence. The first signal input terminal of the second NAND gate serves as the signal input terminal of the ring oscillation unit. The signal output terminal of the second NAND gate is connected to the signal input terminal of the first stage second NOT gate. The second signal input terminal of the second NAND gate is connected to the signal output terminal of the last stage second NOT gate. The number of the first NOT gates is equal to the number of the second NOT gates.

6. The test circuit according to claim 5, characterized in that, Each of the second NOT gates includes a third transistor and a fourth transistor of different types. The first power supply terminal of the second NAND gate and the first terminal of the third transistor are both connected to a third voltage terminal, and the first power supply terminal of the second NAND gate and the first terminal of the fourth transistor are both connected to a fourth voltage terminal. In the same second NOT gate, the second terminal of the third transistor is connected to the second terminal of the fourth transistor and serves as the signal output terminal of the corresponding second NOT gate. The control terminal of the third transistor is connected to the control terminal of the fourth transistor and serves as the signal input terminal of the corresponding second NOT gate.

7. The test circuit according to claim 6, characterized in that, The pulse generation unit includes an even number of pulse generation subunits; Each pulse generation subunit is connected to the second inverting unit and the first inverting unit in a one-to-one correspondence. Each pulse generation subunit is used to generate a corresponding bias pulse signal according to the modulation signal generated by the corresponding connected second inverting unit, and output it to the body terminal of the transistor of the corresponding connected first inverting unit. The number of pulse generation subunits, the number of the first NOT gate, and the number of the second NOT gate are all equal.

8. The test circuit according to claim 7, characterized in that, Each pulse generation subunit includes a pulse logic gate and a pulse NOT gate. The first power supply terminal of the pulse logic gate and the first power supply terminal of the pulse NOT gate are both connected to the third voltage terminal, and the second power supply terminal of the pulse logic gate and the second power supply terminal of the pulse NOT gate are both connected to the fourth voltage terminal. The first signal input terminal of the pulse logic gate is connected to the signal input terminal of the second NOT gate corresponding to the pulse generation subunit, and the second signal input terminal of the pulse logic gate is connected to the signal output terminal of the second NOT gate corresponding to the pulse generation subunit. The signal output terminal of the pulse logic gate is connected to the signal input terminal of the pulse NOT gate. The signal output terminal of the pulse NOT gate serves as the bias output terminal of the pulse generation subunit and is connected to the body terminal of the transistor of the first inverting unit corresponding to the pulse generation subunit.

9. The test circuit according to claim 6, characterized in that, The first transistor and the third transistor are PMOS transistors, and the second transistor and the fourth transistor are NMOS transistors.

10. The test circuit according to claim 8, characterized in that, The pulse logic gate is a NAND gate, and the bias output terminal is connected to the body terminal of the first transistor. The voltage value of the first voltage terminal is a, the voltage value of the third voltage terminal is a1, and the voltage value of the fourth voltage terminal is a2. The voltage values ​​of a, a1, and a2 satisfy the formula: a2=a, a1=2a; the second voltage terminal is grounded.

11. The test circuit according to claim 8, characterized in that, The pulse logic gate is a NOR gate, and the bias output terminal is connected to the body terminal of the second transistor; The voltage value of the first voltage terminal is b, and the voltage value of the fourth voltage terminal is b1. The b and the b1 satisfy the formula: b1=-b, and b>0; the second voltage terminal and the third voltage terminal are both grounded.

12. The test circuit according to any one of claims 1-11, characterized in that, The delay module includes at least two delay NOT gates, which are cascaded in sequence. The signal input terminal of the first-stage delay NOT gate is connected to the signal input terminal of the bias module to receive the enable signal. The signal output terminal of the delay NOT gate in the last stage is connected to the enable input terminal of the ring oscillation module; The delay module is used to generate an enable signal with a preset delay time according to the enable signal, and output it to the enable input terminal.

13. The test circuit according to claim 12, characterized in that, The delay module also includes a delay capacitor, the first electrode of which is connected between any two delay NOT gates, and the second electrode of which is connected to a third voltage terminal.

14. A testing system, characterized in that, The device includes an enable signal generation circuit, a test apparatus, and a test circuit according to any one of claims 1-13. The enable signal output terminal of the enable signal generation circuit is connected to the signal input terminal of the bias module of the test circuit, and the enable signal output terminal is connected to the enable input terminal of the ring oscillation module of the test circuit through the delay module of the test circuit.

15. The testing system according to claim 14, characterized in that, It also includes a frequency divider and an output buffer. The frequency divider is connected to the signal output terminal of the ring oscillation module of the test circuit, and the output buffer is connected to the signal output terminal of the frequency divider.

16. A testing method, characterized in that, For the test system of claim 14 or 15, the test method includes: Apply an enable signal to the test circuit; Obtain the current value at the first voltage terminal of the ring oscillation module of the test circuit and the oscillation frequency of the oscillation signal generated by the ring oscillation module; The effective drive current of the ring oscillation module is determined based on the current value at the first voltage terminal. The equivalent capacitance and equivalent resistance of the transistor in the first inverting unit of the ring oscillation module are determined based on the effective drive current and the oscillation frequency.

17. A semiconductor chip, characterized in that, Includes the test system described in claim 14 or 15.

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