Display panel and display device

Abstract

The application discloses a display panel and a display device, which comprise a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a data writing module; the driving module comprises a driving transistor; the working process of the pixel circuit comprises a data writing stage and a bias stage; in the data writing stage, the data writing module provides a data signal; in the bias stage, the data writing module provides a bias signal; the driving transistor is used for selectively providing a driving current to the light emitting element; the working process of the pixel circuit comprises a first light emitting stage and a first non-light emitting stage; in the first non-light emitting stage, the starting moment of the bias stage to the starting moment of the first light emitting stage is a bias maintaining stage; the working mode of the display panel comprises a first mode and a second mode; the display brightness of the display panel in the first mode is different from the display brightness of the display panel in the second mode; the length of the bias maintaining stage in the first mode is different from the length of the bias maintaining stage in the second mode.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and more particularly to a display panel and a display device. Background Technology

[0002] Display panels typically contain pixel circuits and light-emitting elements. The driving transistors in the pixel circuits can provide driving current to the light-emitting elements based on the data signals they receive, thereby driving the light-emitting elements to emit light and enabling the display panel to display the corresponding image.

[0003] However, over time, the internal characteristics of the driving transistors in the pixel circuit change slowly, causing the threshold voltage of the driving transistors to drift. Moreover, the threshold drift of the driving transistors varies under different display brightness, thus affecting the display uniformity of the display panel. Summary of the Invention

[0004] The present invention provides a display panel and its driving method and display device, which adjust the bias of the driving transistor to different degrees for different brightness modes, thereby improving the display uniformity of the display panel in different brightness modes.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: pixel circuitry and light-emitting elements;

[0006] The pixel circuit includes a driving module and a data writing module; the driving module includes a driving transistor;

[0007] The operation of the pixel circuit includes a data writing stage and a bias stage; in the data writing stage, the data writing module provides a data signal; in the bias stage, the data writing module provides a bias signal.

[0008] The driving transistor is used to selectively provide driving current to the light-emitting element; the pixel circuit operation process includes a first light-emitting stage and a first non-light-emitting stage;

[0009] During the first non-luminescent phase, the period from the start of the bias phase to the start of the first luminescent phase is the bias maintenance phase.

[0010] The display panel has two operating modes: a first mode and a second mode. The display brightness of the display panel in the first mode is different from that in the second mode.

[0011] The length of the bias maintenance phase in the first mode is different from the length of the bias maintenance phase in the second mode.

[0012] In a second aspect, embodiments of the present invention provide a display device including the display panel described in the first aspect.

[0013] The technical solution of this invention provides a bias signal to the driving module during the bias phase of the first non-light-emitting stage. This ensures that the voltage difference between the source and / or drain of the driving transistor and its gate is equal to the voltage difference between the bias adjustment signal and its gate, thereby adjusting the bias of the driving transistor and improving the threshold voltage drift caused by internal ion polarization. Simultaneously, when the display panel is in different modes, it exhibits different display brightness, resulting in differences in the voltage of the data signal provided to the driving module. By setting different durations for the bias maintenance phase in different modes, the source and / or drain of the driving transistor can be held at the bias adjustment signal for different durations, allowing for targeted adjustment of the bias state of the driving transistor in each mode. This ensures display uniformity across different modes and improves the display effect of the display panel.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the pixel circuit in a display panel provided by an embodiment of the present invention;

[0018] Figure 3 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention;

[0020] Figure 5 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0021] Figure 6This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0022] Figure 7 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0023] Figure 8 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0024] Figure 9 Is with Figure 2 A corresponding timing diagram of the pixel circuit in a display panel;

[0025] Figure 10 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0026] Figure 11 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0027] Figure 12 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0028] Figure 13 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0029] Figure 14 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0030] Figure 15 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0031] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a system, product, or device comprising a series of units is not necessarily limited to those steps or units explicitly listed, but may include other units not explicitly listed or inherent to such products or devices.

[0034] Self-emissive display panels include pixel circuits and light-emitting elements. The pixel circuits include driving transistors. By providing a data signal to the gate of the driving transistor, the driving transistor converts the data signal into a driving current to drive the light-emitting element to emit light. However, when the driving transistor is turned on, for PMOS transistors, its gate potential may be higher than its drain potential, and for NMOS transistors, its gate potential may be lower than its drain potential. If this state is maintained for a long time, the ions inside the driving transistor will become polarized, resulting in a built-in electric field inside the driving transistor. This causes the threshold voltage of the driving transistor to drift continuously, biasing the driving transistor and affecting the stability of the driving current provided by the driving transistor, thereby affecting the light-emitting stability of the light-emitting element.

[0035] Furthermore, when the display panel presents different display brightness, the data signals provided to the driving transistor will be different, or the light emission duration of the light-emitting element will be different, resulting in different bias conditions of the driving transistor, that is, different threshold voltage drift of the driving transistor, which affects the display uniformity of the display panel under different display brightness, and thus affects the display effect of the display panel.

[0036] To address the aforementioned technical problems, embodiments of the present invention set different durations for the bias maintenance phase in different modes, enabling the source and / or drain of the driving transistor to maintain the bias adjustment signal for different durations. This allows for targeted adjustment of the bias state of the driving transistor in each mode, thereby ensuring display uniformity in different modes and improving the display effect of the display panel.

[0037] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0038] Figure 1This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the pixel circuit structure in a display panel provided by an embodiment of the present invention. Figure 3 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figures 1 to 3 The display panel 10 includes a pixel circuit 100 and a light-emitting element 200; the pixel circuit 100 includes a driving module 11 and a data writing module 12; the driving module 11 includes a driving transistor M1; the driving module 11 is used to selectively provide driving current to the light-emitting element 200; the operation process of the pixel circuit 100 includes a data writing stage Ta and a bias stage Tb; in the data writing stage Ta, the data writing module 12 provides a data signal Vdata; in the bias stage Tb, the data writing module 12 provides a bias signal Vobs.

[0039] The operation of the pixel circuit 100 includes a first light-emitting stage T21 and a first non-light-emitting stage T11. The first light-emitting stage T21 may be located after the first non-light-emitting stage T11, and the first light-emitting stage T21 and the first non-light-emitting stage T11 are two time-continuous stages. The first non-light-emitting stage T11 may include at least a bias stage Tb. During the first non-light-emitting stage T11, the period from the start of the bias stage Tb to the start of the first light-emitting stage T21 constitutes a bias maintenance stage Tc. When the operating modes of the display panel 10 include a first mode N1 and a second mode N2, and the brightness of the display panel 10 in the first mode N1 differs from the brightness of the display panel 10 in the second mode N2, the length of the bias maintenance stage Tc11 in the first mode N1 differs from the length of the bias maintenance stage Tc21 in the second mode N2.

[0040] It is understood that the display panel 10 may include an array of pixel circuits 100 and light-emitting elements 200 electrically connected to each pixel circuit 100. By providing data signals to each pixel circuit 100, the driving module 11 in the pixel circuit 100 can provide driving current to the light-emitting element 200 during the light-emitting stage Tb, so as to drive the light-emitting element 200 to display light, and enable the display panel 10 to present a display image of corresponding brightness.

[0041] Since the light-emitting element 200 is typically a current-driven element, and the data signal received by the pixel circuit 100 is typically a voltage signal, by setting a driving transistor M1 in the driving module 11, the data signal received by the pixel circuit 100 can be written to the gate of the driving transistor M1. Furthermore, by providing a positive power supply signal PVDD to the source or drain of the driving transistor M1, the driving transistor M1 generates a corresponding driving current based on the voltage difference between its gate potential and the positive power supply signal PVDD, as well as the threshold voltage of the driving transistor M1, and provides it to the light-emitting element 200, thereby driving the light-emitting element 200 to emit light at a corresponding brightness. At this time, one of the source and drain of the driving transistor M1 is coupled to the positive power supply signal terminal, and the other is coupled to the anode of the light-emitting element 200. The cathode of the light-emitting element 200 can be electrically connected to the negative power supply signal terminal. Thus, since there is a voltage difference between the positive power supply signal PVDD at the positive power supply signal terminal and the negative power supply signal PVEE at the negative power supply signal terminal, a current path is formed. Therefore, in the light-emitting stage T2, the driving transistor M1 can generate a driving current and provide it to the light-emitting element 200 to drive the light-emitting element 200 to emit light.

[0042] It is understood that the active layer material of the driving transistor M1 in the driving module 11 may include low-temperature polycrystalline silicon, which gives it a high carrier mobility, thereby meeting the requirements of high response speed and low power consumption. In this case, the driving transistor M1 can be a PMOS type transistor. In other optional embodiments, the active layer material of the driving transistor M1 may also include oxide semiconductor material. In this case, the driving transistor M1 can be an NMOS type transistor. Provided that the core inventive points of this invention can be achieved, this invention does not specifically limit the material and type of the driving transistor M1.

[0043] It should be noted that the source and drain of a transistor are not constant, but change as the state of the transistor changes. Figure 2 The example shown only illustrates the case where the driving transistor M1 is a PMOS type transistor. In this case, the drain of the driving transistor M1 is coupled to the light-emitting element 200, and for the PMOS type driving transistor M1, the driving current I generated by the driving transistor M1 is k(PVDD-Vdata). 2 Positive correlation. The positive power signal PVDD is usually a constant value. When PVDD is always greater than Vdata, the smaller Vdata is, the larger the driving current I is, and the greater the display brightness of the light-emitting element 200.

[0044] For ease of description, unless otherwise specified, the embodiments of the present invention all use PMOS transistors as an example to illustrate the technical solutions of the embodiments of the present invention.

[0045] Among them, in conjunction with reference Figure 2 and Figure 3 As shown, the pixel circuit 100 may also include a data writing module 12. During the data writing stage Ta, the data signal Vdata provided by the data writing module 12 is sent to the driving module 11 and written to the gate of the driving transistor M1. At this time, the data writing module 12 may be directly electrically connected to the gate of the driving transistor M1, or the data writing module 12 may be indirectly electrically connected to the gate of the driving transistor M1.

[0046] In an optional embodiment, the control terminal of the data writing module 12 receives a scan signal SP, the input terminal of the data writing module 12 can receive a data signal during the data writing stage Ta, and the output terminal of the data writing module 12 can be electrically connected to the source of the driving transistor M1. At this time, during the data writing stage Ta, the scan signal SP controls the data writing module 12 to be turned on, so that the data signal Vdata can be transmitted through the data writing module 12 to the source of the driving transistor M1, and then sequentially transmitted through the source and drain of the driving transistor M1 to the gate of the driving transistor M1. In this way, while the data signal Vdata is being written, the threshold voltage Vth of the driving transistor M1 can also be compensated to the gate of the driving transistor M1, so that when the driving transistor M1 generates a driving current according to the voltage of its gate, the driving current can be independent of the threshold voltage Vth of the driving transistor M1, preventing the magnitude of the driving current Id generated by the threshold voltage drift of the driving transistor M1 from being affected, thereby affecting the luminous brightness of the light-emitting element 200.

[0047] Optionally, when the data writing module 12 is electrically connected to the source of the driving transistor M1, the pixel circuit 100 may further include a compensation module 13. This compensation module 13 is electrically connected between the drain and gate of the driving transistor M1. The compensation module 13 can be turned on or off under the control of the scan signal S-N2. At least during the data writing phase Ta, the scan signal S-N2 can control the compensation module 13 to be turned on, thereby forming a path between the drain and gate of the driving transistor M1. The data signal Vdata can then be written sequentially through the data writing module 12, the driving transistor M1, and the compensation module 13 to the gate of the driving transistor M1, compensating the threshold voltage of the driving transistor M1 to the gate of the driving transistor M1.

[0048] In an exemplary embodiment, the compensation module 13 may include a compensation transistor M3, the gate of which receives a scan signal S-N2, a first terminal of which is electrically connected to the drain of a driving transistor M1, and a second terminal of which is electrically connected to the source of the driving transistor M1. Thus, the scan signal S-N2 can control the compensation transistor M3 to conduct at least during the data writing phase Ta.

[0049] Correspondingly, the data writing module 12 can also provide the bias signal Vobs to the driving module 11 during the biasing phase Tb. Since the data writing module 12 is electrically connected to the source of the driving transistor M1, it provides the bias signal Vobs to the source of the driving transistor M1 during the biasing phase Tb. Simultaneously, when the driving transistor M1 is in the on state during the biasing phase Tb, the bias signal Vobs can also be transmitted to the drain of the driving transistor M1. Furthermore, during the biasing phase Tb, the compensation module 13 can be controlled to be in the off state by the scan signal S-N2, preventing the bias signal Vobs from being transmitted to the gate of the driving transistor M1, thus preventing the bias signal Vobs from affecting the gate voltage of the driving transistor M1 and ensuring the accuracy of the driving current generated by the driving transistor M1 during the light-emitting phase T2.

[0050] Understandably, when the data signal Vdata received by the driving transistor M1 is different, the driving current generated by the driving transistor M1 is different, resulting in different light-emitting brightness of the light-emitting element 200. Conversely, when different light-emitting brightness is required for the light-emitting element 200, different data signals are provided to the gate of the driving transistor M1. At this time, if the source / drain voltage of the driving transistor M1 is a fixed value, the voltage difference between the gate of the driving transistor M1 and its source / drain will be different, thus causing the driving transistor M1 to be in different bias states.

[0051] It is also understandable that the display panel 10 can operate in different modes under different application scenarios, and in different operating modes, the display panel 10 can display different brightness levels. For example, in a brighter environment, in order to ensure that the image displayed by the display panel 10 is recognizable by the human eye, the image displayed by the display panel 10 is usually controlled to have a higher brightness; in a darker environment, in order to prevent the image displayed by the display panel 10 from causing damage to the human eye due to high brightness, the image displayed by the display panel 10 is usually controlled to have a lower brightness. Specifically, by adjusting the relationship between grayscale (i.e., the luminous brightness level of the light-emitting element 200) and the data signal, the display panel 10 can achieve different display brightness levels in different operating modes.

[0052] For example, when the operating modes of the display panel 10 include a first mode N1 and a second mode N2, and the brightness of the display panel 10 in the first mode N1 is different from the brightness of the display panel 10 in the second mode N2, when the display panel 10 presents the same image in the first mode N1 and the second mode N2 respectively, for the same light-emitting element 200, the brightness level presented in the first mode N1 is the same as the brightness level presented in the second mode N2, but the voltage of the data signal Vdata received by the pixel circuit 100 used to drive the light-emitting element 200 is different. For example, in the first mode N1, the voltage of the data signal Vdata provided to the gate of the driving transistor M1 used to drive the light-emitting element 200 is V1, while in the second mode N2, the voltage provided to the driving transistor M1 used to drive the light-emitting element 200 is V1. The voltage of the data signal Vdata provided by the gate of M1 is V2, where V1 ≠ V2. At this time, if the voltage between the source and drain of the driving transistor M1 is Vs / d, then in the first mode, the voltage difference between the gate of the driving transistor M1 and its source / drain is V1-Vs / d. However, in the light-emitting stage of the second mode, the voltage difference between the gate of the driving transistor M1 and its source / drain is V2-Vs / d. This results in a difference in the voltage difference between the gate and the source / drain of the driving transistor after the data writing stage in the first and second modes. Consequently, the driving transistor M1 has different bias states after the data writing stage in the first and second modes, leading to different threshold drift amounts of the driving transistor M1. This, in turn, affects the driving current provided by the driving transistor M1 in the subsequent light-emitting stage T2.

[0053] Therefore, after the data writing stage Ta, a bias stage Tb can be set. During this bias stage Tb, the data writing module 12 provides a bias signal Vobs to the source / drain of the driving transistor M1 to adjust the bias of the driving transistor M1. Simultaneously, after providing the bias signal Vobs to the source / drain of the driving transistor M1, if no new signal is written to the source / drain of the driving transistor M1, the source / drain of the driving transistor M1 will continue to maintain the bias signal Vobs. Since the bias sustaining phase Tc is the time period between the start of the bias phase Tb and the start of the first light emission phase T21, and no new signals are written to the source / drain of the driving transistor M1 after the bias phase Tb and before the light emission phase T2, the source / drain of the driving transistor M1 will remain at the bias signal Vobs during the bias sustaining phase Tc. This causes the voltage difference between the gate of the driving transistor M1 and its source / drain to remain at the voltage difference between the data signal Vdata and the bias signal Vobs, thus keeping the driving transistor M1 in the corresponding bias state.

[0054] Furthermore, since the bias of the driving transistor M1 is caused by its internal ion polarization, the bias of the driving transistor M1 changes over time. In this case, by setting different durations for the bias sustaining phase Tc11 in the first mode and the bias sustaining phase Tc21 in the second mode, the bias caused by the different durations of the bias sustaining phase Tc can partially or completely cancel out the bias caused by the different data signals. This ensures that the bias of the driving transistor M1 remains consistent when entering the first light-emitting phase T21 in different modes, thereby improving the display uniformity of the display panel in different modes and ultimately improving the display effect of the display panel 10.

[0055] Understandably, this embodiment of the invention does not specifically limit the display brightness of the display panel in the first mode and the duration of the bias maintenance phase in the second mode, provided that the bias caused by the different data signals is balanced by setting the duration of the bias maintenance phase in the first mode and the duration of the bias maintenance phase in the second mode.

[0056] In an alternative embodiment, reference continues. Figures 1 to 3 When the brightness of the display panel 10 in the first mode N1 is greater than the brightness of the display panel 10 in the second mode N2, if the length of the bias maintenance phase Tc11 in the first mode N1 is t10 and the length of the bias maintenance phase Tc21 in the second mode N2 is t20, then t10 > t20. That is, in the first mode, the voltage difference between the gate of the driving transistor M1 and its source / drain is maintained for a longer time as the voltage difference between the data signal and the bias signal, while in the second mode, the voltage difference between the gate of the driving transistor M1 and its source / drain is maintained for a shorter time as the voltage difference between the data signal and the bias signal.

[0057] Specifically, taking the driving transistor M1 as a PMOS as an example, when the luminous brightness level of the light-emitting element 200 is Q, the voltage V1 of the data signal Vdata in the first mode N1 will be less than the voltage V2 of the data signal Vdata in the second mode N1. This results in the voltage difference between the gate and its source / drain of the driving transistor M1 in the bias maintenance phase Tc11 of the first mode N1 being V1-Vobs, and the voltage difference between the gate and its source / drain of the driving transistor M1 in the bias maintenance phase Tc21 of the second mode N2 being V2-Vobs. Since V1-Vobs is less than V2-Vobs, the internal ion polarization of the driving transistor M1 is relatively small in the first mode N1 due to the voltage difference between the gate and its source / drain, while the internal ion polarization of the driving transistor M1 is relatively large in the second mode N2 due to the voltage difference between the gate and its source / drain. At this time, by setting the bias maintenance phase Tc11 in the first mode N1 to a longer time, the difference between the gate of the driving transistor M1 and its source / drain is maintained at V1-Vobs for a longer time, while the bias maintenance phase Tc21 in the second mode N2 is set to a shorter time, the difference between the gate of the driving transistor M1 and its source / drain is maintained at V1-Vobs for a shorter time. This balances the different degrees of bias caused by the different voltage differences between the gate of the driving transistor M1 and its source / drain in the first and second modes. This ensures that the bias of the driving transistor M1 remains consistent when entering the first light emission phase T21 in different modes, thereby improving the display uniformity of the display panel in different modes.

[0058] It should be noted that the operating modes of the display panel mentioned in the embodiments of the present invention include a first mode and a second mode. This does not simply refer to two operating modes of the display panel 10, but rather uses the first mode and the second mode to represent different operating modes of the display panel 10. Furthermore, the display panel 10 will have different brightness levels under different operating modes. In the embodiments of the present invention, the operating modes of the display panel 10 differ in different application scenarios, resulting in different brightness levels for the display panel 10. For ease of description, unless otherwise specified, the embodiments of the present invention will use the example of the display panel 10 having two operating modes (a first mode and a second mode) to illustrate the technical solutions of the embodiments of the present invention.

[0059] It is understood that the first non-light-emitting stage T11 includes at least the bias stage Tb. In this case, the first non-light-emitting stage T11 can be the first non-light-emitting stage T1 in a frame of time. Alternatively, the first non-light-emitting stage T11 can also include the data writing stage Ta.

[0060] Optional, continue to refer to Figures 1 to 3 The frame time of the display panel 10 may include the data write frame DT; when the display brightness of the display panel 10 in the first mode N1 is greater than the display brightness of the display panel 10 in the second mode N2, in the first mode, the length of the bias maintenance phase Tc11 in the data write frame DT is t11; in the second mode, the length of the bias maintenance phase Tc21 in the data write frame DT is t21; where t11>t21.

[0061] It is understood that a single frame of a video frame includes at least one non-light-emitting phase and at least one light-emitting phase, with the non-light-emitting and light-emitting phases alternating. Typically, the first non-light-emitting phase and the first light-emitting phase in a single frame constitute a data write frame. During the non-light-emitting phase of a data write frame, the data signal from the previous frame is cleared, and the data signal from the current frame is written; that is, the non-light-emitting phase of a data write frame should at least include a data write phase. When the non-light-emitting phase of a data write frame is the first non-light-emitting phase, this first non-light-emitting phase can simultaneously include a data write phase and an offset phase.

[0062] For details, please refer to [link / reference]. Figures 1 to 3 When the first non-light-emitting stage T11 of the data write frame DT includes both the data write stage Ta and the bias stage Tb, the data write stage Ta is usually located before the bias stage Tb. This ensures that when entering the bias stage Tb, the voltage difference between the gate of the driving transistor M1 and its source / drain is equal to the voltage difference between the data signal Vdata and the bias signal Vobs. At this time, because the brightness of the display panel in the first mode is greater than that in the second mode, the voltage difference between the gate of the driving transistor M1 and its source / drain is smaller in the first mode, while the voltage difference between the gate of the driving transistor M1 and its source and / or drain is larger in the second mode. Therefore, to ensure that the driving transistor M1 in the first mode and the second mode can have the same voltage difference when entering the first light-emitting stage T21 after the first non-light-emitting stage T11, the voltage difference between the driving transistor M1 in the first mode and the second mode must be equal. The different bias conditions allow the gate and source / drain of the driving transistor M1 in the first mode to maintain the voltage difference between the data signal Vdata and the bias signal Vobs for a longer time, while the time it takes for the gate and source / drain of the driving transistor M1 in the second mode to maintain the voltage difference between the data signal Vdata and the bias signal Vobs is shorter. This balances the bias caused by different data signals, ensuring that the bias of the driving transistor M1 in the light-emitting stage in the first mode is consistent with that in the light-emitting stage in the second mode. This allows the driving transistor M1 to stably provide the driving current corresponding to the received data signal, enabling the light-emitting element 200 to emit light accurately. This is beneficial for the uniformity of display in different modes and also improves the display effect of the display panel.

[0063] In an optional embodiment, the bias signal Vobs provided by the data writing module 12 of each pixel circuit 100 to its driving transistor M1 in the data writing frame DT can be the same or different. That is, the voltage of the bias signal Vobs in the data writing frame DT can be a fixed value or a non-fixed value, which can be set according to actual needs. This embodiment of the invention does not make specific limitations on this.

[0064] Optional, refer to the reference Figures 1 to 3 The data writing module 12, which provides bias and data signals, may include a writing transistor M2. In this case, the display panel 10 may also include a first signal line L1. The gate of the writing transistor M2 is electrically connected to the scan signal SP, so that the scan signal SP can control the writing transistor M2 to be turned on or off. The first terminal of the writing transistor M2 is electrically connected to the first signal line L1, which can transmit the data signal Vdata or the bias signal Vobs. The second terminal of the writing transistor M2 is electrically connected to the driving module 11. For example, the second terminal of the writing transistor M2 may be electrically connected to the source of the driving transistor M1 in the driving module 11. At this time, during the data writing phase Ta, the scan signal SP controls the writing transistor M2 to turn on, and the first signal line L1 transmits the data signal Vdata. The data signal Vdata is received by the first terminal of the writing transistor M2 and transmitted to the source of the driving transistor M1, and then transmitted to the gate of the driving transistor M1 via the driving transistor M1 and the compensation transistor M3. During the bias phase Tb, the scan signal SP again controls the writing transistor M2 to turn on, and the first signal line L1 transmits the bias signal Vobs. The bias signal Vobs is received by the first terminal of the writing transistor M2 and transmitted to the source of the driving transistor M1, and can also be transmitted to the drain of the driving transistor M1. At this time, there is no need to set separate transistors for providing bias signals and data signals, which simplifies the structure of the pixel circuit 100 and helps to increase the number of pixel circuits 100 per unit area of ​​the display panel 10, thereby improving the resolution of the display panel 10. At the same time, when the transistors providing bias signals Vobs and data signals Vdata are the same write transistor M2, the write transistor M2 can be controlled to conduct in the bias stage Tb and the data writing stage Ta respectively by the same scan signal SP, so as to reduce the number of signals provided to the pixel circuit 100, thereby simplifying the structure of the moving register of the display panel 10 for providing the scan signal SP and improving the narrow bezel of the display panel 10.

[0065] In this configuration, the gates of the write transistors M2 in the pixel circuits located in the same row typically receive the same scan signal SP, and the write transistors M2 in the same column are typically electrically connected to the same first signal line L1. This first signal line L1 is used for time-division multiplexing of the data signals Vdata of each write transistor M2. At this time, the bias stage Tb of the i-th row pixel circuit 100 can overlap with the data writing stage Ta of the (i+j)-th row pixel circuit 100, and the data signal Vdata of the (i+j)-th row pixel circuit 100 can be multiplexed as the bias signal Vobs of the i-th row pixel circuit 100. This eliminates the need to provide additional bias signals Vobs to each pixel circuit 100, which helps to reduce the number of signals provided to the pixel circuit 100, thereby simplifying the structure of the display panel 10. Correspondingly, since there are differences between the data signals Vdata of the pixel circuits 100 located in the same column, the bias signals Vobs provided to each pixel circuit 100 in the data writing frame DT are non-fixed signals.

[0066] In other optional embodiments, when the bias signal Vobs of the i-th row pixel circuit 100 does not reuse the data signal Vdata of the (i+j)-th row pixel circuit 100, the bias stages Tb of each row pixel circuit 100 can be entered sequentially or simultaneously after the data writing stage Ta of the last row pixel circuit 100. At this time, all signal lines can transmit the bias signal Vobs simultaneously. The voltage of the bias signal Vobs can be a fixed value so that the bias signal Vobs transmitted in each signal line remains unchanged, preventing the signal lines from being continuously charged / discharged due to frequent changes in the bias signal Vobs, which would result in additional power consumption. That is, by making the voltage of the bias signal Vobs a fixed value, it is beneficial to reduce the power consumption of the display panel 10.

[0067] In another alternative embodiment, Figure 4 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention, as shown below. Figure 4As shown, the data writing module 12 may include a first transistor M21 and a second transistor M22. The gate of the first transistor M21 receives a first scan signal S-P1, the first terminal of the first transistor M21 receives a data signal Vdata, and the second terminal of the first transistor M21 is electrically connected to the driving module 11. For example, the second terminal of the first transistor M21 may be electrically connected to the source of the driving transistor M1 in the driving module 11. During the data writing stage Ta, the first scan signal S-P1 controls the first transistor M21 to be turned on, so that the data signal Vdata can pass through the first transistor M21 and the driving transistor M1. The compensation module 13 transmits the signal to the gate of the driving transistor M1; the gate of the second transistor M22 receives the second scan signal S-P2, the first terminal of the second transistor M22 receives the bias signal Vobs, and the second terminal of the second transistor M22 is electrically connected to the driving module 11. For example, the second terminal of the second transistor M22 can be electrically connected to the source of the driving transistor M1 in the driving module 11. During the biasing phase, the second scan signal S-P2 controls the second transistor M22 to turn on, so that the bias signal Vobs can be transmitted to the source of the driving transistor M1, and also to the drain of the driving transistor M1. In this way, different transistors are used to transmit the data signal Vdata and the bias signal Vobs respectively, so that the transmission of the data signal Vdata and the bias signal Vobs do not affect each other, which is beneficial to improving the accuracy of the transmitted signal.

[0068] Understandable, Figure 4 The example shown is only illustrative of the case where the second terminals of both the first transistor M21 and the second transistor M22 are electrically connected to the source of the driving transistor M1. In other embodiments of the present invention, one of the first transistor and the second transistor may be electrically connected to the source of the driving transistor, and the other may be electrically connected to the drain of the driving transistor. Provided that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not specifically limit the connection method between the first transistor, the second transistor and the driving transistor.

[0069] Optional, see reference Figure 2 or Figure 4 The pixel circuit 100 may also include an initialization module 14. One end of the initialization module 14 receives an initialization signal Vref1, and the other end is electrically connected to the gate of the driving transistor M1. During the initialization phase Td, the initialization module 14 can transmit the initialization signal Vref1 to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1.

[0070] Specifically, the initialization module 14 can be turned on or off under the control of the scan signal S-N1. When the scan signal S-N1 controls the initialization module 14 to be turned on, the initialization signal Vref1 is transmitted to the gate of the driving transistor M1. At this time, the initialization module 12 may include an initialization transistor M4. The gate of the initialization transistor M4 receives the scan signal S-N1, the first terminal of the initialization transistor M4 receives the initialization signal Vref1, and the second terminal of the initialization transistor M4 is electrically connected to the gate of the driving transistor M1.

[0071] Optional, continue to refer to Figure 2 or Figure 4 The pixel circuit 100 may further include a reset module 15, which provides a reset signal Vref2 to the anode of the light-emitting element 200 during the reset phase to reset the anode of the light-emitting element 200, preventing the signal provided to the anode of the light-emitting element 200 in the previous light-emitting phase from affecting the light-emitting accuracy of the light-emitting element 200 in the next light-emitting phase. Thus, the reset phase in which the reset module 15 provides the reset signal Vref2 to the light-emitting element 200 should be located in the non-light-emitting phase before the light-emitting phase. Specifically, one end of the reset module 15 can receive the reset signal Vref2, and the other end can be electrically connected to the anode of the light-emitting element 200. The reset module 15 can also be turned on or off under the control of the scan signal SP. When the scan signal SP controls the reset module 15 to be turned on, the reset module 15 can transmit the reset signal Vref2 to the anode of the light-emitting element 200 to reset the light-emitting element 200. At this time, the reset module 15 may include a reset transistor M5. The gate of the reset transistor M5 can receive the scan signal SP, the first terminal of the reset transistor M5 receives the reset signal Vref2, and the second terminal of the reset transistor M5 is electrically connected to the anode of the light-emitting element 200. At this time, the reset stage can be the same stage as the data writing stage Ta, so as to shorten the length of the non-light-emitting stage T1 between the light-emitting stages T2, ensuring that the light-emitting stage T2 has a sufficient length and ensuring the display brightness of the display panel 10.

[0072] Optional, continue to refer to Figure 2 or Figure 4The pixel circuit 100 may further include a light-emitting control module 16, which can control the duration of the driving transistor M1 providing driving current to the light-emitting element 200 during the light-emitting stage T2. The light-emitting control module 16 can be connected in series with the light-emitting element 200 and the driving transistor M1 between the positive and negative power supply signal terminals. The light-emitting control module 16 may include a first light-emitting control transistor M6 and a second light-emitting control transistor M7. The gates of both the first and second light-emitting control transistors receive a light-emitting control signal Emit, which can control the first and second light-emitting control transistors M6 and M7 to be simultaneously turned on or off. The first terminal of the first light-emitting control transistor M6 receives a positive power supply signal PVDD, and the second terminal of the first light-emitting control transistor M6 is electrically connected to the source of the driving transistor M1. The first terminal of the second light-emitting control transistor M7 is electrically connected to the drain of the driving transistor M1, and the second terminal of the second light-emitting control transistor M7 is electrically connected to the anode of the light-emitting element 200.

[0073] Understandably, the types of transistors in the pixel circuit 100 can be set as needed. For example, to prevent instability of the gate voltage of the driving transistor M1 during non-data writing and non-initialization phases, the initialization transistor M4 and compensation transistor M3 can be set as NMOS transistors, while the other transistors can be set as PMOS transistors. NMOS transistors conduct when the voltage difference between their gate and source is greater than their threshold voltage, while PMOS transistors conduct when the voltage difference between their gate and source is less than their threshold voltage. Therefore, the signal supplied to the gate of each transistor can be adaptively adjusted so that each transistor is in the conducting state during its designated conduction phase.

[0074] In addition, continue to refer to Figure 2 or Figure 4 The pixel circuit 100 may further include a storage capacitor C, which can be used to store the gate potential of the driving transistor M1. The specific connection method of the storage capacitor C can be determined according to specific circumstances. Provided that the storage of the gate potential of the driving transistor M1 can be achieved, this embodiment of the invention does not specifically limit the connection method of the storage capacitor.

[0075] In other alternative embodiments, when the bias signal of the data write frame in the first mode N1 is V3 and the bias signal of the data write frame in the second mode N2 is V4, V4 ≠ V3.

[0076] Specifically, since the gate voltage of the driving transistor M1 when writing data frame DT in the first mode is different from that in the second mode, the bias signal V3 for writing data frame DT in the first mode N1 and the bias signal V4 for writing data frame DT in the second mode N2 can be set to different values ​​to adjust the bias of the driving transistor in different modes, so that the bias of the driving transistor M1 in the light emission stage T2 in different modes can be kept consistent.

[0077] Optional, Figure 5 This is another driving timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention. Figure 6 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figure 1 , Figure 2 ,as well as Figures 4 to 6 When a frame of the display panel 10 includes at least one hold frame HT, in the first mode, the length of the offset maintenance phase in the hold frame is t12; in the second mode, the length of the offset maintenance phase in the hold frame is t22; wherein, t12>t22.

[0078] It should be noted that, Figure 5 and Figure 6 The example shown only illustrates that the time for one frame of the display panel 10 includes one hold frame HT. However, in this embodiment of the invention, the number of hold frames within the time of one frame of the display panel 10 can be any non-negative integer. It is understood that the number of hold frames within the time it takes for the display panel to display one frame is related to the ratio between the display refresh rate and the base refresh rate; for example, when the display refresh rate is 1 / 2 times the base refresh rate, the number of hold frames within the time of one frame is 1; while when the display refresh rate is 1 / 3 times the base refresh rate, the number of hold frames within the time of one frame is 2. For ease of description, this embodiment of the invention uses the time of one frame, including one data write frame and one hold frame HT, as an example to illustrate the technical solution of this embodiment.

[0079] Continue to refer to Figure 1 , Figure 2 ,as well as Figures 4 to 6When a frame of the display panel 10 includes a data write frame DT and a hold frame HT, and the non-light-emitting phase T12 of the hold frame HT is also the first non-light-emitting phase, the first non-light-emitting phase T12 of the hold frame DT includes a bias phase Tb22. During this bias phase T22, the data write module 12 can also provide a bias signal Vobs to the source / drain of the driving transistor M1 to adjust the bias of the driving transistor M1. Simultaneously, since there is at least one light-emitting phase T2 before the first non-light-emitting phase T12 of the hold frame HT, the bias signal Vobs provided to the driving transistor M1 during the bias phase Tb22 of the hold frame HT can adjust the bias generated by the driving transistor M1 in the light-emitting phase T2 preceding the hold frame HT.

[0080] Understandably, when the driving transistor M1 is a PMOS transistor, during the light-emitting phase T2, the gate voltage of the driving transistor M1 will be less than its source voltage (PVDD), resulting in a negative voltage difference between the gate and source of the driving transistor M1. Simultaneously, because the brightness of the display panel in the first mode N1 is greater than that in the second mode N2, the voltage of the data signal Vdata at the gate of the driving transistor M1 during the light-emitting phase T2 in the first mode N1 is greater than that in the second mode N2. Furthermore, the data... The voltage of signal Vdata is usually positive, which makes the absolute value of the voltage difference between the gate and the source of driving transistor M1 in the light emission stage T2 under the first mode N1 greater than the absolute value of the voltage difference between the gate and the source of driving transistor M1 in the light emission stage T under the second mode N2. As a result, the degree of ion polarization inside driving transistor M1 is higher after the light emission stage T2 under the first mode N1, while the degree of ion polarization inside driving transistor M1 is lower after the light emission stage T2 under the second mode N2. This results in driving transistor M1 being in different bias states after the light emission stage T2 under different modes. At this time, by setting the bias maintenance phase Tc12 in the hold frame HT under the first mode N1 to a longer time and the bias maintenance phase Tc22 in the hold frame HT under the second mode N2 to a shorter time, the ion polarization degree inside the driving transistor M1 is higher in the bias maintenance phase Tc12 of the hold frame HT under the first mode N1, and the ion polarization degree inside the driving transistor M1 is lower in the bias maintenance phase Tc22 of the hold frame HT under the second mode N2. This balances the bias degree of the driving transistor M1 in the light emission phase T2 of the hold frame HT, so that the bias state of the driving transistor M1 can remain consistent when the next light emission phase T22 arrives in different modes. This helps to improve the display uniformity of the display panel in different modes and ensures that the display panel can accurately present the corresponding display brightness.

[0081] In an optional embodiment, the bias signal Vobs provided by the data writing module 12 of each pixel circuit 100 to its driving transistor M1 in the hold frame HT can also be the same or different. That is, the voltage of the bias signal Vobs in the hold frame HT can be a fixed value or a non-fixed value, which can be set according to actual needs. This embodiment of the invention does not impose any specific limitation on this. When the voltage of the bias signal Vobs in the hold frame HT is a fixed value, there is no need to frequently adjust the voltage of the bias signal in the hold frame, avoiding additional power consumption caused by voltage fluctuations on the signal line transmitting the bias signal Vobs, thereby contributing to the low power consumption of the display panel.

[0082] In other alternative embodiments, when the bias signal of the hold frame is V3 in the first mode N1 and the bias signal of the hold frame is V4 in the second mode N2, V4 ≠ V3.

[0083] Specifically, since the gate voltage of the driving transistor M1 during the hold frame HT in the first mode is different from that during the hold frame HT in the second mode, the bias signal V3 of the hold frame in the first mode N1 and the bias signal V4 of the hold frame in the second mode N2 can be set to different values ​​to adjust the bias of the driving transistor in different modes, so that the bias of the driving transistor M1 in the light emission stage T2 in different modes can be kept consistent.

[0084] In another optional embodiment, since providing a bias signal to the source / drain of the driving transistor M1 in the data write frame DH can cancel or weaken the bias caused by writing a data signal to the gate of the driving transistor M1; while providing a bias signal to the source / drain of the driving transistor M1 in the hold frame HT can adjust the bias of the driving transistor M1 in the light emission stage T21 before the hold frame HT; that is, the purpose of adjusting the bias of the driving transistor M1 in the data write frame DT and the hold frame HT is different; therefore, the voltage Vobs of the bias signal provided to the driving transistor M1 can be adaptively adjusted according to the purpose of bias adjustment, so that the voltage of the bias signal Vobs in the hold frame HT is not equal to the voltage of the bias signal in the data write frame DT.

[0085] In other alternative embodiments, the voltage of the bias signal Vobs in frame HT can be equal to the voltage of the bias signal in data writing frame DT to meet special display driving requirements. As long as the bias adjustment of the driving transistor M1 can be achieved, the embodiments of the present invention do not impose specific limitations on this.

[0086] Optional, see reference Figure 1 , Figure 2 ,as well as Figures 4 to 6 When a frame of the display panel 10 includes both a data write frame DH and a hold frame HT, t11 = t12 and / or t21 = t22 can be made. Thus, in the same mode, the bias sustaining phase Tc of the data write frame DH has the same length as the bias sustaining phase in the hold frame HT. That is, in different frames (data write frame, hold frame) of the same mode, the time between the start time of the bias phase Tb and the start time of the first light emission phase T2 is the same. Therefore, when the display panel displays a frame, there is no need to adjust the relative time of the start time of the bias phase Tb, which simplifies the driving timing of the display panel 10, reduces the computational power of the driver chip used to drive the display panel 10, and consequently reduces the cost of the display panel 10.

[0087] It is understood that the above description is merely exemplified by using the example that the length t11 of the bias maintenance phase Tc11 of the data write frame DT in the first mode N1 is the same as the length t12 of the bias maintenance phase Tc12 of the hold frame HT, and the length t21 of the bias maintenance phase Tc21 of the data write frame DT in the second mode N2 is the same as the length t22 of the bias maintenance phase Tc22 of the hold frame HT. In other embodiments of the present invention, in the same mode, the relationship between the length of the bias maintenance phase of the data write frame DT and the length of the bias maintenance phase of the hold frame HT can be set as needed, and the embodiments of the present invention do not specifically limit this.

[0088] In an alternative embodiment, Figure 7 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention. Figure 8 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figure 1 , Figure 2 , Figure 4 ,as well as Figures 7 to 8 When a frame of the display panel includes both the data write frame DH and the hold frame HT, t11≠t12 and t21≠t22 can be made so that, in the same mode, the length of the bias hold phase of the data write frame DT is different from the length of the bias hold phase of the hold frame HT.

[0089] Specifically, in the data write frame DH, the length of the bias sustaining phase Tc11 / Tc21 can be set according to the voltage of the data signal written to the gate of the driving transistor M1 during the data write phase Ta, in order to balance the bias caused by the written data signal. In the hold frame HT, the length of the bias sustaining phase Tc12 / Tc22 is set according to the bias of the driving transistor during the light emission phase T21 preceding the hold frame HT, so that the driving transistor M1 can accurately provide the driving current in the next light emission phase T22. Thus, the degree of bias adjustment of the driving transistor M1 during the bias sustaining phase Tc of the data write frame DT and the hold frame HT is somewhat different. Therefore, the lengths of the bias sustaining phase Tc of the data write frame DT and the hold frame HT can be specifically set to ensure that the bias of the driving transistor M1 remains consistent in each light emission phase T2, ensuring that the driving current generated by the driving transistor M1 remains consistent in each light emission phase T2 of the same frame, thereby improving the display uniformity of the display panel.

[0090] In other optional embodiments, the length t11 of the bias maintenance phase Tc11 of the data write frame DT in the first mode N1 may be the same as the length t12 of the bias maintenance phase Tc12 of the hold frame HT, while the length t21 of the bias maintenance phase Tc21 of the data write frame DT in the second mode N2 may be different from the length t22 of the bias maintenance phase Tc22 of the hold frame HT, i.e., t11 = t12 and t21 ≠ t22; or, the length t21 of the bias maintenance phase Tc21 of the data write frame DT in the second mode N2 may be the same as the length t22 of the bias maintenance phase Tc22 of the hold frame HT, while the length t11 of the bias maintenance phase Tc11 of the data write frame DT in the first mode N1 may be different from the length t12 of the bias maintenance phase Tc12 of the hold frame HT, i.e., t11 ≠ t12 and t21 = t22. Under the premise of achieving the core inventive points of the embodiments of the present invention, the embodiments of the present invention address each mode.

[0091] It is understood that the above-described driving timing diagrams are merely exemplary timing diagrams for embodiments of the present invention. Each timing diagram shows that the number of bias stages Tb included in the data write frame DT and the hold frame HT is the same, and is 1 in each case. In other embodiments of the present invention, the data write frame DT and the hold frame HT may also include multiple bias stages Tb. Furthermore, the number of bias stages Tb in the data write frame DT and the hold frame HT may be the same or different, and can be set according to actual needs. The embodiments of the present invention do not impose specific limitations on this.

[0092] In one exemplary embodiment, Figure 9 Is with Figure 2 A corresponding timing diagram for driving the pixel circuit in a display panel, in conjunction with a reference. Figure 2 and Figure 9 When the write transistor M2 provides the data signal Vdata during the data writing phase Ta and the bias signal Vobs during the bias phase Tb, in the data writing frame DH, the scan signal SP used to control the conduction of the write transistor M2 includes two valid pulses. The duration of one valid pulse is the data writing phase Ta, and the duration of the other valid pulse is the bias phase Tb11 / Tb21. The duration from the start of the data writing phase Ta to the next light-emitting phase T21 is t01. In the holding frame HT, the scan signal SP used to control the conduction of the write transistor M2 can also include two valid pulses, both of which are during the bias phase. Tb12 / Tb22 makes the hold frame HT include two bias stages Tb12 / Tb22. The duration from the start time of the first bias stage Tb12 / Tb22 to the start time of the next light emission stage T21 is t02, where t01 can be equal to t02. Thus, the number of bias stages Tb in the data write frame DT and the hold frame HT are different, while the number of effective pulses of the scan signal SP in the data write frame DT and the hold frame HT are the same, and the relative time of the start time of the effective pulses is the same. This allows the control logic used to provide the scan signal SP in the data write frame DT and the hold frame HT to be the same, which helps to simplify the control method of the display panel.

[0093] It is understood that when the first non-light-emitting stage T11 includes both the data writing stage Ta and the bias stage Tb, the interval between the data writing stage Ta and the bias stage Tb can be a fixed value. Alternatively, the interval between the data writing stage Ta and the bias stage Tb can be different in different modes. The specific implementation method can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0094] Optional, see reference Figure 2 and Figure 7 or Figure 4 and Figure 8 When the first non-light-emitting stage T11 also includes the data writing stage Ta, if the time interval between the start time of the data writing stage Ta and the start time of the bias stage Tb in the first non-light-emitting stage T11 is the third time interval Tg, then the length of the third time interval Tg1 under the first mode N1 is different from the length of the third time interval Tg2 under the second mode N2.

[0095] Specifically, when entering the data writing stage Ta, the data signal Vdata is provided to the source of the driving transistor M1 through the data writing module 12, transmitted to its drain through the driving transistor M1, and transmitted to the gate of the driving transistor M1 through the compensation module 13. This causes the voltages of the source, drain, and gate of the driving transistor M1 to begin to approach the voltage of the data signal Vdata. At this time, the data signal Vdata provided to the source, drain, and gate of the driving transistor M1 can be used to adjust the bias of the driving transistor M1. Meanwhile, before the signal is provided to the source, drain, and gate of the driving transistor M1, the source, drain, and gate of the driving transistor M1 will remain at the voltages during the data writing stage Ta. That is, during the third time period Tg between the start of the data writing stage Ta and the start of the bias stage Tb, the source, drain, and gate of the driving transistor M1 will remain at the voltages during the data writing stage Ta. Meanwhile, because the brightness of the display panel differs between the first mode N1 and the second mode N2, the data signal Vdata provided to the driving transistor M1 is different. This results in a difference in the degree of bias adjustment of the driving transistor M1 using the data signal Vdata provided to it in the first mode compared to the degree of bias adjustment in the second mode N2. Therefore, the third time period Tg1 in the first mode N1 can be different from the third time period Tg2 in the second mode N2. The duration for bias adjustment of the driving transistor M1 in mode N2 is different from the duration for bias adjustment using the data signal Vdata in mode N2. This results in different bias degrees for the driving transistor M1 in different modes due to the different durations for bias adjustment using the data signal Vdata. This can balance at least part of the bias caused by the different data signals Vdata written to the source, drain, and gate of the driving transistor M1. As a result, when entering the first light emission stage T21 of different modes, the consistency of the bias state of the driving transistor M1 can be improved, which in turn helps to improve the display uniformity of the display panel in different modes.

[0096] In an alternative embodiment, reference continues. Figure 2 and Figure 7 or Figure 4 and Figure 8, when the display brightness of the display panel in the first mode N1 is greater than the display brightness of the display panel in the second mode N2, if in the first mode N1, the length of the third time period Tg1 is t32, and in the second mode N2, the length of the third time period Tg2 is t42, then t32 < t42. At this time, in the first mode N1, the duration for the source, drain, and gate of the driving transistor M1 to approach the data signal Vdata is shorter, and in the second mode N1, the duration for the source, drain, and gate of the driving transistor M1 to approach the data signal Vdata is longer, so as to balance the biasing conditions of the driving transistor M1 in the first mode N1 and in the second mode N2 due to the lower voltage of the driving signal Vdata provided to the driving transistor M1 in the first mode N1 and the higher voltage of the driving signal Vdata provided to the driving transistor M1 in the second mode N2. Thus, at the starting moment of the biasing stage Tb, the biasing conditions of the driving transistor M1 in different modes can tend to be the same.

[0097] Optionally, continue to refer to FIG. Figure 2 and Figure 7 or Figure 4 and Figure 8 , if in the first mode N1, the length of the bias maintenance stage Tc11 is t10, and in the second mode N2, the length of the bias maintenance stage Tc21 is t20, then t10 + t32 = t20 + t42. At this time, the duration between the starting moment of the data writing stage Ta and the starting moment of the first light emitting stage T21 in the first mode N1 is the same as the duration between the starting moment of the data writing stage Ta and the starting moment of the first light emitting stage T21 in the second mode N2. Thus, it can be ensured that the duration for the gate of the driving transistor M1 to be the data signal in different modes is the same, and by setting the durations for the source / drain of the driving transistor M1 to maintain different voltages differently during this period, it can be ensured that the biasing conditions of the driving transistor M1 can remain the same when entering the first light emitting stage T21 in different modes, which is beneficial to improving the display uniformity of the display panel in different modes.

[0098] In other embodiments, Figure 10 is another driving timing diagram of the pixel circuit in the display panel provided by the embodiment of the present invention. Figure 11 is another driving timing diagram of the pixel circuit in the display panel provided by the embodiment of the present invention. Refer to Figure 2 and Figure 10 or Figure 4 and Figure 11When the first non-light-emitting stage T11 includes the data writing stage Ta, and the time interval between the start time of the data writing stage Ta and the start time of the bias stage Tb in the first non-light-emitting stage T11 is the third time interval Tg, if the length of the third time interval Tg1 under the first mode N1 is t30 and the length of the third time interval Tg2 under the second mode N2 is t40, then t30 = t40.

[0099] Thus, the duration for the signals at the gate, source, and drain of the driving transistor M1 in the first mode N1 to converge to the data signal Vdata is the same as the duration for the signals at the gate, source, and drain of the driving transistor M1 in the second mode N2 to converge to the data signal Vdata. This makes the bias of the driving transistor M1 in the bias stage Tb11 of the first mode N1 different from the bias of the driving transistor M1 in the bias stage Tb21 of the second mode N2. Subsequently, the bias of the driving transistor M1 can be adjusted to different degrees through the bias maintenance stage Tc11 in the first mode N1 and the bias maintenance stage Tc12 in the second mode N1, so that the bias of the driving transistor M1 can remain consistent when entering the first light emission stage T21 of different modes, thereby improving the display uniformity of the display panel in different modes.

[0100] It is understandable that, since the duration of the bias sustaining phase Tc11 under the first mode N1 is different from that under the second mode N1, when the length of the third time period Tg1 under the first mode N1 is the same as that under the second mode N2, the duration between the start time of the data writing phase Ta and the start time of the first light emission phase T21 under the first mode N1 will be different from that under the first mode N1. In this case, the bias of the driving transistor M1 can be adjusted based on this to meet the requirements of display uniformity.

[0101] Optional, continue to refer to Figure 2 and Figure 10 or Figure 4 and Figure 11 When the first non-light-emitting stage T11 includes the data writing stage Ta, and the time from the start of the data writing stage Ta to the start of the first light-emitting stage T21 is the first time period Te, the length of the first time period Te1 under the first mode N1 is different from the length of the first time period Te2 under the second mode N2. That is, the duration for which the gate of the driving transistor M1 remains as the data signal Vdata under the first mode N1 is different from that under the second mode N2.

[0102] Specifically, when entering the data writing stage Ta, the data signal Vdata is provided to the source of the driving transistor M1 through the data writing module 12, transmitted to its drain through the driving transistor M1, and transmitted to its gate through the compensation module 13. This causes the voltages at the source, drain, and gate of the driving transistor M1 to approach the voltage of the data signal Vdata. At this time, the data signal Vdata provided to the source, drain, and gate of the driving transistor M1 can be used to adjust the bias of the driving transistor M1. Simultaneously, because the brightness of the display panel differs between the first mode N1 and the second mode N2, the data signal Vdata provided to the driving transistor M1 is different. This allows for bias adjustment of the driving transistor M1 using the data signal Vdata provided to it in the first mode. The degree of bias adjustment of the driving transistor M1 using the data signal Vdata provided to the driving transistor M1 in the first mode differs from that in the second mode. In this case, the first time period Te1 in the first mode can be different from the first time period Te2 in the second mode. That is, the duration of the gate of the driving transistor M1 being a data signal in the first mode is different from that in the second mode. This makes the duration of bias adjustment of the driving transistor M1 using the data signal in different modes different, resulting in different bias degrees. This can balance the bias caused by the different data signals written to the gate of the driving transistor M1, so that the bias state of the driving transistor M1 can remain consistent when entering the first light emission stage T21 of different modes, thereby improving the display uniformity of the display panel in different modes.

[0103] Understandably, this embodiment of the invention does not specifically limit the display brightness of the display panel in the first mode and the duration of the first time period in the second mode, or the duration of the first time period in the first mode and the second mode, under the premise of balancing the bias caused by the different data signals by setting the duration of the first time period in the first mode and the duration of the first time period in the second mode.

[0104] In an alternative embodiment, reference continues. Figure 2 and Figure 10 or Figure 4 and Figure 11 When the display brightness of the display panel in the first mode N1 is greater than that in the second mode N2, if the length of the first time period Te1 in the first mode N1 is t30 and the length of the first time period Te2 in the second mode N2 is t40, then t30 > t40. That is, the time for biasing the driving transistor M1 using data signals is longer in the first mode, while the time for biasing the driving transistor M1 using data signals is shorter in the second mode.

[0105] Specifically, taking the driving transistor M1 as a PMOS as an example, when the luminous brightness level of the light-emitting element 200 is Q, the voltage V1 of the data signal Vdata in the first mode N1 will be less than the voltage V2 of the data signal Vdata in the second mode N1. This results in a smaller degree of ion polarization inside the driving transistor M1 due to the provision of the data signal Vdata to the driving transistor M1 in the first mode N1, while a larger degree of ion polarization inside the driving transistor M1 due to the provision of the data signal Vdata to the driving transistor M1 in the second mode N2. At this time, by setting the first time period Te1 under the first mode N1 to a longer time, the driving transistor M1 has a longer bias time under the action of the data signal Vdata, while the first time period Te2 under the second mode N2 is set to a shorter time, the driving transistor M1 has a shorter bias time under the action of the data signal Vdata. This balances the different degrees of bias caused by the different data signals Vdata provided to the driving transistor M1 under the first and second modes, so that the bias of the driving transistor M1 can remain consistent when entering the first light emission stage T21 of different modes, thereby improving the display uniformity of the display panel under different modes.

[0106] Optional, continue to refer to Figure 2 and Figure 10 or Figure 4 and Figure 11 The time interval Tf is the second time interval from the start time of the first non-light-emitting stage T11 to the start time of the data writing stage Ta. The length of the second time interval Tf1 under the first mode N1 is t31, and the length of the second time interval Tf2 under the second mode is t32. Wherein, t31 < t41.

[0107] Specifically, since the length t31 of the second time period Tf1 in the first mode N1 is less than the length t33 of the second time period Tf2 in the second mode, after entering the first non-light-emitting stage T11 of the first mode N1, the data writing stage Ta can be entered in a short time, providing the data signal Vdata to the driving transistor M1. However, after entering the first non-light-emitting stage T11 of the second mode N2, the data writing stage Ta is entered after a longer time, providing the data signal Vdata to the driving transistor M1. Simultaneously, after providing the data signal Vdata to the driving transistor M1, before entering the first light-emitting stage T21, the driving transistor M1 can continuously maintain the data signal Vdata, allowing the bias adjustment of the driving transistor M1 to be performed using this data signal Vdata. That is, the bias adjustment of the driving transistor M1 is performed using the data signal Vdata in the first time period Te. Thus, t31 < t41, ensuring that t30 > t40, guaranteeing that the duration of the first time period in the first mode is greater than the duration in the second mode, satisfying the bias adjustment requirements of the driving transistor M1 in different modes.

[0108] In an optional embodiment, when the length t30 of the first time period Te1 under the first mode N1 is greater than the length t40 of the first time period Te2 under the second mode N2, and the length t31 of the second time period Tf1 under the first mode N1 is less than the length t32 of the second time period Tf2 under the second mode, t30 + t31 = t40 + t41 can be made. In this case, the duration between the start time of the first non-light-emitting stage T11 and the start time of the first light-emitting stage T21 is the same in both the first and second modes. This ensures that the length of the first non-light-emitting stage T11 under the first mode N1 is the same as the length of the first non-light-emitting stage T11 under the second mode N2, thereby maintaining a sufficiently long light-emitting stage T2 in different modes. This, in turn, helps to improve the overall display brightness of the display panel and enhance its display effect.

[0109] Where t30+t31=t40+t41, and the length of the first time period Te under the first mode N1 is different from the length of the first time period Te under the second mode N2, the data writing stage Ta under the second mode N2 can be shifted compared to the data writing stage Ta under the first mode N1; or, as Figure 12 or Figure 13 As shown, when t30+t31=t40+t41, and the length of the first time period Te under the first mode N1 is different from the length of the first time period Te under the second mode N2, the non-luminescent stage T11 under the second mode N2 can be shifted compared to the non-luminescent stage T11 under the first mode N1. Under the premise of achieving the core inventive points of this embodiment, this embodiment does not limit the specific timing settings.

[0110] In other alternative embodiments, such as Figure 14 or Figure 15 When the length of the first time period Te under the first mode N1 is different from the length of the first time period Te under the second mode N2, the duration of the non-light-emitting stage T111 under the first mode N1 can also be different from the duration of the non-light-emitting stage T112 under the second mode N2, so as to further adjust the display brightness of the display panel and enable the display panel to have a more refined brightness adjustment method.

[0111] Optionally, the operating modes of the display panel may also include a third mode and a fourth mode; the display brightness of the display panel in the first mode and the display brightness of the display panel in the second mode are both greater than the display brightness of the display panel in the third mode and the display brightness of the display panel in the fourth mode; the display brightness of the display panel in the third mode is different from the display brightness of the display panel in the fourth mode; the length of the first non-light-emitting stage in the third mode is different from the length of the first non-light-emitting stage in the fourth mode.

[0112] It is understandable that by making the grayscale and brightness of the light-emitting element different in different modes, the display panel can have different brightness in different modes; or, by setting the duration of the light-emitting phase in different modes to different values, the integral value of the human eye on the brightness can be different, which can also achieve the adjustment of the display brightness in different modes. Since the duration of a frame phase (such as a data writing frame or a holding frame) is usually a fixed value, that is, the total duration of a light-emitting phase and a non-light-emitting phase is a fixed value, adjusting the duration of the light-emitting phase is equivalent to adjusting the duration of the non-light-emitting phase.

[0113] At this time, when the display brightness of the display panel is in a low brightness range, the brightness of the display panel can be adjusted by adjusting the duration of the non-light-emitting phase in different modes. This allows the display panel to have different durations of the non-light-emitting phase in the third and fourth modes with lower brightness. At this time, the third and fourth modes can have the same grayscale and data signal correspondence.

[0114] Optionally, since the display brightness is low in the third and fourth modes and the correspondence between grayscale and data signal is the same, the bias caused by data signal is similar in the third and fourth modes. In this case, the length of the bias maintenance phase in the third mode can be set to be equal to the length of the bias maintenance phase in the fourth mode. Thus, in the low brightness range, there is no need to change the length of the bias maintenance phase in each mode, which helps to simplify the driving method of the display panel.

[0115] In another optional embodiment, the operating modes of the display panel may further include a fifth mode and a sixth mode, wherein the display brightness of the display panel in the first mode and the display brightness of the display panel in the second mode are both less than the display brightness of the display panel in the fifth mode and the display brightness of the display panel in the sixth mode; the display brightness of the display panel in the fifth mode is different from the display brightness of the display panel in the sixth mode; the length of the first non-emitting phase in the fifth mode is the same as the length of the first non-emitting phase in the sixth mode; and the length of the bias maintenance phase in the fifth mode is equal to the length of the bias maintenance phase in the sixth mode.

[0116] Specifically, because the brightness of the display panel in modes five and six is ​​higher than that in modes one and two, the display panel's brightness falls within a higher brightness range in both modes. Within this range, the brightness adjustment method can be the same as in modes one and two; that is, the grayscale correspondence between modes five and six differs, while the duration of the non-emissive phase can be the same. Furthermore, due to the higher brightness in modes five and six, slight fluctuations in brightness within this range are less noticeable to the human eye. Therefore, modes five and six can have the same bias maintenance phase length, eliminating the need to change the bias maintenance phase length in higher brightness ranges and simplifying the display panel's driving mechanism.

[0117] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 16 This is a schematic diagram of a display device according to an embodiment of the present invention. The display device includes any of the display panels provided in the above embodiments. For example, refer to... Figure 16 The display device 1 includes a display panel 10. Therefore, the display device also has the beneficial effects of the display panel and array substrate in the above embodiments. The similarities can be understood with reference to the explanation of the display panel and array substrate above, and will not be repeated below.

[0118] The display device 1 provided in this embodiment of the invention can be Figure 16 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0119] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a data writing module; the driving module includes a driving transistor; The operation of the pixel circuit includes a data writing stage and a bias stage; in the data writing stage, the data writing module provides a data signal; in the bias stage, the data writing module provides a bias signal. The driving transistor is used to selectively provide driving current to the light-emitting element; The pixel circuit operation process includes a first light-emitting stage and a first non-light-emitting stage; During the first non-luminescent phase, the period from the start of the bias phase to the start of the first luminescent phase is the bias maintenance phase. The display panel has two operating modes: a first mode and a second mode. The display brightness of the display panel in the first mode is different from that in the second mode. The length of the bias maintenance phase in the first mode is different from the length of the bias maintenance phase in the second mode; The display panel must satisfy at least one of the following: In the first mode, the brightness of the display panel is greater than that in the second mode; in the first mode, the length of the bias maintenance phase is t10; in the second mode, the length of the bias maintenance phase is t20; wherein, t10>t20; or, The first non-light-emitting stage includes a data writing stage. During the first non-light-emitting stage, the time from the start of the data writing stage to the start of the first light-emitting stage is a first time period. The length of the first time period in the first mode is different from the length of the first time period in the second mode. or, The first non-light-emitting phase includes the data writing phase; in the first non-light-emitting phase, the time period between the start time of the data writing phase and the start time of the bias phase is a third time period; the length of the third time period in the first mode is different from the length of the third time period in the second mode.

2. The display panel according to claim 1, characterized in that, The display brightness of the display panel in the first mode is greater than that in the second mode; One frame of the display panel includes a data write frame; In the first mode, the length of the bias maintenance phase in the data write frame is t11; in the second mode, the length of the bias maintenance phase in the data write frame is t21; wherein, t11>t21.

3. The display panel according to claim 2, characterized in that, The display panel's frame time also includes at least one hold frame; In the first mode, the length of the offset maintenance phase in the hold frame is t12; in the second mode, the length of the offset maintenance phase in the hold frame is t22; wherein, t12>t22.

4. The display panel according to claim 3, characterized in that, t11≠t12 and / or t21≠t22.

5. The display panel according to claim 3, characterized in that, t11=t12 and / or t21=t22.

6. The display panel according to claim 3, characterized in that, In the hold frame, the voltage of the bias signal is a fixed value; and / or, in the data write frame, the voltage of the bias signal is a fixed value.

7. The display panel according to claim 6, characterized in that, The voltage of the bias signal in the hold frame is not equal to the voltage of the bias signal in the data write frame.

8. The display panel according to claim 3, characterized in that, In the first mode, the bias signal for the data write frame is V1, and in the second mode, the bias signal for the data write frame is V2, where V2 ≠ V1; and / or, in the first mode, the bias signal for the hold frame is V3, and in the second mode, the bias signal for the hold frame is V4, where V4 ≠ V3.

9. The display panel according to claim 1, characterized in that, The data writing module includes a first transistor and a second transistor; The gate of the first transistor receives a first scan signal, the first electrode of the first transistor receives the data signal, and the second electrode of the first transistor is electrically connected to the driving module; during the data writing phase, the first scan signal controls the first transistor to turn on. The gate of the second transistor receives the second scan signal, the first terminal of the second transistor receives the bias signal, and the second terminal of the second transistor is electrically connected to the driving module; during the bias phase, the second scan signal controls the second transistor to turn on.

10. The display panel according to claim 1, characterized in that, Also includes: The first signal line; the data writing module includes a writing transistor; the gate of the writing transistor receives a scan signal, the first terminal of the writing transistor is electrically connected to the first signal line, and the second terminal of the writing transistor is electrically connected to the driving module; During the data writing phase, the scan signal controls the writing transistor to turn on, and the first signal line transmits the data signal. During the bias phase, the scan signal controls the write transistor to turn on, and the first signal line transmits the bias signal.

11. The display panel according to claim 1, characterized in that, The display brightness of the display panel in the first mode is greater than the brightness of the display panel in the second mode; When the first non-light-emitting stage includes a data writing stage, and the time from the start of the data writing stage to the start of the first light-emitting stage is a first time period, the length of the first time period in the first mode is t30, and the length of the first time period in the second mode is t40; wherein, t30 > t40.

12. The display panel according to claim 11, characterized in that, The second time period is from the start time of the first non-light-emitting stage to the start time of the data writing stage. In the first mode, the length of the second time period is t31, and in the second mode, the length of the second time period is t32; where t31 < t41.

13. The display panel according to claim 12, characterized in that, t30+t31=t40+t41.

14. The display panel according to claim 1, characterized in that, The display brightness of the display panel in the first mode is greater than that in the second mode; When the first non-light-emitting phase includes the data writing phase, and the time interval between the start time of the data writing phase and the start time of the bias phase in the first non-light-emitting phase is a third time interval, in the first mode, the length of the third time interval is t32; in the second mode, the length of the third time interval is t42; wherein, t32 <t42。 15. The display panel according to claim 14, characterized in that, In the first mode, the length of the bias maintenance phase is t10; in the second mode, the length of the bias maintenance phase is t20; wherein, t10+t32=t20+t42.

16. The display panel according to claim 1, characterized in that, The first non-light-emitting phase includes the data writing phase; in the first non-light-emitting phase, the time period between the start time of the data writing phase and the start time of the bias phase is a third time period; When t10>t20, or when the length of the first time period in the first mode is different from the length of the first time period in the second mode, the length of the third time period in the first mode is t30; the length of the third time period in the second mode is t40; where t30=t40.

17. The display panel according to claim 1, characterized in that, In the first mode, the length of the first non-luminescent phase is the same as the length of the first non-luminescent phase in the second mode.

18. The display panel according to claim 17, characterized in that, The display panel's operating modes also include a third mode and a fourth mode; the display brightness of the display panel in the first mode and the display brightness of the display panel in the second mode are both greater than the display brightness of the display panel in the third mode and the display brightness of the display panel in the fourth mode; the display brightness of the display panel in the third mode is different from the display brightness of the display panel in the fourth mode; The length of the first non-luminescent phase in the third mode is different from the length of the first non-luminescent phase in the fourth mode.

19. The display panel according to claim 18, characterized in that, The length of the bias maintenance phase in the third mode is equal to the length of the bias maintenance phase in the fourth mode.

20. The display panel according to claim 17, characterized in that, The display panel's operating modes also include a fifth mode and a sixth mode; the display brightness of the display panel in the first mode and the display brightness of the display panel in the second mode are both less than the display brightness of the display panel in the fifth mode and the display brightness of the display panel in the sixth mode; the display brightness of the display panel in the fifth mode is different from the display brightness of the display panel in the sixth mode; The length of the first non-emitting phase in the fifth mode is the same as the length of the first non-emitting phase in the sixth mode, and the length of the bias maintenance phase in the fifth mode is equal to the length of the bias maintenance phase in the sixth mode.

21. A display device, characterized in that, include: The display panel according to any one of claims 1-20.

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