PCIE SSD data migration method, system, device and storage medium

Through the Host master control system and the HMB cache system working together, data migration is bypassed by the CPU of the SSD disk, solving the complex problem of data migration based on PCIE bus of the SSD hard disk, and simplified data migration and reduced CPU load are achieved.

CN115774521BActive Publication Date: 2025-08-26CHANGSHA ZHICUN TECH CO LTD
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Patent Information

Application Number
CN202211544548.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-12-02
Publication Date
2025-08-26
Estimated Expiration
2042-12-02

AI Technical Summary

Technical Problem

In the prior art, the data migration process of SSD hard disks based on PCIE bus is too complicated and uses too much data, resulting in an increase in system load.

Method used

The data address is sent to the HMB cache system through the Host master control system. The HMB cache system captures the target data and sends a write modification command to the target migration system. The target migration system modifys the queue permission information and registers, obtains the target data from the HMB cache system, and bypasses the CPU of the SSD disk for data migration.

Benefits of technology

It reduces the load on the CPU, realizes in-band data transmission, simplifies the data migration process within the PCIE bus, and is suitable for data migration and backup of enterprise-level servers.

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Abstract

The present invention relates to the field of hard disk data migration, and discloses a data migration method, system, device, and storage medium for PCIE SSD. The method comprises: a host control system sends a data address to an HMB cache system; the HMB cache system receives the data address and captures target data corresponding to the source data address from the data source system; a write modification command is sent to a target migration system; the target migration system receives the write modification command, modifies preset target write queue permission information and a register value, and obtains new target write queue permission information and a new register value; and obtains target data from the HMB cache system based on the new target write queue permission information and the new register value. The present invention is conducive to reducing the load on the CPU. The system cluster of PCIE SSD can realize in-band data transmission, i.e., in-band management is very important in the application of enterprise-level servers. After the service life expires, the data can be migrated to a new disk, data backup, and multi-hotspot data management can be achieved.
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Description

Technical Field

[0001] The present invention relates to the field of hard disk data migration, and in particular to a PCIE SSD data migration method, system, device and storage medium. Background Art

[0002] In the prior art, different devices bypass the host controller through routing via the PCIE bus protocol, find other SSD hard drives in the PCIE bus, and then transmit related data through the PCIE bus. However, this method is relatively complicated and the PCIE bus schedules too much data.

[0003] Therefore, to address the technical issues that the current internal scheduling of SSD hard drives based on PCIE bus data migration is too complex and uses too much data, a new SSD hard drive internal scheduling process is needed. Summary of the Invention

[0004] The main purpose of the present invention is to solve the technical problems that the internal scheduling of SSD hard disk based on PCIE bus data migration is too complicated and too much data is used.

[0005] A first aspect of the present invention provides a PCIE SSD data migration method, which is applied to a PCIE SSD data migration system. The PCIE SSD data migration system includes: a data source system, a target migration system, a host control system, and an HMB cache system. The PCIE SSD data migration method includes:

[0006] The Host control system sends a data address to the HMB cache system, wherein the data address includes: a source data address and a target migration address;

[0007] The HMB cache system receives the data address and fetches target data corresponding to the source data address from the data source system;

[0008] Sending a write modification command to the target migration system;

[0009] The target migration system receives the write modification command, and based on the write modification command, modifies the preset target write queue permission information and the register value to obtain new target write queue permission information and a new register value;

[0010] The target data is obtained from the HMB cache system according to the new target write queue permission information and the new register value.

[0011] Optionally, in a first implementation of the first aspect of the present invention, the source data address includes: a source write queue address and a source execution queue address.

[0012] Optionally, in a second implementation of the first aspect of the present invention, the target migration address includes: a target write queue address and a target execution queue address.

[0013] Optionally, in a third implementation of the first aspect of the present invention, the HMB cache system receiving the data address and fetching target data corresponding to the source data address from the data source system includes:

[0014] The HMB cache system receives the data address and fetches target data corresponding to the source data address from the data source system;

[0015] Based on the source write queue address and the source execute queue address, the source write queue and the source execute queue of the data source system are modified to obtain a new source write queue and a new source execute queue.

[0016] Optionally, in a fourth implementation of the first aspect of the present invention, obtaining the target data from the HMB cache system according to the new target write queue permission information and the new register value includes:

[0017] generating a data acquisition request according to the new target write queue permission information and the new register value, and sending the data acquisition request to the HMB cache system;

[0018] The HMB cache system receives the data acquisition request and sends the target data to the target migration system based on the data acquisition request.

[0019] Optionally, in a fifth implementation of the first aspect of the present invention, sending the target data to the target migration system based on the data acquisition request includes:

[0020] According to the data acquisition request, the target data is sent to the target migration system via the target write queue address.

[0021] Optionally, in a sixth implementation of the first aspect of the present invention, sending the target data to the target migration system includes:

[0022] The target data is transferred to a target write queue of the target migration system.

[0023] A second aspect of the present invention provides a PCIE SSD data migration system, the PCIE SSD data migration system comprising:

[0024] Data source system, target migration system, Host control system, HMB cache system;

[0025] The Host control system is configured to send a data address to the HMB cache system, wherein the data address includes: a source data address and a target migration address;

[0026] The HMB cache system is configured to receive the data address and fetch target data corresponding to the source data address from the data source system;

[0027] Sending a write modification command to the target migration system;

[0028] The target migration system is configured to receive the write modification command, and based on the write modification command, modify the preset target write queue permission information and the register value to obtain new target write queue permission information and a new register value;

[0029] The target data is obtained from the HMB cache system according to the new target write queue permission information and the new register value.

[0030] A third aspect of the present invention provides a PCIE SSD data migration device, comprising: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a line; the at least one processor calls the instructions in the memory so that the PCIE SSD data migration device executes the above-mentioned PCIE SSD data migration method.

[0031] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the above-mentioned PCIE SSD data migration method.

[0032] In an embodiment of the present invention, the Host control system informs the data source disk and the target migration disk of the address information of the Submission Queue (SQ) and Completion Queue (CQ) based on message transmission, and then uses the HMB cache system to move data. After the source data is moved to the HMB cache system, the SQ entry of the target migration disk is modified, and the number of registers (tailer) is modified at the same time. In this way, the CPU of the SSD disk is bypassed to realize data migration within the PCIE bus, which is beneficial to reducing the CPU load. The system cluster of PCIE SSD can realize in-band data transmission (in-band management), which is very important in the application of enterprise-level servers. After the service life expires, the data can be migrated to the new disk, data backup, multi-hotspot data management, etc., which solves the technical problems of SSD hard disk internal scheduling based on PCIE bus data migration being too complex and using too much data. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of a method for migrating data from a PCIE SSD according to an embodiment of the present invention;

[0034] Figure 2 FIG1 is a schematic diagram of another embodiment of a method for migrating data from a PCIE SSD according to an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of a PCIE SSD data migration system according to an embodiment of the present invention;

[0036] Figure 4 FIG. 1 is a schematic diagram of an embodiment of a PCIE SSD data migration device in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Embodiments of the present invention provide a PCIE SSD data migration method, system, device, and storage medium.

[0038] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0039] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 In one embodiment of a PCIE SSD data migration method according to an embodiment of the present invention, the PCIE SSD data migration method is applied to a PCIE SSD data migration system. The PCIE SSD data migration system includes: a data source system, a target migration system, a host control system, and an HMB cache system. The PCIE SSD data migration method includes:

[0040] 101. The Host control system sends a data address to the HMB cache system, where the data address includes: a source data address and a target migration address;

[0041] 102. The HMB cache system receives the data address and fetches the target data corresponding to the source data address from the data source system;

[0042] 103. Send a write modification command to the target migration system;

[0043] 104. The target migration system receives the write modification command and modifies the preset target write queue permission information and the register value based on the write modification command to obtain new target write queue permission information and a new register value.

[0044] 105. Obtain target data from the HMB cache system according to the new target write queue permission information and the new register value.

[0045] In steps 101-105, the Host control system sends the data address to the HMB cache system, notifying the HMB cache system of the source data address and the target migration address. The command sent by the Host control to the SSD is stored in the Submission Queue (SQ), and the SSD stores the status of the success or failure of the command execution in the Completion Queue (CQ). Because the sent command is in the Host control system Submission Queue (SQ), it is also necessary to write to the SSD's Doorbell Register (DB) for notification. After receiving the data address, the HMB cache system first obtains the target data to be migrated from the SSD disk of the data source system, and then the HMB cache system sends a write modification command to the target migration system. The write modification command is mainly used to modify the target write queue permission information (SQ entry) and register number (tailer) of the SSD disk of the target migration system. Then, the target migration system pulls the target data from the HMB cache system based on the new target write queue permission information (SQ entry) and register number (tailer). When the target write queue permission information (SQ entry) is confirmed, it enters the target write queue Submission Queue (SQ) and executes the acquisition of the target data. After completion, the register number (tailer) increases, and the completed task enters the queue of Completion Queue (CQ).

[0046] In an embodiment of the present invention, the Host control system informs the data source disk and the target migration disk of the address information of the Submission Queue (SQ) and Completion Queue (CQ) based on message transmission, and then uses the HMB cache system to move the data. After the source data is moved to the HMB cache system, the SQ entry of the target migration disk is modified, and the number of registers (tailer) is modified at the same time. In this way, the CPU of the SSD disk is bypassed to realize data migration within the PCIE bus, solving the technical problems of the SSD hard disk's internal scheduling based on the PCIE bus data migration being too complex and using too much data.

[0047] See also Figure 2 In another embodiment of the PCIE SSD data migration method according to the embodiment of the present invention, the PCIE SSD data migration method is applied to a PCIE SSD data migration system. The PCIE SSD data migration system includes: a data source system, a target migration system, a host control system, and an HMB cache system. The PCIE SSD data migration method includes:

[0048] 201. The Host control system sends a data address to the HMB cache system, wherein the data address includes: a source data address and a target migration address; the source data address includes: a source write queue address and a source execution queue address; and the target migration address includes: a target write queue address and a target execution queue address.

[0049] In this embodiment, the source data address includes the address of the source write queue (SQ) and the address of the source execution queue (CQ). The target migration address includes the address of the target write queue (SQ) and the address of the target execution queue (CQ). In other words, the SSDs of the data source system and the target migration system have SQ and CQ addresses, respectively. The host control system sends the data address to the HMB cache system, which then fetches the data.

[0050] 202. The HMB cache system receives the data address and fetches the target data corresponding to the source data address from the data source system;

[0051] 203. Based on the source write queue address and the source execution queue address, modify the source write queue and the source execution queue of the data source system to obtain a new source write queue and a new source execution queue;

[0052] In steps 202-203, the HMB cache system receives the data address, and while grabbing the target data from the data source system SSD disk, modifies the data of SQ and CQ in the data source system SSD disk according to the addresses of SQ and CQ to obtain new SQ and CQ.

[0053] 204. Send a write modification command to the target migration system;

[0054] 205. The target migration system receives the write modification command and modifies the preset target write queue permission information and the register value based on the write modification command to obtain new target write queue permission information and a new register value.

[0055] In steps 204-205, the HMB cache system writes the target write queue permission information SQ entry and the register value (tailer) of the target migration system SSD disk based on the write modification command to obtain a new SQ entry and register value (tailer).

[0056] 206. Generate a data acquisition request based on the new target write queue permission information and the new register value, and send the data acquisition request to the HMB cache system;

[0057] 207. The HMB cache system receives the data acquisition request and sends the target data to the target migration system based on the data acquisition request.

[0058] In steps 206-207, the target migration system obtains the target data from the HMB cache system based on the contents of the SQ entry and the register value (tailer), and pulls relevant information from the HMB cache system. That is, the target migration system and the HMB cache system transmit data based on the modified SQ entry and register value (tailer) to transfer the target data to the SSD disk in the target migration system.

[0059] Furthermore, in step 207, the following steps may be performed:

[0060] 2071. According to the data acquisition request, the target data is sent to the target migration system through the target write queue address.

[0061] In step 2071 , the data acquisition request triggers the sending program to write the target data into the SSD program of the target migration system based on the address of the target write queue SQ.

[0062] Among them, 2071 can perform the following steps:

[0063] 20711. Transfer the target data to the target write queue of the target migration system.

[0064] In step 20711, the name of the target data is written into the target write queue SQ, and then the existing program of the SSD disk obtains the target data based on the target write queue SQ.

[0065] In an embodiment of the present invention, the Host control system informs the data source disk and the target migration disk of the address information of the Submission Queue (SQ) and Completion Queue (CQ) based on message transmission, and then uses the HMB cache system to move data. After the source data is moved to the HMB cache system, the SQ entry of the target migration disk is modified, and the number of registers (tailer) is modified at the same time. In this way, the CPU of the SSD disk is bypassed to realize data migration within the PCIE bus, which is beneficial to reducing the CPU load. The system cluster of PCIE SSD can realize in-band data transmission (in-band management), which is very important in the application of enterprise-level servers. After the service life expires, the data can be migrated to the new disk, data backup, multi-hotspot data management, etc., which solves the technical problems of SSD hard disk internal scheduling based on PCIE bus data migration being too complex and using too much data.

[0066] The above describes the data migration method of the PCIE SSD in the embodiment of the present invention. The following describes the data migration system of the PCIE SSD in the embodiment of the present invention. Figure 3 In one embodiment of the present invention, a data migration system for a PCIE SSD includes:

[0067] Data source system 301, target migration system 302, host control system 303, HMB cache system 304;

[0068] The Host control system 303 is configured to send a data address to the HMB cache system, wherein the data address includes: a source data address and a target migration address;

[0069] The HMB cache system 304 is configured to receive the data address and fetch target data corresponding to the source data address from the data source system;

[0070] Sending a write modification command to the target migration system;

[0071] The target migration system 302 is configured to receive the write modification command and modify the preset target write queue permission information and the register value based on the write modification command to obtain new target write queue permission information and a new register value;

[0072] The target data is obtained from the HMB cache system according to the new target write queue permission information and the new register value.

[0073] The source data address includes a source write queue address and a source execution queue address, and the target migration address includes a target write queue address and a target execution queue address. The HMB cache system 304 is specifically configured to:

[0074] Receiving the data address, and fetching target data corresponding to the source data address from the data source system;

[0075] Based on the source write queue address and the source execute queue address, the source write queue and the source execute queue of the data source system are modified to obtain a new source write queue and a new source execute queue.

[0076] The target migration system 302 is specifically used for:

[0077] generating a data acquisition request according to the new target write queue permission information and the new register value, and sending the data acquisition request to the HMB cache system;

[0078] The HMB cache system receives the data acquisition request and sends the target data to the target migration system based on the data acquisition request.

[0079] The target migration system 302 is further specifically configured to:

[0080] According to the data acquisition request, the target data is sent to the target migration system via the target write queue address.

[0081] The target migration system 302 is further specifically configured to:

[0082] The target data is transferred to a target write queue of the target migration system.

[0083] In an embodiment of the present invention, the Host control system informs the data source disk and the target migration disk of the address information of the Submission Queue (SQ) and Completion Queue (CQ) based on message transmission, and then uses the HMB cache system to move data. After the source data is moved to the HMB cache system, the SQ entry of the target migration disk is modified, and the number of registers (tailer) is modified at the same time. In this way, the CPU of the SSD disk is bypassed to realize data migration within the PCIE bus, which is beneficial to reducing the CPU load. The system cluster of PCIE SSD can realize in-band data transmission (in-band management), which is very important in the application of enterprise-level servers. After the service life expires, the data can be migrated to the new disk, data backup, multi-hotspot data management, etc., which solves the technical problems of SSD hard disk internal scheduling based on PCIE bus data migration being too complex and using too much data.

[0084] above Figure 3 The data migration system of the PCIE SSD in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The data migration device of the PCIE SSD in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0085] Figure 41 is a schematic diagram of the structure of a PCIE SSD data migration device provided by an embodiment of the present invention. The PCIE SSD data migration device 400 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 410 (for example, one or more processors) and a memory 420, and one or more storage media 430 (for example, one or more mass storage devices) storing application programs 433 or data 432. Among them, the memory 420 and the storage medium 430 can be temporary storage or permanent storage. The program stored in the storage medium 430 may include one or more modules (not shown in the figure), each of which may include a series of instruction operations in the PCIE SSD data migration device 400. Furthermore, the processor 410 can be configured to communicate with the storage medium 430 to execute a series of instruction operations in the storage medium 430 on the PCIE SSD data migration device 400.

[0086] The PCIE SSD-based data migration device 400 may further include one or more power supplies 440, one or more wired or wireless network interfaces 450, one or more input / output interfaces 460, and / or one or more operating systems 431, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. It will be understood by those skilled in the art that Figure 4 The illustrated structure of the PCIE SSD data migration device does not limit the PCIE SSD-based data migration device and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0087] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions. When the instructions are executed on a computer, the computer executes the steps of the PCIE SSD data migration method.

[0088] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system or system or unit can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0089] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., various media that can store program code.

[0090] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PCIE SSD data migration method, characterized in that: The PCIE SSD data migration method is applied to a PCIE SSD data migration system. The PCIE SSD data migration system includes: a data source system, a target migration system, a Host main control system, and an HMB cache system. The PCIE SSD data migration method includes: The Host control system sends a data address to the HMB cache system, wherein the data address includes: a source data address and a target migration address, wherein the source data address includes: a source write queue address and a source execution queue address, wherein the target migration address includes: a target write queue address and a target execution queue address; The HMB cache system receives the data address and fetches target data corresponding to the source data address from the data source system; Based on the source write queue address and the source execute queue address, modify the source write queue and the source execute queue of the data source system to obtain a new source write queue and a new source execute queue; Sending a write modification command to the target migration system; The target migration system receives the write modification command, and based on the write modification command, modifies the preset target write queue permission information and the register value to obtain new target write queue permission information and a new register value; generating a data acquisition request according to the new target write queue permission information and the new register value, and sending the data acquisition request to the HMB cache system; The HMB cache system receives the data acquisition request and sends the target data to the target migration system based on the data acquisition request.

2. The PCIE SSD data migration method according to claim 1, wherein: The sending the target data to the target migration system based on the data acquisition request includes: According to the data acquisition request, the target data is sent to the target migration system via the target write queue address.

3. The PCIE SSD data migration method according to claim 1, wherein: The sending the target data to the target migration system includes: The target data is transferred to a target write queue of the target migration system.

4. A PCIE SSD data migration system, characterized in that: The PCIE SSD data migration system includes: Data source system, target migration system, Host control system, HMB cache system; The Host control system is configured to send a data address to the HMB cache system, wherein the data address includes a source data address and a target migration address, wherein the source data address includes a source write queue address and a source execute queue address, and wherein the target migration address includes a target write queue address and a target execute queue address; The HMB cache system is configured to receive the data address and fetch target data corresponding to the source data address from the data source system; based on the source write queue address and the source execute queue address, modify the source write queue and the source execute queue of the data source system to obtain a new source write queue and a new source execute queue; Sending a write modification command to the target migration system; The target migration system is configured to receive the write modification command, and based on the write modification command, modify the preset target write queue permission information and the register value to obtain new target write queue permission information and a new register value; generating a data acquisition request according to the new target write queue permission information and the new register value, and sending the data acquisition request to the HMB cache system; The HMB cache system receives the data acquisition request and sends the target data to the target migration system based on the data acquisition request.

5. A PCIE SSD data migration device, characterized in that: The PCIE SSD data migration device includes: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a line; The at least one processor calls the instruction in the memory to enable the PCIE SSD data migration device to execute the PCIE SSD data migration method according to any one of claims 1 to 3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the PCIE SSD data migration method according to any one of claims 1 to 3 is implemented.

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