Methods and computer systems for generating source code

Abstract

This invention relates to a method for generating source code from one or more blocks of a block diagram, the block diagram including at least two blocks and at least one signal connection between the two blocks. The generation of source code includes converting the block diagram into an intermediate representation, progressively optimizing the intermediate representation, and compiling the optimized intermediate representation into source code. According to the invention, equivalent assignments are identified and minimized during the conversion, so that these equivalent assignments do not need to be considered in subsequent optimization steps. The invention also relates to a method for configuring a controller, a computer program product, and a computer system.

Description

Technical Field

[0001] This invention relates to generating executable code from block diagrams, and in particular to programming controllers. Background Technology

[0002] Controllers are used in a wide range of applications to detect the physical parameters of a process and / or influence the process via connected actuators; this could be, for example, anti-lock braking control of a braking process. The time constants that determine the dynamic characteristics of the process are typically conditioned on cycle times of 1 ms or less, thus requiring real-time capabilities from the controller. For cost reasons, controllers are often microcontrollers with limited memory and computational power, making the size and efficiency of the executable code critical.

[0003] To accelerate controller design, control strategies are often developed using models in computational environments such as MATLAB / Simulink. Therefore, the process and / or controller, or the characteristics of the controller in general, can be simulated first to check for the existence of desired characteristics. The model can, in particular, be a block diagram, comprising blocks that perform operations such as computations, where a block, for example, can compute an output signal from multiple input signals. Typically, the block diagram is executed cyclically, with all blocks continuously stored in memory, each block executing once per time step. Specifically, a block can apply one or more operations to the input signals from the preceding block at each time step to generate the output signal for the current step. The block diagram can also additionally include sub-models for describing discrete characteristics, defining a number or more states and transition conditions. Source code for programming the controller can be generated directly from the model using a code generator. For example, a code generator for generating production quality source code is known from the document "Production Quality Code Generation from Simulink Block Diagrams" (Proceedings of the 1999 International Symposium on Computer-Aided Control System Design, Kohala Coast, Hawaii, by H. Hanselmann et al.).

[0004] When a model is described as a block diagram, the blocks are connected by directional or signal connections to exchange data or forward signals. A common method of code generation is to create a variable in the source code for each output of a block. However, a drawback of this approach is that the number of block variables initially created is often more than actually needed. Subsequent optimizations can reduce the number of block variables or, in general, the code size. Therefore, as known from EP2418577A1, the block diagram is converted into an intermediate representation, and at least one optimization is applied to this intermediate representation to generate an optimized intermediate representation. Several other optimizations, known to be constructed by the compiler itself, can be applied sequentially to generate further optimized intermediate representations. C code is then generated, in particular, from the optimized intermediate representation.

[0005] Because each optimization causes a change in the intermediate representation, the overall degree of code optimization can depend on the order of the optimization steps. Function calls located between two processing blocks—with no other information available about their local state—can prevent optimization from taking place. This drawback is particularly significant in the case of multiple set variables, as even simple copying can be accompanied by high memory consumption and considerably long execution times. For example, copying a vector or matrix can be done as an assignment to all variables via assignment in a loop or by assigning elements one by one, making it possible that even identical operations cannot always be recognized in the intermediate representation.

[0006] When writing to special media (such as flash memory, especially with a limited number of write cycles), US10078500B2 recommends checking whether the block group's value has been changed by assignment operations on only portions of multiple sets of meta-variables, and then generating write instructions only for the individual relevant elements. Therefore, it's important to identify special block groups and modify the generated code accordingly. However, for many block groups or operations that do not fall under this special scheme, there may be increased memory requirements and execution times longer than actually needed. Summary of the Invention

[0007] In this context, the objective of this invention is to further improve the prior art and, in particular, to assist in the generation of more concise source code, while avoiding undesirable side effects.

[0008] The task is accomplished by the method for generating source code according to the invention, the computer program product according to the invention, and the computer system according to the invention. Advantageous extensions are the technical solutions described in the dependent claims.

[0009] This invention relates to a computer-executed method for generating source code from one or more blocks of a block diagram, the block diagram including at least two non-virtual blocks and at least one signal connection between the two non-virtual blocks, the non-virtual blocks being processing blocks for calculating output values ​​and / or at least assigning values ​​to portions of signals, wherein the generation of source code includes converting the block diagram into an intermediate representation, progressively optimizing the intermediate representation, and compiling the optimized intermediate representation into source code, wherein the conversion of non-virtual blocks includes creating associations of block output variables, characterized in that the conversion of a first block among the at least two non-virtual blocks having access to a set of multiple variables includes: checking whether a block pair consisting of the first block and an adjacent block has an equi-value assignment, the multiple variables being a vector including multiple variables of the same data type, a matrix including multiple vectors, or a matrix including any The structure of multiple variables of a given data type, or a vector or matrix of a structure, wherein the block pair consists either of a first block and a preceding block or a first block and a subsequent block, depending on the type of the first block, wherein an equivalence assignment exists if at least a portion of the polynomial variables of one block of the block pair is copied in an unchanged form to a portion of the polynomial variables of the other block of the block pair, wherein, in the presence of an equivalence assignment, a variable association substitution is performed, wherein either the association of the portion of the polynomial variables of the one block of the block pair is replaced by the association of the corresponding portion of the polynomial variables of the other block of the block pair, or the association of the output variable of the first block is replaced by the association of the data storage variable; and the transformation includes deleting assignments in which the association of the same variable exists on both sides.

[0010] This invention provides a method for generating source code from one or more blocks of a block diagram, the block diagram including at least two non-virtual blocks and at least one signal connection between the two non-virtual blocks. The source code generation includes converting the block diagram into an intermediate representation, progressively optimizing the intermediate representation, and compiling the optimized intermediate representation into source code. The conversion of non-virtual blocks includes creating associations (Bezug) for block output variables. According to the invention, the conversion for a first block having access to polynomial variables includes checking whether a block pair consisting of the first block and an adjacent block has an equi-assignment (or equi-allocation, wertgleiche Zuweisung), the block pair consisting of the first block and its preceding block or the first block and its subsequent block. An equi-assignment exists if at least a portion of the polynomial variables of the first block is copied unchanged to a portion of the polynomial variables of the subsequent block. If an equi-assignment exists, a variable association is replaced, in which the association of the portion of the variables of the first block is replaced by the association of the corresponding portion of the variables of the subsequent block, or the association of the output variables of the first block is replaced by the association of data storage variables. In addition, the transformation includes deleting assignments in which there is an association of the same variable on both sides.

[0011] Data or signals can be transmitted via signal connections; the first block outputs a single value or, by definition, multiple related values, and the second block receives these values ​​and considers them when determining one or more related output values ​​for the second block. Signals can contain scalar variables and / or structured data types such as arrays, as is the case in a bus, for example. If a block includes access to multi-component variables, saving these variables can significantly save memory space and execution time, for example, by not generating instructions in the code to copy the individual components or elements of the variables and therefore not having to execute them at runtime. Multi-component variables can be vectors containing multiple variables of the same data type, matrices containing multiple vectors, structures containing multiple variables of arbitrary data types, or vectors or matrices of structures.

[0012] The transformation process may include multiple sub-steps, such as checking multiple rules and appending further code generation information. The optimization principles according to the invention can be performed at any intermediate step of the transformation. In the intermediate representation, the blocks have been compiled into instructions with a fixed execution order, thereby semantically representing a text-based programming language (corresponding to C code). Variables that are copied immutably can also be constants.

[0013] A "virtual block" refers to a block used only for constructing a block diagram but having no direct impact on the simulation. For example, a Mux- or Demux block (multiplexer or demultiplexer block) that combines multiple signals into a virtual vector or extracts an element signal from a virtual vector is a virtual block. Processing blocks that compute output values ​​and / or at least assign values ​​to portions of signals constitute non-virtual blocks. Block associations can be, in particular, block names. Block variables can be explicitly defined within a block or automatically generated, for example, through signal connections, where appropriate for the block's output signals are the generated block variables, i.e., block output variables. The identifiers or names of block variables can be fixed or defined using generation rules. Therefore, the identifiers of block output variables can include the block name and / or the name of the port in the block from which the signal originates. Since the present invention tracks the signal flow in the block diagram and does not merely compare intermediate variable names, optimization can be independent of naming conventions or generation rules.

[0014] Advantageously, the method according to the invention identifies different block pairs or groups and block variables that cause equivalent assignments, and respectively overwrites one of the variables in the identified block pairs to cause assignments between the same variable or parts of the same variable. In this case, it is not necessary to create them at all when generating the intermediate representation, or assign the same value to the same variable, thereby omitting at least one of the variables. This not only generates more efficient code overall, but also accelerates the optimization of intermediate representations because fewer variables or code patterns need to be considered from the beginning.

[0015] Preferably, equality assignment is checked for one or more of the following block types:

[0016] DataStore-Read-block read from data storage - variables;

[0017] DataStore-Write-blocks that write data to data storage variables;

[0018] A switch block that selectively connects one output to one of multiple inputs;

[0019] Model the Bus-Outport block for output to the bus;

[0020] Modeled output Outport-block; and / or

[0021] The Delay block is a block that outputs the input signal after a one-time-step delay.

[0022] Preferably, in the case of a DataStore-Read block, the DataStore-Read block is considered together with subsequent blocks, and when an equivalent assignment exists, the association of the output variable of the DataStore-Read block is replaced by the association of the corresponding part of the data storage variable. Similarly, in the case of DataStore-Write blocks, Switch blocks, Bus-Outport blocks, Outport blocks, and / or Switch blocks, they are considered together with preceding blocks, and when an equivalent assignment exists, the association of the output variable of the preceding block is replaced by the association of the variable in the first block. One output of the preceding block is directly connected to one input of the subsequent block via a signal. The output variable of the DataStore-Read block can be a puffer variable, a data storage variable, or a DataStore-Memory variable. In the case of a DataStore-Write block, it is preferable that the output variable of the preceding block is replaced by the data storage variable or the corresponding part of the data storage variable.

[0023] Therefore, optimization can be achieved by identifying equivalent values ​​based on block attributes. The optimization according to the invention can also be applied in the same simple way, or regardless of the number of components, to complex signals or multi-component block variables. Only a few rules need to be checked here, which pertain to a small number of blocks and the signals connected to them. Thus, the correctness of the sub-steps can be easily verified, ensuring that the same modeling leads to equally effective code.

[0024] If a block diagram includes multiple blocks, and the block types of the multiple blocks correspond to the block types to be checked for equivalence assignments, then it is preferable to perform equivalence assignment checks on each of the multiple blocks according to the block type, and replace variable associations when equivalence assignments exist.

[0025] It is appropriate to examine possible replacements for all blocks of suitable type present in the block diagram, especially for one of the blocks in all considered block pairs—the block pair consisting of the block and its adjacent blocks in the signal flow, particularly directly adjacent blocks—to check for equivalent assignments and, in that case, replace the corresponding variable associations. It is appropriate to treat preceding or subsequent blocks as part of a block pair based on their block type. Virtual blocks can be skipped to determine adjacency relationships.

[0026] Preferably, the block diagram is hierarchically defined, where a block in a higher level can include multiple blocks in a lower level, multiple blocks in a lower level can be assigned to a block in a higher level, and if an equality assignment is checked for a DataStore-Read block, then the DataStore-Write block accessing the same data store variable is searched in the comprehensive (umfassend) hierarchical blocks, especially in the atomic hierarchical blocks.

[0027] If a DataStore-Read block and a DataStore-Write block accessing the same data storage variable are found in the comprehensive hierarchical blocks, it is particularly preferable to check whether the DataStore-Read block and the DataStore-Write block are at least partially connected in the signal flow such that the portion of the data storage variable read into the DataStore-Read block has a non-empty intersection with the portion of the data storage variable written into the DataStore-Write block, wherein at least one block is located in the signal flow between the DataStore-Read block and the DataStore-Write block, wherein the one or more blocks located therebetween include at least one non-virtual processing block that processes the input variable to generate an output variable. As an additional condition, it is checked whether the one or more blocks located therebetween have a processing order such that the at least one processing block is executed before the DataStore-Write block, and if this additional condition is met, the portion of the output variable of the DataStore-Read block corresponding to the intersection is replaced by the portion of the data storage variable corresponding to the intersection.

[0028] If a DataStore-Read block and a DataStore-Write block accessing the same data store variable are not connected in the semaphore stream, the blocks can be checked independently for equivalent assignments. A semaphore stream connection exists only if the portion of the data store variable read into the DataStore-Read block has a non-empty intersection with the portion written to it in the DataStore-Write block. If other components of the accessed variable are accessed, such as other elements of a vector or parallel portions in a bus hierarchy, the intersection is empty; for a structure S, for example, Sa has a non-empty intersection with Sab but not with Scb. Processing can also involve assigning a new value to a portion of a variable, thus a block performing dynamic assignment also constitutes a processing block in this sense. If multiple DataStore-Write blocks in a comprehensive hierarchical block access the same data store variable as the DataStore-Read block, then for each DataStore-Write block, a forward data flow relationship is checked, meaning that data is always read from the data store variable before being written to it. Alternatively, it can be stipulated that the block accessing the data storage variable and the blocks in between must have only one explicit sequential or serial execution order, i.e., either read first or write first, to allow for optimization. Checking prerequisites or additional conditions, such as an explicit sequential or serial execution order, ensures that no undesirable side effects arise from optimizations according to the invention.

[0029] If the additional conditions are not initially met, it is particularly preferable to change the processing order of at least one of the intermediate blocks to satisfy the additional conditions. If the processing order of one or more blocks is not predetermined by modeling itself or by the technical environment, this provides the freedom to reorder the blocks to satisfy the prerequisites or additional conditions.

[0030] If a DataStore-Read block and a DataStore-Write block that access the same data storage variable are found in the comprehensive hierarchical block, it is particularly preferred to check whether the DataStore-Read block and the DataStore-Write block are at least partially connected in the signal stream such that the portion of the data storage variable read into the DataStore-Read block has a non-empty intersection with the portion of the data storage variable written into the DataStore-Write block, wherein at least one block is located in the signal stream between the DataStore-Read block and the DataStore-Write block, and the one or more blocks located therebetween include at least one non-virtual processing block that processes the input variable to generate the output variable. In this case, for the preceding block of the DataStore-Write-block, i.e., the processing block closest to the DataStore-Write-block in the semaphore flow, as an additional condition, it is checked whether the part of the preceding block's block output corresponding to the intersection is connected to the DataStore-Write-block without a semaphore flow branch, and whether the preceding block's block output variable is consistent with the at least part of the connection in the semaphore flow in terms of dimension and data type. If these additional conditions are met, the preceding block's block output variable is replaced by the part of the data storage variable corresponding to the intersection.

[0031] Preferably, the block diagram is hierarchically defined, where a block in a higher level can include multiple blocks in a lower level, and multiple blocks in a lower level can be assigned to a block in a higher level. If checking whether the first DataStore-Read block is assigned an equal value, then other DataStore-Write blocks that access the same data storage variable are searched in the comprehensive hierarchical blocks, especially in atomic hierarchical blocks. And as an exclusion reason for the variable association in the block pair that replaces the first DataStore-Write block, for each other DataStore-Write block found, it is checked whether the other DataStore-Write block writes to the part of the data storage variable that was also written by the first DataStore-Write block. If the exclusion reason exists, then even if there is an equal value assignment, the association of the data storage variable written by the DataStore-Write block is not used to replace the association of the output variable of the preceding block.

[0032] If multiple DataStore-Write-blocks access the same part of a data store variable, the write order must be fixed and unchangeable to avoid unpredictable side effects; otherwise, optimization will be abandoned.

[0033] Preferably, variables can be designated as states, and even if there is an equivalence assignment between the first and second variables in a block pair, the association of the first variable is replaced by the association of the second variable only if the first variable is not designated as a state and / or the second variable is designated as a state. Preferably, if the second variable has a static storage time and an initial value, the second variable can act as a state; in this case, if the initial values ​​are the same, the first variable designated as a state can also be replaced by the second variable.

[0034] In particular, the Delay block includes state variables. Since state variables affect the output value at the next time step, they can only be replaced with the same state variable to avoid erroneous behavior.

[0035] Preferably, even though there is an equivalence assignment between the first and second variables in a block pair, if one or more of the exclusion reasons mentioned below exist, the association of the second variable is not used to replace the association of the first variable, wherein, in the case where the equivalence assignment exists only for portions of the first and second variables, only those portions are considered in the exclusion reasons:

[0036] -The first and second variables have different dimensions.

[0037] - At least one element of the first variable has a different data type than the corresponding element of the second variable.

[0038] - The first variable is specified as necessary.

[0039] - The execution order of blocks through signal flow branches and / or connections results in unpredictable data flow.

[0040] Variables are only necessary when the user manually assigns them specific data types. This is achieved by optimizing or reducing automatically generated block variables, particularly through the method according to the invention. If the first and second variables have the same dimension (i.e., not different dimensions), they also occupy the same number of storage locations, thus allowing the associations of these variables to be swapped (this also applies to parts of the variables). Specifically, partitions of data storage-variables or DataStore-Memory elements can be copied at the DataStore-Read-block DSR and the connected DataStore-Write-block, for example, by assigning DSR[0..4] = DSM[3..7], i.e., copying a partition of a vector with dimension 5.

[0041] Particularly preferably, the block diagram is defined hierarchically, where a block in a higher level can include multiple blocks in a lower level, and multiple blocks in a lower level can be assigned to a block in a higher level. The system checks whether there are any exclusion reasons for all blocks in the hierarchy of the first block and all blocks assigned to these blocks.

[0042] The present invention also relates to a method for configuring a controller, the controller including at least one computing unit and preferably having at least one sensor and / or at least one actuator to detect data of a physical process and / or act on the physical process, the method comprising the following steps:

[0043] a. Read in the flowchart;

[0044] b. Generate source code using the method according to the present invention.

[0045] c. Compile the source code used for the computing unit to generate executable code;

[0046] d. Transfer the executable code to the controller; and

[0047] e. Store the executable code in the controller's non-volatile memory and / or execute the executable code through the controller's computing unit.

[0048] The present invention also relates to a computer program product having a computer-readable storage medium on which instructions are embedded, which, when executed by a processor, cause the processor to perform the method according to the present invention.

[0049] The present invention also relates to a computer system including a human-computer interface, non-volatile memory, and a processor configured to perform the method according to the present invention. Attached Figure Description

[0050] The invention is described in detail below with reference to the accompanying drawings. Similar parts have the same names. The illustrated embodiments are highly illustrative, i.e., distances and lateral and vertical dimensions are not drawn to scale and do not have any derived geometric relationships with each other, unless otherwise stated.

[0051] The attached image is as follows:

[0052] Figure 1 This illustrates a preferred embodiment of the computer system;

[0053] Figure 2 A schematic diagram is shown of a software component preferably located on a computer system;

[0054] Figure 3 A schematic flowchart illustrating one embodiment of the method for generating source code according to the present invention is shown;

[0055] Figure 4 This shows a block diagram section with dynamic assignment.

[0056] Figure 5 A block diagram showing a portion with a read-modify-update mechanism is shown;

[0057] Figure 6 A block diagram showing a portion with a read-update-use mechanism is shown;

[0058] Figure 7 A block diagram showing the parallel and return delay states is provided.

[0059] Figure 8 A block diagram portion showing an iterative system is shown; and

[0060] Figure 9 This shows a block diagram portion with a Switch block. Detailed Implementation

[0061] Figure 1 An exemplary implementation of a computer system PC is shown. This computer system has a processor CPU, which can be implemented, in particular as a multi-core processor, working memory (or system memory) RAM, and a bus controller BC. Preferably, the computer system PC is designed for direct manual operation by a user, with a display DIS connected via a graphics card GPU and a keyboard KEY and mouse MOU connected via a peripheral interface HMI. In principle, the human-machine interface of the computer system PC can also be configured as a touch interface. The computer system also includes non-volatile data storage HDD—which can be designed, in particular, as a hard disk and / or solid-state drive—and an interface NET, in particular a network interface. A controller ES can be connected via the interface NET. In principle, one or more arbitrary interfaces, in particular wired interfaces, can exist on the computer system PC and can be used to connect to the controller ES. Preferably, a network interface according to the Ethernet standard is used; this interface NET can also be designed wirelessly, such as, in particular, as a WLAN interface or according to a standard such as Bluetooth.

[0062] The controller ES can be designed as a batch controller or an evaluation board for the target platform. Preferably, the controller includes an interface NET for connection to a computer system (PC), a microcontroller MCR with an architecture different from the computer system's processor, working memory RAM, and non-volatile memory NVM. With the controller ES present, it is preferable to be able to perform processor-in-the-loop emulation of the generated code.

[0063] Figure 2 A schematic diagram illustrates software components preferably installed on a computer system (PC). These software components utilize operating system (OS) mechanisms to, for example, access non-volatile memory (HDD) or establish connections with external computers via a network interface (NET).

[0064] The Technical Computing Environment (TCE) can create models and generate source code from them. In the Modeling Environment (MOD), models of dynamic systems can preferably be created via a graphical user interface. This can be, in particular, a block diagram comprising multiple blocks and describing the temporal characteristics and / or internal states of the dynamic system. At least some blocks are connected by signals, i.e., directed connections for data exchange, which can be scalar or composite. The individual blocks can be atomic, i.e., forming a unit from the perspective of a comprehensive block, in which all input signals must be present at the start of a computational step and all output signals must be present at the end of the computational step. If the block diagram is hierarchical, multiple blocks at lower levels can describe the structure of a single block at a higher level. Hierarchical or composite blocks, even atomic ones, can be included in multiple blocks at lower levels. Composite blocks can, in particular, be subsystems; subsystems can have additional properties, such as being implemented as separate functions and / or having their execution triggered by dedicated signals. Special blocks can be set within subsystems to further specify the properties of the subsystem. The TCE includes one or more libraries (BIBs) from which blocks or modules can be selected to build models. In the scripting environment MAT, instructions can be entered interactively or via batch files (Batchdatei) to perform calculations or modify models. The computational environment TCE also includes the simulation environment SIM, which is set up to interpret or execute block diagrams to examine the system's time characteristics. These calculations are preferably performed on one or more cores of the computer system's microprocessor CPU in high-precision floating-point numbers.

[0065] The code generator PCG can be used to generate source code from the created model, preferably in a programming language such as C. It is suitable to store additional information about the model, especially about block variables, in the definition dataset DDT. It is also suitable to assign value ranges and / or numerical scaling or calibration to block variables to support model computation using fixed-point instructions. Desired properties of the source code (e.g., conformance to MISRA standards) can also be set or stored in the definition dataset DDT. It is also suitable to assign a predetermined variable type to each block variable and set one or more desired properties, such as the allowance for optimizations (e.g., variable merging). The code generator PCG preferably evaluates the settings of the definition dataset DDT and takes them into account when generating the source code. The definition dataset DDT can have a tree structure or be stored as a simple file in the computer system's memory; alternatively, it can be specified that the definition data is stored in a dedicated database system. The definition dataset can have a program interface and / or import / export functionality.

[0066] The computer system PC has a compiler (COM) and a linker (LIN), which are appropriately configured to generate binaries that can be executed on the controller ES and / or the computer system PC. In principle, multiple compilers can exist, especially cross-compilers for different target platforms, to support controllers or evaluation board ESs with different processor architectures.

[0067] Figure 3 A schematic flowchart illustrating one embodiment of a method for generating source code according to the present invention is shown. The method can be executed entirely by the processor of an exemplary embodiment of a computer system PC; however, the method can also be used in a client-server environment having an operating computer and one or more servers connected via a network, particularly with computationally intensive steps performed on the server.

[0068] In step S1 (reading in the block diagram), a block diagram is read in. This block diagram includes at least two processing blocks connected by signals and may include multiple other blocks. Preferably, the read-in block diagram also includes reading at least one block attribute and / or code generation-related settings from the definition dataset DDT, such as the data type of a variable.

[0069] In step S2 (converting to intermediate representation), the selected model is converted from one or more blocks of the block diagram into an intermediate representation, which preferably includes one or more hierarchical diagrams. This can be, in particular, a data flow diagram, a control flow diagram, or a tree structure. In addition to the block diagram, it is suitable to consider customizing additional information from the dataset DDT or incorporating additional information from the definition dataset DDT into the intermediate representation when generating it. This may also include generating elements based on information in the definition dataset DDT or extracting attributes or code generation-related settings from the definition dataset DDT, such as the data type of variables.

[0070] In step S3 (Other block pairs?), check whether the block diagram includes other block pairs that have not been considered so far, in which optimizations according to the invention can potentially be considered. If so, proceed to step S4; otherwise, continue execution in step S8.

[0071] In step S4 (equivalent assignment?), for block pairs not yet considered, check if at least a portion of one variable can be assigned to another variable (or a portion of that variable) without changing its value. If so, proceed to step S5; otherwise, continue in step S3 to determine if there is another block pair that can be checked.

[0072] This invention is based on the consideration that block ensembles, especially block pairs, and block variables that lead to equivalent assignments are already identified within the atomic subsystem during the conversion to an intermediate representation. By overriding block variables or replacing associations, assignments (Zuweisung) can be made between identical variables or portions of identical variables, in which case they do not need to be created at all when creating the block code, or the same value can be assigned to the same variable (usually a state variable) to omit at least one of the variables.

[0073] Since the optimization occurs during the conversion to an intermediate representation, all information about the block diagram remains available. Therefore, the results of the block diagram conversion can be considered, and / or a suitable block execution order can be selected or facilitated, provided the corresponding degrees of freedom exist. Furthermore, a suitable order can be chosen so that the corresponding replacements can be performed multiple times or with maximum efficiency.

[0074] In one embodiment of the invention, the output of a block (which can be considered an atomic unit, especially an atomic system) can be replaced by the output and / or state of subsequent blocks, provided suitable modeling exists. Preferably, this replacement occurs before the internal workings of the atomic system are considered; initial values, initialization characteristics, and state reset characteristics are preferably considered when examining exclusionary causes.

[0075] In step S5 (Is there a reason for exclusion?), it is checked whether there is a reason for exclusion that prevents the optimization according to the invention from being achieved. If so, execution continues in step S3. Possible reasons for exclusion for the optimization include, in particular:

[0076] - The variables involved differ in dimensional width, data type, and / or numerical scaling.

[0077] - The block diagram includes signal line branches, based on which eliminating variables can lead to necessary buffering or state loss.

[0078] - There is an unknown data stream, for example, through

[0079] Release or enable (Freigabe) variable merging

[0080] Calling external functions

[0081] Other DataStore-Write and / or DataStore-Read blocks that do not have an explicit data flow relationship with the currently considered block.

[0082] - The variable to be eliminated is specified in such a way that it must appear in the initial code pattern.

[0083] If no exclusion reason exists, execution continues in step S6 (replace variable associations), where the association (Bezug) of the variable with the same assignment is replaced by the association of the variable in the corresponding adjacent block. Then, in step S7 (remove identical assignments), identical assignments that may have been caused by the replacement of variable associations are removed from the intermediate representation. Then, execution continues in step S3 to handle any other possible block pairs.

[0084] In step S8 (further optimization of intermediate representation), the hierarchical graph is optimized to reduce the number of required variables and / or memory consumption, such as stack footprint, and / or the number of operations or processor instructions and / or the execution time of the source code. This optimization may include multiple intermediate steps in which additional intermediate representations are generated between the model / block diagram and the source code / program text. Specifically, it can be specified that in each intermediate step, a transformation of one original set of hierarchical graphs into another modified set of hierarchical graphs is provided, where one or more optimization rules are applied. Different strategies, such as "constant folding" or elimination of "dead code," can be applied during optimization. In principle, multiple variables generated within the transformation range can be merged in step S. However, according to the invention, it is preferable to already merge multiple variables of the block diagram during the transformation to the intermediate representation, such that the first intermediate representation still contains only one variable.

[0085] In step S9 (compiling the intermediate representation into source code), the optimized intermediate representation or optimized layered graph generated by all the executed intermediate steps is compiled into source code in a text-based programming language, such as, in particular, C code. Further optimizations can also be performed in this step, especially optimizations such that the generated instructions constitute a subset of the instructions contained in that language and / or the generated control structures constitute a subset of the control structures contained in that language. This allows for the satisfaction of precisely defined rules. Alternatively or additionally, it can be specified that additional information, such as the relationships between program lines and blocks of the block diagram, is generated and, in particular, incorporated into the source code as comments, to improve the readability of the source code and / or simplify debugging.

[0086] During or after code generation, information such as warnings about the current block diagram or code generation results can be stored in a defined dataset. This information can, for example, be used to influence the compilation of the generated source code or to provide metadata for other tools, such as calibration information in ASAP2 format or information for generating intermediate layers according to the AUTOSAR standard. In an alternative embodiment of the invention, the generation of hardware description language code or the configuration of programmable hardware modules from the block diagram can be specified.

[0087] Exemplary embodiments of the present invention will be explained below with reference to some parts of the block diagram.

[0088] Figure 4The diagram illustrates a portion with dynamic assignment. This portion includes a data storage (data storage) read block (read from data storage A), an Assembly block, and a DataStore-Write block (write to data storage A). The Assembly block receives a vector value read from data storage A, an index Idx1, and a scalar replacement value U as input signals. After the previous value of A at Idx1 is replaced by the replacement value U, the Assembly block outputs the resulting signal to the DataStore-Write block.

[0089] For this part, the following code will be generated in the direct implementation without optimization:

[0090]

[0091] The best possible optimization would result in the following code:

[0092] A[Idx1] = U;

[0093] Compared to the unoptimized code, the cached variables Sa1_Assignment and Sa1_Data_Store_Read1 were eliminated.

[0094] The following initial conditions are identified in a method according to the invention:

[0095] Equality assignment in block code mode of the DataStore-Read block

[0096] Equivalence assignment at the input of the -Assigment- block

[0097] Equality assignment in block code mode of the DataStore-Write block

[0098] - No data storage variables were modified multiple times.

[0099] - There is no read / write order conflict between the DataStore-Read block and the DataStore-Write block.

[0100] Therefore, at the output of the DataStore-Read block, Sa1_Data_Store_Read1 can be replaced by A' of DataStore-Memory; here and below, the apostrophe attached to the identifier indicates whether the identifier is located in the block on the left or upstream of the signal stream (in this case, one apostrophe) or in the block on the right or downstream of the signal stream (in this case, two apostrophes). Furthermore, at the output of the Assignment block, Sa1_Assignment can be replaced by A" of the downstream DataStore-Write block.

[0101] Therefore, we can conclude that:

[0102]

[0103] As possible initial code (for better readability, C source code is used for explanation, although optimizations are actually performed before compilation to source code). The apostrophes here and below are only used to indicate their association with one of the blocks and do not change the fact that they all refer to the same identifier.

[0104] According to the present invention, converting a block diagram into an intermediate representation includes deleting assignments in which the same variable is associated on both sides (as described above, there is no reason for exclusion).

[0105] Therefore, the three "A[Aux_S32] = A[Aux_S32]" assignments, including the contained loop, will not be created at all; that is, they are generated immediately.

[0106] A“[Idx1]=U;

[0107] Therefore, the method according to the present invention has the following advantages: it does not generate unnecessary statements and variables at all, thereby immediately generating efficient code, and obviously unnecessary variables and statements do not need to undergo further optimization steps or code generation.

[0108] exist Figure 4 The block diagram shown models the reading from a data store—a variable, the change of a portion of the variable's value, and the writing of at least the changed portion of the variable to the same data store. However, even if the value of a variable is written to another data store—a variable, efficient source code can still be generated using the method according to the invention. Therefore, if the data store—a variable—of the DataStore-Write block is another variable, such as B, then instead of A, "B" will appear in the initial code. The two apostrophes here indicate that the identifier is the block on the right. Without optimization, the following initial code would be obtained:

[0109]

[0110] By removing such assignments according to the present invention, where the same variable exists on both sides, i.e., by omitting unnecessary identical copying actions, the following code is obtained:

[0111]

[0112] Without further information, this is the best possible code pattern. Advantageously, in the method for generating source code according to the invention, it is not necessary to perform a joint analysis of all three blocks; only block pairs need to be considered. Therefore, the following two parts are considered at this stage:

[0113] 1. Does the DataStore-Read block output have no signal line branch downstream, or does it have a defined data flow-driven order relative to the possible DataStore-Write blocks used for all subsequent blocks? In this case, the dedicated block output variable can be partially replaced by the selection of the DataStore-Memory variable for dynamic assignment.

[0114] 2. Does the block output variable of the preceding block of the DataStore-Write-block input have the same properties as the selected portion of the DataStore-Memory variable and have no signal line branches? In this case, the block output variable of the preceding block can be replaced by the selected portion of the DataStore-Memory variable.

[0115] Figure 5 A block diagram of a section with a read-modify-update mechanism is shown. This section includes a DataStore-Read block for reading from data storage A, a Selector block, a computation block, an Assigment block, and a DataStore-Write block for writing to data storage A. The Selector block receives the vector value and index Idx read from data storage A as input signals and provides the value of the element at position Idx1 of the input vector as output to the subsequent computation block. The computation block DoSomething is designed as a hierarchical block and can apply any operation until the result is output as a scalar replacement value to the Assigment block. In addition to the scalar replacement value U, the Assigment block receives the vector value and index Idx1 read from data storage A as input signals. After replacing the previous value of A at position Idx1 with the replacement value U, the Assigment block outputs the result signal to the DataStore-Write block.

[0116] Compared to the previous examples, the focus here is on the branching to the Selector-block. The DataStore-Read-block output variables are cached as DataStore-Memory values ​​upon reading. The DataStore-Read-block output cannot be deleted if the code in the Selector-block, or in the case of a static selection, might execute after the data storage write block or its preceding block. If "DoSomething" is a chain of blocks—which also drive the U inputs of the Assembly-block—or if "DoSomething" is an atomic system, the correct execution order of the blocks is guaranteed, and block variables can be substituted. This results in the following source code:

[0117]

[0118]

[0119] Therefore, after removing the redundant assignments, we get:

[0120] Sa1_Selector=A'[Idx1]; / *Ausgangsvariabledes Selector-Blocks* / … / *DoSomething berechnet U und liest Sa1_Selector* / A”[Idx1]=U;

[0121] Optimized source code can also be generated even when there are branches in the signal flow, by checking and adjusting the block execution order as necessary.

[0122] Figure 6The diagram illustrates a portion of a read-update-use mechanism that combines reading data from a data store—variables—changing values, and writing back a portion of the variable with computation based on the changed variable. This portion includes a DataStore-Read block for reading from DataStore-Memory A, an Assigment block, and a DataStore-Write block for writing to DataStore-Memory A. In addition to the scalar replacement value U, the Assigment block receives the vector value and index Idx1 read from DataStore-Memory A as input signals. After the previous value of A at position Idx1 is replaced by the replacement value U, the Assigment block outputs the result signal to the DataStore-Write block and the computation block performCalculation. The output signal of the DataStore-Read block is additionally connected to a Selector block, which receives the vector value and index Idx1 read from DataStore-Memory A as input signals and outputs the value of the element of the input vector at position Idx1 as an output signal. This output signal is connected to the trigger input of the calculation block performCalculation, which can apply any operation to the updated value of the data storage variable until the result is output to the output port sumofValues.

[0123] The key difference here compared to the previous case is that there is no guarantee that the Selector block executes before the DataStoreWrite block. Based on current technology, code generation typically produces the following code:

[0124]

[0125] This causes optimizations for the intermediate representation to no longer work, and the block output variable Sa1_Data_Store_Read is unnecessarily retained.

[0126] If the computation order of the blocks is ensured, i.e., the Selector block always executes before the DataStore-Write block, optimized code can be generated for block pairs consisting of the DataStore-Read block and the Selector block. According to a preferred embodiment of the invention, it is suitable that the production code generator checks whether the execution of the Assembly block and the Selector block can move freely relative to each other and, in this case, determines the virtual data flow dependency between the Selector block and the Assembly block (as the preceding block of the DataStore-Write block). This facilitates a suitable execution order of the blocks or ensures the timely execution of the Selector block.

[0127] Furthermore, optimization of the block pair consisting of the Assembly-block and the DataStore-Write-block is only possible if the DataStore-Read-block is not executed after the Assembly-block, or—in the case of eliminating DataStore-Read-output variables—the DataStore-Read-subsequent block is executed. Only in this way can the Assembly-block receive the data storage Memory-variable as an output variable as a preceding block to the DataStore-Write-block, or can the output variables of the Assembly-block be deleted.

[0128] Therefore, the signal line branch needs to check more than two blocks to ensure the allowable performance according to the invention. This also applies to situations where multiple DataStore-Read and Write blocks access the same DataStore-Memory block.

[0129] If the desired execution order of the blocks connected in the semaphore stream is maintained, the following code is generated:

[0130]

[0131] After removing redundant assignments to the variable itself, we get:

[0132]

[0133] Figure 7 The diagram shows a portion of the parallel and return states of a Delay-block that delays a signal by one time step. The subsystem receives an input signal In. The input signal encounters a summing block S, whose output is connected both to an output port and to a first Delay-block with state X1. The output of the Delay-block is connected to the first input of a Selector-block, which also receives a constant and can selectively output one value. The output of the Selector-block forms the second input of the summing block S. The subsystem's output signal Out is connected to a second Delay-block (Unit-Delay-block) with state X2. This modeling with Delay-blocks of the same type can occur, for example, when using library blocks from a block library.

[0134] Unless the atomic system boundary causes a different update order for the two states or specifies different initial values, X1 and X2 can have the same state variables:

[0135] … / *Use X1* /

[0136] S = ...;

[0137] … / *Use X2* /

[0138] … / *Use S* /

[0139] X1 = S;

[0140] …

[0141] X2 = S;

[0142] This results in the following code, where the unnecessary double definitions were removed later through optimization:

[0143] … / *Use X1* /

[0144] S = ...;

[0145] … / *Use X1* /

[0146] … / *Use S* /

[0147]

[0148] …

[0149] X1 = S;

[0150] If no parallel state can be optimized in this way, the returned delay can replace the previous block output variable. That is, if the explicit subsystem is atomic, then Sa2_Out1 is obtained as the block output variable of the subsystem:

[0151] … / *Use X1* /

[0152] S = ...;

[0153] Sa2_Out1 = S;

[0154] X1 = S;

[0155] … / *Use X2* /

[0156] … / *Use Sa2_Out1* /

[0157] …

[0158] X2 = Sa2 Out1;

[0159] The following code is generated in the optimization of the equivalent assignment according to the present invention:

[0160] … / *Use X1* /

[0161] X1 = ...;

[0162] Sa2_Out1 = X1;

[0163]

[0164] … / *Use X2* /

[0165] … / *Use Sa2_Out1* /

[0166] …

[0167] X2 = Sa2_Out1;

[0168] If the atomic system is a conditionally executed subsystem, the output (endpoint) acquires an initial value and can represent the state's role in the generated serial code for its static storage duration. If such a state has the same initial value as X1, it is a parallel state, similar to X2 in the unconditional execution case. That is, if the initial values ​​are the same, the state can also be replaced by the output of the atomic system:

[0169] … / *Use Sa2_Out1* /

[0170] Sa2_Out1 = ...;

[0171]

[0172] … / *Use X2* /

[0173] … / *Use Sa2_Out1* /

[0174] …

[0175] X2 = Sa2_Out1;

[0176] Here, if this does not involve a system with conditional execution or a system output specification predefined by the user, and if the cell delay state has sufficient visibility, it is more advantageous to change the order first, i.e., to replace the block output with the system output (regardless of whether or how it is initialized) to avoid identical initialization conditions:

[0177] … / *Use X1* /

[0178] X1 = ...;

[0179]

[0180] … / *Use X2* /

[0181] … / *Use X1* /

[0182] …

[0183] X2 = X1;

[0184] Figure 8The diagram shows a portion of a block diagram with an iterative system. In iterative systems, nonscalar signals can exhibit internal loops, which can negatively impact performance, especially when constructing vectors or matrices via Assembly blocks. The processing of the vector signal is illustrated. The For-Iterator block receives a signal width through a first input port, which predetermines the number of iterations, i.e., the frequency at which the For-Iterator block can execute consecutive blocks within a time step. The output of the For-Iterator block is connected to the index input Idx1 of the Selector block and Assembly block A. The Selector block selects an element of the vector input signal received at the second input port and forwards that element to the processing block doSth, which is additionally connected to a third input port. The output signal Out1 of the processing block doSth is provided to Assembly block A as a new value U. The output of the Assembly block is returned, on the one hand, as the vector Y0 to be changed through the Delay block, and on the other hand, output through output port O.

[0185] The following code is generated for the portion of the diagram showing a returned Delay block:

[0186]

[0187]

[0188] The optimization resulted in the following code, with the redundant code that was later removed here—and elsewhere—displayed by crossing out:

[0189]

[0190] Therefore, the internal loops that are difficult to optimize using conventional methods are eliminated through the optimization according to the present invention.

[0191] Figure 9The diagram shows a portion of the block diagram using a switch block. A vector input signal is received through the first input port A and fed to gain block G1, which multiplies the value by a factor of 123. A scalar signal is received through the second input port B and fed to gain block G2, which multiplies the value by a factor of 456. The output signals of the two gain blocks are fed to a switch block S1, which selects which signal to forward based on the value on input port Cond1. The output of switch block S1 is connected to the first input of a second switch block S2. Another vector input signal is received through input port C and fed to a third gain block G3, which multiplies the value by a factor of 456 and outputs it to the second input of switch block S2. The second switch block S2 switches between the output of the first switch block S1 and the output of the third gain block G3 via another input port Cond2. The active signal is output through output port O.

[0192] When the production code generator moves the preceding block of a Switch-block or multi-port Switch-block to the control flow branch of the data input based on the block diagram, the block outputs of the directly adjacent preceding blocks are directly copied to the block output variables of the Switch-block or multi-port Switch-block, respectively. In this case, they can be replaced by Switch-outputs.

[0193]

[0194]

[0195] This occurs during the previous copying of S2 and S1, as well as output (terminal) O:

[0196]

[0197]

[0198] Here, O' represents the association from the substitution of the block pair with G1, O” represents the association from the substitution of the block pair with S1, O”' represents the association from the substitution of the block pair with S2, and O”” represents the association from the substitution of the block pair with G3. Because of the exclusion criterion that the signals have different widths, G2 cannot be optimized.

[0199] The method according to the invention can significantly reduce memory requirements and otherwise execution time required for copying, particularly when using multi-group variables with high memory consumption, such as those found in bus modeling.

Claims

1. A computer-executable method for generating source code from one or more blocks of a block diagram, the block diagram comprising at least two non-virtual blocks and at least one signal connection between the two non-virtual blocks, the non-virtual blocks being processing blocks for calculating output values ​​and / or at least assigning values ​​to portions of the signals, wherein, The generation of source code involves converting the block diagram into an intermediate representation, progressively optimizing the intermediate representation, and compiling the optimized intermediate representation into source code. The transformation of non-virtual blocks includes creating associations for block output variables. The transformation for a first block with access to multi-group variables in the at least two non-virtual blocks is characterized by: checking whether a block pair consisting of the first block and an adjacent block has an equi-assignment, wherein the multi-group variable is a vector comprising multiple variables of the same data type, a matrix comprising multiple vectors, a structure comprising multiple variables of arbitrary data type, or a vector of a structure, or a matrix of a structure, wherein the block pair consists either of the first block and its preceding block or of the first block and its subsequent block, depending on the type of the first block, wherein an equi-assignment exists if at least a portion of the multi-group variables of one block of the block pair is copied unchanged to a portion of the multi-group variables of the other block of the block pair, wherein, when an equi-assignment exists, a variable association replacement is performed, wherein either the association of the portion of the multi-group variables of the one block of the block pair is replaced by the association of the corresponding portion of the multi-group variables of the other block of the block pair, or the association of the output variable of the first block is replaced by the association of the data storage variable; and the transformation includes deleting assignments in which the association of the same variable exists on both sides.

2. The method according to claim 1, characterized in that, Equivalence assignment is checked for one or more of the following block types: data storage read block that reads from data storage variables, data storage write block that writes to data storage variables, switching block that selectively connects an output to one of multiple inputs, output block that models the output, and / or delay block that re-outputs the input signal after a delay of one time step. in, In the case of a data storage read block, the data storage read block is considered together with subsequent blocks, and when there is an equivalent assignment, the association of the output variable of the data storage read block is replaced by the association of the corresponding part of the data storage variable, and / or In the case of data storage write blocks, switching blocks, bus output blocks, output blocks, and / or delay blocks, they are considered together with the preceding blocks, and when there is an equivalent assignment, the association of the output variables of the preceding blocks is replaced by the association of the multi-group variables of the first block.

3. The method according to claim 1 or 2, characterized in that, A block diagram includes multiple blocks, the block types of which correspond to the block types of the equality assignments to be checked, and Specifically, for each of the multiple blocks, an equivalence assignment check is performed based on the block type, and variable associations are replaced if equivalence assignments exist.

4. The method according to claim 1, characterized in that, The block diagram is defined hierarchically, where a block at a higher level can include multiple blocks at lower levels, and each block at a lower level is assigned to a block at a higher level. If an equal assignment is checked for a data storage read block, then a search is conducted within the comprehensive hierarchical blocks for data storage write blocks that access the same data storage variable.

5. The method according to claim 4, characterized in that, The comprehensive hierarchical block is an atomic hierarchical block.

6. The method according to claim 4 or 5, characterized in that, If a data storage read block and a data storage write block that access the same data storage variable are found in the comprehensive hierarchical block, it is checked whether the data storage read block and the data storage write block are at least partially connected in the signal flow such that the portion of the data storage variable read into the data storage read block has a non-empty intersection with the portion of the data storage variable written into the data storage write block, wherein at least one block is located in the signal flow between the data storage read block and the data storage write block, wherein one or more blocks located therebetween include at least one non-virtual processing block that processes the input variable to generate an output variable, and wherein, as an additional condition, it is checked whether the one or more blocks located therebetween have an execution order such that the at least one non-virtual processing block is executed before the data storage write block, and when the additional condition is met, the portion of the output variable of the data storage read block corresponding to the intersection is replaced by the portion of the data storage variable corresponding to the intersection.

7. The method according to claim 6, characterized in that, If the additional condition is not initially met, the execution order of at least one of the blocks in between is changed to meet the additional condition.

8. The method according to claim 4 or 5, characterized in that, If a data storage read block and a data storage write block accessing the same data storage variable are found in the comprehensive hierarchical block, it is checked whether the data storage read block and the data storage write block are at least partially connected in the signal flow such that the portion of the data storage variable read into the data storage read block has a non-empty intersection with the portion of the data storage variable written into the data storage write block, wherein at least one block is located in the signal flow between the data storage read block and the data storage write block, wherein one or more blocks located therebetween include at least one non-virtual processing block that processes the input variable to generate an output variable, and in this case, as an additional condition, for the preceding block of the data storage write block, i.e., the processing block closest to the data storage write block in the signal flow, it is checked whether the portion of the block output of the preceding block corresponding to the intersection is connected to the data storage write block without a signal flow branch, and whether the block output variable of the preceding block is consistent with the at least partially connected portion in the signal flow in terms of dimension and data type, wherein if these additional conditions are met, the block output variable of the preceding block is replaced by the portion of the data storage variable corresponding to the intersection.

9. The method according to claim 1, characterized in that, The block diagram is defined hierarchically, where a block in a higher level can include multiple blocks in lower levels, and each block in the lower level is assigned to a block in the higher level. Specifically, if an equality assignment is checked on the first data storage write block, then other data storage write blocks accessing the same data storage variable are searched within the comprehensive hierarchical blocks, and... As an exclusion reason for the association of variables in the block pair that replaces the first data storage write block, for each other data storage write block found, it is checked whether the other data storage write block writes to the part of the data storage variable that is also described by the first data storage write block. If the exclusion reason exists, the association of the output variable of the preceding block is not replaced by the association of the part of the data storage variable described by the first data storage write block, even if there is an equivalent assignment.

10. The method according to claim 1, characterized in that, Variables can be assigned as states that affect the output value at the next time step. Even if there is an equivalence assignment between the first and second variables in a block pair, the association of the first variable is replaced by the association of the second variable only if the first variable is not assigned as a state and / or the second variable is assigned as a state.

11. The method according to claim 1, characterized in that, Even if there is an equality assignment between the first and second variables in a block pair, the association of the second variable shall not be replaced by the association of the first variable if one or more of the exclusion reasons mentioned below exist: -The first and second variables have different dimensions. - At least one element in the first variable has a different data type than the corresponding element in the second variable. - The first variable is specified as necessary. - Unpredictable data flow exists due to the execution order of signal flow branches and / or connected blocks.

12. The method according to claim 11, characterized in that, The block diagram is defined hierarchically, where if a block in a higher level includes multiple blocks in a lower level, then all blocks in the lower level are checked for exclusion reasons.

13. The method according to claim 11, characterized in that, In cases where there are only equivalent assignments for the first and second variables, only those portions are considered in the exclusion reasons.

14. The method according to claim 2, characterized in that, The output block includes a bus output block that models the output to the bus.

15. A method for configuring a control unit, wherein, The control unit includes at least one computing unit, and the method includes: a. Read in the flowchart; b. Generate source code using the method according to any one of claims 1 to 14; c. Compile the source code used for the computing unit to generate executable code; d. Transfer the executable code to the control unit; and e. Store the executable code in the non-volatile memory of the control unit and / or execute the executable code through the computing unit of the control unit.

16. The method according to claim 15, characterized in that, The control unit has at least one sensor and / or at least one actuator to detect data of the physical process and / or influence the physical process.

17. A computer program product having a computer-readable storage medium, wherein instructions are embedded on the computer-readable storage medium, the instructions, when executed by a processor, cause the processor to be configured to perform the method according to any one of claims 1 to 14.

18. A computer system comprising a human-computer interface, non-volatile memory, and a processor, said processor being configured to perform the method according to any one of claims 1 to 14.

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