A multi-core tensor processor based on distributed on-chip storage
By using a multi-core tensor processor with distributed on-chip storage, a modular interconnect structure, and a channel selection module, the problem of high interconnect device quantity and bandwidth requirements is solved, achieving high-performance computing and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN YIPU SMART TECH CO LTD
- Filing Date
- 2022-10-28
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies cannot meet the interconnection requirements of neural network multi-core tensor processors with high interconnection device counts and high interconnection bandwidth requirements. At the same time, there is a "memory wall" problem that limits the computing performance of multi-core tensor processors.
The distributed on-chip storage based on a modular interconnect structure is adopted. The in-memory computing module includes a tensor processor and on-chip memory, which are interconnected in a head-to-tail manner. The MUX2, MUX3, DEMUX2, DEMUX3 modules and an arbitration module are used for channel selection and arbitration to achieve high-bandwidth interconnection.
It achieves high-performance computing in multi-core systems, breaks the "memory wall" limitation, and has excellent scalability and high-bandwidth interconnect capabilities.
Smart Images
Figure CN115796248B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of neural network tensor processors, and in particular to a multi-core tensor processor based on distributed on-chip storage. Background Technology
[0002] Existing SoC (System on Chip) systems use a bus architecture to enable data interaction between modules within the system. This bus typically follows a standard protocol (such as the AMBA protocol), allowing any module conforming to this protocol to easily connect to the bus and access or be accessed by other modules on the bus.
[0003] Buses generally employ two technical solutions: multiplexer buses and crossbar buses. A multiplexer bus can provide interconnection functionality for M master devices and N slave devices, but only one master device can access one slave device at a time. A crossbar bus can also provide interconnection functionality for M master devices and N slave devices, and allows M devices to access M slave devices simultaneously, provided that the master devices' access targets do not conflict (assuming the number of master devices M is less than the number of slave devices N).
[0004] Multiplexer bus solutions are simple to design, have low power consumption and area overhead, can connect a large number of devices, and have high scalability, making them suitable for systems with low bus bandwidth requirements. Crossbar switch buses are more complex to design, have higher power consumption and area overhead, and the area and power consumption increase accordingly as the number of devices increases, making them suitable for systems with high bus bandwidth requirements but a small number of modules.
[0005] For tensor processors, especially multi-core tensor processors, the number of processor cores can be quite large, such as 1024. On the other hand, neural network multi-core tensor processors are typically used to perform computational tasks with high data volumes, requiring high bandwidth in the interconnect architecture. Therefore, traditional multiplexer buses and crossbar switches cannot meet the interconnect requirements of neural network multi-core tensor processors with a high number of interconnect devices and high interconnect bandwidth requirements.
[0006] Furthermore, for multi-core tensor processors, computational performance is determined by both computing power and memory bandwidth. Traditional solutions use off-chip memory (such as DDR DRAM) to store data. Since the bandwidth of off-chip memory is usually limited by a specific value imposed by the physical interface, there is a common situation where the computing power of a multi-core tensor processor increases but the off-chip memory bandwidth remains unchanged. This is the well-known "memory wall" problem, where memory bandwidth limits the processor's computational performance. Summary of the Invention
[0007] To address the aforementioned problems, this invention proposes a multi-core tensor processor based on distributed on-chip storage. The multi-core tensor processor employs a distributed on-chip storage structure based on a modular interconnect architecture. The number of on-chip memories is proportional to the number of cores in the tensor processor, and the modular interconnect architecture provides high-bandwidth interconnects.
[0008] The technical solution of the present invention is as follows:
[0009] A multi-core tensor processor based on distributed on-chip storage, the multi-core tensor processor comprising n in-memory computing modules; each in-memory computing module includes two master device interfaces M0, M1 and two slave device interfaces S0, S1; the master device interface and the slave device interface are composed of read / write channels and read / write return channels;
[0010] The n in-memory computing modules are interconnected in a head-to-tail manner; the master device interface M1 of the (n-1)th in-memory computing module is connected to the slave device interface S0 of the nth in-memory computing module; the slave device interface S1 of the (n-1)th in-memory computing module is connected to the master device interface M0 of the nth in-memory computing module; the master device interface M0 of the (n-1)th in-memory computing module is connected to the slave device interface S1 of the (n-2)th in-memory computing module; the slave device interface S0 of the (n-1)th in-memory computing module is connected to the master device interface M1 of the (n-2)th in-memory computing module.
[0011] The in-memory computing module includes a tensor processor, on-chip memory, a MUX2 module, a MUX3 module, a DEMUX2 module, a DEMUX3 module, an address decoding module, a tag decoding module, and an arbitration module;
[0012] The tensor processor sends read address or write address information to the on-chip memory through the read / write channel, and receives read data or write confirmation information from the on-chip memory through the read / write return channel.
[0013] The on-chip memory is used to store the data required for calculations by the tensor processor.
[0014] The MUX2 module and DEMUX2 module are dual-channel selection modules; there are two MUX2 modules, which are used for channel selection of slave device interfaces S0 and S1 respectively; there are two DEMUX2 modules, which are used for channel selection of master device interfaces M0 and M1 respectively.
[0015] The MUX3 module and DEMUX3 module are three-channel selection modules; the MUX3 module is used for channel selection of the on-chip memory; the DEMUX3 module is used for channel selection of the tensor processor.
[0016] Inside the in-memory computing module, the slave device interface S0 is connected to the DEMUX3 module of the tensor processor and the DEMUX2 module of the master device interface M1 via the MUX2 module; the tensor processor is connected to the slave device interface S0 via the DEMUX3 module and the MUX2 module of the slave device interface S0; the master device interface M1 is connected to the slave device interface S0 via the DEMUX2 module of the master device interface M1 and the MUX2 module of the slave device interface S0.
[0017] Inside the in-memory computing module, the slave interface S1 is connected to the DEMUX3 module of the tensor processor and the DEMUX2 module of the master interface M0 via the MUX2 module; the tensor processor is connected to the slave interface S1 via the DEMUX3 module and the MUX2 module of the slave interface S1; the master interface M0 is connected to the slave interface S1 via the DEMUX2 module of the master interface M0 and the MUX2 module of the slave interface S1.
[0018] Inside the in-memory computing module, the master device interface M0 is connected to the on-chip memory's MUX3 module and the slave device interface S1's MUX2 module via the DEMUX2 module; the on-chip memory is connected to the master device interface M0 via the MUX3 module and the master device interface M0's DEMUX2 module; the slave device interface S1 is connected to the master device interface M0 via the slave device interface S1's MUX2 module and the master device interface M0's DEMUX2 module.
[0019] Inside the in-memory computing module, the master device interface M1 is connected to the on-chip memory's MUX3 module and the slave device interface S0's MUX2 module via the DEMUX2 module; the on-chip memory is connected to the master device interface M1 via the MUX3 module and the master device interface M1's DEMUX2 module; the slave device interface S0 is connected to the master device interface M1 via the slave device interface S0's MUX2 module and the master device interface M1's DEMUX2 module.
[0020] Inside the in-memory computing module, the tensor processor is connected to the on-chip memory's MUX3 module, the slave device interface S0's MUX2 module, and the slave device interface S1's MUX2 module via the DEMUX3 module. The tensor processor's read / write requests are sent to the local on-chip memory via the DEMUX3 module, or to any on-chip memory located in other in-memory computing modules via S0 or the slave device interface S1.
[0021] The address decoding module obtains the address of the read / write channel and, based on the built-in fixed address range and port mapping information, determines the channel selection of the internal data distributor of the DEMUX2 module or the DEMUX3 module.
[0022] The tag decoding module obtains the tag of the read / write return channel and determines the channel selection of the data distributor inside the MUX2 module or MUX3 module based on the built-in fixed tag and port mapping information.
[0023] The arbitration module obtains valid request information for the read / write channel or read / write return channel, and determines the channel selection of the DEMUX2 module, DEMUX3 module, MUX2 module, or the multiplexer inside the MUX3 module based on the built-in fixed priority.
[0024] Furthermore, the MUX2 module internally includes a dual-channel data distributor and a 2-to-1 multiplexer; the dual-channel data distributor is used to select one of the two output read / write return channels and connect it to the input read / write return channel, the channel selection being determined by the tag decoding module; the 2-to-1 multiplexer is used to select one of the two input read / write channels and connect it to the output read / write channel, the channel selection being determined by the arbitration module.
[0025] Furthermore, the MUX3 module internally includes a three-way data distributor and a three-to-one multiplexer; the three-way data distributor is used to select one of the three output read / write return channels and connect it to the input read / write return channel, and the channel selection is determined by the tag decoding module; the three-to-one multiplexer is used to select one of the three input read / write channels and connect it to the output read / write channel, and the channel selection is determined by the arbitration module.
[0026] Furthermore, the DEMUX2 module internally includes a dual-channel data distributor and a 2-to-1 multiplexer; the dual-channel data distributor is used to select one of the two output read / write channels and connect it to the input read / write channel, and the channel selection is determined by the address decoding module; the 2-to-1 multiplexer is used to select one of the two input read / write return channels and connect it to the output read / write return channel, and the channel selection is determined by the arbitration module.
[0027] Furthermore, the DEMUX3 module is a three-channel selection module, which internally includes a three-channel data distributor and a three-to-one multiplexer. The three-channel data distributor is used to select one channel from the three output read / write channels and connect it to the input read / write channel. The channel selection is determined by the address decoding module. The three-to-one multiplexer is used to select one channel from the three input read / write return channels and connect it to the output read / write return channel. The channel selection is determined by the arbitration module.
[0028] Furthermore, each in-memory computing module is assigned a unique ID number; this ID number is sent to the on-chip memory by the tensor processor via the read / write channel as supplementary information; when the on-chip memory responds to a read / write request from the read / write channel, it adds the corresponding ID number to the corresponding read / write return channel information, and this ID number is the tag of the read / write return channel.
[0029] Furthermore, the read / write channel is configured as a single channel with shared read and write information, or a dual channel with separate read and write information; the read / write return channel is configured as a single channel with shared read and write information, or a dual channel with separate read and write information.
[0030] This invention achieves the following technical effects:
[0031] The in-memory computing module of this invention includes a tensor processor for computation and an on-chip memory for storage. The tensor processor and on-chip memory within the in-memory computing module can form a complete computing system to perform neural network algorithm calculations. Therefore, increasing the number of in-memory computing modules can simultaneously increase computing power and storage bandwidth, thus breaking the "memory wall" limitation and achieving high performance in multi-core systems. On the other hand, based on the structured characteristics of the in-memory computing module, N-fold expansion of the in-memory computing module does not lead to an increase in interconnect complexity, and N-fold expansion of the in-memory computing module can be relatively easily achieved. Therefore, this invention has excellent scalability characteristics. Attached Figure Description
[0032] Figure 1 This is a schematic diagram showing the connection between the two in-memory computing modules of the present invention;
[0033] Figure 2 This is a schematic diagram showing the connection of n in-memory computing modules of the present invention;
[0034] Figure 3 This is the internal structure of the in-memory computing module of the present invention;
[0035] Figure 4 This is a functional diagram of the MUX2 module involved in the present invention;
[0036] Figure 5 This is a functional diagram of the MUX3 module involved in the present invention;
[0037] Figure 6 This is a functional diagram of the DEMUX2 module involved in the present invention;
[0038] Figure 7 This is a functional diagram of the DEMUX3 module involved in this invention. Detailed Implementation
[0039] To further illustrate the various embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention, primarily used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementations and the advantages of the present invention.
[0040] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.
[0041] This invention proposes a multi-core tensor processor based on distributed on-chip storage. The multi-core tensor processor consists of multiple in-memory computing modules. For example... Figure 1 As shown, the in-memory computing module includes two master device interfaces M0 and M1, and two slave device interfaces S0 and S1. Each master and slave device interface consists of a read / write channel and a read / write return channel. The read / write channel is the data channel from the master device interface to the slave device interface, primarily used for sending read or write addresses and other related information from the master device interface to the slave device interface. The read / write return channel is the data channel from the slave device interface to the master device interface, primarily used for sending read data or write confirmations and other related information from the slave device interface to the master device interface.
[0042] Multiple in-memory computing modules are interconnected using a head-to-tail connection method, with the connection rules as follows: Figure 2 As shown: the master device interface M1 of the in-memory computing module n-1 is connected to the slave device interface S0 of the in-memory computing module n; the slave device interface S1 of the in-memory computing module n-1 is connected to the master device interface M0 of the in-memory computing module n; the master device interface M0 of the in-memory computing module n-1 is connected to the slave device interface S1 of the in-memory computing module n-2; the slave device interface S0 of the in-memory computing module n-1 is connected to the master device interface M1 of the in-memory computing module n-2.
[0043] The internal structure of the in-memory computing module is as follows: Figure 3 and Figure 4 As shown, A / W represents the read / write channel, and R represents the read / write return channel.
[0044] The in-memory computing module consists of a tensor processor, on-chip memory, MUX2 module, MUX3 module, DEMUX2 module, DEMUX3 module, address decoding module, tag decoding module, and arbitration module.
[0045] The tensor processor refers to a processor that performs neural network algorithm calculations. The tensor processor sends read or write address information to the on-chip memory via a read / write channel and receives read data or write confirmation information from the on-chip memory via a read / write return channel. The on-chip memory refers to the memory located inside the chip, used to store the data required for the tensor processor's calculations.
[0046] The MUX2 module is a dual-channel selection module, internally containing a dual-channel data distributor and a 2-to-1 multiplexer. The dual-channel data distributor selects one channel from two output read / write return channels and connects it to the input read / write return channel; the channel selection is determined by the tag decoding module. The 2-to-1 multiplexer selects one channel from two input read / write channels and connects it to the output read / write channel; the channel selection is determined by the arbitration module.
[0047] The MUX3 module is a three-channel selection module, internally containing a three-channel data distributor and a three-to-one multiplexer. The three-channel data distributor selects one channel from the three output read / write return channels and connects it to the input read / write return channel; the channel selection is determined by the tag decoding module. The three-to-one multiplexer selects one channel from the three input read / write channels and connects it to the output read / write channel; the channel selection is determined by the arbitration module.
[0048] The DEMUX2 module is a dual-channel selection module, internally containing a dual-channel data distributor and a 2-to-1 multiplexer. The dual-channel data distributor selects one of the two output read / write channels and connects it to the input read / write channel; the channel selection is determined by the address decoding module. The 2-to-1 multiplexer selects one of the two input read / write return channels and connects it to the output read / write return channel; the channel selection is determined by the arbitration module.
[0049] The DEMUX3 module is a three-channel selection module, internally containing a three-channel data distributor and a three-to-one multiplexer. The three-channel data distributor selects one channel from the three output read / write channels and connects it to the input read / write channel; the channel selection is determined by the address decoding module. The three-to-one multiplexer selects one channel from the three input read / write return channels and connects it to the output read / write return channel; the channel selection is determined by the arbitration module.
[0050] The address decoding module obtains the address of the read / write channel and, based on the built-in fixed address range and port mapping information, determines the channel selection of the internal data distributor of the DEMUX2 or DEMUX3 module.
[0051] The tag decoding module obtains the tag of the read / write return channel and determines the channel selection of the data distributor inside the MUX2 or MUX3 module based on the built-in fixed tag and port mapping information.
[0052] The arbitration module obtains valid request information for the read / write channel or read / write return channel, and determines the channel selection of the multiplexer inside the DEMUX2, DEMUX3, MUX2, or MUX3 module based on the built-in fixed priority.
[0053] The address decoding module, tag decoding module, and arbitration module are general-purpose modules for the processor. Relevant technical personnel can generate corresponding modules based on the parameter requirements (such as data interface width, number of data channels, etc.) of modules such as MUX2, MUX3, DEMUX2, and DEMUX3.
[0054] The multi-core tensor processor based on distributed on-chip storage consists of multiple in-memory computing modules, each assigned a unique ID. This ID, as supplementary information, is sent by the tensor processor to the on-chip memory via read / write channels. When responding to a read / write request from a read / write channel, the on-chip memory adds the corresponding ID to the relevant read / write return channel information; this ID serves as the tag for the read / write return channel.
[0055] The specific connection relationships within the in-memory computing module are as follows:
[0056] Within the in-memory computing module, the slave interface S0 is connected to the DEMUX3 module of the tensor processor and the DEMUX2 module of the master interface M1 via the MUX2 module. The tensor processor can be connected to the slave interface S0 via the DEMUX3 module and the MUX2 module of the slave interface S0. The master interface M1 can be connected to the slave interface S0 via the DEMUX2 module of the master interface M1 and the MUX2 module of the slave interface S0.
[0057] Within the in-memory computing module, the slave interface S1 is connected to both the tensor processor's DEMUX3 module and the master interface M0's DEMUX2 module via the MUX2 module. The tensor processor can connect to the slave interface S1 via the DEMUX3 module and the slave interface S1's MUX2 module. Similarly, the master interface M0 can connect to the slave interface S1 via the master interface M0's DEMUX2 module and the slave interface S1's MUX2 module.
[0058] Within the in-memory computing module, the master device interface M0 is connected to the on-chip memory's MUX3 module and the slave device interface S1's MUX2 module via the DEMUX2 module. The on-chip memory can be connected to the master device interface M0 via the MUX3 module and the master device interface M0's DEMUX2 module. Similarly, the slave device interface S1 can be connected to the master device interface M0 via the slave device interface S1's MUX2 module and the master device interface M0's DEMUX2 module.
[0059] Within the in-memory computing module, the master device interface M1 is connected to the on-chip memory's MUX3 module and the slave device interface S0's MUX2 module via the DEMUX2 module. The on-chip memory can be connected to the master device interface M1 via the MUX3 module and the master device interface M1's DEMUX2 module. Similarly, the slave device interface S0 can be connected to the master device interface M1 via the slave device interface S0's MUX2 module and the master device interface M1's DEMUX2 module.
[0060] Within the in-memory computing module, the tensor processor is connected to the on-chip memory's MUX3 module, the slave device interface S0's MUX2 module, and the slave device interface S1's MUX2 module via the DEMUX3 module. Read / write requests from the tensor processor can be sent to the local on-chip memory via the DEMUX3 module, or via S0 or the slave device interface S1 to any on-chip memory located in other in-memory computing modules.
[0061] The multi-core tensor processor based on distributed on-chip storage can have a single channel for sharing read and write information, or a dual channel for separating read and write operations. Similarly, the read / write return channel can also be a single channel for sharing read and write information, or a dual channel for separating read and write operations.
[0062] The in-memory computing module includes a tensor processor for computation and on-chip memory for storage. The tensor processor and on-chip memory within the in-memory computing module can form a complete computing system to perform neural network algorithm calculations. Therefore, increasing the number of in-memory computing modules can simultaneously increase computing power and storage bandwidth. Ideally, through compiler software, the neural network algorithm can be divided into N parts, loaded into N in-memory computing modules, and the N tensor processors can simultaneously access the N on-chip memories to complete the computation. Compared to a single in-memory computing module, the computing power and storage bandwidth of N in-memory computing modules can be increased by N times. Therefore, the "memory wall" limitation can be broken to achieve high performance in multi-core systems. On the other hand, based on the structured characteristics of the in-memory computing module, an N-fold expansion of the in-memory computing module does not lead to an increase in interconnect complexity, and an N-fold expansion of the in-memory computing module can be relatively easily implemented. Therefore, this invention has excellent scalability characteristics.
[0063] Although the invention has been specifically shown and described in conjunction with preferred embodiments, those skilled in the art should understand that various changes in form and detail may be made to the invention without departing from the spirit and scope of the invention as defined in the appended claims, all of which shall be within the scope of protection of the invention.
Claims
1. A distributed on-chip memory based many-core tensor processor, characterized in that, The multi-core tensor processor includes n in-memory computing modules; each in-memory computing module includes two master device interfaces M0 and M1 and two slave device interfaces S0 and S1; the master device interface and the slave device interface are composed of a read / write channel and a read / write return channel. The n in-memory computing modules are interconnected in a head-to-tail manner; the master device interface M1 of the (n-1)th in-memory computing module is connected to the slave device interface S0 of the nth in-memory computing module; the slave device interface S1 of the (n-1)th in-memory computing module is connected to the master device interface M0 of the nth in-memory computing module; the master device interface M0 of the (n-1)th in-memory computing module is connected to the slave device interface S1 of the (n-2)th in-memory computing module; the slave device interface S0 of the (n-1)th in-memory computing module is connected to the master device interface M1 of the (n-2)th in-memory computing module. The in-memory computing module includes a tensor processor, on-chip memory, a MUX2 module, a MUX3 module, a DEMUX2 module, a DEMUX3 module, an address decoding module, a tag decoding module, and an arbitration module; The tensor processor sends read address or write address information to the on-chip memory through the read / write channel, and receives read data or write confirmation information from the on-chip memory through the read / write return channel. The on-chip memory is used to store the data required for calculations by the tensor processor. The MUX2 module and DEMUX2 module are dual-channel selection modules; there are two MUX2 modules, which are used for channel selection of slave device interfaces S0 and S1 respectively; there are two DEMUX2 modules, which are used for channel selection of master device interfaces M0 and M1 respectively. The MUX3 module and the DEMUX3 module are three-channel selection modules; the MUX3 module is used for channel selection of the on-chip memory; the DEMUX3 module is used for channel selection of the tensor processor. Inside the in-memory computing module, the slave device interface S0 is connected to the DEMUX3 module of the tensor processor and the DEMUX2 module of the master device interface M1 via the MUX2 module; the tensor processor is connected to the slave device interface S0 via the DEMUX3 module and the MUX2 module of the slave device interface S0; the master device interface M1 is connected to the slave device interface S0 via the DEMUX2 module of the master device interface M1 and the MUX2 module of the slave device interface S0. Inside the in-memory computing module, the slave device interface S1 is connected to the tensor processor's DEMUX3 module and the master device interface M0's DEMUX2 module via the MUX2 module. The tensor processor is connected to the slave interface S1 via the DEMUX3 module and the MUX2 module of the slave interface S1; the master interface M0 is connected to the slave interface S1 via the DEMUX2 module of the master interface M0 and the MUX2 module of the slave interface S1. Inside the in-memory computing module, the master device interface M0 is connected to the on-chip memory MUX3 module and the slave device interface S1 MUX2 module through the DEMUX2 module; the on-chip memory is connected to the master device interface M0 through the MUX3 module and the master device interface M0 DEMUX2 module. The slave device interface S1 is connected to the master device interface M0 through the MUX2 module of the slave device interface S1 and the DEMUX2 module of the master device interface M0; Inside the in-memory computing module, the master device interface M1 is connected to the on-chip memory MUX3 module and the slave device interface S0 MUX2 module through the DEMUX2 module; the on-chip memory is connected to the master device interface M1 through the MUX3 module and the master device interface M1 DEMUX2 module. The slave device interface S0 is connected to the master device interface M1 through the MUX2 module of the slave device interface S0 and the DEMUX2 module of the master device interface M1; Inside the in-memory computing module, the tensor processor is connected to the MUX3 module of the on-chip memory, the MUX2 module of the slave device interface S0, and the MUX2 module of the slave device interface S1 via the DEMUX3 module. The read / write requests of the tensor processor are sent to the local on-chip memory via the DEMUX3 module, or to any on-chip memory located in other in-memory computing modules via the slave device interface S0 or the slave device interface S1. The address decoding module obtains the address of the read / write channel and, based on the built-in fixed address range and port mapping information, determines the channel selection of the internal data distributor of the DEMUX2 module or the DEMUX3 module. The tag decoding module obtains the tag of the read / write return channel and determines the channel selection of the data distributor inside the MUX2 module or MUX3 module based on the built-in fixed tag and port mapping information. The arbitration module obtains valid request information for the read / write channel or read / write return channel, and determines the channel selection of the DEMUX2 module, DEMUX3 module, MUX2 module, or the multiplexer inside the MUX3 module based on the built-in fixed priority.
2. The distributed on-chip memory based many-core tensor processor of claim 1, wherein, The MUX2 module contains a dual-channel data distributor and a 2-to-1 multiplexer; the dual-channel data distributor is used to select one channel from two output read / write return channels and connect it to the input read / write return channel, and the channel selection is determined by the tag decoding module. The two-to-one multiplexer is used to select one of the two input read / write channels and connect it to the output read / write channel. The channel selection is determined by the arbitration module.
3. The multi-core tensor processor based on distributed on-chip storage as described in claim 1, characterized in that, The MUX3 module contains a three-way data distributor and a three-to-one multiplexer. The three-way data distributor is used to select one of the three output read / write return channels and connect it to the input read / write return channel. The channel selection is determined by the tag decoding module. The three-to-one multiplexer is used to select one of the three input read / write channels and connect it to the output read / write channel. The channel selection is determined by the arbitration module.
4. The multi-core tensor processor based on distributed on-chip storage as described in claim 1, characterized in that, The DEMUX2 module contains a dual-channel data distributor and a 2-to-1 multiplexer. The dual-channel data distributor is used to select one of the two output read / write channels and connect it to the input read / write channel. The channel selection is determined by the address decoding module. The two-to-one multiplexer is used to select one of the two input read / write return channels and connect it to the output read / write return channel. The channel selection is determined by the arbitration module.
5. The multi-core tensor processor based on distributed on-chip storage as described in claim 1, characterized in that, The DEMUX3 module is a three-channel selection module, which internally contains a three-channel data distributor and a three-to-one multiplexer; the three-channel data distributor is used to select one channel from the three output read / write channels and connect it to the input read / write channel, and the channel selection is determined by the address decoding module; The three-to-one multiplexer is used to select one of the three input read / write return channels and connect it to the output read / write return channel. The channel selection is determined by the arbitration module.
6. The multi-core tensor processor based on distributed on-chip storage as described in claim 1, characterized in that, Each in-memory computing module is assigned a unique ID number; this ID number, as supplementary information, is sent to the on-chip memory by the tensor processor via a read / write channel. When the on-chip memory responds to a read / write request from the read / write channel, it adds the corresponding ID number to the corresponding read / write return channel information. This ID number is the tag of the read / write return channel.
7. The multi-core tensor processor based on distributed on-chip storage as described in claim 1, characterized in that, The read / write channel is configured as a single channel with shared read and write information, or a dual channel with separate read and write information; the read / write return channel is configured as a single channel with shared read and write information, or a dual channel with separate read and write information.