Shift register, display panel

Abstract

The present invention discloses a shift register and a display panel. The shift register includes: a first power supply introduction submodule, a first output submodule, a first trigger writing submodule, a second power supply introduction submodule, a second output submodule, a second trigger writing submodule, and a first feedback submodule; the second power supply introduction submodule is configured to write the first power supply signal to the third node according to the first light-emitting control signal; the second trigger writing submodule is configured to write the potential of the second node to the fourth node according to the second light-emitting control signal; and the second output submodule is configured to output the first power supply signal or the second power supply signal according to the potentials of the third and fourth nodes; wherein, within a frame time, the end time of the pulse of the first light-emitting control signal and the start time of the second light-emitting control signal are both later than the end time of the pulse of the trigger signal. The present invention can output two scanning signals using a single shift register.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register and a display panel. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more extensive, and the corresponding requirements for display technology are also becoming higher and higher.

[0003] Pixel circuits in existing display panels usually require multiple scanning signals, and the display panel usually requires a shift register to provide the scanning signals. However, the existing shift register can only output one form of scanning signal, which limits the further development of display technology. Summary of the Invention

[0004] The present invention provides a shift register and a display panel, which can output two scanning signals by using one shift register.

[0005] According to one aspect of the present invention, there is provided a shift register, comprising:

[0006] a first power supply introduction submodule, a first output submodule, a first trigger writing submodule, a second power supply introduction submodule, a second output submodule, a second trigger writing submodule, and a first feedback submodule;

[0007] The first power introduction submodule is configured to write the first power signal into the first node according to the first clock signal;

[0008] The first trigger writing submodule is configured to write a trigger signal into the second node according to the first clock signal;

[0009] The first output submodule is configured to output a second clock signal or a second power supply signal according to the potentials of the first node and the second node;

[0010] The second power supply introduction submodule is configured to write the first power supply signal into the third node according to the first light emitting control signal;

[0011] The second trigger writing submodule is configured to write the potential of the second node into the fourth node according to the second light emitting control signal;

[0012] The second output submodule is configured to output a first power signal or a second power signal according to the potentials of the third node and the fourth node;

[0013] The first feedback submodule is configured to write a second power supply signal into the third node according to the potential of the fourth node;

[0014] Wherein, within one frame time, the end time of the pulse of the first light-emitting control signal and the start time of the second light-emitting control signal are both later than the end time of the pulse of the trigger signal.

[0015] Optionally, pulses of the first light emitting control signal and the second light emitting control signal at least partially overlap;

[0016] Preferably, the second light-emitting control signal and the first light-emitting control signal are the same signal.

[0017] Optionally, within one frame time, the pulse start time of the first light-emitting control signal is earlier than or equal to the pulse start time of the trigger signal.

[0018] Optionally, the shift register further includes a third power introduction submodule, which is connected between the second power introduction submodule and the third node, and is configured to be turned on or off according to the second light-emitting control signal.

[0019] Optionally, the first output submodule includes:

[0020] a first pull-up submodule, wherein a first end of the first pull-up submodule is connected to a second power signal, and a control end of the first pull-up submodule is electrically connected to the first node;

[0021] a first pull-down submodule, wherein a first end of the first pull-down submodule is connected to a second clock signal, a control end of the first pull-down submodule is electrically connected to the second node, and a second end of the first pull-down submodule is electrically connected to the second end of the first pull-up submodule to serve as an output end of the first output submodule.

[0022] Optionally, the second output submodule includes:

[0023] a second pull-up submodule, wherein a first terminal of the second pull-up submodule is connected to a second power signal, and a control terminal of the second pull-up submodule is electrically connected to the third node;

[0024] a second pull-down submodule, wherein the first end of the second pull-down submodule is connected to the first power supply signal, the control end of the second pull-down submodule is electrically connected to the fourth node, and the second end of the second pull-down submodule is electrically connected to the second end of the second pull-up submodule to serve as the output end of the second output submodule.

[0025] Optionally, the second output submodule further includes:

[0026] a first coupling unit, wherein a first end of the first coupling unit is electrically connected to a first end of the second pull-up submodule, and a second end of the first coupling unit is electrically connected to a control end of the second pull-up submodule;

[0027] A second coupling unit, wherein a first end of the second coupling unit is electrically connected to the control end of the second pull-down submodule, and a second end of the second coupling unit is electrically connected to the second end of the second pull-down submodule.

[0028] Optionally, the second power introduction submodule includes a first transistor, the first feedback submodule includes a second transistor, and a channel width-to-length ratio of the second transistor is greater than a channel width-to-length ratio of the first transistor.

[0029] According to another aspect of the present invention, a display panel is provided, which includes a display area and a non-display area, wherein a plurality of pixel circuits are arranged in the display area, and a first gate drive circuit is arranged in the non-display area, wherein the first gate drive circuit includes a cascade of multiple stages of shift registers as described above, and wherein the shift register is used to provide a scanning signal to the pixel circuits of the corresponding rows.

[0030] Optionally, a second gate driving circuit is further provided in the non-display area, and the second gate driving circuit includes n-level light emitting control signal output terminals for providing light emitting control signals to pixel circuits of corresponding rows;

[0031] The m-th stage light emitting control signal output terminal of the second gate driving circuit is used to output the first light emitting control signal and the second light emitting control signal to the m-th stage shift register in the first gate driving circuit;

[0032] Alternatively, the mth level light-emitting control signal output terminal of the second gate driving circuit is used to provide a second light-emitting control signal to the mth level shift register in the first gate driving circuit, and the m-1th level light-emitting control signal output terminal of the second gate driving circuit is used to provide a first light-emitting control signal to the mth level shift register in the first gate driving circuit.

[0033] The technical solution of the embodiment of the present invention adopts a shift register, which, by setting a second power supply introduction submodule, a second trigger writing submodule, a second output submodule and a first feedback submodule, cooperates with the second node, the first light-emitting control signal and the second light-emitting control signal, so that the shift register can output an output signal shifted relative to the trigger signal and an output signal with adjustable pulse width. That is, by using one shift register to output two output signals, two scanning signals can be provided for the pixel circuit, which greatly simplifies the design of the display panel.

[0034] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0037] Figure 2 A timing diagram of a shift register provided by an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0039] Figure 4 A timing diagram of another shift register provided in an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0041] Figure 6 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0042] Figure 7 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0043] Figure 8 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] Figure 1 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 2 A timing diagram of a shift register provided by an embodiment of the present invention, Figure 2 and Figure 1 Corresponding, combining Figure 1 and Figure 2 The shift register includes: a first power supply introduction submodule 11, a first output submodule 12, a first trigger writing submodule 13, a second power supply introduction submodule 14, a second output submodule 15 and a second trigger writing submodule 16; the first power supply introduction submodule 11 is configured to write the first power supply signal VGL into the first node N1 according to the first clock signal SCK1; the first trigger writing submodule 13 is configured to write the trigger signal Sn-1 into the second node N2 according to the first clock signal SCK1; the first output submodule 12 is configured to output the second clock signal SCK according to the potential of the first node N1 and the second node N2 2 or the second power signal VGH; the second power introduction submodule 14 is configured to write the first power signal VGL into the third node N3 according to the first light-emitting control signal; the second trigger writing submodule 16 is configured to write the potential of the second node N2 into the fourth node N4 as the second light-emitting control signal; the second output submodule 15 is configured to output the first power signal VGL or the second power signal VGH according to the potentials of the third node N3 and the fourth node N4; wherein, within one frame time, the pulse end time of the first light-emitting control signal and the pulse start time of the second light-emitting control signal are both later than the pulse end time of the trigger signal Sn-1.

[0047] Specifically, the shift register can shift the input trigger signal Sn-1 and output it from its output terminal. In this embodiment, the first output submodule 12 can adjust its output signal based on the potentials of the first node N1 and the second node N2, so that the output signal of the first output submodule 12 is shifted relative to the trigger signal Sn-1. When the first node N1 is at an effective potential, the first output submodule 12 outputs the second power supply signal VGH. When the second node N2 is at an effective potential, the first output submodule 12 outputs the second clock signal SCK2. It should be noted that the effective potential described in this embodiment can be either a low level or a high level. The following description uses the effective potential being a low level as an example. The first power supply signal VGL and the second power supply signal VGH have different high and low levels. The first power supply signal VGL can be at a low level, and the second power supply signal VGH can be at a high level accordingly. The first clock signal SCK1 and the second clock signal SCK2 can be clock signals with opposite phases. Of course, there can be a certain timing margin between the effective levels of the first clock signal SCK1 and the second clock signal SCK2. The second output submodule 15 can adjust its output signal according to the potentials of the third node N3 and the fourth node N4. For example, when the third node N3 is at a valid potential, the second output submodule 15 outputs the second power signal VGH. When the fourth node N4 is at a valid potential, the second output submodule outputs the first power signal VGL.

[0048] The working process of the shift register can be divided into five stages:

[0049] During phase T1, trigger signal Sn-1 is high, and a high level is also written to the second node N2. Since the second output submodule 15 is expected to output a high level at this time, the first light-emitting control signal can be either low or high. When the first light-emitting control signal is high, the parasitic parameters within the second output submodule 15 can ensure that the second output submodule 15 maintains a high output level. The second light-emitting control signal is low, turning on the second trigger writing submodule 16 and writing a high level to the fourth node N4. Simultaneously, when the first clock signal SCK1 is low, the first power supply introduction submodule 11 and the first trigger writing submodule 13 are turned on, causing the first power supply signal VGL (low) to be written to the first node N1. Consequently, the first output submodule 12 outputs the second power supply signal VGH (high). When the first trigger writing submodule 13 is turned on, the trigger signal Sn-1 is written to the second node N2. Trigger signal Sn-1 is now high, so the second node N2 is high. In summary, in the stage T1 , the output signal Sn of the first output submodule 12 and the output signal Sm of the second output submodule 15 are both at a high level.

[0050] During phase T2, the trigger signal Sn-1 transitions to a low level, the first clock signal SCK1 is low, and the second clock signal SCK2 is high. At this point, the first power supply introduction submodule 11 and the first trigger write submodule 13 are turned on, causing the first node N1 to be written at a low level. The second node N2 is also at a low level. However, since the second clock signal SCK2 is high, the first output submodule 12 outputs two signals, but there is no competition between them, and the output signal Sn remains high. At this point, the first light-emitting control signal can be either low or high. For example, if the first light-emitting control signal is low, the second power supply introduction submodule 14 is turned on. However, since the second node N2 is low, the pulse start time of the second light-emitting control signal is later than the pulse end time of the trigger signal. This means that the high-level pulse of the second light-emitting control signal has not yet arrived, and the second light-emitting control signal remains low. This also means that the second trigger write submodule 16 is turned on, and the fourth node N4 is low, turning the first feedback submodule 18 on, and the second power supply signal VGH is also written to the third node N3. By setting the first feedback submodule 18 to have a stronger output capability than the second power introduction submodule 14 , the third node N3 is at a high level, and the output signal Sm of the second output submodule 15 is at a low level.

[0051] During the T3 phase, the trigger signal Sn-1 transitions to a high level, the first clock signal SCK1 transitions to a high level, and the second clock signal SCK2 transitions to a low level. At this point, the first power supply input submodule 11 and the first trigger write submodule 13 are turned off. Due to the influence of internal capacitance or internal parasitic capacitance of the first output submodule 12, the second power supply signal VGH is coupled to the first node N1, and the output signal Sn is coupled to the second node N2. This causes the first node N1 to be high and the second node N2 to be low, thereby causing the output signal Sn to be low. And the pulse end time of the first light-emitting control signal is later than the pulse end time of the trigger signal. In other words, at this time, the pulses of the first light-emitting control signal and the second light-emitting control signal both arrive. It can be understood that the pulses of both are high level, so that the second trigger writing submodule 16 and the second power introduction submodule 14 are both turned off. Due to the influence of the internal capacitance or internal parasitic capacitance of the second output submodule 15, the second power supply signal VGH is coupled to the third node N3, and the output signal Sm of the second output submodule 15 is coupled to the fourth node N4, so that the third node N3 maintains a high level, the fourth node N4 maintains a low level, and the output signal Sm of the second output submodule 15 is still a low level.

[0052] During stage T4, the trigger signal Sn-1 remains high, the first clock signal SCK1 is low, and the second clock signal SCK2 is high. The first and second light-emission control signals can still be high. At this point, the first trigger writing submodule 13 and the first power introduction submodule 11 are turned on, a low level is written to the first node N1, a high level is written to the second node N2, and the output signal Sn of the first output submodule 12 becomes high. Furthermore, since the first and second light-emission control signals are still high, the second power introduction submodule 14 and the second trigger writing submodule 16 are both turned off. The third and fourth nodes N3 and N4 have no other signal inputs and remain in the same state as in the previous stage. Therefore, the output signal Sm of the second output submodule 15 remains low.

[0053] In stage T5, the trigger signal Sn-1 is still at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level. At this time, no other signal is input to the first node N1 and the second node N2, and the state of the previous stage is maintained, so that the first output submodule 12 still outputs a high level. However, because the first light-emitting control signal and the second light-emitting control signal jump to a low level, the second trigger writing submodule 16 and the second power supply introduction submodule 14 are turned on, the third node N3 is written to a low level, and the fourth node N4 is written to a high level, thereby causing the output signal Sm of the second output submodule 15 to jump to a high level.

[0054] It should be noted that the duration of the T4 phase can be controlled by adjusting the pulse widths of the first light-emitting control signal and the second light-emitting control signal, thereby adjusting the pulse width of the output signal Sm of the second output submodule 15 .

[0055] From the above, it can be seen that the shift register of this embodiment can output low-level signals with two pulse widths, and is more suitable for existing pixel circuits.

[0056] The technical solution of this embodiment adopts a shift register, which, by setting a first power introduction submodule, a first output submodule, a first trigger writing submodule, a second power introduction submodule, a second trigger writing submodule, a second output submodule and a first feedback submodule, cooperates with the second node, the first light-emitting control signal and the second light-emitting control signal to enable the shift register to output both an output signal shifted relative to the trigger signal and an output signal with adjustable pulse width. That is, by using one shift register to output two output signals, two scanning signals can be provided for the pixel circuit, greatly simplifying the design of the display panel.

[0057] Optionally, continue to refer to Figure 1 and Figure 2, the pulses of the first light emitting control signal and the light emitting control signal at least partially overlap; preferably, the second light emitting control signal and the first light emitting control signal are the same signal Emn (attached Figure 2 middle).

[0058] Specifically, the pulses of the first light-emitting control signal and the second light-emitting control signal are set to at least partially overlap. In the stage of pulse overlap, the second power supply introduction submodule and the second trigger writing submodule are both in the off state. At this time, the second output submodule 15 will maintain the state of the previous moment, and the output signal of the second output submodule 15 will also maintain the level of the previous stage, that is, maintain a low level, thereby ensuring that the second output submodule can output a low level that lasts longer than the output signal of the first output submodule. In addition, the shift register described in the present application is applied to the display panel to provide a scanning signal. It is well known to those skilled in the art that another set of gate drive circuits for providing light-emitting control signals is also provided in the display panel. The light-emitting control signal in the shift register in this embodiment can be provided by a shift register of the same level in another set of gate drive circuits. Reference Figure 2 , the first light-emitting control signal and the second light-emitting control signal of this embodiment are recorded as light-emitting control signals Emn.

[0059] During the T1 phase, the trigger signal Sn-1 is high, and a high level is also written to the second node N2. Since the light-emission control signal Emn is low at this time, the second trigger write submodule 16 is turned on, and a high level is written to the fourth node N4. Simultaneously, when the first clock signal SCK1 is low, the first power supply introduction submodule 11 and the first trigger write submodule 13 are turned on, causing the first power supply signal VGL (low) to be written to the first node N1. Consequently, the first output submodule 12 outputs the second power supply signal VGH (high). When the first trigger write submodule 13 is turned on, the trigger signal Sn-1 is written to the second node N2. At this point, the trigger signal Sn-1 is high, so the second node N2 is also high. In summary, during the T1 phase, the output signal Sn of the first output submodule 12 and the output signal Sm of the second output submodule 15 are both high.

[0060] During phase T2, trigger signal Sn-1 transitions to a low level, first clock signal SCK1 is low, and second clock signal SCK2 is high. At this point, first power supply introduction submodule 11 and first trigger write submodule 13 are turned on, causing first node N1 to be written at a low level. Second node N2 is also at a low level. However, because second clock signal SCK2 is high, although first output submodule 12 outputs two signals, there is no competition between them, and output signal Sn remains high. At this point, emission control signal EMN is low, second power supply introduction submodule 14 is turned on, second trigger write submodule 16 is turned on, and fourth node N4 is low, turning on first feedback submodule 18 and writing second power supply signal VGH to third node N3. By configuring first feedback submodule 18 to have a stronger output capability than second power supply introduction submodule 14, third node N3 is now high, and output signal Sm from second output submodule 15 is low. For example, the first feedback submodule 18 includes a first transistor, and the second power introduction submodule 14 includes a second transistor. The channel width-to-length ratio of the first transistor is set to be greater than the channel width-to-length ratio of the second transistor, so that the first feedback submodule has a stronger output capability, ensuring that a high level is written to the third node N3 at this time.

[0061] During phase T3, the trigger signal Sn-1 transitions to a high level, the first clock signal SCK1 transitions to a high level, and the second clock signal SCK2 transitions to a low level. At this point, the first power supply introduction submodule 11 and the first trigger write submodule 13 are turned off. Due to the influence of internal capacitance or parasitic capacitance of the first output submodule 12, the second power supply signal VGH is coupled to the first node N1, and the output signal Sn is coupled to the second node N2. This causes the first node N1 to be high and the second node N2 to be low, thereby causing the output signal Sn to be low. At this point, a pulse of the light emission control signal EMN arrives. Both the second trigger write submodule 16 and the second power supply introduction submodule 14 are turned off. Due to the influence of internal capacitance or parasitic capacitance of the second output submodule 15, the second power supply signal VGH is coupled to the third node N3, and the output signal Sm of the second output submodule 15 is coupled to the fourth node N4. This causes the third node N3 to remain high, the fourth node N4 to remain low, and the output signal Sm of the second output submodule 15 to remain low.

[0062] During stage T4, trigger signal Sn-1 remains high, first clock signal SCK1 is low, second clock signal SCK2 is high, and emission control signal Emn can still be high. At this point, first trigger write submodule 13 and first power supply introduction submodule 11 are conductive, a low level is written to first node N1, a high level is written to second node N2, and the output signal Sn of first output submodule 12 becomes high. Furthermore, emission control signal EMN remains high, second power supply introduction submodule 14 and second trigger write submodule 16 are both off, and third node N3 and fourth node N4 have no other signal inputs, maintaining the same state as in the previous stage. Therefore, output signal Sm of second output submodule 15 remains low.

[0063] In stage T5, the trigger signal Sn-1 is still at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level. At this time, no other signal is input to the first node N1 and the second node N2, and the state of the previous stage is maintained, so that the first output submodule 12 still outputs a high level. However, because the light-emitting control signal EMN jumps to a low level, the second trigger writing submodule 16 and the second power introduction submodule 14 are turned on, the third node N3 is written to a low level, and the fourth node N4 is written to a high level, thereby causing the output signal Sm of the second output submodule 15 to jump to a high level.

[0064] In the above embodiment, by setting the first light-emitting control signal and the second light-emitting control signal to be the same signal, the number of signals required for the shift register can be reduced, thereby reducing the number of signal lines, which is beneficial to the wiring design of the shift register.

[0065] Optionally, the pulse start time of the first light emitting control signal is earlier than or equal to the pulse start time of the trigger signal.

[0066] Specifically, Figure 3 A circuit diagram of another shift register provided by an embodiment of the present invention is shown. Figure 4 A timing diagram of another shift register provided in an embodiment of the present invention, Figure 4 and Figure 3 Corresponding, combined Figure 3 and Figure 4 In this embodiment, the first light-emitting control signal is labeled as Emnn-1, and the second light-emitting control signal is labeled as Emn. Emn-1 is the output signal of the previous stage of Emn in the gate driving circuit.

[0067] During the T1 phase, the trigger signal Sn-1 is high, and the second node N2 is also written to a high level. Since the first light-emitting control signal Emn-1 and the second light-emitting control signal Emn are low at this time, the second trigger writing submodule 16 is turned on, the fourth node N4 is written to a high level, the second power introduction submodule 14 is turned on, and the third node N3 is written to a low level. Simultaneously, when the first clock signal SCK1 is low, the first power introduction submodule 11 and the first trigger writing submodule are turned on, causing the first node N1 to be written to the first power signal VGL, so that the first output submodule 12 outputs the second power signal VGH. When the first trigger writing submodule 13 is turned on, the trigger signal Sn-1 is written to the second node N2. The trigger signal Sn-1 is now high, so the second node N2 is also high. In summary, during the T1 phase, the output signal Sn of the first output submodule 12 and the output signal Sm of the second output submodule 15 are both high.

[0068] During phase T2, trigger signal Sn-1 transitions to a low level, first clock signal SCK1 is low, and second clock signal SCK2 is high. At this point, first power supply introduction submodule 11 and first trigger write submodule 13 are turned on, causing a low level to be written to first node N1. Second node N2 is also at a low level. However, since second clock signal SCK2 is high, although first output submodule 12 outputs two signals, there is no competition between them, and output signal Sn remains high. At this point, first light-emission control signal Emn-1 is high, second power supply introduction submodule 14 is turned off, second light-emission control signal Emn is low, second trigger write submodule 16 is turned on, fourth node N4 is low, turning first feedback submodule 18 on, and second power supply signal VGH is also written to third node N3. Since the pulse start time of the first light-emitting control signal Emn-1 is earlier than or equal to the pulse start time of the trigger signal, and the pulse end time of the first light-emitting control signal is later than the pulse end time of the trigger signal, that is, in the T2 stage, the first light-emitting control signal Emn-1 maintains a high level, so that the second power supply introduction sub-module 14 is turned off, thereby ensuring that there is no competition relationship between the second power supply introduction sub-module 14 and the first feedback sub-module 18.

[0069] During the T3 phase, the trigger signal Sn-1 transitions to a high level, the first clock signal SCK1 transitions to a high level, and the second clock signal SCK2 transitions to a low level. At this point, the first power supply input submodule 11 and the first trigger write submodule 13 are turned off. Due to the influence of internal capacitance or internal parasitic capacitance of the first output submodule 12, the second power supply signal VGH is coupled to the first node N1, and the output signal Sn is coupled to the second node N2. This causes the first node N1 to be high and the second node N2 to be low, thereby causing the output signal Sn to be low. At this time, the first light-emitting control signal Emn-1 and the second light-emitting control signal Emn are both at a high level. At this time, the second trigger writing sub-module 16 and the second power supply introduction sub-module 14 are both turned off. Due to the influence of the internal capacitance or internal parasitic capacitance of the second output sub-module 15, the second power supply signal VGH is coupled to the third node N3, and the output signal Sm of the second output sub-module 15 is coupled to the fourth node N4, thereby maintaining the third node N3 at a high level and the fourth node N4 at a low level. The output signal Sm of the second output sub-module 15 is still at a low level.

[0070] During stage T4, trigger signal Sn-1 remains high, first clock signal SCK1 is low, second clock signal SCK2 is high, first light-emission control signal Emn-1 is low, and second light-emission control signal Emn is high. At this point, first trigger write submodule 13 and first power supply introduction submodule 11 are conductive, a low level is written to first node N1, a high level is written to second node N2, and the output signal Sn of first output submodule 12 becomes high. Furthermore, second power supply introduction submodule 14 is conductive, second trigger write submodule 16 is off, and fourth node N4 remains low, turning on first feedback submodule 18. By configuring first feedback submodule 18 to have a stronger output capability than second power supply introduction submodule 14, third node N3 is now high, and output signal Sm of second output submodule 15 is low.

[0071] In stage T5, the trigger signal Sn-1 is still at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level. At this time, no other signal is input to the first node N1 and the second node N2, and the state of the previous stage is maintained, so that the first output submodule 12 still outputs a high level. However, because the light-emitting control signal EMN jumps to a low level, the second trigger writing submodule 16 and the second power introduction submodule 14 are turned on, the third node N3 is written to a low level, and the fourth node N4 is written to a high level, thereby causing the output signal Sm of the second output submodule 15 to jump to a high level.

[0072] Optionally, Figure 5 A circuit diagram of another shift register provided by an embodiment of the present invention is shown. Figure 4 The timing diagram shown can also be applied to Figure 5 The shift register shown, combined with Figure 4 and Figure 5 In this embodiment, the shift register further includes a third power supply introduction submodule 17. The third power supply introduction submodule 17 is connected between the second power supply introduction submodule 14 and the third node N3. The third power supply introduction submodule 17 is configured to be turned on or off according to the second light-emitting control signal Emn.

[0073] Specifically, through Figure 1 and Figure 3 The illustrated embodiment demonstrates that, in the aforementioned embodiment, a competition relationship exists between the first feedback submodule and the second power introduction submodule during the T2 or T4 phases. In this embodiment, through the third power introduction submodule and the second power introduction submodule, during the T2 phase, the first light-emitting control signal Emn-1 is at a high level, and the second power introduction submodule 14 is turned off, preventing the first power signal VGL from being written to the third node. Consequently, only the first feedback submodule can write to the third node N3. During the T4 phase, the second light-emitting control signal Emn is at a high level, causing the third power introduction submodule Emn to be turned off. Similarly, the first power signal VGL is not written to the third node N3. Consequently, only the first feedback submodule can write to the third node N3. This ensures that, during the T2 and T4 phases, there is no competition between the first feedback submodule and the second power introduction submodule.

[0074] Optionally, Figure 6 A circuit diagram of another shift register provided by an embodiment of the present invention is provided. Figure 6The first output submodule 12 includes: a first pull-up submodule 121, a first end of the first pull-up submodule 121 is connected to the second power supply signal VGH, and a control end of the first pull-up submodule 121 is electrically connected to the first node N1; a first pull-down submodule 122, a first end of the first pull-down submodule 122 is connected to the second clock signal SCK2, a control end of the first pull-down submodule 122 is electrically connected to the second node N2, and a second end of the first pull-down submodule 122 is electrically connected to the second end of the first pull-up submodule 121 to serve as the output end of the first output submodule 12. The second output submodule 15 includes: a second pull-up submodule 151, a first end of which is connected to the second power signal VGH, and a control end of which is electrically connected to a third node N3; a second pull-down submodule 152, a first end of which is connected to the first power signal VGL, a control end of which is electrically connected to a fourth node N4, and a second end of which is electrically connected to the second end of the second pull-up submodule 151 to serve as an output end of the second output submodule 15. The second output submodule 15 also includes: a first coupling unit 153, a first end of which is electrically connected to the first end of the second pull-up submodule, and a second end of which is electrically connected to the control end of the second pull-up submodule 151; and a second coupling unit 154, a first end of which is electrically connected to the control end of the second pull-down submodule 152, and a second end of which is electrically connected to the second end of the second pull-down submodule 152. The shift register also includes a third coupling submodule 123, a first end of which is electrically connected to the first end of the first pull-up submodule 121, and a second end of which is electrically connected to the control end of the first pull-up submodule 121. A fourth coupling submodule 124, a first end of which is electrically connected to the control end of the first pull-down submodule 122, and a second end of which is electrically connected to the second end of the first pull-down submodule 122. A second feedback submodule 19 is configured to write the first clock signal to the first node N1 based on the potential of the second node N2. A third feedback submodule 20 is configured to write the potential of the first node to the second node based on the potentials of the first node and the second clock signal. A normally open submodule is connected between the second node and the control end of the first pull-down submodule to reduce leakage current.

[0075] In the above embodiment, the second power supply introduction submodule 14 includes a first transistor M1, the first feedback submodule 18 includes a second transistor M2, the second trigger write submodule 16 includes a third transistor M3, the second pull-up submodule 151 includes a fourth transistor M4, the second pull-down submodule 152 includes a fifth transistor M5, the first coupling submodule 153 includes a first capacitor C1, the second coupling submodule 154 includes a second capacitor C2, the first power supply introduction submodule 11 includes a sixth transistor M6, the first trigger write submodule 13 includes a seventh transistor M7, the first pull-up submodule 121 includes an eighth transistor M8, the first pull-down submodule 122 includes a ninth transistor M9, the second feedback submodule 19 includes a tenth transistor M10, the third feedback submodule 20 includes an eleventh transistor M11 and a twelfth transistor M12, the third coupling submodule 123 includes a third capacitor C3, and the fourth coupling submodule 124 includes a fourth capacitor C4. The above transistors may be N-type transistors or P-type transistors, preferably all of which are P-type transistors.

[0076] The first terminal of the first transistor M1 is connected to the first power signal VGL, the second terminal of the first transistor M1 is electrically connected to the third node N3, and the control terminal of the first transistor M1 is connected to the first light-emitting control signal. In this embodiment, both the second light-emitting control signal and the first light-emitting control signal are Emn signals. The first terminal of the second transistor M2 is connected to the second power signal VGH, the second terminal of the second transistor M2 is electrically connected to the third node N3, and the control terminal of the second transistor M2 is electrically connected to the fourth node N4. The first terminal of the third transistor M3 is electrically connected to the second node N2, the second terminal of the third transistor M3 is electrically connected to the fourth node N4, and the control terminal of the third transistor M3 is connected to the second light-emitting control signal. The first terminal of the fourth transistor M4 is connected to the second power signal VGH, the second terminal of the fourth transistor M4 is electrically connected to the second terminal of the fifth transistor M5, and serves as the output terminal of the second output submodule. The control terminal of the fourth transistor M4 is electrically connected to the third node N3. The first terminal of the fifth transistor M5 is connected to the first power signal VGL, and the control terminal of the fifth transistor M5 is electrically connected to the fourth node N4. A first end of the first capacitor C1 is electrically connected to the first end of the fourth transistor M4, and a second end of the first capacitor C1 is electrically connected to the control end of the fourth transistor M4. A first end of the second capacitor C2 is electrically connected to the second end of the fifth transistor M5, and a second end of the second capacitor C2 is electrically connected to the control end of the fifth transistor M5. A first end of the sixth transistor M6 is electrically connected to the first power supply signal VGL, a second end of the sixth transistor M6 is electrically connected to the first node N1, and a control end of the sixth transistor M6 is connected to the first clock signal SCK1. A first end of the seventh transistor M7 is electrically connected to the trigger signal Sn-1, a second end of the seventh transistor M7 is electrically connected to the second node N2, and a control end of the seventh transistor M7 is connected to the first clock signal SCK1. A first end of the eighth transistor M8 is electrically connected to the first power supply signal VGH, a second end of the eighth transistor M8 is electrically connected to the second end of the ninth transistor M9, and serves as the control end of the first output submodule. The control end of the eighth transistor M8 is electrically connected to the first node N1. A first end of the ninth transistor M9 is connected to the second clock signal SCK2. A first terminal of the thirteenth transistor M13 is electrically connected to the second node N2, a second terminal of the thirteenth transistor M13 is electrically connected to the control terminal of the ninth transistor M9, and the control terminal of the thirteenth transistor M13 is connected to the first power supply signal VGL. A first terminal of the third capacitor C3 is electrically connected to the first terminal of the eighth transistor M8, and a second terminal of the third capacitor C3 is electrically connected to the control terminal of the eighth transistor M8. A first terminal of the fourth capacitor C4 is electrically connected to the second terminal of the ninth transistor M9, and a second terminal of the fourth capacitor C4 is electrically connected to the control terminal of the ninth transistor M9. A first terminal of the tenth transistor M10 is electrically connected to the first clock signal SCK1, a second terminal of the tenth transistor M10 is electrically connected to the first node N1, and the control terminal of the tenth transistor M10 is electrically connected to the second node N2.A first terminal of the eleventh transistor M11 is connected to the second power supply signal VGH, a second terminal of the eleventh transistor M11 is electrically connected to the first terminal of the twelfth transistor M12, and a control terminal of the eleventh transistor M11 is electrically connected to the first node N1. A control terminal of the twelfth transistor M12 is connected to the second clock signal SCK2, and a second terminal of the twelfth transistor M12 is electrically connected to the second node N2.

[0077] The embodiment of the present invention further provides a display panel, such as Figure 7 As shown, Figure 7 A structural schematic diagram of a display panel provided in an embodiment of the present invention, the display panel includes a display area and a non-display area, a plurality of pixel circuits PX are provided in the display area, a first gate drive circuit 201 is provided in the non-display area, and the first gate drive circuit 201 includes a plurality of cascaded shift registers 2011 provided in any embodiment of the present invention, and the shift register 2011 is used to provide a scanning signal to the pixel circuit of the corresponding row.

[0078] Specifically, the display panel may be provided with scan lines and data lines Data that are staggered horizontally and vertically within the display area. The scan lines and data lines intersect to define the area of the pixel circuit PX. The specific circuit structure of the pixel circuit PX is well known to those skilled in the art and will not be described in detail here. The trigger signal Sn-1 of the first-stage shift register is provided by the trigger signal line SIN. Since the display panel provided by the embodiment of the present invention includes the shift register provided by any embodiment of the present invention, it also has the same beneficial effects and will not be described in detail here.

[0079] Optionally, continue to refer to Figure 7 A second gate driver circuit 202 is further provided in the non-display area. The second gate driver circuit 202 includes an n-level light-emitting control signal output terminal for providing a light-emitting control signal to the pixel circuits in the corresponding row. The m-th level light-emitting control signal output terminal of the second gate driver circuit 202 is used to output the first light-emitting control signal and the second light-emitting control signal to the m-th level shift register in the first gate driver circuit 201. Alternatively, the m-th level light-emitting control signal output terminal of the second gate driver circuit 202 is used to provide the second light-emitting control signal to the m-th level shift register in the first gate driver circuit 201, and the m-1-th level light-emitting control signal output terminal of the second gate driver circuit 202 is used to provide the first light-emitting control signal to the m-th level shift register in the first gate driver circuit.

[0080] Specifically, the second gate driving circuit 202 includes a plurality of cascaded light emitting control shift registers 2021. When the m-th level light emitting control signal output terminal of the second gate driving circuit 202 is used to output the first light emitting control signal and the second light emitting control signal to the m-th level shift register in the first gate driving circuit 201, it can correspond to Figure 1When the m-th level light emitting control signal output terminal of the second gate driving circuit 202 is used to provide the second light emitting control signal to the m-th level shift register in the first gate driving circuit 201, and the m-1-th level light emitting control signal output terminal of the second gate driving circuit 202 is used to provide the first light emitting control signal to the m-th level shift register in the first gate driving circuit, it can correspond to Figure 3 or Figure 5 The shift register shown in .

[0081] Figure 8 This is a schematic structural diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel provided in any embodiment of the present invention and thus has the same beneficial effects. Detailed description is omitted here. The display device can be a mobile phone, tablet computer, MP3, MP4, smart watch, smart helmet, or other wearable device. Because it includes the display panel provided in any embodiment of the present invention and thus has the same beneficial effects, detailed description is omitted here.

[0082] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0083] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A shift register, characterized in that: The shift register comprises: a first power supply introduction submodule, a first output submodule, a first trigger writing submodule, a second power supply introduction submodule, a second output submodule, a second trigger writing submodule, and a first feedback submodule; The first power introduction submodule is configured to write the first power signal into the first node according to the first clock signal; The first trigger writing submodule is configured to write a trigger signal into the second node according to the first clock signal; The first output submodule is configured to output a second clock signal or a second power supply signal according to the potentials of the first node and the second node; The second power supply introduction submodule is configured to write the first power supply signal into the third node according to the first light emitting control signal; The second trigger writing submodule is configured to write the potential of the second node into the fourth node according to the second light emitting control signal; The second output submodule is configured to output the first power signal or the second power signal according to the potentials of the third node and the fourth node; The first feedback submodule is configured to write the second power supply signal into the third node according to the potential of the fourth node; Wherein, within one frame time, the end time of the pulse of the first light-emitting control signal and the start time of the second light-emitting control signal are both later than the end time of the pulse of the trigger signal.

2. The shift register according to claim 1, wherein: Pulses of the first light emitting control signal and the second light emitting control signal at least partially overlap.

3. The shift register according to claim 2, wherein: The second light-emitting control signal and the first light-emitting control signal are the same signal.

4. The shift register according to claim 1, wherein: Within one frame time, a pulse start time of the first light-emitting control signal is earlier than or equal to a pulse start time of the trigger signal.

5. The shift register according to claim 4, wherein: The shift register further includes a third power supply introduction submodule, which is connected between the second power supply introduction submodule and the third node, and is configured to be turned on or off according to the second light emitting control signal.

6. The shift register according to claim 1, wherein: The first output submodule includes: a first pull-up submodule, wherein a first end of the first pull-up submodule is connected to the second power signal, and a control end of the first pull-up submodule is electrically connected to the first node; a first pull-down submodule, wherein a first end of the first pull-down submodule is connected to the second clock signal, a control end of the first pull-down submodule is electrically connected to the second node, and a second end of the first pull-down submodule is electrically connected to the second end of the first pull-up submodule to serve as an output end of the first output submodule.

7. The shift register according to claim 1, wherein: The second output submodule includes: a second pull-up submodule, wherein a first terminal of the second pull-up submodule is connected to the second power signal, and a control terminal of the second pull-up submodule is electrically connected to the third node; a second pull-down submodule, wherein a first end of the second pull-down submodule is connected to the first power signal, a control end of the second pull-down submodule is electrically connected to the fourth node, and a second end of the second pull-down submodule is electrically connected to the second end of the second pull-up submodule to serve as an output end of the second output submodule.

8. The shift register according to claim 7, wherein: The second output submodule further includes: a first coupling unit, wherein a first end of the first coupling unit is electrically connected to a first end of the second pull-up submodule, and a second end of the first coupling unit is electrically connected to a control end of the second pull-up submodule; A second coupling unit, wherein a first end of the second coupling unit is electrically connected to the control end of the second pull-down submodule, and a second end of the second coupling unit is electrically connected to the second end of the second pull-down submodule.

9. The shift register according to claim 1, wherein: The second power introduction submodule includes a first transistor, the first feedback submodule includes a second transistor, and a channel width-to-length ratio of the second transistor is greater than a channel width-to-length ratio of the first transistor.

10. A display panel, characterized in that: The display panel includes a display area and a non-display area, a plurality of pixel circuits are arranged in the display area, a first gate driving circuit is arranged in the non-display area, the first gate driving circuit includes a cascade of multiple stages of shift registers as described in any one of claims 1 to 9, and the shift register is used to provide a scanning signal to the pixel circuit of the corresponding row.

11. The display panel according to claim 10, wherein: A second gate driving circuit is further provided in the non-display area, and the second gate driving circuit includes n-level light emitting control signal output terminals for providing light emitting control signals to the pixel circuits of the corresponding rows; The m-th stage light emitting control signal output terminal of the second gate driving circuit is used to output the first light emitting control signal and the second light emitting control signal to the m-th stage shift register in the first gate driving circuit; Alternatively, the mth level light-emitting control signal output terminal of the second gate driving circuit is used to provide a second light-emitting control signal to the mth level shift register in the first gate driving circuit, and the m-1th level light-emitting control signal output terminal of the second gate driving circuit is used to provide a first light-emitting control signal to the mth level shift register in the first gate driving circuit.

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