Shifting register, driving circuit and display substrate

Abstract

The utility model provides a shift register, a driving circuit and a display substrate. The shift register comprises an input circuit, a control circuit and an output circuit. The input circuit is configured to provide a signal of a signal input end for a first node and provide a signal of a first power supply end for a second node under the control of a first clock signal end; the control circuit is configured to control the signals of the third node and the fourth node according to the signals of the first node and the second node; and the output circuit is configured to provide the signal of the second clock signal end to the signal output end under the control of the third node and the fourth node. The LTPO circuit can output a signal without a falling edge step, so that the problem that the LTPO circuit has the falling step can be solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a shift register, a driving circuit, and a display substrate. Background Art

[0002] Low-Temperature Polycrystalline Oxide (LTPO) circuits are currently the driving circuits for flagship products in the market. Due to their unique ability to achieve low-frequency displays and save power, they have been widely researched and applied, becoming the mainstream circuit architecture for subsequent mobile phone products. LTPO circuits are essentially shift register circuits, designed to drive pixel illumination in the display area row by row. However, the NGate circuits of LTPO circuits have long suffered from a falling edge step, which causes current fluctuations in the pixel's light-emitting current, adversely affecting display quality. Utility Model Content

[0003] The present application provides a shift register, a driving circuit and a display substrate, which can output a signal without a falling edge step, thereby solving the falling step problem existing in the LTPO circuit, improving the stability of the output signal of the LTPO circuit, and reducing the adverse impact on image quality.

[0004] In a first aspect, a shift register is provided, comprising an input circuit, a control circuit, and an output circuit. The input circuit is electrically connected to a signal input terminal, a first power supply terminal, a first clock signal terminal, a first node, and a second node, respectively. The input circuit is configured to, under the control of the first clock signal terminal, provide a signal from the signal input terminal to the first node and provide a signal from the first power supply terminal to the second node. The control circuit is electrically connected to the first node, the second node, the third node, the fourth node, the second clock signal terminal, and the second power supply terminal, respectively. The control circuit is configured to control the signals from the third node and the fourth node based on the signals from the first node and the second node. The output circuit is electrically connected to the third node, the fourth node, the second clock signal terminal, the second power supply terminal, and a signal output terminal, respectively. The output circuit is configured to, under the control of the third node and the fourth node, provide a signal from the second clock signal terminal to the signal output terminal.

[0005] In combination with the first aspect, in a possible implementation, the shift register further includes a voltage stabilizing circuit, which is electrically connected to the third node and the first clock signal end, respectively. The voltage stabilizing circuit is configured to reduce the voltage of the third node after the output circuit switches the high-level signal output by the second clock signal end to the signal output end to a low-level signal, so as to ensure that the output circuit provides the signal of the second power supply end to the signal output end.

[0006] In combination with the first aspect, in a possible implementation, the voltage stabilizing circuit includes a first switching tube and a first capacitor; the control electrode, the first electrode, and the second electrode of the first switching tube are electrically connected to the first electrode of the first capacitor, the second electrode of the first capacitor, and the first clock signal end, respectively; the first electrode of the first capacitor is also electrically connected to the third node.

[0007] In combination with the first aspect, in a possible implementation, the voltage stabilization circuit includes a first capacitor; a first electrode and a second electrode of the first capacitor are electrically connected to the third node and the first clock signal end, respectively.

[0008] In combination with the first aspect, in a possible implementation, the shift register further includes a step-down circuit, which is electrically connected to the second node, the control circuit, and the second power supply terminal, respectively, and the step-down circuit is configured to reduce the potential of the second node under the control of the second power supply terminal.

[0009] In combination with the first aspect, in a possible implementation, the step-down circuit includes a second switch tube, and the control electrode, the first electrode, and the second electrode of the second switch tube are electrically connected to the second power supply terminal, the second node, and the control circuit respectively.

[0010] In combination with the first aspect, in a possible implementation, the control circuit includes a third switch tube, a fourth switch tube, a fifth switch tube and a second capacitor; the control electrode, the first electrode and the second electrode of the third switch tube are electrically connected to the second clock signal end, the first node and the fifth node, respectively; the control electrode, the first electrode and the second electrode of the fourth switch tube are electrically connected to the second power supply end, the fifth node and the third node, respectively; the control electrode, the first electrode and the second electrode of the fifth switch tube are electrically connected to the fifth node, the second clock signal end and the sixth node, respectively; the first electrode and the second electrode of the second capacitor are electrically connected to the sixth node and the second clock signal end, respectively.

[0011] In combination with the first aspect, in a possible implementation, the input circuit includes a sixth switching tube, a seventh switching tube and a third capacitor; the control electrode, the first electrode and the second electrode of the sixth switching tube are electrically connected to the signal input end, the seventh node and the first power supply end, respectively; the control electrode, the first electrode and the second electrode of the seventh switching tube are electrically connected to the seventh node, the first clock signal end and the second node, respectively; the first electrode and the second electrode of the third capacitor are electrically connected to the first clock signal end and the seventh node, respectively.

[0012] In combination with the first aspect, in a possible implementation, the output circuit includes an eighth switching tube and a ninth switching tube; the control electrode, the first electrode, and the second electrode of the eighth switching tube are electrically connected to the fourth node, the second clock signal terminal, and the signal output terminal, respectively; the control electrode, the first electrode, and the second electrode of the ninth switching tube are electrically connected to the third node, the second power supply terminal, and the signal output terminal, respectively.

[0013] In a second aspect, a driving circuit is provided, comprising a plurality of cascaded shift registers according to the first aspect or any possible implementation of the first aspect; the input signal terminal of the first-stage shift register is connected to the enable signal line, the input signal terminal of the n-th-stage shift register is connected to the output terminal of the nx-th-stage shift register, the first clock signal terminal and the second clock signal terminal of each of the shift registers are connected to two different clock signal lines, and the two clock signal lines connected to each shift register are not exactly the same, wherein n is a positive integer greater than or equal to 2, x is an integer greater than or equal to 1, and n>x.

[0014] In a third aspect, a display substrate is provided, comprising a display area, a frame area located around the display area, and the driving circuit described in the second aspect, wherein the driving circuit is located in the frame area.

[0015] In an embodiment of the present application, through the coordinated work of various circuits, when the signal output from the signal output end switches from a high level to a low level, the signal output by the output circuit to the signal output end is synchronized with the signal of the second clock signal end. At this time, there is no threshold loss. Therefore, the shift register can output a signal without a falling edge step, thereby solving the problem of the falling step in the LTPO circuit and improving the stability of the output signal of the LTPO circuit to reduce the adverse effect on image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the drawings without creative work.

[0017] Figure 1 This is a structural diagram of a shift register provided in an embodiment of the present application.

[0018] Figure 2 This is a circuit diagram of a shift register provided in an embodiment of the present application.

[0019] Figure 3 This is a schematic diagram of a shift register driving method provided in an embodiment of the present application.

[0020] Figure 4 Schematic diagram of the control signal timing of the shift register provided in an embodiment of the present application.

[0021] Figures 5 to 9 A schematic diagram of the states of the shift register provided in an embodiment of the present application at different stages.

[0022] Figure 10 This is a schematic structural diagram of another shift register provided in an embodiment of the present application.

[0023] Figure 11 This is a circuit diagram of another shift register provided in an embodiment of the present application.

[0024] Figure 12 This is a circuit diagram of another shift register provided in an embodiment of the present application.

[0025] Figure 13 This is a structural diagram of another shift register provided in an embodiment of the present application.

[0026] Figure 14 This is a circuit diagram of another shift register provided in an embodiment of the present application.

[0027] Figure 15 This is a schematic diagram of a driving circuit provided in an embodiment of the present application.

[0028] Figure 16 Schematic diagram of the control signal timing of the driving circuit provided in an embodiment of the present application.

[0029] Description of reference numerals:

[0030] 10-input circuit, 20-control circuit, 30-output circuit, 40-voltage stabilizing circuit, 50-voltage step-down circuit. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0032] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of this application and the appended claims, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one, two or more. The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0033] References to "one embodiment," "some embodiments," "one embodiment," or "some embodiments" described in the embodiments of the present application mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," and "in some other embodiments" appearing at different points in this specification do not necessarily all refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0034] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0035] The ordinal numbers "first," "second," "third," and the like used in the embodiments of the present disclosure do not indicate any order, quantity, or importance. They are provided to avoid confusion among constituent elements, rather than to limit the number. Similar words do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Words such as "include" or "comprising" mean that the element or object preceding the word includes the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0036] In the description of the embodiments of the present application, "electrical connection" includes situations where components are electrically connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the electrically connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0037] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0038] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0039] In the circuit structure provided in the embodiments of the present disclosure, the switching tube used in the circuit structure can be a thin film transistor (TFT), a field effect switch tube (MOS), an insulated gate bipolar transistor (IGBT), a gallium nitride (GaN) high electron mobility transistor (HEMT) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using a thin film switch tube as an example.

[0040] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each switching transistor is either a source or a drain, and the second electrode of each switching transistor is the other of the source or drain. Because the source and drain of the switching transistor can be structurally symmetrical, their source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the switching transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, the first electrode of the switching transistor is the source, and the second electrode is the drain, or the first electrode of the switching transistor is the drain, and the second electrode is the source.

[0041] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual components, but represent related connected junctions in the circuit diagram. That is, these nodes are nodes formed by the equivalent of related connected junctions in the circuit diagram.

[0042] The switching transistors included in the circuit structure provided in the embodiments of the present disclosure can all be N-type switching transistors, or can all be P-type switching transistors. In the present disclosure, the P-type switching transistor can be turned on under the control of a low-level signal, and the N-type switching transistor can be turned on under the control of a high-level signal. The following is a schematic description using the example of the switching transistors included in the circuit structure provided in the embodiments of the present disclosure, in which all the switching transistors are P-type switching transistors.

[0043] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, certain well-known parts may not be shown in the drawings.

[0044] LTPO circuits are currently the driving circuits for mainstream flagship products. Due to their unique ability to achieve low-frequency display and save power, they have been widely researched and applied, becoming the mainstream circuit architecture for subsequent mobile phone products. Essentially a shift register circuit, the LTPO circuit's purpose is to drive the display pixels row by row. However, the NGate circuit of the LTPO circuit has long suffered from a falling edge step, which causes current fluctuations in the pixel's light-emitting current, adversely affecting display quality.

[0045] Based on this, the present application provides a shift register that can output a signal without a falling edge step, thereby solving the falling step problem existing in the LTPO circuit, improving the stability of the output signal of the LTPO circuit, and reducing the adverse effects on image quality.

[0046] The shift register described in this application will be described in detail below with reference to the accompanying drawings.

[0047] Figure 1 Schematic diagram of a shift register provided by an embodiment of the present application. Figure 1 As shown, the shift register includes an input circuit 10 , a control circuit 20 , and an output circuit 30 .

[0048] The input circuit 10 is electrically connected to the signal input terminal STV, the first power supply terminal VGH, the first clock signal terminal CK2, the first node N1 and the second node N2, respectively. The input circuit 10 is configured to provide the signal of the signal input terminal STV to the first node N1 and provide the signal of the first power supply terminal VGH to the second node N2 under the control of the first clock signal terminal CK2.

[0049] The control circuit 20 is electrically connected to the first node N1, the second node N2, the third node N3, the fourth node N4, the second clock signal terminal CK1, and the second power supply terminal VGL, respectively. The control circuit 20 is configured to control the signals of the third node N3 and the fourth node N4 according to the signals of the first node N1 and the second node N2.

[0050] The output circuit 30 is electrically connected to the third node N3, the fourth node N4, the second clock signal terminal CK1, the second power supply terminal VGL and the signal output terminal OUT, respectively. The output circuit 30 is configured to provide the signal of the second clock signal terminal to the signal output terminal OUT under the control of the third node N3 and the fourth node N4.

[0051] The shift register provided in the embodiment of the present application can, through the coordinated work of various circuits, ensure that when the signal output from the signal output terminal OUT switches from a high level to a low level, the signal output by the output circuit 30 to the signal output terminal OUT is synchronized with the signal of the second clock signal terminal CK1. At this time, there is no threshold loss. Therefore, the shift register can output a signal without a falling edge step, thereby solving the problem of the falling step existing in the LTPO circuit, improving the stability of the output signal of the LTPO circuit, and reducing the adverse effects on image quality.

[0052] Figure 2 is a circuit diagram of a shift register provided in an embodiment of the present application. Figure 2 As shown, the shift register includes switch tubes M3 to M9, a second capacitor C2, and a third capacitor C3.

[0053] See also Figure 2 The control circuit 20 includes a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5 and a second capacitor C2.

[0054] The control electrode, first electrode, and second electrode of the third switch transistor M3 are electrically connected to the second clock signal terminal CK1, the first node N1, and the fifth node N5, respectively. The control electrode, first electrode, and second electrode of the fourth switch transistor M4 are electrically connected to the second power supply terminal VGL, the fifth node N5, and the third node N3, respectively. The control electrode, first electrode, and second electrode of the fifth switch transistor M5 are electrically connected to the fifth node N5, the second clock signal terminal CK1, and the sixth node N6, respectively. The first electrode and second electrode of the second capacitor C2 are electrically connected to the sixth node N6 and the second clock signal terminal CK1, respectively.

[0055] Continue to see Figure 2 The input circuit 10 includes a sixth switch tube M6, a seventh switch tube M7 and a third capacitor C3.

[0056] The control electrode, first electrode, and second electrode of the sixth switch M6 are electrically connected to the signal input terminal STV, the seventh node N7, and the first power supply terminal VGH, respectively. The control electrode, first electrode, and second electrode of the seventh switch M7 are electrically connected to the seventh node N7, the first clock signal terminal CK2, and the second node N2, respectively. The first electrode and second electrode of the third capacitor C3 are electrically connected to the first clock signal terminal CK2 and the seventh node N7, respectively.

[0057] Continue to see Figure 2 The output circuit 30 includes an eighth switch tube M8 and a ninth switch tube M9.

[0058] Among them, the control electrode, first electrode, and second electrode of the eighth switch tube M8 are electrically connected to the fourth node N4, the second clock signal terminal CK1, and the signal output terminal OUT, respectively; the control electrode, first electrode, and second electrode of the ninth switch tube M9 are electrically connected to the third node N3, the second power supply terminal VGL, and the signal output terminal OUT, respectively.

[0059] Among them, Figure 2 For this explanation, all the switches in the circuit are P-type switches. The first power supply terminal, VGH, continuously outputs a high level, while the second power supply terminal, VGL, continuously outputs a low level. When a low level is applied to the control electrode of the P-type switch, the P-type switch turns on; when a high level is applied to the control electrode of the P-type switch, the P-type switch turns off. Accordingly, a clock signal periodically switches between two different levels, and these two levels are typically used to turn the switch on and off, respectively. Therefore, the higher of the two levels is often referred to as the high level, and the lower as the low level.

[0060] However, it should be understood that the specific level values ​​of the high / low levels in the first power supply terminal and the second power supply terminal are not necessarily equal to the level values ​​of the high / low levels in the clock signal (of course, for the sake of driving convenience, the two can usually be equal).

[0061] like Figure 3As shown, the embodiment of the present application further provides a shift register driving method 300, which is applied to Figure 2 For the pixel circuit shown, the driving method may include steps 310 to 350.

[0062] 310, in the first stage, a signal from the signal input terminal is provided to the first node, the signal from the first node is transmitted to the sixth node through the third switch tube and the fifth switch tube, the eighth switch tube is turned on, and a low-level signal output from the second clock signal terminal is provided to the signal output terminal.

[0063] 320, second stage, providing the signal of the first clock signal end to the second node, the signal of the second node is transmitted to the fourth node, the eighth switch tube is turned on, and providing the low level signal output by the second clock signal end to the signal output end.

[0064] 330, the third stage, providing the signal of the first clock signal end to the second node, the signal of the second node is transmitted to the fourth node, the eighth switch tube is turned on, and the high level signal output by the second clock signal end is provided to the signal output end.

[0065] 340, in the fourth stage, the signal of the signal input terminal is provided to the first node, the third switch tube, the fourth switch tube, the eighth switch tube, and the ninth switch tube are all turned off, so that the fourth node is floating and maintains the third stage state, and the high-level signal output by the second clock signal terminal is provided to the signal output terminal.

[0066] 350, the fifth stage, providing the signal of the signal input terminal to the first node, the signal of the first node is transmitted to the sixth node through the third switch tube and the fifth switch tube, the eighth switch tube is turned on, and the low-level signal output by the second clock signal terminal is provided to the signal output terminal.

[0067] like Figure 4 FIG2 is a schematic diagram of the control signal timing of the shift register provided in an embodiment of the present application.

[0068] In the first phase T1 , the signal input terminal STV and the second clock signal terminal CK1 both provide low-level signals, and the first clock signal terminal CK2 provides a high-level signal. Figure 5 Schematic diagram of the state of the shift register in the first stage T1.

[0069] In the first phase T1, due to the low-level signal provided by STV, switch M6 is turned on. At this point, switch M6 provides a high-level signal, output from the first power supply terminal VGH, to the seventh node N7. CK2 also provides a high-level signal to the seventh node N7, thus turning switch M7 off. Because CK1 provides a low-level signal, switch M3 is turned on. The low-level signal provided by the signal input terminal STV is written to the fifth node N5 via switch M3, causing the fifth node N5 to reach a low potential. When the fifth node N5 reaches a low potential, switch M5 is turned on. Due to the low-level signal provided by CK1, the low-level signal provided by CK1 is written to the sixth node N6, causing the sixth node N6 to reach a low potential. Switch M8 is turned on, causing CK1 to provide a low-level signal to the signal output terminal OUT.

[0070] The switch M3 is turned on, providing a low-level signal from the signal input terminal STV to the fifth node N5, resulting in a low potential. Since the gate of the switch M4 is connected to the second power supply terminal VGL, and the second power supply terminal VGL provides a low-level signal, the switch M4 remains in the on state. Therefore, the signal at the fifth node N5 is written to the third node N3 via the switch M4, resulting in a low potential. The switch M9 is turned on, and the second power supply terminal VGL provides a low-level signal to the signal output terminal OUT.

[0071] In summary, the signal output terminal OUT outputs a low-level signal in the first stage T1.

[0072] In the second phase T2 , the signal input terminal STV provides a high-level signal, and the first clock signal terminal CK2 and the second clock signal terminal CK1 both provide low-level signals. Figure 6 FIG. 4 is a state diagram of the shift register in the second stage T2. FIG.

[0073] In the second phase T2, CK1 provides a low-level signal, turning on switch M3. The high-level signal provided by STV is written to the fifth node N5, which is at a high potential. Furthermore, because switch M4 remains on, the high-level signal provided by STV continues to be written to the third node N3, which is at a high potential. Switch M9 is turned off. When the fifth node N5 is at a high potential, a high-level signal is input to the gate of switch M5, turning it off.

[0074] Because STV provides a high-level signal, switch M6 is turned off. Furthermore, because CK2 provides a low-level signal, CK2 is connected to the gate of switch M7 via the third capacitor C3, which is equivalent to inputting a low-level signal to the gate of switch M7. Therefore, switch M7 is turned on, and the low-level signal provided by CK2 is written into the sixth node N6 and the fourth node N4. The sixth node N6 and the fourth node N4 are at a low potential, and switch M8 is turned on. As a result, CK1 provides a low-level signal to the signal output terminal OUT, and the signal output terminal OUT outputs a low-level signal in the second phase T2.

[0075] In the third phase T3 , the signal input terminal STV and the second clock signal terminal CK1 both provide high-level signals, and the first clock signal terminal CK2 provides a low-level signal. Figure 7 FIG. 4 is a state diagram of the shift register in the third stage T3.

[0076] In the third phase T3, due to the high-level signal provided by STV, switch M6 is turned off. Due to the high-level signal provided by CK1, both switch M3 and switch M5 are turned off. Since switch M3 is turned off, node N3 maintains the high potential from the previous phase T2, and switch M9 remains off. Furthermore, due to the low-level signal provided by CK2, CK2 is connected to the gate of switch M7 via the third capacitor C3, causing switch M7 to remain on. The low-level signal provided by CK2 is written to the sixth node N6 and the fourth node N4. The sixth node N6 and the fourth node N4 remain at a low potential, turning switch M8 on. At this time, CK1 provides a high-level signal, thus providing a high-level signal to the signal output terminal OUT, causing the signal output terminal OUT to output a high-level signal in the third phase T3.

[0077] In the fourth phase T4 , the signal input terminal STV provides a low-level signal, and the first clock signal terminal CK2 and the second clock signal terminal CK1 both provide high-level signals. Figure 8 FIG. 4 is a state diagram of the shift register in the fourth stage T4.

[0078] In the fourth phase T4, CK1 provides a high-level signal, turning off switch M3. Consequently, node N3 maintains the high potential from the previous phase T3, and switch M9 remains off. Furthermore, STV provides a low-level signal, turning on switch M6. As a result, the high-level signal from the first power supply terminal VGH is input to the gate of switch M7, turning off switch M7. Consequently, the fourth node N4 maintains the low potential from the previous phase T3, turning on switch M8. CK2 provides a high-level signal to signal output terminal OUT, causing signal output terminal OUT to output a high-level signal in the fourth phase T4.

[0079] In the fifth stage T5 , the signal input terminal STV and the second clock signal terminal CK1 both provide low-level signals, and the first clock signal terminal CK2 provides a high-level signal. Figure 9 FIG. 4 is a state diagram of the shift register in the fifth stage T5. FIG.

[0080] In the fifth stage T5, since CK1 provides a low-level signal, the switch tube M3 is turned on, so that the low-level signal provided by STV is written to the fifth node N5, and the fifth node N5 is at a low potential. Since the switch tube M4 is continuously in the on state, the low potential of the fifth node N5 is further written into the third node N3, and the third node N3 is at a low potential, and the switch tube M9 is turned on.

[0081] Furthermore, when the fifth node N5 is at a low potential, the switch M5 is turned on. Thus, the low-level signal provided by STV is written to the sixth node N6 and the fourth node N4 via the switch M5. The sixth node N6 and the fourth node N4 are at low potentials, and the switch M8 is turned on. Since CK1 provides a low-level signal at this time, CK1 provides a low-level signal to the signal output terminal OUT, and the signal output terminal OUT outputs a low-level signal in the fifth phase T5.

[0082] Combining the fourth stage T4 and the fifth stage T5, it can be seen that the process of the signal output terminal OUT jumping from a high-level signal to a low-level signal is substantially synchronized with the signal provided by CK1. In some embodiments, when the signal output terminal OUT jumps from a high-level signal to a low-level signal, the low-level signal provided by STV is written to the third node N3 through the switches M3 and M4 to turn on the switch M9. Due to the threshold loss of the switches M3 and M4, the signal written to the third node N3 by the low-level signal provided by STV will also be lost, resulting in a falling edge step when the signal output terminal OUT jumps from a high-level signal to a low-level signal. In the embodiment of the present application, since the process of the signal output terminal OUT jumping from a high-level signal to a low-level signal is substantially synchronized with the signal provided by CK1, there is no threshold loss at this time. Therefore, the shift register can output a signal without a falling edge step, thereby solving the falling edge step problem existing in the LTPO circuit, thereby improving the stability of the LTPO circuit output signal, and further reducing the adverse effects on image quality.

[0083] Figure 10 This is a schematic diagram of another shift register provided in an embodiment of the present application. Figure 10As shown, the shift register also includes a voltage stabilizing circuit 40, which is electrically connected to the third node N3 and the first clock signal terminal CK2 respectively. The voltage stabilizing circuit 40 is configured to reduce the voltage of the third node N3 after the output circuit 30 switches the high-level signal output by the second clock signal terminal CK1 to the signal output terminal OUT to a low-level signal, so as to ensure that the output circuit 30 provides the signal of the second power supply terminal VGL to the signal output terminal OUT.

[0084] Figure 11 This is a circuit diagram of another shift register provided in an embodiment of the present application. Figure 11 The voltage stabilizing circuit 40 includes a first switch tube M1 and a first capacitor C1.

[0085] The control electrode, first electrode and second electrode of the first switch tube M1 are electrically connected to the first electrode of the first capacitor C1, the second electrode of the first capacitor C1 and the first clock signal terminal CK2 respectively; the first electrode of the first capacitor C1 is also electrically connected to the third node N3.

[0086] Figure 12 This is a circuit diagram of another shift register provided in an embodiment of the present application. Figure 12 The voltage stabilizing circuit 40 includes a first capacitor C1. A first electrode and a second electrode of the first capacitor C1 are electrically connected to the third node N3 and the first clock signal terminal CK2, respectively.

[0087] In one embodiment, method 300 further includes: in a sixth stage, inputting a signal from the first clock signal end to the third node to reduce the potential of the third node, turning on the ninth switch tube, and continuously providing a low-level signal output from the second power supply end to the signal output end.

[0088] Continue to refer Figure 4 In the sixth stage T6, the signal input terminal STV, the first clock signal terminal CK2, and the second clock signal terminal CK1 all provide low-level signals. Figure 11 Taking the circuit diagram shown as an example, because CK1 provides a low-level signal, switch M3 is turned on. Furthermore, because switch M4 remains in the on state, the low-level signal provided by STV is written to third node N3 via switches M3 and M4, resulting in a low potential at third node N3. Because the gate of switch M1 is connected to third node N3, this is equivalent to a low-level signal being input to the gate of switch M1. Switch M1 is turned on, and the low-level signal provided by CK2 is written to third node N3 via switch M1. This further lowers the potential of third node N3, ensuring reliable conduction of switch M9. Consequently, the second power supply terminal VGL continuously provides a low-level signal to signal output terminal OUT, ensuring that signal output terminal OUT continuously outputs a low-level signal and that the waveform outputted by signal output terminal OUT is correct.

[0089] Figure 12 The principle of the circuit diagram shown is the same as above Figure 11 Similarly, the purpose is to reduce the potential of the third node N3 in the sixth stage to ensure that the signal output terminal OUT continuously outputs a low-level signal, thereby ensuring the correctness of the waveform output by the signal output terminal OUT.

[0090] Figure 13 This is a schematic diagram of another shift register provided in an embodiment of the present application. Figure 13 As shown, the shift register further includes a step-down circuit 50, which is electrically connected to the second node N2, the control circuit 20, and the second power supply terminal VGL respectively. The step-down circuit 50 is configured to reduce the potential of the second node N2 under the control of the second power supply terminal VGL.

[0091] Figure 14 This is a circuit diagram of another shift register provided in an embodiment of the present application. Figure 14 The step-down circuit 50 includes a second switch tube M2 , and a control electrode, a first electrode, and a second electrode of the second switch tube M2 are electrically connected to the second power supply terminal VGL, the second node N2 , and the control circuit 20 , respectively.

[0092] In one embodiment, the method 300 further includes: in each of the first stage to the fifth stage, inputting a low-level signal output by the second power supply terminal to the second node to reduce the potential of the second node.

[0093] In the embodiment of the present application, when the switch M7 is turned on, an excessively high voltage between the drain and source of the switch M7 may cause the switch M7 to fail, thereby reducing the life of the switch M7. Therefore, the present application designs a step-down circuit 50 that can reduce the potential of the second node N2, thereby reducing the voltage between the drain and source of the switch M7 to prevent failure of the switch M7.

[0094] Specifically, since the gate of the switch tube M2 is connected to the second power supply terminal VGL, and the second power supply terminal VGL continuously provides a low-level signal, the switch tube M2 is always in the on state. In this way, the switch tube M2 can bear part of the voltage, thereby reducing the potential of the second node N2, thereby reducing the voltage between the drain and source of the switch tube M7. In this way, the failure of the switch tube M7 can be prevented, thereby extending the life of the switch tube M7.

[0095] Those skilled in the art will appreciate that, in any of the shift registers shown in the above embodiments, all switches may also be N-type transistors. When N-type transistors are used, the states of the first power supply terminal VGH, the second power supply terminal VGL, the input signal terminal STV, the first clock signal terminal CK2, and the second clock signal terminal CK1 are opposite to those when P-type transistors are used.

[0096] In the disclosed embodiments, the switch transistors can all be N-type thin film transistors or P-type thin film transistors, which can unify the process flow, reduce the process steps, and help improve the product yield. In addition, considering that the leakage current of low-temperature polysilicon thin film transistors is relatively small, it is preferred that all transistors in the embodiments of the present application be low-temperature polysilicon thin film transistors. Specifically, the thin film transistors can be bottom-gate thin film transistors or top-gate thin film transistors, as long as they can achieve the switching function.

[0097] It should be noted that the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be parasitic capacitors of the transistor or external capacitors, which are not limited in the present disclosure.

[0098] The present application also provides a driving circuit, which includes a plurality of cascaded shift registers as in any of the above embodiments.

[0099] The input signal terminal of the first-stage shift register is connected to the enable signal line, the input signal terminal of the n-stage shift register is connected to the output terminal of the nx-stage shift register, the first clock signal terminal and the second clock signal terminal of each shift register are connected to two different clock signal lines, and the two clock signal lines connected to each shift register are not exactly the same, wherein n is a positive integer greater than or equal to 2, x is an integer greater than or equal to 1, and n>x.

[0100] Take n as 4 as an example, refer to Figure 15 The signal input terminal STV of the first-stage shift register is connected to the enable signal line, the signal output terminal OUT1 of the first-stage shift register is connected to the signal input terminal STV of the second-stage shift register, the signal output terminal OUT2 of the second-stage shift register is connected to the signal input terminal STV of the third-stage shift register, and the signal output terminal OUT3 of the third-stage shift register is connected to the signal input terminal STV of the fourth-stage shift register.

[0101] Moreover, the two clock signal terminals CK1 and CK2 of the first-stage shift register are connected to the CK1 and CK2 signal lines respectively, the two clock signal terminals CK1 and CK2 of the second-stage shift register are connected to the CK2 and CK3 signal lines respectively, the two clock signal terminals CK1 and CK2 of the third-stage shift register are connected to the CK3 and CK4 signal lines respectively, and the two clock signal terminals CK1 and CK2 of the fourth-stage shift register are connected to the CK4 and CK1 signal lines respectively.

[0102] In the embodiment of the present application, the driving signals of the enable signal line STV and the four clock signal lines are as follows: Figure 16 As shown, the signal output terminals of the four shift registers output the signal reference Figure 16 OUT1, OUT2, OUT3, OUT4 shown. Figure 16 It can be seen that the time period of the high-level signal output by the signal output terminal OUT1 of the first-stage shift register is consistent with the time period of one of the high-level signals of the CK1 signal line, the time period of the high-level signal output by the signal output terminal OUT2 of the second-stage shift register is consistent with the time period of one of the high-level signals of the CK2 signal line, the time period of the high-level signal output by the signal output terminal OUT3 of the third-stage shift register is consistent with the time period of one of the high-level signals of the CK3 signal line, and the time period of the high-level signal output by the signal output terminal OUT4 of the fourth-stage shift register is consistent with the time period of one of the high-level signals of the CK4 signal line.

[0103] It should be understood that the above Figure 15 The connection relationship of the multiple shift registers shown is only an example and may also include other connection relationships, which should not cause any special limitation to this application.

[0104] In addition, the present application also provides a display substrate, which includes a display area, a frame area located around the display area, and the driving circuit described in the above embodiment, and the driving circuit is located in the frame area.

[0105] The embodiment of the present application further provides a computer program product, which includes: computer program code, which enables the computer to execute method 300 in the above embodiment when the computer program code is executed on the computer.

[0106] The embodiment of the present application further provides a computer-readable medium, wherein the computer-readable medium stores a program code. When the computer program code is executed on a computer, the computer executes the method 300 in the above embodiment.

[0107] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0108] The terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0109] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0110] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and components or steps may be substituted with equivalents without departing from the scope of the present application. In particular, the various technical features described in the various embodiments may be combined in any manner, provided there are no conflicts in structure or method steps. The present application is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A shift register, characterized in that: Including input circuit, control circuit and output circuit; The input circuit is electrically connected to the signal input terminal, the first power terminal, the first clock signal terminal, the first node, and the second node respectively. The input circuit is configured to provide the signal of the signal input terminal to the first node and provide the signal of the first power terminal to the second node under the control of the first clock signal terminal. The control circuit is electrically connected to the first node, the second node, the third node, the fourth node, the second clock signal terminal, and the second power supply terminal, respectively, and is configured to control the signals of the third node and the fourth node according to the signals of the first node and the second node; The output circuit is electrically connected to the third node, the fourth node, the second clock signal terminal, the second power supply terminal and the signal output terminal, respectively. The output circuit is configured to provide the signal of the second clock signal terminal to the signal output terminal under the control of the third node and the fourth node.

2. The shift register according to claim 1, wherein: The shift register also includes a voltage stabilizing circuit, which is electrically connected to the third node and the first clock signal terminal respectively. The voltage stabilizing circuit is configured to reduce the voltage of the third node after the output circuit switches the high-level signal output by the second clock signal terminal to the signal output terminal to a low-level signal, so as to ensure that the output circuit provides the signal of the second power supply terminal to the signal output terminal.

3. The shift register according to claim 2, wherein: The voltage stabilizing circuit includes a first switch tube and a first capacitor; The control electrode, the first electrode, and the second electrode of the first switch tube are electrically connected to the first electrode of the first capacitor, the second electrode of the first capacitor, and the first clock signal terminal respectively; The first electrode of the first capacitor is also electrically connected to the third node.

4. The shift register according to claim 2, wherein: The voltage stabilizing circuit includes a first capacitor; A first electrode and a second electrode of the first capacitor are electrically connected to the third node and the first clock signal end, respectively.

5. The shift register according to any one of claims 1 to 4, characterized in that: The shift register further includes a step-down circuit, which is electrically connected to the second node, the control circuit, and the second power supply terminal respectively. The step-down circuit is configured to reduce the potential of the second node under the control of the second power supply terminal.

6. The shift register according to claim 5, wherein: The step-down circuit includes a second switch tube, and a control electrode, a first electrode, and a second electrode of the second switch tube are electrically connected to the second power supply terminal, the second node, and the control circuit respectively.

7. The shift register according to any one of claims 1 to 4, characterized in that: The control circuit includes a third switch tube, a fourth switch tube, a fifth switch tube and a second capacitor; The control electrode, the first electrode, and the second electrode of the third switch tube are electrically connected to the second clock signal terminal, the first node, and the fifth node respectively; The control electrode, the first electrode and the second electrode of the fourth switch tube are electrically connected to the second power supply end, the fifth node and the third node respectively; The control electrode, the first electrode, and the second electrode of the fifth switch tube are electrically connected to the fifth node, the second clock signal terminal, and the sixth node respectively; A first electrode and a second electrode of the second capacitor are electrically connected to the sixth node and the second clock signal end, respectively.

8. The shift register according to any one of claims 1 to 4, characterized in that: The input circuit includes a sixth switching tube, a seventh switching tube and a third capacitor; The control electrode, the first electrode, and the second electrode of the sixth switch tube are electrically connected to the signal input terminal, the seventh node, and the first power supply terminal respectively; The control electrode, the first electrode, and the second electrode of the seventh switch tube are electrically connected to the seventh node, the first clock signal terminal, and the second node respectively; A first electrode and a second electrode of the third capacitor are electrically connected to the first clock signal terminal and the seventh node respectively.

9. The shift register according to any one of claims 1 to 4, characterized in that: The output circuit includes an eighth switching tube and a ninth switching tube; The control electrode, the first electrode, and the second electrode of the eighth switch tube are electrically connected to the fourth node, the second clock signal terminal, and the signal output terminal respectively; The control electrode, the first electrode, and the second electrode of the ninth switch tube are electrically connected to the third node, the second power supply end, and the signal output end, respectively.

10. A driving circuit, characterized in that: A shift register comprising a plurality of cascaded shift registers according to any one of claims 1 to 9; The input signal terminal of the first-stage shift register is connected to the enable signal line, the input signal terminal of the n-stage shift register is connected to the output terminal of the nx-stage shift register, the first clock signal terminal and the second clock signal terminal of each shift register are connected to two different clock signal lines, and the two clock signal lines connected to each shift register are not exactly the same, wherein n is a positive integer greater than or equal to 2, x is an integer greater than or equal to 1, and n>x.

11. A display substrate, characterized in that: The device comprises a display area, a frame area located around the display area, and the driving circuit according to claim 10, wherein the driving circuit is located in the frame area.

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