Light emitting diode display panel, manufacturing method and display device

Abstract

This invention provides a light-emitting diode (LED) display panel, a manufacturing method, and a display device. The LED display panel includes: a substrate; LED chips, with multiple LED chips arranged in an m×n array on the substrate; and a driving circuit disposed on the substrate and electrically connected to the multiple LED chips, including a positive driving sub-circuit and a negative driving sub-circuit. The positive terminals of the multiple LED chips are respectively connected to the positive driving sub-circuit, and the negative terminals of the multiple LED chips are respectively connected to the negative driving sub-circuit. In this invention, the LED chips and the driving circuit are directly integrated on the substrate, which reduces the need for mass transfer and bonding processes after separately manufacturing the LED chips and the driving circuit backplane, effectively avoiding yield losses caused by mass transfer processes. The reduced process steps correspondingly reduce material and equipment consumption, save production costs, and improve production efficiency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing, and in particular relates to a light-emitting diode display panel, a manufacturing method thereof, and a display device. Background Technology

[0002] The current bottlenecks in Micro-LED display technology mainly lie in chip fabrication, mass transfer, and full-color display, with mass transfer being the most crucial technology, where yield losses typically occur. Traditional techniques are inefficient for mass transfer, as millions of chips can be transferred at once. Currently, the industry mainstream utilizes electrostatic / magnetic / vacuum adsorption, Vandewall printing, adhesive bonding, and fluid assembly technologies for mass chip transfer. Vandewall printing is widely used; it employs PDMS as a medium to create bumps, using the slight adhesion of PDMS for selective transfer. However, this material requires extremely high flatness, resulting in high market prices including mold costs, and the size of the transfer head is limited by the manufacturing process, thus restricting transfer efficiency and posing a risk to yield.

[0003] Therefore, there is an urgent need for a technical solution that integrates chips and circuits directly on the substrate for display without requiring mass transfer. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a light-emitting diode display panel technology solution that does not require mass transfer, in order to solve the yield loss problem of Micro-LED in the mass transfer process.

[0005] To achieve the above and other related objectives, the specific technical solutions provided by the present invention are as follows.

[0006] A method for manufacturing a light-emitting diode (LED) display panel includes:

[0007] Provide substrate;

[0008] Multiple light-emitting diode chips arranged in an m×n array are formed on the substrate, where m and n are integers greater than or equal to 2;

[0009] A driving circuit is formed on the substrate, the driving circuit including a positive driving sub-circuit and a negative driving sub-circuit; and

[0010] The plurality of light-emitting diode chips are electrically connected to the driving circuit respectively, the positive terminals of the plurality of light-emitting diode chips are electrically connected to the positive terminal driving sub-circuit respectively, and the negative terminals of the plurality of light-emitting diode chips are electrically connected to the negative terminal driving sub-circuit respectively.

[0011] In the above-mentioned method for manufacturing LED display panels, the LED chips and driving circuits are directly integrated on the substrate, which reduces the need for mass transfer and bonding processes after independently manufacturing the LED chips and driving circuit backplanes. This effectively avoids yield losses caused by mass transfer processes. The reduction in process steps also reduces material and equipment consumption, saves production costs, and improves production efficiency. The positive terminals of multiple array-designed LED chips are electrically connected to the positive terminal driving sub-circuit, and the negative terminals of multiple array-designed LED chips are electrically connected to the negative terminal driving sub-circuit. In other words, multiple array-designed LED chips are connected in parallel and driven to light up simultaneously. The driving circuit structure is simple and the driving efficiency is high.

[0012] Optionally, the step of forming light-emitting diode chips arranged in an m×n array on the substrate includes:

[0013] An epitaxial layer is formed on the substrate, the epitaxial layer comprising at least an N-type layer and a P-type layer;

[0014] The epitaxial layer is etched to form multiple independent epitaxial units arranged in an m×n array.

[0015] An insulating layer is formed covering multiple epitaxial units;

[0016] The insulating layer is etched to form a first insulating portion located on the top of the epitaxial cell, a second insulating portion located on the first side of the epitaxial cell, and a third insulating portion located on the second side of the epitaxial cell. The top of the second insulating portion is flush with the bottom of the N-type layer of the epitaxial cell, and the top of the third insulating portion is flush with the bottom of the P-type layer of the epitaxial cell.

[0017] Optionally, forming an epitaxial layer on the substrate includes:

[0018] A sacrificial layer, an N-type layer, a multiple quantum well layer, and a P-type layer are sequentially stacked on the substrate.

[0019] Optionally, the etching of the insulating layer includes:

[0020] A first photoresist is coated on the insulating layer, and the first photoresist is exposed. After exposure, the first photoresist only covers the insulating layer on the top of the epitaxial unit and the insulating layer on the second side of the epitaxial unit.

[0021] Using the exposed first photoresist as a mask, etching is performed to remove the exposed insulating layer, leaving only a portion of the insulating layer on the first side of the epitaxial unit. The top of the portion of the insulating layer retained on the first side of the epitaxial unit is flush with the bottom of the N-type layer in the epitaxial unit, thus obtaining the second insulating portion.

[0022] Remove the residual first photoresist, coat the second photoresist on the insulating layer, expose the second photoresist, and after exposure, the second photoresist only covers the insulating layer at the top of the epitaxial unit and the second insulating portion;

[0023] Using the exposed second photoresist as a mask, etching is performed to remove the exposed insulating layer, leaving only a portion of the insulating layer on the second side of the epitaxial unit. The top of the portion of the insulating layer retained on the second side of the epitaxial unit is flush with the bottom of the P-type layer in the epitaxial unit, thus obtaining the third insulating portion.

[0024] Remove the remaining second photoresist, retain the insulating layer on top of the epitaxial unit, and obtain the first insulating portion.

[0025] Optionally, forming a driving circuit on the substrate includes:

[0026] A negative electrode driving sub-circuit is formed on the substrate. The negative electrode driving sub-circuit includes a negative electrode energizing region and n negative electrode line regions. The n negative electrode line regions are electrically connected to the negative electrode energizing region. The n negative electrode line regions are spaced apart from each other along a first direction. The n negative electrode line regions correspond one-to-one with and are adjacent to the second insulating portions of the n columns of light-emitting diode chips.

[0027] A positive driving sub-circuit is formed on the substrate. The positive driving sub-circuit includes a positive energized region and n positive line regions. The n positive line regions are electrically connected to the positive energized region. The n positive line regions are spaced apart from each other along a first direction. The n positive line regions correspond one-to-one with the third insulating portion of the n columns of light-emitting diode chips and are arranged adjacent to each other.

[0028] Among them, the n negative electrode line areas and the n positive electrode line areas are staggered in the first direction and arranged in a cross tooth shape.

[0029] Optionally, electrically connecting the plurality of light-emitting diode chips to the driving circuit respectively includes:

[0030] A negative electrode is formed on the second insulating portion of the light-emitting diode chip and the negative electrode line region. The negative electrode electrically connects the N-type layer of the epitaxial unit to the negative electrode line region, and the negative electrode of the light-emitting diode chip is electrically led out from the N-type layer of the epitaxial unit.

[0031] A positive electrode is formed on the third insulating portion of the light-emitting diode chip and the positive electrode line region. The positive electrode electrically connects the P-type layer of the epitaxial unit to the positive electrode line region, and the positive electrode of the light-emitting diode chip is electrically led out from the P-type layer of the epitaxial unit.

[0032] A light-emitting diode display panel, comprising:

[0033] Substrate;

[0034] Light-emitting diode (LED) chips, wherein a plurality of LED chips are arranged in an m×n array on the substrate, where m and n are integers greater than or equal to 2; and

[0035] A driving circuit is disposed on the substrate and electrically connected to a plurality of light-emitting diode chips, including a positive driving sub-circuit and a negative driving sub-circuit. The positive terminals of the plurality of light-emitting diode chips are respectively electrically connected to the positive driving sub-circuit, and the negative terminals of the plurality of light-emitting diode chips are respectively electrically connected to the negative driving sub-circuit.

[0036] In the aforementioned LED display panel, the LED chips and driving circuits are directly integrated onto the substrate. This reduces the need for mass transfer and bonding processes after independently fabricating the LED chips and driving circuit backplanes, effectively avoiding yield losses caused by mass transfer. The reduction in processes also reduces material and equipment consumption, saving production costs and improving production efficiency. The positive terminals of multiple array-designed LED chips are electrically connected to the positive driving sub-circuit, and the negative terminals are electrically connected to the negative driving sub-circuit. In other words, multiple array-designed LED chips are connected in parallel and driven to light up simultaneously. The driving circuit structure is simple and the driving efficiency is high.

[0037] Optionally, the light-emitting diode chip includes an epitaxial cell, a first insulating portion located on top of the epitaxial cell, a second insulating portion located on a first side of the epitaxial cell, and a third insulating portion located on a second side of the epitaxial cell. The epitaxial cell includes at least an N-type layer and a P-type layer. The top of the second insulating portion is flush with the bottom of the N-type layer of the epitaxial cell. The N-type layer of the epitaxial cell leads out the negative electrode of the light-emitting diode chip. The top of the third insulating portion is flush with the bottom of the P-type layer of the epitaxial cell. The P-type layer of the epitaxial cell leads out the positive electrode of the light-emitting diode chip.

[0038] Optionally, the positive drive sub-circuit includes a positive energized area and n positive line areas. The n positive line areas are spaced apart from each other along a first direction, and each of the n positive line areas is electrically connected to the positive energized area. The positive terminal of the i-th column of the LED chip is electrically connected to the i-th positive line area, where i is an integer from 1 to n. The negative drive sub-circuit includes a negative energized area and n negative line areas. The n negative line areas are spaced apart from each other along the first direction. The n negative line areas are staggered from the n positive line areas in the first direction, and each of the n negative line areas is electrically connected to the negative energized area. The negative terminal of the i-th column of the LED chip is electrically connected to the i-th negative line area, where i is an integer from 1 to n.

[0039] A display device comprising a light-emitting diode display panel as described in any of the preceding claims.

[0040] In the aforementioned display device, the light-emitting diode (LED) chip and the driving circuit are directly integrated on the substrate, which reduces the need for mass transfer, bonding, and other processes after separately fabricating the LED chip and the driving circuit backplane. This effectively avoids yield loss caused by the mass transfer process. The reduction in process steps saves production costs and improves production efficiency. Multiple LED chips arranged in an array are connected in parallel and driven to light up simultaneously, resulting in a simple driving circuit structure and high driving efficiency. Attached Figure Description

[0041] Figures 1-2 This is a schematic diagram of the structure of a light-emitting diode display panel in one embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram illustrating the steps of the LED display panel manufacturing method of the present invention.

[0043] Figure 4 - Figure 19 for Figure 1 A process flow diagram of the manufacturing method of a light-emitting diode display panel.

[0044] Explanation of icon numbers

[0045] 1—Substrate, 2—Epilithographic layer, 21—Sacrificial layer, 22—N-type layer, 23—Multiple quantum well layer, 24—P-type layer, 2'—Epilithographic unit, 2”—Light emitting diode chip, 3—Insulating layer, 31—First insulating part, 32—Second insulating part, 33—Third insulating part, 4—First photoresist, 5—Second photoresist, 6—Driving circuit, 61—Negative electrode driving sub-circuit, 62—Positive electrode driving sub-circuit, 611—Negative electrode energizing region, 612—Negative electrode line region, 621—Positive electrode energizing region, 622—Positive electrode line region, 71—Negative electrode, 72—Positive electrode. Detailed Implementation

[0046] As described in the background section, the inventors discovered that in the existing Micro-LED manufacturing process, mass transfer is inefficient, requires stringent process conditions, and inevitably results in yield loss, which greatly reduces production efficiency and increases production costs.

[0047] Based on this, the present invention proposes a manufacturing technology solution for a light-emitting diode display panel: directly integrating light-emitting diode chips and driving circuits on a substrate to reduce the massive transfer, bonding and welding processes after independently manufacturing the backplane of the light-emitting diode chips and driving circuits; and directly driving multiple light-emitting diode chips arranged in an array in parallel through the driving circuit to drive them to light up simultaneously, thereby improving driving efficiency.

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please see Figures 1 to 19 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0050] like Figures 1-2 As shown, an embodiment of the present invention provides a light-emitting diode display panel, which includes:

[0051] Substrate 1;

[0052] Light-emitting diode chip 2”, and multiple light-emitting diode chips 2” are arranged in an m×n array on substrate 1, where m and n are integers greater than or equal to 2; and

[0053] The driving circuit 6 is disposed on the substrate 1 and electrically connected to multiple light-emitting diode chips 2”. It includes a positive driving sub-circuit 62 and a negative driving sub-circuit 61. The positive terminals of the multiple light-emitting diode chips 2” are electrically connected to the positive driving sub-circuit 62, and the negative terminals of the multiple light-emitting diode chips 2” are electrically connected to the negative driving sub-circuit 61.

[0054] The substrate 1 can be a non-conductive substrate such as sapphire or glass, or a semiconductor substrate such as gallium arsenide or gallium nitride, and there is no limitation on it.

[0055] It is understandable that the LED chip 2” is not limited to Figure 1 The 3×5 array design shown can also be other m×n array structure designs such as 2×2, 2×3, 3×4, etc., in other optional embodiments of the present invention, where m and n are integers greater than or equal to 2.

[0056] In detail, such as Figure 2 As shown, the light-emitting diode chip 2” includes an epitaxial cell 2’, a first insulating portion 31 located on the top of the epitaxial cell 2’, a second insulating portion 32 located on the first side of the epitaxial cell 2’, and a third insulating portion 33 located on the second side of the epitaxial cell 2’. The epitaxial cell 2’ includes at least an N-type layer 22 and a P-type layer 24. The top of the second insulating portion 32 is flush with the bottom of the N-type layer 22 of the epitaxial cell 2’. The negative electrode of the light-emitting diode chip 2” is led out from the N-type layer of the epitaxial cell 2’. The top of the third insulating portion 33 is flush with the bottom of the P-type layer 24 of the epitaxial cell 2’. The positive electrode of the light-emitting diode chip 2” is led out from the P-type layer 24 of the epitaxial cell 2’.

[0057] In detail, such as Figures 1-2 As shown, the positive drive sub-circuit 62 includes a positive energized area 621 and n positive line areas 622. The n positive line areas 622 are spaced apart from each other along a first direction (horizontal direction), and each of the n positive line areas 622 is electrically connected to the positive energized area 621. The positive terminal of the i-th column of LED chip 2” is electrically connected to the i-th positive line area 622 through the positive electrode 72, where i is an integer from 1 to n. The negative drive sub-circuit 61 includes a negative energized area 611 and n negative line areas 612. The n negative line areas 612 are spaced apart from each other along a first direction. The n negative line areas 612 and the n positive line areas 622 are staggered in the first direction, and each of the n negative line areas 612 is electrically connected to the negative energized area 611. The negative terminal of the i-th column of LED chip 2” is electrically connected to the i-th negative line area 612 through the negative electrode 71, where i is an integer from 1 to n.

[0058] Thus, as Figures 1-2As shown, the light-emitting diode chip 2” and the driving circuit 6 are directly integrated on the substrate 1, reducing the need for mass transfer and bonding processes after independently fabricating the light-emitting diode chip and the driving circuit backplane, thus avoiding yield loss caused by mass transfer. The reduction in process steps will correspondingly reduce material and equipment consumption, save production costs, and improve production efficiency. The positive terminals of multiple array-designed light-emitting diode chips 2” are electrically connected to the positive terminal driving sub-circuit 62, and the negative terminals of multiple array-designed light-emitting diode chips 2” are electrically connected to the negative terminal driving sub-circuit 61. That is, multiple light-emitting diode chips 2” in an m×n array are arranged in parallel and driven to light up simultaneously. The driving circuit structure is simple and the driving efficiency is high.

[0059] Meanwhile, the present invention also provides a display device, which includes a light-emitting diode display panel as described in any of the above claims. Based on the structural design of the light-emitting diode display panel, which "directly integrates the light-emitting diode chip 2 and the driving circuit 6 on the substrate 1", the process flow is saved, the production efficiency is improved, and the product yield is increased. Moreover, the driving circuit structure is simple and the driving efficiency is high.

[0060] Furthermore, the present invention also provides a method for manufacturing a light-emitting diode (LED) display panel, used for manufacturing the aforementioned LED display panel, such as... Figure 3 As shown, it includes the following steps:

[0061] S1, Provide substrate 1;

[0062] S2. Multiple light-emitting diode chips 2” are formed on substrate 1 in an m×n array, where m and n are integers greater than or equal to 2;

[0063] S3. A driving circuit 6 is formed on the substrate 1. The driving circuit 6 includes a positive driving sub-circuit 62 and a negative driving sub-circuit 61; and

[0064] S4. Connect multiple LED chips 2” to the driving circuit 6 respectively, connect the positive terminals of multiple LED chips 2” to the positive driving sub-circuit 62 respectively, and connect the negative terminals of multiple LED chips 2” to the negative driving sub-circuit 61 respectively.

[0065] In detail, in step S1, the substrate 1 can be a non-conductive substrate such as sapphire or glass, or a semiconductor substrate such as gallium arsenide or gallium nitride, and there is no limitation on it here.

[0066] In detail, such as Figures 4-13 As shown, step S2, which involves forming a plurality of light-emitting diode chips 2 arranged in an m×n array on substrate 1, further includes:

[0067] S21, such as Figure 4As shown, an epitaxial layer 2 is formed on the substrate 1, and the epitaxial layer 2 includes at least an N-type layer 22 and a P-type layer 24;

[0068] S22, such as Figures 5-6 As shown, the epitaxial layer 2 is etched to form multiple independent epitaxial units 2' arranged in an m×n array;

[0069] S23, such as Figure 7 As shown, an insulating layer 3 is formed covering multiple epitaxial units 2';

[0070] S24, such as Figures 8-13 As shown, the insulating layer 3 is etched to form a first insulating portion 31 located on the top of the epitaxial cell 2', a second insulating portion 32 located on the first side of the epitaxial cell 2', and a third insulating portion 33 located on the second side of the epitaxial cell 2'. The top of the second insulating portion 32 is flush with the bottom of the N-type layer of the epitaxial cell 2', and the top of the third insulating portion 33 is flush with the bottom of the P-type layer of the epitaxial cell 2'.

[0071] More in detail, such as Figure 4 As shown, step S21, which involves forming an epitaxial layer 2 on substrate 1, further includes:

[0072] A sacrificial layer 21, an N-type layer 22, a multiple quantum well layer 23, and a P-type layer 24 are sequentially stacked on a substrate 1.

[0073] Optionally, in an optional embodiment of the present invention, the sacrificial layer 231 is made of U-type gallium nitride, the N-type layer 22 is made of N-type gallium nitride, and the P-type layer 24 is made of P-type gallium nitride; the N-type layer 22 and the P-type layer 24 form a PN junction. After being energized, electrons and holes in the PN junction collide to excite photons, thereby emitting light. The multiple quantum well layer 23 is mainly used to improve the recombination efficiency of electrons and holes.

[0074] More specifically, in step S22, such as Figures 5-6 As shown, a plateau etching (MESA) is performed using a photomask to etch the epitaxial layer 2, removing a portion of the epitaxial layer 2. The etching remains on the substrate 1, forming multiple independent epitaxial units 2' arranged in a 3x5 array on the substrate 1. It is understood that the epitaxial units 2' are not limited to... Figure 1 The 3×5 array design shown can also be other m×n array structure designs such as 2×2, 2×3, 3×4, etc., in other optional embodiments of the present invention, where m and n are integers greater than or equal to 2.

[0075] More specifically, in step S23, such as Figure 7 As shown, an insulating layer 3 is formed using processes such as chemical vapor deposition. The insulating layer 3 covers at least a plurality of epitaxial units 2', and isolates and protects the epitaxial units 2' through the insulating layer 3. The insulating layer 3 can be made of insulating materials such as silicon oxide.

[0076] More in detail, such as Figures 8-13 As shown, step S24 of etching the insulating layer 3 further includes:

[0077] S241, such as Figure 8 As shown, a first photoresist 4 is coated on the insulating layer 3 and exposed. After exposure and development, the first photoresist 4 only covers the insulating layer 3 on the top of the epitaxial unit 2' and the insulating layer 3 on the second side of the epitaxial unit 2'.

[0078] S242, such as Figure 9 As shown, using the first photoresist 4 after exposure as a mask, etching is performed to remove the exposed insulating layer 3, leaving only a portion of the insulating layer 2' on the first side of the epitaxial unit 2'. The top of the portion of the insulating layer 2' retained on the first side of the epitaxial unit 2' is flush with the bottom of the N-type layer 22 in the epitaxial unit 2', thus obtaining the second insulating part 32.

[0079] S243, such as Figure 10 As shown, the residual first photoresist 4 is removed, the second photoresist 5 is coated on the insulating layer 3, and the second photoresist 5 is exposed. The exposed second photoresist 5 only covers the insulating layer 3 on the top of the epitaxial unit 2' and the second insulating part 32.

[0080] S244, such as Figure 11 As shown, using the exposed second photoresist 5 as a mask, etching is performed to remove the exposed insulating layer 3, leaving only a portion of the insulating layer 3 on the second side of the epitaxial unit 2'. The top of the portion of the insulating layer 3 retained on the second side of the epitaxial unit 2' is flush with the bottom of the P-type layer 24 in the epitaxial unit 2', thus obtaining the third insulating part 33.

[0081] S245, such as Figures 12-13 As shown, the residual second photoresist 5 is removed, and the insulating layer 3 on top of the epitaxial unit 2' is retained to obtain the first insulating part 31.

[0082] Thus, we obtain Figures 12-13 The light-emitting diode chip 2” shown includes an epitaxial cell 2’, a first insulating portion 31 located on top of the epitaxial cell 2’, a second insulating portion 32 located on the first side of the epitaxial cell 2’, and a third insulating portion 33 located on the second side of the epitaxial cell 2’. The top of the second insulating portion 32 is flush with the bottom of the N-type layer 22 of the epitaxial cell 2’. The second insulating portion 32 just covers the sacrificial layer 21, leaving the N-type layer 22 exposed. The negative electrode of the light-emitting diode chip 2” is led out from the N-type layer 22 of the epitaxial cell 2’. The top of the third insulating portion 33 is flush with the bottom of the P-type layer 24 of the epitaxial cell 2’. The third insulating portion 33 just covers the sacrificial layer 21, the N-type layer 22 and the multiple quantum well layer 23, leaving the P-type layer 24 exposed. The positive electrode of the light-emitting diode chip 2” is led out from the P-type layer 24 of the epitaxial cell 2’.

[0083] In detail, such as Figures 14-16 As shown, step S3 of forming the driving circuit 6 on the substrate 1 further includes:

[0084] S31, such as Figures 14-15 As shown, a negative electrode driving sub-circuit 61 is formed on substrate 1 through photolithography and vapor deposition processes. The negative electrode driving sub-circuit 61 includes a negative electrode energized area 611 and n negative electrode line areas 612. The n negative electrode line areas 612 are electrically connected to the negative electrode energized area 611. The n negative electrode line areas 612 are arranged at intervals along a first direction. The n negative electrode line areas 612 correspond one-to-one with the second insulating part 32 of the n columns of light-emitting diode chips 2” and are arranged adjacent to each other.

[0085] S32, such as Figure 14 or Figure 16 As shown, a positive drive sub-circuit 62 is formed on substrate 1 through photolithography and vapor deposition processes. The positive drive sub-circuit 62 includes a positive energized area 621 and n positive line areas 622. The n positive line areas 622 are electrically connected to the positive energized area 621. The n positive line areas 622 are spaced apart from each other along a first direction. The n positive line areas 622 are respectively corresponding to and adjacent to the third insulating part 33 of the n columns of light-emitting diode chips 2”.

[0086] Among them, the negative driving sub-circuit 61 and the positive driving sub-circuit 62 can be made of high melting point conductive metals (such as titanium, molybdenum, tungsten) or metal alloy materials, and are mainly used for subsequent power-on driving of the light-emitting diode chip 2”.

[0087] More in detail, such as Figure 14 or Figure 16 As shown, the n negative line regions 612 and the n positive line regions 622 are staggered in the first direction and arranged in a cross tooth shape, that is, the negative driving sub-circuit 61 and the positive driving sub-circuit 62 are designed as two intersecting comb-shaped structures; in an optional embodiment of the present invention, the dimensions of the negative line region 612 and the positive line region 622 in the first direction are 3±0.5μm.

[0088] In detail, such as Figure 17-19 As shown, step S4, which electrically connects multiple light-emitting diode chips 2” to the driving circuit 6 respectively, further includes:

[0089] S41. A negative electrode 71 is formed on the second insulating part 32 and the negative electrode line region 612 of the light-emitting diode chip 2”. The negative electrode 71 electrically connects the N-type layer 22 of the epitaxial unit 2’ to the negative electrode line region 612, and the negative electrode of the light-emitting diode chip 2” is electrically led out from the N-type layer 22 of the epitaxial unit 2’.

[0090] S42. A positive electrode 72 is formed on the third insulating part 33 and the positive electrode line region 622 of the LED chip 2”. The positive electrode 72 electrically connects the P-type layer 24 of the epitaxial unit 2’ to the positive electrode line region 622, and the positive electrode of the LED chip 2” is electrically led out from the P-type layer 24 of the epitaxial unit 2’.

[0091] The negative electrode 71 and the positive electrode 72 can be made of a highly conductive metal material (such as gold) for electrode electrical lead-out connections. The negative electrode 71 and the positive electrode 72 can be prepared by a deposition-then-etching process. One end of the prepared negative electrode 71 is in ohmic contact with the N-type layer 22 of the epitaxial unit 2' and the other end is in ohmic contact with the negative electrode line region 612. One end of the prepared positive electrode 72 is in ohmic contact with the P-type layer 24 of the epitaxial unit 2' and the other end is in ohmic contact with the positive electrode line region 622. The thickness of the negative electrode 71 is slightly less than the thickness of the N-type layer 22 in the epitaxial unit 2', and the thickness of the positive electrode 72 is slightly less than the thickness of the P-type layer 24 in the epitaxial unit 2'.

[0092] It should be noted that the above description of the manufacturing process of LED display panels omits many specific descriptions of photolithography, etching, evaporation, deposition, and other processes, which are well known to those skilled in the art and will not be repeated here.

[0093] In summary, in the LED display panel and its manufacturing method and display device provided by this invention, the LED chip and driving circuit are directly integrated on the substrate, which reduces the need for mass transfer, bonding and welding processes after independently manufacturing the LED chip and driving circuit backplane, effectively avoiding yield loss caused by mass transfer. The reduction in process steps correspondingly reduces material and equipment consumption, saves production costs, and improves production efficiency. The positive electrodes of multiple array-designed LED chips are electrically connected to the positive electrode driving sub-circuit, and the negative electrodes of multiple array-designed LED chips are electrically connected to the negative electrode driving sub-circuit, that is, multiple array-designed LED chips are arranged in parallel and driven to light up simultaneously. The driving circuit structure is simple and the driving efficiency is high.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a light emitting diode display panel, characterized by, include: Provide substrate; Multiple m-shaped The array consists of n LED chips, where m and n are integers greater than or equal to 2. A driving circuit is formed on the substrate, the driving circuit including a positive driving sub-circuit and a negative driving sub-circuit; and The plurality of light-emitting diode chips are electrically connected to the driving circuit respectively, the positive terminals of the plurality of light-emitting diode chips are electrically connected to the positive terminal driving sub-circuit respectively, and the negative terminals of the plurality of light-emitting diode chips are electrically connected to the negative terminal driving sub-circuit respectively. The m-shaped formation on the substrate The n-array configuration includes LED chips, including: An epitaxial layer is formed on the substrate, the epitaxial layer comprising at least an N-type layer and a P-type layer; Etching the epitaxial layer to form multiple m-shaped layers n-array of independent epitaxial cells; An insulating layer is formed covering multiple epitaxial units; The insulating layer is etched to form a first insulating portion located on the top of the epitaxial cell, a second insulating portion located on the first side of the epitaxial cell, and a third insulating portion located on the second side of the epitaxial cell. The top of the second insulating portion is flush with the bottom of the N-type layer of the epitaxial cell, and the top of the third insulating portion is flush with the bottom of the P-type layer of the epitaxial cell.

2. The method for manufacturing a light-emitting diode display panel according to claim 1, characterized in that, The formation of the epitaxial layer on the substrate includes: A sacrificial layer, an N-type layer, a multiple quantum well layer, and a P-type layer are sequentially stacked on the substrate.

3. The method for manufacturing a light-emitting diode display panel according to claim 2, characterized in that, The etching of the insulating layer includes: A first photoresist is coated on the insulating layer, and the first photoresist is exposed. After exposure, the first photoresist only covers the insulating layer on the top of the epitaxial unit and the insulating layer on the second side of the epitaxial unit. Using the exposed first photoresist as a mask, etching is performed to remove the exposed insulating layer, leaving only a portion of the insulating layer on the first side of the epitaxial unit. The top of the portion of the insulating layer retained on the first side of the epitaxial unit is flush with the bottom of the N-type layer in the epitaxial unit, thus obtaining the second insulating portion. Remove the residual first photoresist, coat the second photoresist on the insulating layer, expose the second photoresist, and after exposure, the second photoresist only covers the insulating layer at the top of the epitaxial unit and the second insulating portion; Using the exposed second photoresist as a mask, etching is performed to remove the exposed insulating layer, leaving only a portion of the insulating layer on the second side of the epitaxial unit. The top of the portion of the insulating layer retained on the second side of the epitaxial unit is flush with the bottom of the P-type layer in the epitaxial unit, thus obtaining the third insulating portion. Remove the remaining second photoresist, retain the insulating layer on top of the epitaxial unit, and obtain the first insulating portion.

4. The method for manufacturing a light-emitting diode display panel according to claim 3, characterized in that, The process of forming a driving circuit on the substrate includes: A negative electrode driving sub-circuit is formed on the substrate. The negative electrode driving sub-circuit includes a negative electrode energizing region and n negative electrode line regions. The n negative electrode line regions are electrically connected to the negative electrode energizing region. The n negative electrode line regions are spaced apart from each other along a first direction. The n negative electrode line regions correspond one-to-one with and are adjacent to the second insulating portions of the n columns of light-emitting diode chips. A positive driving sub-circuit is formed on the substrate. The positive driving sub-circuit includes a positive energized region and n positive line regions. The n positive line regions are electrically connected to the positive energized region. The n positive line regions are spaced apart from each other along a first direction. The n positive line regions correspond one-to-one with the third insulating portion of the n columns of light-emitting diode chips and are arranged adjacent to each other. Among them, the n negative electrode line areas and the n positive electrode line areas are staggered in the first direction and arranged in a cross tooth shape.

5. The method for manufacturing a light-emitting diode display panel according to claim 4, characterized in that, The step of electrically connecting the plurality of light-emitting diode chips to the driving circuit respectively includes: A negative electrode is formed on the second insulating portion of the light-emitting diode chip and the negative electrode line region. The negative electrode electrically connects the N-type layer of the epitaxial unit to the negative electrode line region, and the negative electrode of the light-emitting diode chip is electrically led out from the N-type layer of the epitaxial unit. A positive electrode is formed on the third insulating portion of the light-emitting diode chip and the positive electrode line region. The positive electrode electrically connects the P-type layer of the epitaxial unit to the positive electrode line region, and the positive electrode of the light-emitting diode chip is electrically led out from the P-type layer of the epitaxial unit.

6. A light-emitting diode display panel, characterized in that, include: Substrate; LED chips, wherein multiple LED chips are arranged in an m An n-array is disposed on the substrate, where m and n are integers greater than or equal to 2; as well as A driving circuit is disposed on the substrate and electrically connected to a plurality of light-emitting diode chips, including a positive driving sub-circuit and a negative driving sub-circuit. The positive terminals of the plurality of light-emitting diode chips are respectively electrically connected to the positive driving sub-circuit, and the negative terminals of the plurality of light-emitting diode chips are respectively electrically connected to the negative driving sub-circuit. The light-emitting diode chip includes an epitaxial cell, a first insulating portion located on top of the epitaxial cell, a second insulating portion located on a first side of the epitaxial cell, and a third insulating portion located on a second side of the epitaxial cell. The epitaxial cell includes at least an N-type layer and a P-type layer. The top of the second insulating portion is flush with the bottom of the N-type layer of the epitaxial cell. The N-type layer of the epitaxial cell leads out the negative electrode of the light-emitting diode chip. The top of the third insulating portion is flush with the bottom of the P-type layer of the epitaxial cell. The P-type layer of the epitaxial cell leads out the positive electrode of the light-emitting diode chip.

7. The light-emitting diode display panel according to claim 6, characterized in that, The positive drive sub-circuit includes a positive energized area and n positive line areas. The n positive line areas are spaced apart from each other along a first direction, and each of the n positive line areas is electrically connected to the positive energized area. The positive terminal of the i-th column of the LED chip is electrically connected to the i-th positive line area, where i is an integer from 1 to n. The negative drive sub-circuit includes a negative energized area and n negative line areas. The n negative line areas are spaced apart from each other along the first direction. The n negative line areas are staggered from the n positive line areas in the first direction, and each of the n negative line areas is electrically connected to the negative energized area. The negative terminal of the i-th column of the LED chip is electrically connected to the i-th negative line area, where i is an integer from 1 to n.

8. A display device, characterized in that, Includes the light-emitting diode display panel as described in claim 6 or 7.

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