A power-on reset circuit, power supply system, chip and electronic device
The power-on reset circuit, composed of a current comparator and a Schmitt trigger, utilizes BJT transistors with different emitter areas to achieve fast power-on reset and integrate power-down detection, solving the problem of slow response speed in traditional power-on reset circuits and making it suitable for communication systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI CHIPANALOG MICROELECTRONICS LTD
- Filing Date
- 2022-12-08
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional power-on reset circuits require charging on-chip capacitors, resulting in slow response speeds that cannot meet the high-quality human-computer interaction requirements of communication systems.
A power-on reset circuit composed of a current comparator and a Schmitt trigger is used. The current comparator is constructed using BJT transistors with different emitter areas. The power supply voltage of the Schmitt trigger is slowly raised through a current mirror to achieve rapid power-on reset and integrates power-down detection function.
It achieves fast power-on reset, avoiding system uncertainty, and features a simple structure, small size, and high robustness, making it suitable for communication systems.
Smart Images
Figure CN115800979B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit technology, specifically to a power-on reset circuit, a power supply system, a chip, and an electronic device. Background Technology
[0002] Power-on reset refers to a method where the voltage is initially high at the RST point after being applied from zero. Then, because this point is grounded through a resistor, the level at the RST point gradually changes to a low level, causing the microcontroller's reset port level to switch from 1 to 0, thus achieving the reset function of the microcontroller.
[0003] Traditional power-on reset circuits reset all circuits by triggering a pulse to charge the on-chip capacitor after the system is powered on. At the moment of power-on, the capacitor charging current is at its maximum, and the capacitor is equivalent to a short circuit. The RST terminal is at a high level, and the circuit is automatically reset. When the voltage across the capacitor reaches the power supply voltage, the capacitor charging current is zero, and the capacitor is equivalent to an open circuit. The RST terminal is at a low level, and the program runs normally, avoiding the circuit being in an uncertain state after power-on.
[0004] However, existing methods are slow because they require charging on-chip capacitors, which can lead to excessively long response times in communication systems and hinder the achievement of high-quality human-computer interaction. Summary of the Invention
[0005] In view of the above, the present disclosure provides a power-on reset circuit, a power supply system, a chip, and an electronic device, which at least partially solves the problems existing in the prior art.
[0006] In a first aspect, embodiments of this disclosure provide a power-on reset circuit, applied in a power supply system, comprising:
[0007] Current comparator, Schmitt trigger, and inverter;
[0008] The current comparator is composed of BJT transistors with different emitter areas, and the current comparator is connected between the power supply voltage and the input terminal of the Schmitt trigger.
[0009] The output of the Schmitt trigger is connected to the inverter and is used to output a reset voltage.
[0010] According to a specific implementation of an embodiment of this disclosure, the current comparator includes:
[0011] The first resistor R1, the first BJT transistor Q1, the second BJT transistor Q2 and the third BJT transistor Q3 with different emitter areas, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5 and the sixth MOSFET M6;
[0012] The first resistor is connected between the power supply voltage, the base of the second BJT transistor Q2, the collector of the first BJT transistor Q1, and the base of the first BJT transistor Q1.
[0013] The collector of the second BJT transistor Q2 is connected to the gate and source of the first MOS transistor M1;
[0014] The collector of the third BJT transistor Q3 is connected to the gate and source of the third MOS transistor M3.
[0015] The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 and the source of the first MOS transistor M1.
[0016] The source of the second MOS transistor M2 is connected to the source of the sixth MOS transistor M6 and the input of the Schmitt trigger;
[0017] The gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 and the source of the third MOS transistor M3.
[0018] The source of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5;
[0019] The gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and the source of the fourth MOS transistor M4.
[0020] The base of the third BJT transistor Q3, the drain of the first MOSFET M1, the drain of the second MOSFET M2, the drain of the third MOSFET M3, and the drain of the fourth MOSFET M4 are connected to the power supply voltage.
[0021] The emitter of the first BJT transistor Q1, the drain of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6 are grounded.
[0022] According to a specific implementation of an embodiment of this disclosure, the current comparator further includes:
[0023] The second resistor R2 is connected to the power supply voltage, the first resistor R1, and the base of the third BJT transistor Q3.
[0024] According to a specific implementation of an embodiment of this disclosure, the current comparator further includes:
[0025] The third resistor R3 has one end connected to the emitter of the second BJT transistor Q2 and the emitter of the third BJT transistor Q3, and the other end grounded.
[0026] According to one specific implementation of this disclosure, the high threshold voltage of the Schmitt trigger is VSPH.
[0027] The power-on reset circuit also includes:
[0028] The power-down detection sub-circuit is connected between the power supply voltage, the current comparator, and the input of the Schmitt trigger.
[0029] According to a specific implementation of an embodiment of this disclosure, the power-down detection sub-circuit includes:
[0030] The fourth BJT transistor Q4, the fifth BJT transistor Q5, the sixth BJT transistor Q6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9;
[0031] The base of the fourth BJT transistor Q4 is connected to the collector of the fourth BJT transistor Q4 and the emitter of the fifth BJT transistor Q5.
[0032] The base of the fifth BJT transistor Q5 is connected to the collector of the fifth BJT transistor Q5 and the emitter of the sixth BJT transistor Q6.
[0033] The base of the sixth BJT transistor Q6 is connected to the collector of the sixth BJT transistor Q6 and the gate of the eighth MOS transistor M8.
[0034] The gate of the seventh MOS transistor M7 is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5.
[0035] The source of the seventh MOS transistor M7 is connected to the source of the eighth MOS transistor M8 and the gate of the ninth MOS transistor.
[0036] The source of the ninth MOS transistor M9 is connected to the Schmitt trigger input terminal;
[0037] The drain of the eighth MOS transistor M8 and the drain of the ninth MOS transistor are connected to the power supply voltage.
[0038] The drain of the seventh MOS transistor M7 and the emitter of the fourth BJT transistor Q4 are grounded.
[0039] According to a specific implementation of an embodiment of this disclosure, the power-down detection sub-circuit further includes:
[0040] The fourth resistor R4 has one end connected to the power supply voltage and the other end connected to the gate of the eighth MOS transistor M8 and the collector of the sixth BJT transistor Q6.
[0041] Secondly, embodiments of this disclosure provide a power supply system including a power-on reset circuit as described in any of the preceding claims.
[0042] Thirdly, embodiments of this disclosure provide a chip including the power-on reset circuit as described in any of the preceding claims.
[0043] Fourthly, embodiments of this disclosure provide an electronic device, including a power-on reset circuit as described in any of the preceding claims and / or a chip as described above.
[0044] The power-on reset circuit scheme in this embodiment includes a current comparator, a Schmitt trigger, and an inverter. The current comparator is composed of BJT transistors with different emitter areas and is connected between the power supply voltage and the input terminal of the Schmitt trigger. The output terminal of the Schmitt trigger is connected to the inverter to output a reset voltage. The power-on reset circuit provided in this embodiment uses BJT transistors with different emitter areas as the input of the current comparator. When the power system is powered on, the power supply voltage of the Schmitt trigger is slowly raised through a current mirror, causing the output of the power-on reset circuit to flip to a low level. When the power supply voltage continues to increase, and the power supply voltage of the comparator reaches the flip threshold, the power supply voltage of the Schmitt trigger decreases, and the output of the power-on reset circuit flips to a high level. It also integrates power-down detection, generating a reset pulse when the system loses power, preventing the system from operating in an undefined state. This scheme achieves a fast power-on reset response through the comparator, offering advantages such as simple circuit structure, small area, and fast response speed. Furthermore, the integrated power-down reset detection function provides better robustness. Attached Figure Description
[0045] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 This is a schematic diagram of a first power-on reset circuit provided in an embodiment of the present disclosure;
[0047] Figure 2 This is a schematic diagram of a second power-on reset circuit provided in an embodiment of this disclosure;
[0048] Figure 3 This is a schematic diagram of a third power-on reset circuit provided in an embodiment of this disclosure;
[0049] Figure 4 This is a schematic diagram of a fourth power-on reset circuit provided in an embodiment of this disclosure;
[0050] Figure 5 A schematic diagram of the simulation results of the power-on reset circuit provided in the embodiments of this disclosure. Detailed Implementation
[0051] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0052] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0053] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0054] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0055] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0056] Figure 1 This is a schematic diagram of a first power-on reset circuit provided in an embodiment of the present disclosure, applied to a power supply system, such as... Figure 1As shown, the circuit includes: a current comparator 102, a Schmitt trigger 101, and an inverter 103;
[0057] The current comparator 102 is composed of BJT transistors with different emitter areas. The current comparator 102 is connected between the power supply voltage VDD and the input terminal of the Schmitt trigger 101. The output terminal of the Schmitt trigger 101 is connected to the inverter 103 to output the reset voltage.
[0058] Specifically, traditional power-on reset circuits reset all circuits by charging the on-chip capacitors and triggering a pulse after the system powers on, thus avoiding an uncertain state after power-on. This method is slow because it requires charging the on-chip capacitors, which can lead to excessively long response times in communication systems, hindering high-quality human-computer interaction. This disclosure provides a power-on reset circuit based on a current comparator, used in various power supply systems for resetting various chips upon startup. When the system powers on, the current in the current mirror gradually increases with the power supply voltage, triggering the threshold of the Schmitt trigger 101. This triggers a low-level signal generated by the inverter 103 to reset the circuit (assuming a low-level reset). The input of current comparator 102 consists of BJT transistors with different emitter areas. As the power supply voltage continues to increase, the voltage in the branch of the BJT devices connected as diodes by resistors also increases with the power supply voltage. This causes the difference between the inputs of current comparator 102 to reach the comparison threshold, thus flipping the output of current comparator 102 and triggering Schmitt trigger 101 again. This causes the output of Schmitt trigger 101 to go high after passing through inverter 103. Therefore, when the system is powered on, Schmitt trigger 101 generates a low-level reset pulse. After power-on, the output of Schmitt trigger 102 is high and no longer affects the normal operation of the circuit.
[0059] Figure 2 This is a schematic diagram of a second power-on reset circuit provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the current comparator 102 includes: a first resistor R1, a first BJT transistor Q1, a second BJT transistor Q2 and a third BJT transistor Q3 with different emitter areas, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5 and a sixth MOSFET M6.
[0060] The first resistor is connected between the power supply voltage, the base of the second BJT transistor Q2, the collector of the first BJT transistor Q1, and the base of the first BJT transistor Q1.
[0061] The collector of the second BJT transistor Q2 is connected to the gate and source of the first MOS transistor M1;
[0062] The collector of the third BJT transistor Q3 is connected to the gate and source of the third MOS transistor M3.
[0063] The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 and the source of the first MOS transistor M1.
[0064] The source of the second MOS transistor M2 is connected to the source of the sixth MOS transistor M6 and the input of the Schmitt trigger;
[0065] The gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 and the source of the third MOS transistor M3.
[0066] The source of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5;
[0067] The gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and the source of the fourth MOS transistor M4.
[0068] The base of the third BJT transistor Q3, the drain of the first MOSFET M1, the drain of the second MOSFET M2, the drain of the third MOSFET M3, and the drain of the fourth MOSFET M4 are connected to the power supply voltage.
[0069] The emitter of the first BJT transistor Q1, the drain of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6 are grounded.
[0070] Furthermore, the current comparator 102 also includes:
[0071] The second resistor R2 is connected to the power supply voltage, the first resistor R1, and the base of the third BJT transistor Q3.
[0072] The third resistor R3 has one end connected to the emitter of the second BJT transistor Q2 and the emitter of the third BJT transistor Q3, and the other end grounded.
[0073] Specifically, a current comparator 102, composed of a first resistor R1, a second resistor R2, and BJT transistors Q1 and Q2 with different emitter areas, and MOSFETs M1, M2, M3, M4, M5, and M6, is used to determine the power supply voltage power-on process.
[0074] When the system voltage increases from zero, the first current I1 flowing through the first resistor R1 produces a voltage drop of I1*R1. The base-emitter voltage differences of the first BJT Q1, the second BJT Q2, and the third BJT Q3 are VBE1, VBE2, and VBE3, respectively. The ratio of the emitter area of the second BJT Q2 to the third BJT Q3 is N. Then, when the circuit operates under normal conditions... The second resistor R2 is used to bias the third BJT transistor Q3. When the system is first powered on, I1 is very small, therefore... The output Vsch of current comparator 102 is large, exceeding the high threshold voltage V of the Schmitt trigger. SPH When the output RST of the Schmitt trigger 101 is inverted by the inverter 103, it is low, and the system is in a reset state (set to "0" for reset). As the power supply voltage increases, I1 increases. When the current comparator 102 outputs Vsch, it decreases. When Vsch becomes small enough to trigger the low threshold voltage V of the Schmitt trigger... SPL After that, RST jumps to a high level, and the system begins to work normally.
[0075] The power-on reset circuit provided in this embodiment uses BJT transistors with different emitter areas as inputs to a current comparator. When the power system is powered on, the power supply voltage of the Schmitt trigger is slowly raised through a current mirror, causing the output of the power-on reset circuit to flip to a low level. As the power supply voltage continues to increase, the power supply voltage of the comparator reaches the flip-flop threshold, causing the power supply voltage of the Schmitt trigger to drop, and the output of the power-on reset circuit to flip to a high level. This comparator enables a fast power-on reset response, offering advantages such as simple circuit structure, small area, and fast response speed.
[0076] Based on the above embodiments, further, such as Figure 3 As shown, the power-on reset circuit also includes:
[0077] The power-down detection sub-circuit 104 is connected between the power supply voltage VDD, the current comparator 102, and the input terminal of the Schmitt trigger 101.
[0078] Specifically, when the system power supply voltage generates a spike (such as a sudden increase in load current), and the power drops to a certain level, the system may be in an unpredictable state, affecting the normal function of the circuit. In this embodiment, the power supply voltage can be detected based on stacked diodes. When the power supply voltage drops to a certain level, the power failure detection sub-circuit 104 pulls the input of the Schmitt trigger 101 high, and the output of the power-on reset circuit flips to a low level. When the power supply voltage recovers from the spike to the normal state, the current comparator 102 pulls the input of the Schmitt trigger 101 low, and the output of the power-on reset circuit flips to a high level.
[0079] The power-on reset circuit provided in this embodiment achieves fast power-on reset response through a current comparator, and also integrates power-down detection. When the system loses power, it can generate a reset pulse to prevent the system from operating in an unpredictable state. The integrated power-down reset detection function has better robustness.
[0080] Based on the above embodiments, further, such as Figure 4 As shown, the power-down detection sub-circuit 104 includes: a fourth BJT transistor Q4, a fifth BJT transistor Q5 and a sixth BJT transistor Q6, a seventh MOSFET M7, an eighth MOSFET M8 and a ninth MOSFET M9;
[0081] The base of the fourth BJT transistor Q4 is connected to the collector of the fourth BJT transistor Q4 and the emitter of the fifth BJT transistor Q5.
[0082] The base of the fifth BJT transistor Q5 is connected to the collector of the fifth BJT transistor Q5 and the emitter of the sixth BJT transistor Q6.
[0083] The base of the sixth BJT transistor Q6 is connected to the collector of the sixth BJT transistor Q6 and the gate of the eighth MOS transistor M8.
[0084] The gate of the seventh MOS transistor M7 is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5.
[0085] The source of the seventh MOS transistor M7 is connected to the source of the eighth MOS transistor M8 and the gate of the ninth MOS transistor.
[0086] The source of the ninth MOS transistor M9 is connected to the input terminal of the Schmitt trigger 101;
[0087] The drain of the eighth MOS transistor M8 and the drain of the ninth MOS transistor are connected to the power supply voltage.
[0088] The drain of the seventh MOS transistor M7 and the emitter of the fourth BJT transistor Q4 are grounded.
[0089] Furthermore, the power failure detection sub-circuit 104 also includes:
[0090] The fourth resistor R4 has one end connected to the power supply voltage and the other end connected to the gate of the eighth MOS transistor M8 and the collector of the sixth BJT transistor Q6.
[0091] Specifically, in this embodiment, a power-down detection sub-circuit 104 is constructed by a fourth resistor R4, a fourth BJT transistor Q4, a fifth BJT transistor Q5, a sixth BJT transistor Q6, a seventh MOSFET M7, an eighth MOSFET M8, and a ninth MOSFET M9 to detect whether the power supply voltage has dropped. The fourth resistor R4 biases the eighth MOSFET M8. The output of the power-on reset circuit and the output of the power-down detection circuit are integrated together, which is Vsch, and used as the input of the Schmitt trigger 101 to generate a reset signal. This eliminates the need for two separate Schmitt triggers for power-on and power-down detection, saving circuit costs.
[0092] When the power supply voltage experiences a spike for some reason, such as a sudden increase in load current, the power supply voltage begins to drop. The fourth BJT Q4, fifth BJT Q5, and sixth BJT Q6, connected by diodes, determine the power-down detection threshold. In this embodiment, the threshold can be set to 3VBE, approximately 2.1V. When the power supply voltage drops below 2.1V, the eighth MOSFET M8 turns off, the gate voltage of the ninth MOSFET M9 is pulled to ground by the seventh MOSFET M7, and the eighth MOSFET M9 turns on, pulling Vsch to the decreasing VDD. If VDD > VDD at this time... SPH When the output RST of the Schmitt trigger is low, the system enters the reset state. After the power supply voltage recovers from the glitches, the eighth MOSFET M8 turns on, the ninth MOSFET M9 turns off, and the sixth MOSFET M6 pulls Vsch low. When Vsch becomes low enough to trigger the low threshold voltage Vsch of the Schmitt trigger... SPL After that, RST jumps to a high level, and the system returns to normal operation.
[0093] Figure 5 This is a schematic diagram of the simulation results of the power-on reset circuit provided in the embodiments of this disclosure, as shown below. Figure 5 As shown, assuming the power supply voltage VDD is 5V, VDD starts powering on from 0s and completes power-on in 20μs. It can be seen that Vsch synchronously generates a high-level pulse, and RST correspondingly generates a low-level reset pulse. When VDD generates a glitch after 0.4ms, with a minimum value of 2V, Vsch synchronously generates another high-level pulse, and RST correspondingly generates a low-level reset pulse, completing the power-down detection and resetting the system.
[0094] The power-on reset circuit provided in this embodiment achieves fast power-on reset response through a current comparator, and also integrates power-down detection. When the system loses power, it can generate a reset pulse to prevent the system from operating in an unpredictable state. The integrated power-down reset detection function has better robustness.
[0095] Based on the same inventive concept, this disclosure also provides a power-on reset power supply system, including a power-on reset circuit, as detailed in the power-on reset circuit described in the above embodiments, which will not be repeated here.
[0096] Based on the same inventive concept, this disclosure also provides a chip including a power-on reset circuit, as detailed in the power-on reset circuit described in the above embodiments, which will not be repeated here.
[0097] Based on the same inventive concept, an electronic device, including a chip, is described in detail in the power-on reset circuit of the above embodiments, and will not be repeated here. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A power-on reset circuit applied in a power supply system, characterized in that, include: Current comparator, Schmitt trigger, and inverter; The current comparator is composed of BJT transistors with different emitter areas, and the current comparator is connected between the power supply voltage and the input terminal of the Schmitt trigger. The output of the Schmitt trigger is connected to the inverter and is used to output a reset voltage; The current comparator includes: The first resistor R1, the first BJT transistor Q1, the second BJT transistor Q2 and the third BJT transistor Q3 with different emitter areas, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5 and the sixth MOSFET M6; The first resistor is connected between the power supply voltage, the base of the second BJT transistor Q2, the collector of the first BJT transistor Q1, and the base of the first BJT transistor Q1. The collector of the second BJT transistor Q2 is connected to the gate and source of the first MOS transistor M1; The collector of the third BJT transistor Q3 is connected to the gate and source of the third MOS transistor M3. The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 and the source of the first MOS transistor M1. The source of the second MOS transistor M2 is connected to the source of the sixth MOS transistor M6 and the input of the Schmitt trigger; The gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 and the source of the third MOS transistor M3. The source of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5; The gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and the source of the fourth MOS transistor M4. The base of the third BJT transistor Q3, the drain of the first MOSFET M1, the drain of the second MOSFET M2, the drain of the third MOSFET M3, and the drain of the fourth MOSFET M4 are connected to the power supply voltage. The emitter of the first BJT transistor Q1, the drain of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6 are grounded.
2. The power-on reset circuit according to claim 1, characterized in that, The current comparator further includes: The second resistor R2 is connected to the power supply voltage, the first resistor R1, and the base of the third BJT transistor Q3.
3. The power-on reset circuit according to claim 2, characterized in that, The current comparator further includes: The third resistor R3 has one end connected to the emitter of the second BJT transistor Q2 and the emitter of the third BJT transistor Q3, and the other end grounded.
4. The power-on reset circuit according to any one of claims 1-3, characterized in that, The power-on reset circuit also includes: The power-down detection sub-circuit is connected between the power supply voltage, the current comparator, and the input of the Schmitt trigger.
5. The power-on reset circuit according to claim 4, characterized in that, The power failure detection sub-circuit includes: The fourth BJT transistor Q4, the fifth BJT transistor Q5, the sixth BJT transistor Q6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9; The base of the fourth BJT transistor Q4 is connected to the collector of the fourth BJT transistor Q4 and the emitter of the fifth BJT transistor Q5. The base of the fifth BJT transistor Q5 is connected to the collector of the fifth BJT transistor Q5 and the emitter of the sixth BJT transistor Q6. The base of the sixth BJT transistor Q6 is connected to the collector of the sixth BJT transistor Q6 and the gate of the eighth MOS transistor M8. The gate of the seventh MOS transistor M7 is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5. The source of the seventh MOS transistor M7 is connected to the source of the eighth MOS transistor M8 and the gate of the ninth MOS transistor. The source of the ninth MOS transistor M9 is connected to the Schmitt trigger input terminal; The drain of the eighth MOS transistor M8 and the drain of the ninth MOS transistor are connected to the power supply voltage. The drain of the seventh MOS transistor M7 and the emitter of the fourth BJT transistor Q4 are grounded.
6. The power-on reset circuit according to claim 5, characterized in that, The power failure detection sub-circuit also includes: The fourth resistor R4 has one end connected to the power supply voltage and the other end connected to the gate of the eighth MOS transistor M8 and the collector of the sixth BJT transistor Q6.
7. A power supply system, characterized in that, Includes the power-on reset circuit as described in any one of claims 1-6.
8. A chip, characterized in that, Includes the power-on reset circuit as described in any one of claims 1-6.
9. An electronic device, characterized in that, Includes the power-on reset circuit as described in any one of claims 1-6 and / or the chip as described in claim 8.