Display substrate and display device

Abstract

A display substrate comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel and a fourth sub-pixel emitting light rays of the same color; at least one sub-pixel comprises a pixel driving circuit and a light emitting device, the pixel driving circuit comprising a driving transistor; the orthographic projection of the anode of the light emitting device in the third sub-pixel on a substrate and the orthographic projection of the gate electrode of the driving transistor in the third sub-pixel on the substrate have a first overlapping area; the orthographic projection of the anode of the light emitting device in the fourth sub-pixel on the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel on the substrate have no overlapping area or a second overlapping area, the area of the second overlapping area being smaller than the area of the first overlapping area; the fourth sub-pixel or the first sub-pixel or the second sub-pixel adjacent to the fourth sub-pixel comprises a conductive block, the orthographic projection of the conductive block on the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel on the substrate have a third overlapping area.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices that use OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, including: a plurality of sub-pixels arranged in an array, the plurality of sub-pixels including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel and a fourth sub-pixel emitting a third color light;

[0005] At least one sub-pixel includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a storage capacitor, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit.

[0006] The orthographic projection of the anode of the light-emitting device in the third sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the third sub-pixel onto the substrate have a first overlapping region;

[0007] The orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate do not overlap; or, the orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate have a second overlapping region, the area of ​​the second overlapping region being smaller than the area of ​​the first overlapping region.

[0008] The fourth sub-pixel, or the first or second sub-pixel adjacent to the fourth sub-pixel, includes a conductive block, and the orthographic projection of the conductive block on the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel on the substrate have a third overlapping region.

[0009] This disclosure also provides a display device, including the aforementioned display substrate.

[0010] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0011] Figure 1 A schematic diagram of the structure of a display device for some exemplary embodiments;

[0012] Figure 2 This is a schematic diagram of the pixel arrangement structure of a display substrate for some exemplary embodiments;

[0013] Figure 3 This is a schematic cross-sectional view of a display substrate for some exemplary embodiments;

[0014] Figure 4 This is an equivalent circuit diagram of the pixel driving circuit of a display substrate for some exemplary embodiments.

[0015] Figure 5 In some exemplary embodiments Figure 4 Timing diagram of the pixel driving circuit;

[0016] Figure 6 A schematic diagram of a display substrate after a semiconductor layer pattern has been formed, for some exemplary embodiments;

[0017] Figure 7a A schematic diagram of a display substrate after the first conductive layer pattern has been formed, for some exemplary embodiments;

[0018] Figure 7b for Figure 7a A planar schematic diagram of the first conductive layer in the middle;

[0019] Figure 8a A schematic diagram of a display substrate after forming a second conductive layer pattern, for some exemplary embodiments;

[0020] Figure 8b for Figure 8a A schematic diagram of the second conductive layer in the middle;

[0021] Figure 9a A schematic diagram of a display substrate after a fourth insulating layer pattern has been formed, for some exemplary embodiments;

[0022] Figure 9b for Figure 9a A schematic diagram of multiple vias in the fourth insulating layer;

[0023] Figure 10a A schematic diagram of a display substrate after a third conductive layer pattern has been formed, for some exemplary embodiments;

[0024] Figure 10b for Figure 10a A schematic diagram of the third conductive layer in the middle;

[0025] Figure 11a A schematic diagram of a display substrate after a first planarization layer pattern has been formed, for some exemplary embodiments;

[0026] Figure 11b for Figure 11a A planar schematic diagram of multiple vias in the first planarization layer;

[0027] Figure 12a A schematic diagram of a display substrate after a fourth conductive layer pattern has been formed, for some exemplary embodiments;

[0028] Figure 12b for Figure 12a A schematic diagram of the fourth conductive layer in the middle;

[0029] Figure 13a A schematic diagram of a display substrate after a second planarization layer pattern has been formed, for some exemplary embodiments;

[0030] Figure 13b for Figure 13a A schematic diagram of multiple vias in the second flattening layer;

[0031] Figure 14a A schematic diagram of a display substrate after an anode pattern has been formed, for some exemplary embodiments;

[0032] Figure 14b for Figure 14a A plan view of the intermediate anode;

[0033] Figure 15a A schematic diagram showing a display substrate after forming a pixel definition layer pattern for some exemplary embodiments;

[0034] Figure 15b for Figure 15a A planar schematic diagram of the pixel definition layer.

[0035] Figure label:

[0036] 11—First active layer; 12—Second active layer; 13—Third active layer;

[0037] 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer;

[0038] 17—Seventh active layer; 21—First scan signal line; 22—Second scan signal line;

[0039] 23—Light-emitting signal line; 24—First electrode plate; 31—Initial signal line;

[0040] 32—Second electrode plate; 33—Shielding electrode; 34—Opening;

[0041] 35—Electrode connection wire; 41—First power supply wire; 42—Data connection electrode;

[0042] 43—First connecting electrode; 44—Second connecting electrode; 45—Third connecting electrode;

[0043] 51—Data signal line; 53—Anode connection electrode; 71—Anode;

[0044] 72—Pixel definition layer; 73—Pixel opening; 101—Base;

[0045] 102—Driver circuit layer; 103—Light-emitting structure layer; 104—Encapsulation layer;

[0046] 301—Anode; 302—Pixel definition layer; 303—Organic light-emitting layer;

[0047] 304—Cathode; 401—First encapsulation layer; 402—Second encapsulation layer;

[0048] 403—Third encapsulation layer. Detailed Implementation

[0049] In this document, a transistor is defined as a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this document, the channel region refers to the region through which current primarily flows.

[0050] In this paper, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this paper, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0051] In this article, "electrical connection" includes the situation where constituent elements are connected together by a component that has some electrical function. There are no particular restrictions on the "component that has some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0052] In this article, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0053] In this article, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0054] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), multiple light emission signal lines (E1 to Eo), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driver to the light emission signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light emission signal driver can sequentially provide transmit signals with off-level pulses to light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured as a shift register and can generate light emission signals by sequentially transmitting light emission stop signals in the form of off-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. The pixel array can include multiple sub-pixels Pxij. Each sub-pixel Pxij can be connected to the corresponding data signal line, the corresponding scan signal line, and the corresponding light emission signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0055] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. Each pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a third color light (both the third sub-pixel P3 and the fourth sub-pixel P4 emit the third color light). For example, the first sub-pixel P1 may emit red light, the second sub-pixel P2 may emit blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may emit green light. Figure 2 As shown in the exemplary embodiment, all sub-pixels on the display substrate can be arranged into multiple pixel rows and multiple pixel columns. Multiple sub-pixels in the same pixel row are arranged along a first direction X, and multiple sub-pixels in the same pixel column are arranged along a second direction Y. The second direction Y intersects (for example, can be perpendicular to) the first direction X. Any fourth sub-pixel P4 and the third sub-pixel P3 adjacent to it are located in the same pixel column. Any fourth sub-pixel P4, the first sub-pixel P1 adjacent to it, and the second sub-pixel P2 are located in the same pixel row. The first sub-pixel P1 and the second sub-pixel P2 are alternately arranged in the same pixel column, and the third sub-pixel P3 and the fourth sub-pixel P4 are alternately arranged in the same pixel column. In the exemplary embodiment, each sub-pixel can include a pixel driving circuit and a light-emitting device. The pixel driving circuit in each sub-pixel is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of that sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of that sub-pixel. The light-emitting device can be an OLED device or a quantum dot light-emitting device, etc.

[0056] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels. For example... Figure 3 As shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may also include other film layers, such as spacers, etc., which are not limited herein.

[0057] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit. Figure 3 The illustration uses only one driving transistor 210 and one storage capacitor 211 as an example. The light-emitting structure layer 103 of each sub-pixel may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 can be connected to the drain electrode of the driving transistor 210 through a via. The pixel definition layer 302 has a pixel opening, covering the portion of the anode 301 near its circumferential edge, while the pixel opening exposes the remaining portion of the anode 301. The organic light-emitting layer 303 is stacked on the anode 301, and the cathode 304 is stacked on the organic light-emitting layer 303. The anode 301, organic light-emitting layer 303, and cathode 304 are stacked to form a light-emitting device. The organic light-emitting layer 303 emits light of the corresponding color under the voltage drive of the anode 301 and cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0058] In an exemplary embodiment, the light-emitting device may further include a hole injection layer, a hole transport layer, and an electron blocking layer sequentially stacked between the anode 301 and the organic light-emitting layer 303, and a hole blocking layer, an electron transport layer, and an electron injection layer sequentially stacked between the organic light-emitting layer 303 and the cathode 304. In an exemplary embodiment, the hole injection layers of all sub-pixels can be connected as a single common layer for all sub-pixels; similarly, the hole transport layer, electron transport layer, and electron injection layer of all sub-pixels can all serve as common layers for all sub-pixels.

[0059] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 4 As shown, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS) and the light-emitting device.

[0060] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0061] The gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first terminal of the first transistor T1 is connected to the initial signal line INIT, and the second terminal of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initial voltage to the gate electrode of the third transistor T3 to initialize the charge on the gate electrode of the third transistor T3.

[0062] The gate electrode of the second transistor T2 (which can be called the compensation transistor) is connected to the first scan signal line S1, the first terminal of the second transistor T2 is connected to the second node N2, and the second terminal of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to its second terminal.

[0063] The gate electrode of the third transistor T3 (which can be called the driving transistor) is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first terminal of the third transistor T3 is connected to the first node N1, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its gate electrode and its first terminal.

[0064] The gate electrode of the fourth transistor T4 (which can be called the write transistor) is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0065] The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode (anode) of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0066] The gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0067] In an exemplary embodiment, the second electrode (cathode) of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line of the current pixel row, and the second scan signal line S2 is the scan signal line of the previous pixel row. That is, for the nth pixel row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current pixel row and the first scan signal line S1 of the previous pixel row are the same signal line, which can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0068] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0069] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0070] Figure 5 This is a timing diagram of a pixel driving circuit. The following is combined with... Figure 5 Exemplary Description Figure 4 The working process of the example pixel driving circuit. Figure 4 The pixel driving circuit in the image includes seven transistors (transistor T1 to transistor T7) and one storage capacitor C. All seven transistors can be P-type transistors.

[0071] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0072] In the first stage, A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage in the capacitor. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the light-emitting device (using an OLED device as an example) does not emit light.

[0073] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0074] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0075] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0076] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0077] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0078] Combination Figures 1 to 5 In the pixel driving circuit, the gate electrode (N2 node) of the third transistor T3 plays a crucial role in the entire circuit. The parasitic capacitance of the N2 node and other nodes affects the display effect of the pixel, and the parasitic capacitance of the N2 node needs to be considered when designing the pixel driving circuit. In some GRB pixel arrangement pixel structures, because the anodes of the two G pixels (pixels emitting green light) are positioned differently relative to the pixel driving circuit of the sub-pixel, the parasitic capacitance of the N2 node of the two G pixels will differ. If the parasitic capacitance of the N2 node of the two G pixels differs significantly, the potential written to the N2 node will be significantly different during signal writing, resulting in a large difference in the current when the two G pixels emit light, which in turn leads to inconsistent brightness between the two G pixels, affecting the display effect.

[0079] This disclosure provides a display substrate, including: a plurality of sub-pixels arranged in an array, the plurality of sub-pixels including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel and a fourth sub-pixel emitting a third color light;

[0080] At least one sub-pixel includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a storage capacitor, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit.

[0081] The orthographic projection of the anode of the light-emitting device in the third sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the third sub-pixel onto the substrate have a first overlapping region;

[0082] The orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate do not overlap; or, the orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate have a second overlapping region, the area of ​​the second overlapping region being smaller than the area of ​​the first overlapping region.

[0083] The fourth sub-pixel, or the first or second sub-pixel adjacent to the fourth sub-pixel, includes a conductive block, and the orthographic projection of the conductive block on the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel on the substrate have a third overlapping region.

[0084] In the display substrate of this embodiment, both the third sub-pixel and the fourth sub-pixel emit third-color light. The orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate does not overlap with the orthographic projection of the gate electrode of the driving transistor in the same sub-pixel onto the substrate, or a second overlapping region exists. The area of ​​the second overlapping region is smaller than the area of ​​the first overlapping region of the third sub-pixel. The fourth sub-pixel, or the first or second sub-pixel adjacent to the fourth sub-pixel, includes a conductive block. The orthographic projection of the conductive block onto the substrate overlaps with the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate in a third overlapping region. Thus, the conductive block can compensate for the parasitic capacitance of the gate electrode of the driving transistor in the adjacent fourth sub-pixel, reducing the difference in parasitic capacitance between the gate electrodes of the driving transistors of the fourth and third sub-pixels, thereby reducing the brightness difference between the fourth and third sub-pixels and improving the display effect.

[0085] In some exemplary embodiments, the conductive block is the anode of the light-emitting device in the sub-pixel where the conductive block is located; or, the pixel driving circuit of the sub-pixel where the conductive block is located includes the conductive block. In this embodiment, the conductive block may be on the same layer or a different layer from the anode of the light-emitting device, and the anode of the light-emitting device in the sub-pixel where the conductive block is located may be connected to or not connected to the conductive block.

[0086] In some exemplary embodiments, the potential of the conductive block may be different from the potential of the anode of the light-emitting device in the fourth sub-pixel. In this embodiment, the conductive block may be on the same layer or a different layer from the anode of the light-emitting device in the fourth sub-pixel, and the conductive block may not be connected to the anode of the light-emitting device in the fourth sub-pixel.

[0087] In some exemplary embodiments, the first or second sub-pixel adjacent to the fourth sub-pixel serves as a compensation sub-pixel, and the conductive block is the anode of the light-emitting device in the compensation sub-pixel. In one example of this embodiment, the potential of the anode of the light-emitting device in the first and second sub-pixels can be higher than the potential of the anode of the light-emitting device in the third sub-pixel, and the area of ​​the third overlapping region can be smaller than the area of ​​the first overlapping region. This helps to reduce the difference in parasitic capacitance of the N2 nodes of the third and fourth sub-pixels, thereby reducing the current difference between the third and fourth sub-pixels, improving the consistency of the electrical environment of the third and fourth sub-pixels, and improving the consistency of the luminous brightness of the third and fourth sub-pixels.

[0088] In some exemplary embodiments, the light-emitting structure layer further includes a pixel definition layer, the pixel definition layer having pixel openings that expose the anode of the light-emitting device;

[0089] One conductive layer in the driving circuit layer that is away from the substrate includes a data signal line;

[0090] At least one of the pixel openings has its orthographic projection on the substrate bypassing the orthographic projection of the conductive layer containing the data signal line on the substrate, or at least one of the pixel openings has its orthographic projection on the substrate bisected by the orthographic projection of the conductive layer containing the data signal line on the substrate.

[0091] In some exemplary embodiments, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate;

[0092] The semiconductor layer includes the active layer of the driving transistor, the first conductive layer includes the first electrode of the storage capacitor and the scan signal line, the second conductive layer includes the second electrode of the storage capacitor, the third conductive layer includes the power line, and the fourth conductive layer includes the data signal line.

[0093] The scan signal line extends along a first direction, and the power line and the data signal line both extend along a second direction, which intersects the first direction.

[0094] In some exemplary embodiments, the pixel driving circuit further includes a write transistor, the gate electrode of which is connected to a scan signal line, the first electrode of which is connected to a data signal line, and the second electrode of which is connected to the first electrode of the driving transistor.

[0095] The orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the write transistor in the adjacent fourth sub-pixel onto the substrate.

[0096] In some exemplary embodiments, the pixel driving circuit further includes a compensation transistor, the gate electrode of which is connected to the scan signal line, the first electrode of which is connected to the gate electrode of the driving transistor, and the second electrode of which is connected to the second electrode of the driving transistor.

[0097] The orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the compensation transistor in the adjacent fourth sub-pixel onto the substrate.

[0098] In some exemplary embodiments, the orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the compensation transistor in the compensation sub-pixel onto the substrate.

[0099] In some exemplary embodiments, the orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the driving transistor in the compensation sub-pixel onto the substrate.

[0100] In some exemplary embodiments, the light-emitting structure layer further includes a pixel definition layer, the pixel definition layer having pixel openings that expose the anode of the light-emitting device;

[0101] The anode of the light-emitting device in the compensation sub-pixel includes a second region, and a third protrusion and a fourth protrusion connected to the second region;

[0102] The shape of the second region is the same as the shape of the pixel opening in the compensation sub-pixel, and the area of ​​the second region is larger than the area of ​​the pixel opening in the compensation sub-pixel;

[0103] The third protrusion is connected to the pixel driving circuit of the compensation sub-pixel through a via.

[0104] The orthographic projection of the fourth protrusion on the substrate and the orthographic projection of the gate electrode of the driving transistor in the adjacent fourth sub-pixel on the substrate have a fourth overlapping region, and the third overlapping region includes the fourth overlapping region.

[0105] In some exemplary embodiments, the second region is hexagonal in shape, the fourth protrusion is trapezoidal in shape, and the two hypotenuses of the fourth protrusion are collinear with the two sides of the second region, respectively.

[0106] In some exemplary embodiments, the anode of the light-emitting device in the fourth sub-pixel includes a fourth region and a ninth protrusion connected to the fourth region;

[0107] The ninth protrusion is located on the side of the fourth region facing the gate electrode of the driving transistor in the fourth sub-pixel, and the ninth protrusion is connected to the pixel driving circuit of the fourth sub-pixel through a via.

[0108] In some exemplary embodiments, the ninth protrusion includes a first side away from the fourth region and a second side connected to the fourth region and adjacent to the first side, wherein the connection between the first side and the second side is provided with a chamfer.

[0109] The fourth protrusion is positioned with one side away from the second region facing the chamfer and parallel to the chamfer.

[0110] In some exemplary embodiments, the pixel driving circuit further includes a compensation transistor, the gate electrode of which is connected to the scan signal line, the first electrode of which is connected to the gate electrode of the driving transistor, and the second electrode of which is connected to the second electrode of the driving transistor.

[0111] The anode of the light-emitting device in the compensation sub-pixel further includes a fifth protrusion and a sixth protrusion connected to the second region, the fifth protrusion and the sixth protrusion being located on opposite sides of the second region;

[0112] The orthographic projection of the fifth protrusion on the substrate overlaps with the orthographic projection of the active layer of the compensation transistor in the adjacent fourth sub-pixel on the substrate, and the orthographic projection of the sixth protrusion on the substrate overlaps with the orthographic projection of the active layer of the compensation transistor in the compensation sub-pixel on the substrate.

[0113] In some exemplary embodiments, the anode of the light-emitting device in the third sub-pixel includes a third region, and a seventh protrusion and an eighth protrusion connected to the third region;

[0114] The shape of the third region is the same as the shape of the pixel opening in the third sub-pixel, and the area of ​​the third region is larger than the area of ​​the pixel opening in the third sub-pixel.

[0115] The seventh protrusion and the eighth protrusion are located on opposite sides of the third region. The seventh protrusion is connected to the pixel driving circuit of the third sub-pixel through a via. The orthographic projection of the eighth protrusion on the substrate overlaps with the orthographic projection of the active layer of the compensation transistor in the third sub-pixel on the substrate.

[0116] In some exemplary embodiments, the plurality of sub-pixels are arranged into a plurality of pixel rows and a plurality of pixel columns, the plurality of sub-pixels in the same pixel row are arranged along a first direction, and the plurality of sub-pixels in the same pixel column are arranged along a second direction, the second direction intersecting the first direction;

[0117] Any fourth sub-pixel and the third sub-pixel adjacent to the fourth sub-pixel are located in the same pixel column, and any fourth sub-pixel, the first sub-pixel adjacent to the fourth sub-pixel, and the second sub-pixel are located in the same pixel row.

[0118] In some exemplary embodiments, the first sub-pixel and the second sub-pixel are alternately arranged in the same pixel column, and the third sub-pixel and the fourth sub-pixel are alternately arranged in the same pixel column.

[0119] In some exemplary embodiments, the first sub-pixel emits red light, the second sub-pixel emits blue light, and the third and fourth sub-pixels both emit green light.

[0120] The structure of a display substrate is illustrated below through an example of its fabrication process. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0121] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0122] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 6 As shown.

[0123] In an exemplary embodiment, the semiconductor layer of each sub-pixel may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 are an integral structure interconnected. The first active layer 11 of the sub-pixel in the Mth row of each pixel column is interconnected with the second active layer 12 of the sub-pixel in the M+1th row.

[0124] In an exemplary embodiment, the second active layer 12 and the fourth active layer 14 in the Mth row of sub-pixels are located on the side of the third active layer 13 of the sub-pixel that is away from the (M+1)th row of sub-pixels. The fifth active layer 15, the sixth active layer 16, the first active layer 11, and the seventh active layer 17 in the Mth row of sub-pixels are located on the side of the third active layer 13 of the sub-pixel that is close to the (M+1)th row of sub-pixels. The first active layer 11 and the seventh active layer 17 are farther away from the third active layer 13 of the sub-pixel than the fifth active layer 15 and the sixth active layer 16.

[0125] In an exemplary embodiment, the first active layer 11 may be approximately n-shaped, the second active layer 12 may be approximately 7-shaped, the third active layer 13 may be approximately Ω-shaped, the fourth active layer 14 may be approximately 1-shaped, and the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be approximately L-shaped.

[0126] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 11-1 of the first active layer 11 also serves as the first region 17-1 of the seventh active layer 17; the second region 11-2 of the first active layer 11 also serves as the first region 12-1 of the second active layer 12; the first region 13-1 of the third active layer 13 also serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15; the second region 13-2 of the third active layer 13 also serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16; and the second region 16-2 of the sixth active layer 16 also serves as the second region 17-2 of the seventh active layer 17. In an exemplary embodiment, the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are separately configured.

[0127] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern includes at least: a first scan signal line 21, a second scan signal line 22, a light-emitting signal line 23, and a first electrode 24, such as... Figure 7a and Figure 7b As shown, Figure 7b for Figure 7a A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE 1) layer.

[0128] like Figures 6 to 7b As shown, the first scan signal line 21, the second scan signal line 22, and the light emission signal line 23 can extend along the first direction X. The first scan signal line 21 in the Mth row of sub-pixels is located on the side of the first electrode plate 24 of the sub-pixel away from the (M+1)th row of sub-pixels. The light emission signal line 23 and the second scan signal line 22 can be located on the side of the first electrode plate 24 of the sub-pixel closer to the (M+1)th row of sub-pixels. The light emission signal line 23 is closer to the first electrode plate 24 of the sub-pixel than the second scan signal line 22.

[0129] In an exemplary embodiment, the first electrode 24 may be rectangular, with chamfered corners. The orthographic projection of the first electrode 24 onto the substrate overlaps with the orthographic projection of the third active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode 24 may simultaneously serve as an electrode of a storage capacitor and a gate electrode of the third transistor T3.

[0130] In an exemplary embodiment, the region of the first scan signal line 21 that overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2. The first scan signal line 21 is provided with a gate block 21-1 protruding towards the side where the second scan signal line 22 is located. The orthographic projection of the gate block 21-1 onto the substrate overlaps with the orthographic projection of the second active layer 12 onto the substrate. In each sub-pixel, the first scan signal line 21 and the second active layer 12 have two overlapping regions, which form the dual-gate structure of the second transistor T2. The region of the first scan signal line 21 that overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4. The region of the second scan signal line 22 that overlaps with the first active layer 11 serves as the gate electrode of the first transistor T1 in the dual-gate structure; the region of the second scan signal line 22 that overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7; the region of the light emission signal line 23 that overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5; and the region of the light emission signal line 23 that overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6.

[0131] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer to the seventh active layer are both conducted.

[0132] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern includes at least: an initial signal line 31, a second electrode 32, a shielding electrode 33, and an electrode connection line 35, such as... Figure 8a and Figure 8b The above, Figure 8b for Figure 8a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE 2) layer.

[0133] like Figures 6 to 8bAs shown, the initial signal line 31 can extend along the first direction X. The initial signal line 31 in the Mth row of sub-pixels is located on the side of the second scan signal line 22 of the sub-pixel away from the (M+1)th row of sub-pixels. The second electrode 32, as the other electrode of the storage capacitor, is located between the first scan signal line 21 and the light-emitting signal line 23 of the sub-pixel. The shielding electrode 33 is located on the side of the first scan signal line 21 of the sub-pixel away from the second electrode 32. The shielding electrode 33 is configured to shield the influence of data voltage jumps on critical nodes, avoid data voltage jumps affecting the potential of critical nodes in the pixel driving circuit, and improve the display effect.

[0134] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate overlaps with the orthographic projection of the first electrode plate 24 on the substrate. The first electrode plate 24 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit. An opening 34 is provided on the second electrode plate 32, and the opening 34 can be located in the middle of the second electrode plate 32. The opening 34 can be rectangular, so that the second electrode plate 32 forms a ring structure. The opening 34 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a subsequently formed first via, and the first via is configured to be located within the opening 34 and expose the first electrode plate 24, so that the second electrode of the subsequently formed first transistor T1 is connected to the first electrode plate 24.

[0135] In an exemplary embodiment, the electrode connection line 35 is disposed between the second electrode plates 32 of adjacent sub-pixels in the first direction X. The first end of the electrode connection line 35 is connected to the second electrode plate 32 of the sub-pixel, and the second end of the electrode connection line 35 extends along the first direction X or the opposite direction of the first direction X and is connected to the second electrode plate 32 of the adjacent sub-pixel. That is, the electrode connection line 35 is configured to connect the second electrode plates of adjacent sub-pixels in a pixel row. In an exemplary embodiment, the electrode connection line 35 allows the second electrode plates of multiple sub-pixels in a pixel row to form an interconnected integrated structure. The integrated structure of the second electrode plates can be reused as power signal lines, ensuring that the second electrode plates of multiple sub-pixels in a pixel row have the same potential. This improves the uniformity of the panel, avoids display defects in the display substrate, and ensures the display effect of the display substrate.

[0136] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer of each sub-pixel is provided with a plurality of vias, the plurality of vias including at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9, such as... Figure 9a and Figure 9b As shown, Figure 9b for Figure 9a A planar schematic diagram of multiple vias in the fourth insulating layer.

[0137] like Figures 6 to 9b As shown, the first via V1 is located within the opening 34 of the second electrode plate 32. The orthographic projection of the first via V1 onto the substrate lies within the range of the orthographic projection of the opening 34 onto the substrate. The fourth and third insulating layers within the first via V1 are etched away, exposing the surface of the first electrode plate 24. The first via V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via.

[0138] In an exemplary embodiment, the second via V2 is located in the region where the second electrode plate 32 is located. The orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second electrode plate 32 onto the substrate. The fourth insulating layer within the second via V2 is etched away, exposing the surface of the second electrode plate 32. The second via V2 is configured to allow a subsequently formed first power line to connect to the second electrode plate 32 through the via. In an exemplary embodiment, multiple second vias V2 may be included as power vias, and these multiple second vias V2 may be arranged sequentially along the second direction Y to increase the connection reliability between the first power line and the second electrode plate 32.

[0139] In an exemplary embodiment, the third via V3 is located in the region of the fifth active layer. The fourth, third, and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to allow a subsequently formed first power line to connect to the fifth active layer through the via.

[0140] In an exemplary embodiment, the fourth via V4 is located in the region of the sixth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fourth via V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via.

[0141] In an exemplary embodiment, the fifth via V5 is located in the region where the fourth active layer is located. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via V5 is configured to allow subsequently formed data signal lines to connect to the fourth active layer through this via, and the fifth via V5 is referred to as a data write via.

[0142] In an exemplary embodiment, the sixth via V6 is located in the region where the second active layer is located. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer). The sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first active layer through the via, and to connect the first electrode of the subsequently formed second transistor T2 to the second active layer through the via.

[0143] In an exemplary embodiment, the seventh via V7 is located in the region of the seventh active layer. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer (which is also the first region of the first active layer). The seventh via V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via, and to connect the first electrode of the subsequently formed first transistor T1 to the first active layer through the via.

[0144] In an exemplary embodiment, the eighth via V8 is located in the region where the shielding electrode 33 is located. The fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the shielding electrode 33. The eighth via V8 is configured to allow a subsequently formed first power line to be connected to the shielding electrode 33 through the via.

[0145] In an exemplary embodiment, the ninth via V9 is located in the region where the initial signal line 31 is located. The fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the initial signal line 31. The ninth via V9 is configured to allow the first terminal of the subsequently formed seventh transistor T7 (which is also the first terminal of the first transistor T1) to be connected to the initial signal line 31 through the via.

[0146] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a third conductive layer disposed on a fourth insulating layer, the third conductive layer including at least: a first power line 41, a data connection electrode 42, a first connection electrode 43, a second connection electrode 44, and a third connection electrode 45, such as Figure 10a and Figure 10b As shown, Figure 10b for Figure 10aA schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0147] like Figures 6 to 10b As shown, the first power line 41 extends along the second direction Y. The first power line 41 is connected to the second electrode plate 32 via the second via V2, to the fifth active layer via the third via V3, and to the shielding electrode 33 via the eighth via V8, ensuring that the shielding electrode 33 and the second electrode plate 32 have the same potential as the first power line 41. The orthographic projection of the shielding electrode 33 onto the substrate overlaps with the orthographic projection of the subsequently formed data signal line onto the substrate. Furthermore, the connection between the shielding electrode 33 and the first power line 41 effectively shields the impact of data voltage jumps on critical nodes in the pixel driving circuit, preventing data voltage jumps from affecting the potential of critical nodes in the pixel driving circuit and improving the display effect.

[0148] In an exemplary embodiment, the data connection electrode 42 is connected to the first region of the fourth active layer through a fifth via V5, and the data connection electrode 42 is configured to be connected to a subsequently formed data signal line.

[0149] In an exemplary embodiment, the first connection electrode 43 extends along the second direction Y. The first end of the first connection electrode 43 is connected to the second region of the first active layer (which is also the first region of the second active layer) through a sixth via V6, and the second end of the first connection electrode 43 is connected to the first electrode plate 24 through a first via V1. The first connection electrode 43 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, so that the first electrode plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential.

[0150] In an exemplary embodiment, the first end of the second connection electrode 44 is connected to the initial signal line 31 through the ninth via V9, and the second end of the second connection electrode 44 is connected to the first region of the seventh active layer (which is also the first region of the first active layer) through the seventh via V7. The second connection electrode 44 can serve as the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1, so that the first electrodes of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the initial signal line 31.

[0151] In an exemplary embodiment, the third connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a fourth via V4. The third connection electrode 45 can serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, such that the second electrodes of the sixth transistor T6 and the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 45 is also configured to connect to a subsequently formed anode connection electrode.

[0152] In an exemplary embodiment, the first power line 41 of each sub-pixel can be a non-uniform width polygonal line. Along the second direction Y, the first power line 41 of each sub-pixel may include a first power portion, a second power portion, a third power portion, and a fourth power portion connected sequentially. The first and third power portions may be parallel to the second direction Y, and are not collinear in the second direction Y. The third power portion is offset relative to the first power portion in the first direction X. The second and fourth power portions are both inclined and can be symmetrically arranged about the center line of the third power portion along the first direction X. The fourth power portion of the first power line 41 of the sub-pixel in the Mth row of multiple sub-pixels in the same column is connected to the first power portion of the first power line 41 of the sub-pixel in the (M+1)th row. The angle between the second power portion and the first power portion may be greater than 0° and less than 90°, and the angle between the fourth power portion and the third power portion may be greater than 0° and less than 90°. The third power portion is provided with a connecting portion extending towards the first direction X, and the connecting portion is configured to connect to the fifth active layer through a third via. The first power line 41 adopts a zigzag design, which facilitates the layout of the pixel structure and reduces the parasitic capacitance between the first power line and the data signal lines formed subsequently.

[0153] (6) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, patterning the first planarization film using a patterning process to form a first planarization layer covering a third conductive layer, wherein the first planarization layer of each sub-pixel is provided with an eleventh via V11 and a thirteenth via V13, such as... Figure 11a and Figure 11b As shown, Figure 11b for Figure 11a A planar schematic diagram of multiple vias in the first flat layer.

[0154] like Figures 6 to 11b As shown, the eleventh via V11 is located in the area where the data connection electrode 42 is located. The first planarization layer inside the eleventh via V11 is removed to expose the surface of the data connection electrode 42. The eleventh via V11 is configured to allow the subsequently formed data signal line to be connected to the data connection electrode 42 through the via.

[0155] The thirteenth via V13 is located in the region where the third connecting electrode 45 is located. The first planarization layer in the thirteenth via V13 is removed to expose the surface of the third connecting electrode 45. The thirteenth via V13 is configured to allow the subsequently formed anode connecting electrode to be connected to the third connecting electrode 45 through the via.

[0156] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a first planarization layer, wherein the fourth conductive layer of each sub-pixel includes at least: a data signal line 51 and an anode connection electrode 53, such as... Figure 12a and Figure 12b As shown, Figure 12b for Figure 12a A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0157] like Figures 6 to 12b As shown, the data signal line 51 can extend along the second direction Y, and is connected to the data connection electrode 42 through the eleventh via V11. Since the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via V5, the data signal line 51 is connected to the first region of the fourth active layer through the data connection electrode 42, allowing data signals to be written to the fourth transistor T4. Placing the data signal line 51 in the fourth conductive layer is beneficial for meeting the requirements of high refresh rates.

[0158] In an exemplary embodiment, the anode connection electrode 53 is connected to the third connection electrode 45 via a thirteenth via V13. Since the third connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via a fourth via V4, the anode connection electrode 53 is thus connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the third connection electrode 45. The anode connection electrode 53 can be rectangular in shape.

[0159] (8) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer, wherein each sub-pixel of the second planarization layer is provided with a fourteenth via V14, such as... Figure 13a and Figure 13b As shown, Figure 13b for Figure 13a A schematic diagram of multiple vias in the second flat layer.

[0160] like Figures 6 to 13b As shown, the fourteenth via V14 is located in the region where the anode connection electrode 53 is located. The second planarization layer in the fourteenth via V14 is removed to expose the surface of the anode connection electrode 53. The fourteenth via V14 is configured to allow the anode to be formed subsequently to be connected to the anode connection electrode 53 through the via.

[0161] (9) Forming an anode pattern. In an exemplary embodiment, forming an anode pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming an anode 71 disposed on a second planarization layer, such as... Figure 14a and Figure 14b As shown, Figure 14b for Figure 14a A planar schematic diagram of the intermediate anode.

[0162] like Figures 6 to 14b As shown, the anode 71 of each sub-pixel is connected to the anode connection electrode 53 through the fourteenth via V14 of the sub-pixel. Since the anode connection electrode 53 is connected to the third connection electrode 45 through the thirteenth via V13, and the third connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fourth via V4, the third connection electrode 45 serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. Therefore, the anode 71 is connected to the sixth transistor T6 and the seventh transistor T7 through the anode connection electrode 53 and the third connection electrode 45, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0163] In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in an array. Each pixel unit P includes a plurality of sub-pixels. Each pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a third color light (both the third sub-pixel P3 and the fourth sub-pixel P4 emit the third color light). For example, the first sub-pixel P1 may emit red light, the second sub-pixel P2 may emit blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may emit green light.

[0164] In an exemplary embodiment, on the display substrate, the sub-pixel in the Mth row and Nth column is the third sub-pixel P3, the sub-pixel in the Mth row and N+1th column is the second sub-pixel P2, the sub-pixel in the Mth row and N+2th column is the fourth sub-pixel P4, the sub-pixel in the Mth row and N+3th column is the first sub-pixel P1, and the sub-pixel in the Mth row and N+4th column is the third sub-pixel P3; the sub-pixel in the M+1th row and Nth column is the fourth sub-pixel P4, the sub-pixel in the M+1th row and N+1th column is the first sub-pixel P1, the sub-pixel in the M+1th row and N+2th column is the third sub-pixel P3, the sub-pixel in the M+1th row and N+3th column is the second sub-pixel P2, and the sub-pixel in the M+1th row and N+4th column is the fourth sub-pixel P4. In this pixel unit, the sub-pixel at row M+1 and column N (second sub-pixel P2), the sub-pixel at row M+1 and column N+1 (first sub-pixel P1), the sub-pixel at row M+2 and column N (fourth sub-pixel P4), and the sub-pixel at row M+1 and column N+2 (third sub-pixel P3) can form a pixel unit. First sub-pixel P1 emits red light, second sub-pixel P2 emits blue light, and third and fourth sub-pixels P3 and P4 both emit green light. On the display substrate, the shape and area of ​​the anodes of all first sub-pixels P1, all second sub-pixels P2, all third sub-pixels P3, and all fourth sub-pixels P4 can be the same. The shape and area of ​​the anodes of first sub-pixels P1, second sub-pixels P2, third sub-pixels P3, and fourth sub-pixels P4 can be different from each other.

[0165] In an exemplary embodiment, the anode of the first sub-pixel P1 may include a first region 711, and a first protrusion 7111 and a second protrusion 7112 connected to the first region 711. The orthographic projection of the first region 711 onto the substrate may overlap with the orthographic projection of the third active layer 13 of the sub-pixel onto the substrate, the orthographic projection of the first region 711 onto the substrate may also overlap with the orthographic projection of the second active layer 12 of the sub-pixel onto the substrate, and the orthographic projection of the first region 711 onto the substrate may also overlap with the orthographic projection of the fourth active layer 14 of the sub-pixel onto the substrate. The shape of the first region 711 may be the same as the shape of the pixel opening of the pixel definition layer of the subsequently formed sub-pixel (e.g., both are hexagonal; "same shape" in this document may have shape differences within the range of process tolerance), and the area of ​​the first region 711 is larger than the area of ​​the pixel opening of the sub-pixel. The shape of the first region 711 may be hexagonal, rectangular, etc., and is exemplarily a hexagon in the figure. The first protrusion 7111 is connected to the anode connection electrode 53 through the fourteenth via V14 of the sub-pixel. The orthographic projection of the second protrusion 7112 on the substrate can overlap with the orthographic projection of the second active layer 12 of the sub-pixel on the substrate. The first protrusion 7111 may include a first extension segment and a second extension segment connected in sequence. The first end of the first extension segment is connected to the first region 711, and the second end of the first extension segment is connected to the first end of the second extension segment. The second end of the second extension segment extends along the second direction Y. The second end of the first extension segment is offset from the first end of the first extension segment in both the first direction X and the second direction Y. The second end of the second extension segment is connected to the anode connection electrode 53 through the fourteenth via V14. The second protrusion 7112 may be rectangular and may protrude along the first direction X.

[0166] In an exemplary embodiment, a second sub-pixel P2 adjacent to the fourth sub-pixel P4 is used as a compensation sub-pixel (in other embodiments, a first sub-pixel P1 can be used as a compensation sub-pixel), and the conductive block is the anode of the light-emitting device in the second sub-pixel P2. The orthographic projection of the anode of the second sub-pixel P2 onto the substrate and the orthographic projection of the gate electrode of the third transistor T3 of the adjacent fourth sub-pixel P4 onto the substrate form a third overlapping region. The area of ​​the third overlapping region can be smaller than the area of ​​the first overlapping region. This helps to reduce the difference in parasitic capacitance between the N2 nodes of the third and fourth sub-pixels, thereby reducing the current difference between the third and fourth sub-pixels, improving the consistency of the electrical environment of the third and fourth sub-pixels, and improving the consistency of the luminous brightness of the third and fourth sub-pixels. The anode of the second sub-pixel P2 may include a second region 712, and a third protrusion 7121, a fourth protrusion 7122, a fifth protrusion 7123, and a sixth protrusion 7124 connected to the second region 712. The shape of the second region 712 can be the same as the shape of the pixel opening of the pixel definition layer of the subsequently formed sub-pixel, and the area of ​​the second region 712 is larger than the area of ​​the pixel opening of the sub-pixel. The shape of the second region 712 can be hexagonal, rectangular, etc., and is exemplarily a hexagon in the figure. The orthographic projection of the second region 712 on the substrate can overlap with the orthographic projection of the second active layer 12 of the sub-pixel on the substrate, and can overlap with the orthographic projections of the fourth active layer 14 of the adjacent fourth sub-pixel P4 and the gate electrode of the third transistor T3 on the substrate. The third protrusion 7121 can be connected to the anode connection electrode 53 through the fourteenth via V14 of the sub-pixel. The third protrusion 7121 may include a third extension segment and a fourth extension segment connected in sequence. The first end of the third extension segment is connected to the second region 712, and the second end of the third extension segment is connected to the first end of the fourth extension segment. The second end of the fourth extension segment extends along the second direction Y. The second end of the third extension segment is offset from the first end of the third extension segment in both the opposite direction of the first direction X and the second direction Y. The second end of the fourth extension segment is connected to the anode connection electrode 53 through the fourteenth via V14. The orthographic projection of the third protrusion 7121 on the substrate may overlap with the orthographic projection of the third active layer 13 of the sub-pixel on the substrate. The orthographic projection of the fourth protrusion 7122 on the substrate may overlap with the orthographic projection of the gate electrode of the third transistor T3 of the adjacent fourth sub-pixel P4 in the same row to form a fourth overlapping region, wherein the third overlapping region includes the fourth overlapping region.The fourth protrusion 7122 can be trapezoidal in shape. The two hypotenuses (the two legs of the trapezoid) of the fourth protrusion 7122 are collinear with the two sides of the second region 712. One side of the second region 712 serves as a common side of the second region 712 and the fourth protrusion 7122. The length of the side of the fourth protrusion 7122 furthest from the second region 712 is smaller than the length of the common side and is parallel to the common side (within a certain range of angles, such as -10 degrees to 10 degrees, is permissible within the process tolerance range). The fifth protrusion 7123 can extend along the first direction X. The shape of the fifth protrusion 7123 can be rectangular. The orthographic projection of the fifth protrusion 7123 onto the substrate can overlap with the orthographic projection of the second active layer 12 of the adjacent fourth sub-pixel P4 in the same row onto the substrate. The sixth protrusion 7124 can extend in the opposite direction to the first direction X. The shape of the sixth protrusion 7124 can be rectangular. The orthographic projection of the sixth protrusion 7124 on the substrate can overlap with the orthographic projection of the second active layer 12 of the sub-pixel on the substrate. The fifth protrusion 7123 and the sixth protrusion 7124 are located on opposite sides of the second region 712, respectively.

[0167] In an exemplary embodiment, the orthographic projection of the anode of the third sub-pixel P3 onto the substrate and the orthographic projection of the gate electrode of the third transistor T3 of the sub-pixel onto the substrate form a first overlapping region. The anode of the third sub-pixel P3 may include a third region 713, and a seventh protrusion 7131 and an eighth protrusion 7132 connected to the third region 713. The shape of the third region 713 may be the same as the shape of the pixel opening of the pixel definition layer of the subsequently formed sub-pixel, and the area of ​​the third region 713 is larger than the area of ​​the pixel opening of the sub-pixel. The shape of the third region 713 may be a pentagon, a rectangle, etc., and is exemplarily a pentagon in the figure. The orthographic projection of the third region 713 onto the substrate may overlap with the orthographic projection of the gate electrode of the third transistor T3 of the sub-pixel onto the substrate to form the first overlapping region. The orthographic projection of the third region 713 onto the substrate may also overlap with the orthographic projection of the second active layer 12 of the sub-pixel onto the substrate. The seventh protrusion 7131 can extend along the second direction Y. The first end of the seventh protrusion 7131 is connected to the third region 713, and the second end of the seventh protrusion 7131 is connected to the anode connection electrode 53 through the fourteenth via V14 of the sub-pixel. The eighth protrusion 7132 can extend in the opposite direction of the second direction Y. The shape of the eighth protrusion 7132 can be rectangular, and the orthographic projection of the eighth protrusion 7132 on the substrate can overlap with the orthographic projection of the second active layer 12 of the sub-pixel on the substrate. The seventh protrusion 7131 and the eighth protrusion 7132 can be located on opposite sides of the third region 713.

[0168] In an exemplary embodiment, the orthographic projection of the anode of the fourth sub-pixel P4 onto the substrate and the orthographic projection of the gate electrode of the third transistor T3 of the sub-pixel onto the substrate may not overlap, or a second overlapping region may exist, the area of ​​the second overlapping region being smaller than the area of ​​the first overlapping region. The anode of the fourth sub-pixel P4 may include a fourth region 714 and a ninth protrusion 7141 connected to the fourth region 714. The shape of the fourth region 714 may be the same as the shape of the pixel opening of the pixel definition layer of the subsequently formed sub-pixel, and the area of ​​the fourth region 714 is larger than the area of ​​the pixel opening of the sub-pixel. The shape of the fourth region 714 may be a pentagon, a rectangle, etc., and is exemplarily a pentagon in the figure. The orthographic projection of the fourth region 714 onto the substrate may not overlap with the orthographic projection of the gate electrode of the third transistor T3 of the sub-pixel onto the substrate. The ninth protrusion 7141 may be provided on the side of the fourth region 714 facing the gate electrode of the third transistor of the sub-pixel, and the ninth protrusion 7141 may extend in the opposite direction of the second direction Y. The orthographic projection of the ninth protrusion 7141 on the substrate may not overlap with or partially overlap with the orthographic projection of the gate electrode of the third transistor T3 of the sub-pixel on the substrate (forming the second overlapping region). The ninth protrusion 7141 can be connected to the anode connection electrode 53 through the fourteenth via V14 of the sub-pixel. The ninth protrusion 7141 may include a first side away from the fourth region 714, and a second side connected to the fourth region 714 and adjacent to the first side. The connection between the first side and the second side may be provided with a chamfer. One side of the fourth protrusion 7122 away from the second region 712 is arranged towards the chamfer and may be parallel to the chamfer. The ninth protrusion 7141 may also include a third side parallel to the second side and adjacent to the first side. The ends of the second side and the third side away from the first side are respectively connected to the middle position (non-end position) of two adjacent sides of the fourth region 714.

[0169] In an exemplary embodiment, the orthographic projection of the anode of the light-emitting device in the fourth sub-pixel P4 onto the substrate and the orthographic projection of the gate electrode of the third transistor T3 of the same sub-pixel onto the substrate do not overlap, or there is a second overlapping region. The area of ​​the second overlapping region is smaller than the area of ​​the first overlapping region of the third sub-pixel P3. This results in the parasitic capacitance of the N2 node in the pixel driving circuit of the third sub-pixel P3 being larger than that of the N2 node in the pixel driving circuit of the fourth sub-pixel P4. If the parasitic capacitance of the N2 node in the pixel driving circuits of the third sub-pixel P3 and the fourth sub-pixel P4 differs significantly, the potential written to the N2 node in the pixel driving circuits of the third sub-pixel P3 and the fourth sub-pixel P4 will differ significantly during signal writing. This will result in a significant difference in the current when the third sub-pixel P3 and the fourth sub-pixel P4 emit light (i.e., the current of the third sub-pixel P3 will be much smaller than that of the fourth sub-pixel P4), which in turn leads to inconsistent brightness between the third sub-pixel P3 and the fourth sub-pixel P4, affecting the display effect. In an exemplary embodiment, the second sub-pixel P2, adjacent to the fourth sub-pixel P4, is used as a compensation sub-pixel. The orthographic projection of the anode of the light-emitting device in the second sub-pixel P2 onto the substrate and the orthographic projection of the gate electrode of the third transistor T3 of the adjacent fourth sub-pixel P4 onto the substrate have a third overlapping region. Thus, by having a third overlapping region between the orthographic projection of the anode of the light-emitting device in the second sub-pixel P2 and the gate electrode of the third transistor T3 of the adjacent fourth sub-pixel P4 onto the substrate (i.e., increasing the overlap area between the gate electrode and the anode of the third transistor T3 of the fourth sub-pixel P4), the parasitic capacitance of the N2 node of the adjacent fourth sub-pixel P4 is compensated, thereby reducing the difference in parasitic capacitance between the N2 nodes of the fourth sub-pixel and the third sub-pixel, thereby reducing the brightness difference between the fourth sub-pixel and the third sub-pixel and improving the display effect. In an exemplary embodiment, a second sub-pixel P2 adjacent to the fourth sub-pixel P4 is used as a compensation sub-pixel. The anode of the light-emitting device in the second sub-pixel P2 includes a fourth protrusion 7122. The orthographic projection of the fourth protrusion 7122 on the substrate can overlap with the orthographic projection of the gate electrode of the third transistor T3 of the adjacent fourth sub-pixel P4 in the same row on the substrate to form a fourth overlapping region. The third overlapping region includes the fourth overlapping region.The fourth protrusion 7122 is shaped as a trapezoid, and one side of the fourth protrusion 7122 away from the second region 712 is set with a chamfered angle towards the anode of the fourth sub-pixel P4 and parallel to the chamfered angle. This increases the facing area of ​​the fourth protrusion 7122 and the ninth protrusion 7141, which is beneficial to increasing the parasitic capacitance formed between the fourth protrusion 7122 and the ninth protrusion 7141. This makes the potential of the fourth protrusion 7122 affected to a certain extent by the anode potential of the fourth sub-pixel P4. As a result, the parasitic capacitance generated between the anode of the light-emitting device in the second sub-pixel P2 and the gate electrode of the third transistor T3 of the adjacent fourth sub-pixel P4 is more like the parasitic capacitance generated by the overlap of the anode of the light-emitting device in the fourth sub-pixel P4 and the gate electrode of the third transistor T3 of the fourth sub-pixel P4. This further helps to make the difference between the parasitic capacitance of the N2 node of the fourth sub-pixel P4 and the parasitic capacitance of the N2 node of the third sub-pixel smaller, thus improving the display effect.

[0170] In other embodiments, the parasitic capacitance of the N2 node of the fourth sub-pixel P4 can be compensated by using the anode of the light-emitting device in the fourth sub-pixel P4 or the anode of the light-emitting device in the first sub-pixel P1, depending on the pixel structure design. For example, the overlap area of ​​the orthogonal projection of the anode of the light-emitting device in the fourth sub-pixel P4 and the gate electrode of the third transistor T3 of the sub-pixel on the substrate can be increased to increase the parasitic capacitance of the N2 node of the fourth sub-pixel P4.

[0171] After testing, without compensation for the parasitic capacitance of the N2 node of the fourth sub-pixel P4, the parasitic capacitance of the N2 node of the third sub-pixel P3 is 55.45 fF (fefat), and the parasitic capacitance of the N2 node of the fourth sub-pixel P4 is 54.66 fF. The current difference between the third sub-pixel P3 and the fourth sub-pixel P4 during illumination is 16.30%. With compensation for the parasitic capacitance of the N2 node of the fourth sub-pixel P4 using the scheme of the exemplary embodiment of this disclosure, the parasitic capacitance of the N2 node of the third sub-pixel P3 is 55.45 fF, and the parasitic capacitance of the N2 node of the fourth sub-pixel P4 is 55.41 fF. The current difference between the third sub-pixel P3 and the fourth sub-pixel P4 during illumination is 6.9%. It can be seen that after compensating for the parasitic capacitance of the N2 node of the fourth sub-pixel P4 using the scheme of the exemplary embodiment of this disclosure, the parasitic capacitance of the N2 node of the fourth sub-pixel P4 is increased, the difference in parasitic capacitance between the N2 nodes of the fourth sub-pixel and the third sub-pixel is reduced, thereby reducing the brightness difference between the fourth sub-pixel and the third sub-pixel.

[0172] (10) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer 72, wherein each sub-pixel's pixel definition layer 72 is provided with a pixel opening 73, the pixel opening 73 exposing the anode and covering the portion of the anode near its circumferential edge, such as... Figure 15a and Figure 15b As shown, Figure 15b for Figure 15a A planar schematic diagram of the pixel definition layer.

[0173] like Figures 6 to 15b As shown, the orthographic projection of at least one pixel opening 73 on the substrate can avoid the orthographic projection of the fourth conductive layer's traces on the substrate; or, the orthographic projection of at least one pixel opening 73 on the substrate can overlap with the orthographic projection of the fourth conductive layer's traces on the substrate, and the orthographic projection of at least one pixel opening 73 on the substrate can be bisected by the orthographic projection of the fourth conductive layer's traces on the substrate along the first direction X or the second direction Y, thus avoiding the large viewpoint color offset problem. For example, the traces of the fourth conductive layer may include a data signal line 51 and an anode connection electrode 53. The pixel opening 731 of the first sub-pixel P1, the pixel opening 733 of the third sub-pixel P3, and the pixel opening 734 of the fourth sub-pixel P4 all avoid the data signal line 51 and the anode connection electrode 53. The pixel opening 732 of the second sub-pixel P2 avoids the anode connection electrode 53, and the orthographic projection of the pixel opening 732 of the second sub-pixel P2 on the substrate is bisected by the orthographic projection of the data signal line 51 on the substrate along the second direction Y.

[0174] In an exemplary embodiment, the shape of the pixel opening 73 of each sub-pixel can be adapted to the shape of the region of the anode of that sub-pixel excluding the protrusion. For example, the first region 711 of the anode of the first sub-pixel P1 is hexagonal in shape, and the pixel opening 731 of the first sub-pixel P1 is hexagonal in shape; the second region 712 of the anode of the second sub-pixel P2 is hexagonal in shape, and the pixel opening 732 of the second sub-pixel P2 is hexagonal in shape; the third region 713 of the anode of the third sub-pixel P3 is pentagonal in shape, and the pixel opening 733 of the third sub-pixel P3 is pentagonal in shape; the fourth region 714 of the anode of the fourth sub-pixel P4 is pentagonal in shape, and the pixel opening 734 of the fourth sub-pixel P4 is pentagonal in shape. In other embodiments, the shape of the pixel opening can be rectangular.

[0175] In an exemplary embodiment, subsequent fabrication processes may include: forming an organic light-emitting layer using vapor deposition or inkjet printing; the organic light-emitting layer being connected to an anode through pixel openings; forming a cathode on the organic light-emitting layer; and connecting the cathode to the organic light-emitting layer. An encapsulation layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0176] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the adhesive layer can be amorphous silicon (a-Si).

[0177] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can all be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can all be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer structures or multi-layer composite structures. The first insulating layer can be called a buffer layer to improve the substrate's resistance to water and oxygen. The second and third insulating layers can be called gate insulating (GI) layers, and the fourth insulating layer can be called an interlayer insulating (ILD) layer. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology. The first and second planarization layers can be made of organic materials, such as resin. The anode can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO); or, the anode can be a multilayer composite structure, such as ITO / Ag / ITO. The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate. The cathode can be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0178] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this disclosure is not limited thereto.

Claims

1. A display substrate, comprising: The array consists of multiple sub-pixels, including a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and a third and fourth sub-pixels that emit a third color light. At least one sub-pixel includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a storage capacitor, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit. The orthographic projection of the anode of the light-emitting device in the third sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the third sub-pixel onto the substrate have a first overlapping region; The orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate do not overlap; or, the orthographic projection of the anode of the light-emitting device in the fourth sub-pixel onto the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel onto the substrate have a second overlapping region, the area of ​​the second overlapping region being smaller than the area of ​​the first overlapping region. The first sub-pixel or the second sub-pixel adjacent to the fourth sub-pixel includes a conductive block, and the orthographic projection of the conductive block on the substrate and the orthographic projection of the gate electrode of the driving transistor in the fourth sub-pixel on the substrate have a third overlapping region; Both the third sub-pixel and the fourth sub-pixel emit green light.

2. The display substrate as claimed in claim 1, wherein: The conductive block is the anode of the light-emitting device in the sub-pixel where the conductive block is located; Alternatively, the pixel driving circuit of the sub-pixel containing the conductive block may include the conductive block.

3. The display substrate as claimed in claim 1, wherein: The potential of the conductive block is different from the potential of the anode of the light-emitting device in the fourth sub-pixel.

4. The display substrate as claimed in claim 2, wherein: The first sub-pixel or the second sub-pixel adjacent to the fourth sub-pixel serves as a compensation sub-pixel, and the conductive block is the anode of the light-emitting device in the compensation sub-pixel.

5. The display substrate as claimed in claim 4, wherein: The area of ​​the third overlapping region is smaller than the area of ​​the first overlapping region.

6. The display substrate according to any one of claims 1 to 5, wherein: The light-emitting structure layer further includes a pixel definition layer, which has pixel openings that expose the anode of the light-emitting device; One conductive layer in the driving circuit layer that is away from the substrate includes a data signal line; At least one of the pixel openings has its orthographic projection on the substrate bypassing the orthographic projection of the conductive layer containing the data signal line on the substrate, or at least one of the pixel openings has its orthographic projection on the substrate bisected by the orthographic projection of the conductive layer containing the data signal line on the substrate.

7. The display substrate as claimed in claim 6, wherein: The driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked sequentially on the substrate; The semiconductor layer includes the active layer of the driving transistor, the first conductive layer includes the first electrode of the storage capacitor and the scan signal line, the second conductive layer includes the second electrode of the storage capacitor, the third conductive layer includes the power line, and the fourth conductive layer includes the data signal line. The scan signal line extends along a first direction, and the power line and the data signal line both extend along a second direction, which intersects the first direction.

8. The display substrate as claimed in claim 4, wherein: The pixel driving circuit further includes a write transistor, the gate electrode of which is connected to the scan signal line, the first electrode of which is connected to the data signal line, and the second electrode of which is connected to the first electrode of the driving transistor. The orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the write transistor in the adjacent fourth sub-pixel onto the substrate.

9. The display substrate as claimed in claim 4, wherein: The pixel driving circuit further includes a compensation transistor, the gate electrode of which is connected to the scan signal line, the first electrode of which is connected to the gate electrode of the driving transistor, and the second electrode of which is connected to the second electrode of the driving transistor. The orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the compensation transistor in the adjacent fourth sub-pixel onto the substrate.

10. The display substrate as claimed in claim 9, wherein: The orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the compensation transistor in the compensation sub-pixel onto the substrate.

11. The display substrate as claimed in claim 4, wherein: The orthographic projection of the anode of the light-emitting device in the compensation sub-pixel onto the substrate also overlaps with the orthographic projection of the active layer of the driving transistor in the compensation sub-pixel onto the substrate.

12. The display substrate as claimed in claim 4, wherein: The light-emitting structure layer further includes a pixel definition layer, which has pixel openings that expose the anode of the light-emitting device; The anode of the light-emitting device in the compensation sub-pixel includes a second region, and a third protrusion and a fourth protrusion connected to the second region; The shape of the second region is the same as the shape of the pixel opening in the compensation sub-pixel, and the area of ​​the second region is larger than the area of ​​the pixel opening in the compensation sub-pixel; The third protrusion is connected to the pixel driving circuit of the compensation sub-pixel through a via. The orthographic projection of the fourth protrusion on the substrate and the orthographic projection of the gate electrode of the driving transistor in the adjacent fourth sub-pixel on the substrate have a fourth overlapping region, and the third overlapping region includes the fourth overlapping region.

13. The display substrate as claimed in claim 12, wherein: The second region is hexagonal in shape, and the fourth protrusion is trapezoidal in shape, with the two hypotenuses of the fourth protrusion being collinear with the two sides of the second region.

14. The display substrate as claimed in claim 13, wherein: The anode of the light-emitting device in the fourth sub-pixel includes a fourth region and a ninth protrusion connected to the fourth region; The ninth protrusion is located on the side of the fourth region facing the gate electrode of the driving transistor in the fourth sub-pixel, and the ninth protrusion is connected to the pixel driving circuit of the fourth sub-pixel through a via.

15. The display substrate as claimed in claim 14, wherein: The ninth protrusion includes a first side away from the fourth region and a second side connected to the fourth region and adjacent to the first side, wherein the connection between the first side and the second side is provided with a chamfer. The fourth protrusion is positioned with one side away from the second region facing the chamfer and parallel to the chamfer.

16. The display substrate as claimed in claim 12, wherein: The pixel driving circuit further includes a compensation transistor, the gate electrode of which is connected to the scan signal line, the first electrode of which is connected to the gate electrode of the driving transistor, and the second electrode of which is connected to the second electrode of the driving transistor. The anode of the light-emitting device in the compensation sub-pixel further includes a fifth protrusion and a sixth protrusion connected to the second region, the fifth protrusion and the sixth protrusion being located on opposite sides of the second region; The orthographic projection of the fifth protrusion on the substrate overlaps with the orthographic projection of the active layer of the compensation transistor in the adjacent fourth sub-pixel on the substrate, and the orthographic projection of the sixth protrusion on the substrate overlaps with the orthographic projection of the active layer of the compensation transistor in the compensation sub-pixel on the substrate.

17. The display substrate as claimed in claim 9, wherein: The anode of the light-emitting device in the third sub-pixel includes a third region, and a seventh protrusion and an eighth protrusion connected to the third region; The shape of the third region is the same as the shape of the pixel opening in the third sub-pixel, and the area of ​​the third region is larger than the area of ​​the pixel opening in the third sub-pixel. The seventh protrusion and the eighth protrusion are located on opposite sides of the third region. The seventh protrusion is connected to the pixel driving circuit of the third sub-pixel through a via. The orthographic projection of the eighth protrusion on the substrate overlaps with the orthographic projection of the active layer of the compensation transistor in the third sub-pixel on the substrate.

18. The display substrate according to any one of claims 1 to 5, wherein: The multiple sub-pixels are arranged into multiple pixel rows and multiple pixel columns. Multiple sub-pixels in the same pixel row are arranged along a first direction, and multiple sub-pixels in the same pixel column are arranged along a second direction. The second direction intersects with the first direction. Any fourth sub-pixel and the third sub-pixel adjacent to the fourth sub-pixel are located in the same pixel column, and any fourth sub-pixel, the first sub-pixel adjacent to the fourth sub-pixel, and the second sub-pixel are located in the same pixel row.

19. The display substrate as claimed in claim 18, wherein: The first sub-pixel and the second sub-pixel are alternately arranged in the same pixel column, and the third sub-pixel and the fourth sub-pixel are alternately arranged in the same pixel column.

20. The display substrate according to any one of claims 1 to 5, wherein: The first sub-pixel emits red light, and the second sub-pixel emits blue light.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

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