Back driver and chip with overdrive capability

By using pull-up and pull-down circuits and bias circuits in the rear driver to provide voltage offset protection transistors, the transistor damage and reliability problems caused by overdrive design in semiconductor manufacturing are solved, and higher system reliability is achieved.

CN115811310BActive Publication Date: 2026-07-10MEDIATEK INC
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Patent Information

Application Number
CN202210911066.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2022-07-12
Filing Date
2022-07-29
Publication Date
2026-07-10
Estimated Expiration
2042-07-29

AI Technical Summary

Technical Problem

In semiconductor manufacturing, as technology advances, the voltage requirements of new-generation chips differ from those of older chips, leading to an increased need for overdrive design. Traditional designs may damage transistors, and multiplexers can cause reliability issues.

Method used

A rear driver with pull-up and pull-down circuits is used to provide voltage offset at the transistor gate through a bias circuit to balance the overdrive voltage, replacing the traditional multiplexer to protect the transistor. PMOS and NMOS transistors are coupled in series and voltage offset is provided through a diode string.

Benefits of technology

It effectively protects transistors from damage under overdrive voltage, improves system reliability, and avoids reliability problems caused by multiplexers in traditional designs.

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Abstract

The application provides a post driver and a chip with overdrive capability. A first biasing circuit is configured to provide a first voltage offset between an output of the post driver and a gate of a first P-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-up circuit is enabled. A second biasing circuit is configured to provide a second voltage offset between the output of the post driver and a gate of a first N-channel metal-oxide-semiconductor (NMOS) transistor of a pull-down circuit when the pull-down circuit is enabled. Thus, both the PMOS transistor in the pull-up circuit and the NMOS transistor in the pull-down circuit are well protected despite being powered by overdrive voltage.
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Citation Information

Patent Citations

  • Output buffer with protective limit of voltage across terminals of devices within the output buffer

    US6081152A