Display panel, manufacturing method thereof, and display device

Abstract

A display panel, a manufacturing method thereof, and a display device. The display panel includes a first transistor (T1), and further includes: a substrate (81), a second conductive layer, a second active layer, a third gate insulating layer (87), and a third conductive layer. The second conductive layer is located on one side of the substrate (81), and the second conductive layer includes a first conductive portion (1G11), and the first conductive portion (1G11) is used to form the first gate of the first transistor (T1); the second active layer is located on the side of the second conductive layer away from the substrate (81), and the second active layer includes a first active portion (71), and the first active portion includes a first sub-active portion (711), a second sub-active portion (712), and a third sub-active portion (713) connected between the first sub-active portion (711) and the second sub-active portion (712); the first sub-active portion (711) is used to form the first pole of the first transistor (T1), the second sub-active portion (712) is used to form the second pole of the first transistor (T1), and a part of the structure of the third sub-active portion (713) is used to form the channel region of the first transistor (T1), and the positive projection of the first conductive portion (1G11) on the substrate (81) covers the positive projection of the third sub-active portion (713) on the substrate (81); the third gate insulating layer (87) is located on the side of the second active layer away from the substrate (81), and the positive projection of the third gate insulating layer (87) on the substrate (81) covers the positive projection of the first active portion (71) on the substrate (81); the third conductive layer is located on the side of the third gate insulating layer away from the substrate (81), and the third conductive layer includes a second conductive portion (2Re12), and the second conductive portion (2Re12) is used to form the second gate of the first transistor (T1), and the positive projection of the second conductive portion (2Re12) on the substrate (81) covers the positive projection of the channel region of the first transistor (T1) on the substrate (81). The display panel has a better driving effect.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] A display panel generally includes various circuits such as pixel driving circuits and gate driving circuits integrated on an array substrate. The various circuits integrated on the array substrate generally include transistors. In related technologies, due to reasons such as manufacturing processes, the size of the transistors cannot meet the preset requirements.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art.

[0004] Disclosure Content

[0005] According to one aspect of the present disclosure, a display panel is provided. The display panel includes a first transistor and includes: a substrate, a second conductive layer, a second active layer, a third gate insulating layer, and a third conductive layer. The second conductive layer is located on one side of the substrate. The second conductive layer includes a first conductive portion for forming a first gate of the first transistor. The second active layer is located on a side of the second conductive layer away from the substrate. The second active layer includes a first active portion, and the first active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion. The first sub-active portion is used to form a first pole of the first transistor, the second sub-active portion is used to form a second pole of the first transistor, and a partial structure of the third sub-active portion is used to form a channel region of the first transistor. The positive projection of the first conductive portion on the substrate covers the positive projection of the third sub-active portion on the substrate. The third gate insulating layer is located on a side of the second active layer away from the substrate. The positive projection of the third gate insulating layer on the substrate covers the positive projection of the first active portion on the substrate. The third conductive layer is located on a side of the third gate insulating layer away from the substrate. The third conductive layer includes a second conductive portion for forming a second gate of the first transistor, and the positive projection of the second conductive portion on the substrate covers the positive projection of the channel region of the first transistor on the substrate.

[0006] In an exemplary embodiment of the present disclosure, the third sub-active part includes a first sub-active part, a second sub-active part, and a third sub-active part. The first sub-active part is connected between the first sub-active part and the third sub-active part. The second sub-active part is connected between the third sub-active part and the second sub-active part. The third sub-active part is used to form the channel region of the first transistor. The positive projection of the second conductive part on the substrate covers the positive projection of the third sub-active part on the substrate, and the positive projection of the second conductive part on the substrate is located between the positive projection of the first sub-active part on the substrate and the positive projection of the second sub-active part on the substrate.

[0007] In an exemplary embodiment of the present disclosure, the difference between the sheet resistance of the first sub-active part and the sheet resistance of the second sub-active part is less than a preset value. The preset value is 0 - 100 Ω / sq. The sheet resistance of the first sub-active part is less than the sheet resistance of the first sub-active part, and the sheet resistance of the first sub-active part is less than the sheet resistance of the second sub-active part.

[0008] In an exemplary embodiment of the present disclosure, the difference between the sheet resistance of the first sub-active part and the sheet resistance of the second sub-active part is less than a preset value. The preset value is 0 - 100 Ω / sq. The sheet resistance of the first sub-active part is 2000 - 20000 Ω / sq.

[0009] In an exemplary embodiment of the present disclosure, the sheet resistance of the first sub-active part is 500 - 2000 Ω / sq, and the sheet resistance of the second sub-active part is 500 - 2000 Ω / sq.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate. The fourth conductive layer includes a third conductive part and a fourth conductive part. The third conductive part is connected to the first sub-active part through a first via, and the fourth conductive part is connected to the second sub-active part through a second via.

[0011] In an exemplary embodiment of the present disclosure, the positive projection of the first via on the substrate is located on the positive projection of the first sub-active part on the substrate. The positive projection of the second via on the substrate is located on the positive projection of the second sub-active part on the substrate. The area of the positive projection of the first via on the substrate is less than or equal to the area of the positive projection of the first sub-active part on the substrate. The area of the positive projection of the second via on the substrate is less than or equal to the area of the positive projection of the second sub-active part on the substrate.

[0012] In an exemplary embodiment of the present disclosure, the edge of the first sub-active portion at least partially coincides with the orthographic projection of the first conductive portion on the substrate substrate; the edge of the second sub-active portion at least partially coincides with the orthographic projection of the first conductive portion on the substrate substrate.

[0013] In an exemplary embodiment of the present disclosure, the first active portion further includes a sixth sub-active portion, the sixth sub-active portion is located between the first sub-active portion and the third sub-active portion, and the orthographic projection of the sixth sub-active portion on the substrate substrate is located between the orthographic projection of the first sub-active portion on the substrate substrate and the orthographic projection of the first conductive portion on the substrate substrate; the sheet resistance of the sixth sub-active portion is 2000 - 20000 Ω / sq.

[0014] In an exemplary embodiment of the present disclosure, the first transistor is an oxide transistor.

[0015] In an exemplary embodiment of the present disclosure, the display panel further includes a pixel driving circuit, the pixel driving circuit includes the first transistor; the pixel driving circuit further includes a driving transistor, a first pole of the first transistor is connected to a gate of the driving transistor, and a second pole is connected to a first initial signal terminal; the pixel driving circuit further includes a second transistor, a first pole of the second transistor is connected to the gate of the driving transistor, and a second pole is connected to a second pole of the driving transistor, and the second transistor is an oxide transistor.

[0016] In an exemplary embodiment of the present disclosure, the first active portion further includes: a fourth sub-active portion and a fifth sub-active portion, the fourth sub-active portion is used to form a second pole of the second transistor; the fifth sub-active portion is connected between the fourth sub-active portion and the first sub-active portion, and a part of the fifth sub-active portion is used to form a channel region of the second transistor; the first sub-active portion is shared as a first pole of the second transistor; the second conductive layer further includes a fifth conductive portion, the fifth conductive portion is used to form a first gate of the second transistor, and the orthographic projection of the fifth conductive portion on the substrate substrate covers the orthographic projection of the fifth sub-active portion on the substrate substrate; the third conductive layer further includes a sixth conductive portion, the sixth conductive portion is used to form a second gate of the second transistor, and the orthographic projection of the sixth conductive portion on the substrate substrate covers the orthographic projection of the channel region of the second transistor on the substrate substrate.

[0017] In an exemplary embodiment of the present disclosure, the fifth sub-active part includes a fourth sub-active part, a fifth sub-active part, and a sixth sub-active part. The fourth sub-active part is connected between the first sub-active part and the sixth sub-active part. The fifth sub-active part is connected between the sixth sub-active part and the fourth sub-active part. The sixth sub-active part is configured to form a channel region of the second transistor. The sixth conductive part orthogonally projects onto the substrate and covers the orthographic projection of the sixth sub-active part on the substrate. The orthographic projection of the sixth conductive part on the substrate is located between the orthographic projection of the fifth sub-active part on the substrate and the orthographic projection of the fourth sub-active part on the substrate.

[0018] In an exemplary embodiment of the present disclosure, the difference between the sheet resistance of the fourth sub-active part and the sheet resistance of the fifth sub-active part is less than a preset value. The preset value is 0 - 100 Ω / sq. The sheet resistance of the fourth sub-active part is less than the sheet resistance of the fourth sub-active part, and the sheet resistance of the fourth sub-active part is less than the sheet resistance of the first sub-active part.

[0019] In an exemplary embodiment of the present disclosure, the difference between the sheet resistance of the fourth sub-active part and the sheet resistance of the fifth sub-active part is less than a preset value. The preset value is 0 - 100 Ω / sq. The sheet resistance of the fourth sub-active part is 2000 - 20000 Ω / sq.

[0020] According to one aspect of the present disclosure, there is provided a method for manufacturing a display panel. The display panel includes a first transistor. The method for manufacturing the display panel includes:

[0021] Providing a substrate;

[0022] Forming a second conductive layer on one side of the substrate. The second conductive layer includes a first conductive part, and the first conductive part is configured to form a first gate of the first transistor;

[0023] Forming a second active material layer on a side of the second conductive layer facing away from the substrate. The second active material layer includes a first active material part. The first active material part includes a first sub-active material part, a second sub-active material part, and a third sub-active material part connected between the first sub-active material part and the second sub-active material part;

[0024] A partial structure of the third sub-active material part is configured to form a channel region of the first transistor, and the first conductive part orthogonally projects onto the substrate and covers the orthographic projection of the third sub-active material part on the substrate;

[0025] A third gate insulating layer is formed on a side of the second active material layer facing away from the substrate, and a positive projection of the third gate insulating layer on the substrate covers a positive projection of the first active material portion on the substrate;

[0026] A third conductive layer is formed on a side of the third gate insulating layer facing away from the substrate. The third conductive layer includes a second conductive portion for forming a second gate of the first transistor, and a positive projection of the second conductive portion on the substrate overlaps with a positive projection of the third sub-active material portion on the substrate;

[0027] The second active material layer is subjected to a conductorization process using the third conductive layer as a mask.

[0028] In an exemplary embodiment of the present disclosure, the first transistor is an oxide transistor, and the second active material layer is an oxide semiconductor.

[0029] In an exemplary embodiment of the present disclosure, subjecting the second active material layer to a conductorization process using the third conductive layer as a mask includes:

[0030] A second dielectric layer is formed on a side of the third conductive layer facing away from the substrate using a chemical vapor deposition process;

[0031] During the formation of the second dielectric layer, conductorization ions are generated, and the conductorization ions can conductize the second active material layer.

[0032] In an exemplary embodiment of the present disclosure, the material of the second dielectric layer is silicon nitride, and the conductorization ions are hydrogen ions.

[0033] In an exemplary embodiment of the present disclosure, the method for manufacturing the display panel further includes:

[0034] A first via hole and a second via hole penetrating through the third gate insulating layer and the second dielectric layer are formed by a dry etching gas. A positive projection of the first via hole on the substrate is located on a positive projection of the first sub-active material portion on the substrate, and a positive projection of the second via hole on the substrate is located on a positive projection of the second sub-active material portion on the substrate. During the dry etching process, the dry etching gas can generate conductorization ions, and the conductorization ions can conductize the second active material layer;

[0035] A fourth conductive layer including a third conductive portion and a fourth conductive portion is formed on a side of the second dielectric layer facing away from the substrate;

[0036] The third conductive portion is connected to the first sub-active material portion through the first via hole, and the fourth conductive portion is connected to the second sub-active material portion through the second via hole.

[0037] In an exemplary embodiment of the present disclosure, the area of the orthographic projection of the first via hole on the substrate is less than or equal to the area of the orthographic projection of the first sub-active material portion on the substrate; the area of the orthographic projection of the second via hole on the substrate is less than or equal to the area of the orthographic projection of the second sub-active material portion on the substrate.

[0038] In an exemplary embodiment of the present disclosure, at least a part of the orthographic projection of the edge of the first sub-active material portion on the substrate coincides with at least a part of the orthographic projection of the first conductive portion on the substrate; at least a part of the orthographic projection of the edge of the second sub-active material portion on the substrate coincides with at least a part of the orthographic projection of the first conductive portion on the substrate.

[0039] In an exemplary embodiment of the present disclosure, the conductorization process of the second active material layer using the third conductive layer as a mask includes:

[0040] Injecting conductorization ions into the second active material layer through an ion implantation process.

[0041] In an exemplary embodiment of the present disclosure, the third sub-active material portion includes a first sub-active material portion, a second sub-active material portion, and a third sub-active material portion. The first sub-active material portion is connected between the first sub-active material portion and the third sub-active material portion, and the second sub-active material portion is connected between the third sub-active material portion and the second sub-active material portion; the orthographic projection of the second conductive portion on the substrate covers the orthographic projection of the third sub-active material portion on the substrate.

[0042] According to an aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0043] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0045] Figure 1Schematic diagram of the circuit structure of a pixel driving circuit in the related art;

[0046] Figure 2 is Figure 1 Timing diagram of each node in a driving method of a pixel driving circuit;

[0047] Figure 3 Structural layout of a display panel in the related art;

[0048] Figure 4 is Figure 3 Structural layout of the first active layer in;

[0049] Figure 5 is Figure 3 Structural layout of the first conductive layer in;

[0050] Figure 6 is Figure 3 Structural layout of the second conductive layer in;

[0051] Figure 7 is Figure 3 Structural layout of the second active layer in;

[0052] Figure 8 is Figure 3 Structural layout of the third conductive layer in;

[0053] Figure 9 is Figure 3 Structural layout of the fourth conductive layer in;

[0054] Figure 10 is Figure 3 Structural layout of the fifth conductive layer in;

[0055] Figure 11 is Figure 3 Structural layout of the first active layer and the first conductive layer in;

[0056] Figure 12 is Figure 3 Structural layout of the first active layer, the first conductive layer, and the second conductive layer in;

[0057] Figure 13 is Figure 3 Structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in;

[0058] Figure 14 is Figure 3 Structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in;

[0059] Figure 15 is Figure 3The structural layout diagrams of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in

[0060] Figure 16 is Figure 15 The partial cross-sectional view at the dashed line A in

[0061] Figure 17 The process flow chart in an exemplary embodiment of the method for manufacturing the display panel of the present disclosure;

[0062] Figure 18 The process flow chart in an exemplary embodiment of the method for manufacturing the display panel of the present disclosure;

[0063] Figure 19 The process flow chart in an exemplary embodiment of the method for manufacturing the display panel of the present disclosure;

[0064] Figure 20 The structural layout diagram of an exemplary embodiment of the display panel of the present disclosure;

[0065] Figure 21 is Figure 20 The structural layout diagram of the first active layer in

[0066] Figure 22 is Figure 20 The structural layout diagram of the first conductive layer in

[0067] Figure 23 is Figure 20 The structural layout diagram of the second conductive layer in

[0068] Figure 24 is Figure 20 The structural layout diagram of the second active layer in

[0069] Figure 25 is Figure 20 The structural layout diagram of the third conductive layer in

[0070] Figure 26 is Figure 20 The structural layout diagram of the fourth conductive layer in

[0071] Figure 27 is Figure 20 The structural layout diagram of the fifth conductive layer in

[0072] Figure 28 is Figure 20 The structural layout diagram of the first active layer and the first conductive layer in

[0073] Figure 29 is Figure 20 The structural layout diagram of the first active layer, the first conductive layer, and the second conductive layer in

[0074] Figure 30 For Figure 20 the structural layout diagrams of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in

[0075] Figure 31 For Figure 20 the structural layout diagrams of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in

[0076] Figure 32 For Figure 20 the structural layout diagrams of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in

[0077] Figure 33 For the partial structural layout diagrams of the second conductive layer and the second active layer in 20;

[0078] Figure 34 For the partial structural layout diagrams of the second conductive layer, the second active layer, and the third conductive layer in 20;

[0079] Figure 35 For Figure 32 the partial cross-sectional view along the dashed line B in

[0080] Figure 36 The structural schematic diagram of the first transistor in another exemplary embodiment of the display panel disclosed herein. Detailed implementation manners

[0081] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0082] The terms "a", "an", and "the" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0083] As Figure 1As shown, it is a schematic circuit diagram of a pixel driving circuit in the related art. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first pole of the second transistor T2 is connected to the node N, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, the second pole is connected to the first pole of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light. The light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors. The N-type metal oxide transistors have a small leakage current, so that during the light-emitting stage, the node N can be prevented from leaking electricity through the first transistor T1 and the second transistor T2. At the same time, the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors. The low-temperature polycrystalline silicon transistors have a high carrier mobility, which is beneficial to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to the actual situation.

[0084] As Figure 2 shown, it is Figure 1Timing diagrams of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage T3, and a light-emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2, and at the same time the data signal terminal Da outputs a driving signal to write a voltage Vdata + Vth to the node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. In the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata + Vth stored in the capacitor C. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current I of the driving transistor in the pixel driving circuit of the present disclosure = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 . The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that Figure 1 the pixel driving circuit shown may also have other driving methods. For example, both the first transistor T1 and the seventh transistor T7 can be reset in the first reset stage, so that the second reset stage can be omitted in this driving method.

[0085] In the related art, the display panel may include Figure 1 the pixel driving circuit shown, and the display panel may further include a substrate substrate, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially stacked. Insulating layers may be provided between the above-mentioned layers. As Figure 3-15 shown Figure 3It is the structural layout of the display panel in the related art. Figure 4 It is Figure 3 the structural layout of the first active layer in Figure 5 It is Figure 3 the structural layout of the first conductive layer in Figure 6 It is Figure 3 the structural layout of the second conductive layer in Figure 7 It is Figure 3 the structural layout of the second active layer in Figure 8 It is Figure 3 the structural layout of the third conductive layer in Figure 9 It is Figure 3 the structural layout of the fourth conductive layer in Figure 10 It is Figure 3 the structural layout of the fifth conductive layer in Figure 11 It is Figure 3 the structural layout of the first active layer and the first conductive layer in Figure 12 It is Figure 3 the structural layout of the first active layer, the first conductive layer, and the second conductive layer in Figure 13 It is Figure 3 the structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 14 It is Figure 3 the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 15 It is Figure 3 the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in

[0086] As shown in Figure 3 and 4 and 11, the first active layer may include active parts 064, 065, 066, 067. Among them, the active part 064 is used to form the channel region of the fourth transistor, the active part 065 is used to form the channel region of the fifth transistor, the active part 066 is used to form the channel region of the sixth transistor, the active part 067 is used to form the channel region of the seventh transistor, and the active part 063 is used to form the channel region of the driving transistor T3. The first active layer may be formed of polycrystalline semiconductor.

[0087] As shown in Figure 3 and 5 and 11, the first conductive layer may include the second gate driving signal line G2, the enable signal line EM, the second reset signal line Re2, and the conductive part 011. Among them, the second gate driving signal line G2 is used to provide Figure 1 the second gate driving signal terminal G2 in Figure 1 the enable signal terminal EM inFigure 1 The second reset signal terminal Re2 in

[0088] As Figure 3 、 6 、shown in 12, the second conductive layer may include: a first sub-reset signal line 1Re1, a first sub-gate drive signal line 1G1, and a conductive portion 021. The first sub-reset signal line 1Re1 is used to provide Figure 1 the first reset signal terminal in Figure 1 and the first sub-gate drive signal line 1G1 is used to provide

[0089] As Figure 3 、 7 、shown in 13, the second active layer may include an active portion 07. The active portion 07 may include an active portion 071 and an active portion 072. The active portion 071 is used to form the channel region of the first transistor, and the active portion 072 is used to form the channel region of the second transistor. The second active layer may be formed of an oxide semiconductor, such as indium gallium zinc oxide.

[0090] As Figure 3 、 8 、shown in 14, the third conductive layer may include: a second sub-reset signal line 2Re1, a second sub-gate drive signal line 2G1. The second sub-reset signal line 2Re1 is used to provide Figure 1 the first reset signal terminal in Figure 1 and the second sub-gate drive signal line 2G1 is used to provide

[0091] As Figure 3 、 9 、shown in 15, the fourth conductive layer may include: a first power supply line VDD1, a first initial signal line Vinit1, a second initial signal line Vinit2, connection portions 041, 042, 043, 044. The first power supply line VDD1 is used to provide Figure 1 the first power supply terminal inFigure 1 the first initial signal terminal, and the second initial signal line Vinit2 is used to provide Figure 1 the second initial signal terminal in. The connecting portion 041 can be connected to the first active layer on one side of the active portion 064 through a via (black square) to connect the first pole of the fourth transistor. The connecting portion 042 can be respectively connected to the second active layer between the conductive portion 011, the active portion 071, and the active portion 072 through vias to connect the gate of the driving transistor and the first pole of the first transistor, and the gate of the driving transistor and the first pole of the second transistor. The connecting portion 043 can be respectively connected to the first active layer on one side of the active portion 066 and the second active layer on one side of the active portion 072 through vias to connect the first pole and the second pole of the sixth transistor. The connecting portion 044 can be connected to the first active layer on one side of the active portion 066 through a via to connect the second pole of the sixth transistor. The first power supply line VDD1 can be connected to the first active layer on one side of the active portion 065 through a via to connect the first pole of the fifth transistor and the first power supply terminal, and the first power supply line VDD1 can also be connected to the conductive portion 021 through a via to connect the capacitor C and the first power supply terminal. The first initial signal line Vinit1 can be connected to the second active layer on one side of the active portion 071 through a via to connect the second pole of the first transistor and the first initial signal terminal. The second initial signal line can be connected to the first active layer on one side of the active portion 067 through a via to connect the second initial signal terminal and the second pole of the seventh transistor.

[0092] As Figure 3 , 10 shown, the fifth conductive layer can include: a second power supply line VDD2, a data line Da, and a connecting portion 051. Among them, the second power supply line VDD2 is used to provide Figure 1 the first power supply terminal in, and the data line Da is used to provide Figure 1 the data signal terminal in. The second power supply line VDD2 can be connected to the first power supply line VDD1 through a via. The data line Da can be connected to the connecting portion 041 through a via to connect the first pole of the fourth transistor and the data signal terminal. The connecting portion 051 can be connected to the connecting portion 044 through a via, and the connecting portion 051 can be used to connect Figure 1 the anode of the light-emitting unit in. As Figure 3 described, the orthographic projection of the first power supply line VDD1 on the substrate can be located between the orthographic projection of the data line Da on the substrate and the orthographic projection of the conductive portion 011 on the substrate, and the first power supply line VDD1 can shield the interference of the data line Da on the conductive portion 011.

[0093] As Figure 16 shown, for Figure 15Partial cross-sectional view at the dashed line A in the middle. Among them, the display panel further includes a first buffer layer 082, a first gate insulating layer 083, a second gate insulating layer 084, a first dielectric layer 085, a second buffer layer 086, a third gate insulating layer 087, and a second dielectric layer 088. Among them, the substrate 081, the first buffer layer 082, the first active layer, the first gate insulating layer 083, the first conductive layer, the second gate insulating layer 084, the second conductive layer, the first dielectric layer 085, the second buffer layer 086, the second active layer, the third gate insulating layer 087, the third conductive layer, the second dielectric layer 088, and the fourth conductive layer are stacked in sequence. As Figure 16 shown, in the related art, the method of making the second active layer conductive is as follows: after forming the third conductive layer on the side of the third gate insulating layer 087 facing away from the substrate 081, the third gate insulating layer not covered by the third conductive layer is removed, and then the second dielectric layer 088 is formed on the side of the third conductive layer facing away from the substrate by a chemical vapor deposition process. Among them, during the formation of the second dielectric layer 088, conductive ions capable of making the second active layer conductive will be generated. For example, the second dielectric layer can be silicon nitride, the second dielectric layer can be synthesized from silane and nitrogen, and hydrogen ions will be formed during the synthesis of the second dielectric layer, and the hydrogen ions can achieve the conductivity of the active part 07. However, during the process of making the active part 07 conductive, the lateral diffusion of hydrogen ions will cause the actual length L1 of the second transistor channel region to be less than its designed length L1 + 2L2, where the designed length L1 + 2L2 of the channel region is the length of the transistor gate in the lateral direction. As a result, the second transistor is prone to the short-channel effect. In this case, the threshold voltage Vth of the second transistor will be related to its channel length to a very serious degree, which is not conducive to the realization of the stability and uniformity of the threshold voltage Vth.

[0094] Based on this, the present exemplary embodiment provides a method for a display panel device, as Figure 17 shown, which is a process flow chart in an exemplary embodiment of the method for manufacturing the display panel of the present disclosure. Among them, the display panel may include a first transistor T1, and the method for manufacturing the display panel may include:

[0095] Step S1: Provide a substrate 81.

[0096] Step S2: Form a second conductive layer on one side of the substrate 81. The second conductive layer may include a first conductive part 1Re11, and the first conductive part 1Re11 is used to form the first gate of the first transistor T1.

[0097] Step S3: Form a second active material layer on a side of the second conductive layer facing away from the substrate 81. The second active material layer includes a first active material portion 71. The first active material portion 71 includes a first sub-active material portion 711, a second sub-active material portion 712, and a third sub-active material portion 713 connected between the first sub-active material portion 711 and the second sub-active material portion 712.

[0098] A partial structure of the third sub-active material portion 713 is used to form a channel region of the first transistor T1. A positive projection of the first conductive portion 1Re11 on the substrate covers a positive projection of the third sub-active material portion 713 on the substrate.

[0099] Step S4: Form a third gate insulating layer 87 on a side of the second active material layer facing away from the substrate 81. A positive projection of the third gate insulating layer 87 on the substrate covers a positive projection of the first active material portion 71 on the substrate.

[0100] Step S5: Form a third conductive layer on a side of the third gate insulating layer 87 facing away from the substrate 81. The third conductive layer includes a second conductive portion 2Re12. The second conductive portion 2Re12 is used to form a second gate of the first transistor T1. A positive projection of the second conductive portion 2Re12 on the substrate partially overlaps a positive projection of the third sub-active material portion 713 on the substrate, and a partial structure of the third sub-active material portion 713 does not intersect a positive projection of the second conductive portion 2Re12 on the substrate in the positive projection on the substrate. The third conductive layer can be formed by a photolithography process. Among them, the third conductive layer can be etched by a dry etching process. The dry etching process has a smaller CD Bias (Critical Dimension Bias, the deviation between the photoresist and the edge of the etched body), so that a third conductive layer with higher dimensional accuracy can be realized. Among them, the CD Bias of the dry etching process can reach 0.5 microns.

[0101] Step S6: Conductify the second active material layer using the third conductive layer as a mask.

[0102] In this exemplary embodiment, the first transistor can be an oxide transistor, and the second active material layer is an oxide semiconductor. For example, the material of the second active material layer can be indium gallium zinc oxide. The display panel in this exemplary embodiment can include a pixel driving circuit, and the display driving circuit can be as Figure 1 shown, where the first transistor in this exemplary embodiment can be Figure 1The first transistor in it. It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel may also have other structures, such as an 8T1C structure; Figure 17 The first transistor in it may also be a low-temperature polysilicon transistor, Figure 17 The first transistor in it may also be located in other circuit structures in the display panel. For example, the first transistor may be located in the gate driving circuit in the display panel.

[0103] In this exemplary embodiment, as Figure 17 shown, using the third conductive layer as a mask to conduct the second active material layer may include: forming a second dielectric layer 88 on the side of the third conductive layer facing away from the substrate using a chemical vapor deposition process. During the formation of the second dielectric layer 88, conductive ions can be generated, and the conductive ions can conduct the second active material layer not covered by the third conductive layer. For example, the second dielectric layer 88 may be silicon nitride, the second dielectric layer 88 can be synthesized from silane and nitrogen, and hydrogen ions will be formed during the synthesis of the second dielectric layer 88, and the hydrogen ions can conduct the second active material layer.

[0104] As Figure 17 shown, when conducting the second active material layer in this exemplary embodiment, since the third gate insulating layer 87 is covered on the second active material layer, the third gate insulating layer 87 has a blocking effect on the diffusion of conductive ions. Thus, the diffusion amount of the conductive ions in the lateral direction is extremely small or even zero. Furthermore, the length of the channel region formed using the second conductive portion 2Re12 as a mask in the lateral direction is the same as the length of the second conductive portion 2Re12 in the lateral direction, or the length of the channel region in the lateral direction is slightly smaller than the length of the second conductive portion 2Re12 in the lateral direction. That is, the manufacturing method of the display panel can greatly reduce Figure 16The value of L2 in the middle, so that the manufacturing method of the display panel can form a channel region with a larger size under the action of the second conductive part 2Re12 with a limited size. At the same time, since the third gate insulating layer 87 has a blocking effect on the diffusion of conductive ions, the ion doping concentration of the part of the third sub-active material part 713 not covered by the second conductive part 2Re12 is relatively low, and the sheet resistance is relatively large. Therefore, the on-current of the first transistor is relatively small. In addition, in this exemplary embodiment, the positive projection of the first conductive part 1Re11 on the substrate covers the positive projection of the third sub-active material part 713 on the substrate. Under the action of the conduction voltage of the first conductive part 1Re11, the sheet resistance of the third sub-active material part 713 located between the first pole and the second pole of the first transistor and not covered by the second conductive part 2Re12 is reduced, so that a relatively large on-current of the first transistor can be achieved. In addition, since the third sub-active material part 713 not covered by the second conductive part 2Re12 has a relatively large sheet resistance, the off-current of the first transistor is relatively small, so that the leakage current of the node N through the first transistor during the light-emitting stage can be further reduced. It should be noted that Figure 17 The horizontal direction therein can be the distribution direction of the first sub-active material part 711, the third sub-active material part 713, and the second sub-active material part 712, that is, the length direction of the channel region.

[0105] In this exemplary embodiment, as Figure 17 shown, the third sub-active material part 713 may include a first sub-active material part 7131, a second sub-active material part 7132, and a third sub-active material part 7133. The first sub-active material part 7131 may be connected between the first sub-active material part 711 and the third sub-active material part 7133. The second sub-active material part 7132 may be connected between the third sub-active material part 7133 and the second sub-active material part 712. The positive projection of the second conductive part 2Re12 on the substrate may cover the positive projection of the third sub-active material part 7133 on the substrate. Among them, after the second active layer is made conductive, the third sub-active material part 7133 may form a channel region of the first transistor.

[0106] In this exemplary embodiment, using the third conductive layer as a mask to conductivize the second active material layer may also include other methods. For example, before forming the second dielectric layer 88: through an ion implantation process, conductive ions are implanted into the second active layer. The ion implantation process provides a certain initial energy to the conductive ions, so that the conductive ions pass through the third gate insulating layer 87 and reach the second active layer. Among them, the conductive ions can be B, Al, F, In, Zn and other ions. In this exemplary embodiment, the conductivization of the second active material layer can be achieved solely through the ion implantation process, or on the basis of the above-mentioned second dielectric layer chemical vapor deposition process, the conductivization degree of the second active material layer can be further improved through the ion implantation process.

[0107] In this exemplary embodiment, such as Figure 18As shown, it is a process flow diagram of an exemplary embodiment of the method for manufacturing a display panel of the present disclosure. The method for manufacturing the display panel may further include: forming a first via hole H1 and a second via hole H2 penetrating through the third gate insulating layer 87 and the second dielectric layer 88 through a dry etching gas. The orthographic projection of the first via hole H1 on the substrate may be located on the orthographic projection of the first sub-active material portion 711 on the substrate, and the orthographic projection of the second via hole H2 on the substrate may be located on the orthographic projection of the second sub-active material portion 712 on the substrate. Wherein, the dry etching gas can generate conductive ions during the dry etching process, and the conductive ions can conductivize the second active material layer, thereby improving the conductivity of the first sub-active material portion 711 and the second sub-active material portion 712. For example, the dry etching gas may contain fluorine elements, hydrogen elements, etc., and the conductive ions may be fluoride ions, hydrogen ions. Conductive ions such as fluoride ions can occupy the lattice voids of indium gallium zinc oxide to conductivize indium gallium zinc oxide. In addition, after the dry etching is completed, the indium gallium zinc oxide layer can be further conductivized by argon gas Ar. Ar can also occupy the lattice voids of indium gallium zinc oxide to conductivize indium gallium zinc oxide, and the inert gas Ar will not affect the characteristics of the oxide transistor. Thus, the conductivity of the first sub-active material portion 711 and the second sub-active material portion 712 can be higher than that of the first sub-sub-active material portion 7131 and the second sub-sub-active material portion 7132. That is, the sheet resistance of the conductivized first sub-sub-active material portion 7131 is less than the sheet resistance of the conductivized first sub-active material portion 711, that is, the sheet resistance of the conductivized first sub-sub-active material portion 7131 is less than the sheet resistance of the conductivized second sub-active material portion 712. In addition, the sheet resistance of the conductivized first sub-sub-active material portion 7131 may be equal to the sheet resistance of the conductivized second sub-sub-active material portion 7132. The sheet resistance of the conductivized first sub-active material portion 711 may be equal to the sheet resistance of the second sub-active material portion 712. The conductivized first sub-active material portion 711 can be used to form the first pole of the first transistor, and the conductivized second sub-active material portion 712 can be used to form the second pole of the first transistor. In this exemplary embodiment, the sheet resistance of the conductivized first sub-sub-active material portion may be 2000 - 20000 Ω / sq, for example, 2000 Ω / sq, 5000 Ω / sq, 10000 Ω / sq, 20000 Ω / sq. The sheet resistance of the conductivized first sub-active material portion may be 500 - 2000 Ω / sq, for example, 500 Ω / sq, 1000 Ω / sq, 2000 Ω / sq. The sheet resistance of the conductivized second sub-active material portion may be 500 - 2000 Ω / sq, for example, 500 Ω / sq, 1000 Ω / sq, 2000 Ω / sq.

[0108] It should be noted that during the process of conducting the first sub-active material portion 711 and the second sub-active material portion 712 by the conducting ions generated by the dry etching gas during the dry etching process, the conducting ions will diffuse laterally. As a result, the orthographic projection of the first via H1 on the substrate can be slightly smaller than the orthographic projection of the first sub-active material portion 711 on the substrate, and the orthographic projection of the second via H2 on the substrate can be slightly smaller than the orthographic projection of the second sub-active material portion 712 on the substrate.

[0109] In this exemplary embodiment, Figure 17 As shown, the orthographic projection of the edge 7111 of the first sub-active portion 711 on the substrate substrate may at least partially overlap with the orthographic projection of the first conductive portion 1Re11 on the substrate substrate, and the orthographic projection of the edge 7121 of the second sub-active portion 712 on the substrate substrate may at least partially overlap with the orthographic projection of the first conductive portion 1Re11 on the substrate substrate. In other exemplary embodiments, the orthographic projection of the first conductive portion 1Re11 on the substrate substrate may also at least partially overlap with the orthographic projection of the first via H1 on the substrate substrate, and the orthographic projection of the first conductive portion 1Re11 on the substrate substrate may also at least partially overlap with the orthographic projection of the second via H2 on the substrate substrate.

[0110] It should be understood that in the exemplary embodiment, the first transistor may also be of other structures, for example, the first transistor may also include a plurality of channel regions connected in parallel or in series. Accordingly, other embodiments may also utilize the above structure to increase the channel length of the first transistor.

[0111] In this exemplary embodiment, Figure 19 , which is a process flow chart of an exemplary embodiment of the display panel manufacturing method disclosed herein. The display panel manufacturing method may further include: forming a fourth conductive layer on the side of the second dielectric layer 88 away from the base substrate 81, and the fourth conductive layer may include a third conductive portion 43 and a fourth conductive portion Vinit14. The third conductive portion 43 may be connected to the first sub-active material portion 711 through the first via H1, and the fourth conductive portion Vinit14 may be connected to the second sub-active material portion 712 through the second via H2.

[0112] In this exemplary embodiment, Figure 1 The second transistor in Figure 17-19 The first transistor in has the same structure.

[0113] The present exemplary embodiment also provides a display panel, which can be manufactured by the display panel manufacturing method.

[0114] In addition, the display panel may include Figure 1The pixel driving circuit shown, the display panel may further include a first active layer, a first conductive layer, and a fifth conductive layer. Among them, the substrate substrate, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be sequentially stacked. As Figure 20-32 shown, Figure 20 This is the structural layout of an exemplary embodiment of the display panel of the present disclosure. Figure 21 is Figure 20 the structural layout of the first active layer in Figure 20 the structural layout of the first conductive layer in Figure 23 is Figure 20 the structural layout of the second conductive layer in Figure 24 is Figure 20 the structural layout of the second active layer in Figure 25 is Figure 20 the structural layout of the third conductive layer in Figure 26 is Figure 20 the structural layout of the fourth conductive layer in Figure 27 is Figure 20 the structural layout of the fifth conductive layer in Figure 28 is Figure 20 the structural layout of the first active layer and the first conductive layer in Figure 29 is Figure 20 the structural layout of the first active layer, the first conductive layer, and the second conductive layer in Figure 30 is Figure 20 the structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 31 is Figure 20 the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 32 is Figure 20 the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in Figure 33 is a partial structural layout of the second conductive layer and the second active layer in 20. Figure 34 is a partial structural layout of the second conductive layer, the second active layer, and the third conductive layer in 20.

[0115] As Figure 20 , 21 , and as shown in 28, the first active layer may include active portions 63, 64, 65, 66, and 67. Among them, the active portion 64 is used to form the channel region of the fourth transistor, the active portion 65 is used to form the channel region of the fifth transistor, the active portion 66 is used to form the channel region of the sixth transistor, the active portion 67 is used to form the channel region of the seventh transistor, and the active portion 63 is used to form the channel region of the driving transistor T3. The first active layer may be formed of polycrystalline semiconductor.

[0116] As shown Figure 20 in 22 , Figures 28, the first conductive layer may include a second gate driving signal line G2, an enable signal line EM, a second reset signal line Re2, and a conductive part 11. Among them, the second gate driving signal line G2 is used to provide the second gate driving signal terminal in Figure 1 , the enable signal line EM is used to provide the enable signal terminal in Figure 1 , and the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 1 . The orthographic projection of the second gate driving signal line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate may extend along the first direction X. The conductive part 11 is used to form the gate of the driving transistor T3 and one electrode of the capacitor C. Among them, the first active layer may be formed by using the first conductive layer as a mask, that is, the part shielded by the first conductive layer forms the channel region of the transistor, and the part not shielded by the first conductive layer forms a conductive structure.

[0117] As shown Figure 20 in 23 , Figures 29, the second conductive layer may include: a first sub-reset signal line 1Re1, a first sub-gate driving signal line 1G1, and a conductive part 21. Among them, the first sub-reset signal line 1Re1 is used to provide the first reset signal terminal in Figure 1 , the first sub-gate driving signal line 1G1 is used to provide the first gate driving signal terminal in Figure 1 , and the conductive part 21 may form the other electrode of the capacitor C. The first sub-reset signal line 1Re1 may include a first conductive part 1Re11, and the first conductive part 1Re11 may be used to form the first gate of the first transistor; the first sub-gate driving signal line 1G1 may include a fifth conductive part 1G15, and the fifth conductive part may be used to form the first gate of the second transistor T2. The orthographic projection of the first sub-reset signal line 1Re1 on the substrate and the orthographic projection of the first sub-gate driving signal line 1G1 on the substrate may extend along the first direction X.

[0118] As shown Figure 20 in 24, as shown in FIGS. 30 and 33, the second active layer may include a first active portion 71. The orthographic projection of the first active portion 71 on the substrate may extend along the second direction Y, where the second direction Y and the first direction X may intersect. For example, the second direction Y and the first direction X may be perpendicular. The first active portion 71 may include a first sub-active portion 711, a second sub-active portion 712, and a third sub-active portion 713 connected between the first sub-active portion 711 and the second sub-active portion 712. The first sub-active portion 711 may be used to form the first pole of the first transistor T1, the second sub-active portion 712 may be used to form the second pole of the first transistor T1, and a partial structure of the third sub-active portion 713 may be used to form the channel region of the first transistor T1. The third sub-active portion 713 may include a first sub-active portion 7131, a second sub-active portion 7132, and a third sub-active portion 7133. The first sub-active portion 7131 is connected between the first sub-active portion 711 and the third sub-active portion 7133, the second sub-active portion 7132 is connected between the third sub-active portion 7133 and the second sub-active portion 712, and the third sub-active portion 7133 may be used to form the channel region of the first transistor T1. The first active portion 71 may further include a fourth sub-active portion 714 and a fifth sub-active portion 715. The fourth sub-active portion 714 may be used to form the second pole of the second transistor T2. The fifth sub-active portion 715 may be connected between the fourth sub-active portion 714 and the first sub-active portion 711, and a partial structure of the fifth sub-active portion 715 may be used to form the channel region of the second transistor T2. The fifth sub-active portion 715 may include a fourth sub-active portion 7154, a fifth sub-active portion 7155, and a sixth sub-active portion 7156. The fourth sub-active portion 7154 is connected between the first sub-active portion 711 and the sixth sub-active portion 7156, the fifth sub-active portion 7155 is connected between the sixth sub-active portion 7156 and the fourth sub-active portion 714, and the sixth sub-active portion 7156 may be used to form the channel region of the second transistor T2. Among them, the orthographic projection of the second sub-active portion 712 on the substrate, the orthographic projection of the second sub-active portion 7132 on the substrate, the orthographic projection of the third sub-active portion 7133 on the substrate, the orthographic projection of the first sub-active portion 7131 on the substrate, the orthographic projection of the first sub-active portion 711 on the substrate, the orthographic projection of the fourth sub-active portion 7154 on the substrate, the orthographic projection of the sixth sub-active portion 7156 on the substrate, the orthographic projection of the fifth sub-active portion 7155 on the substrate, and the orthographic projection of the fourth sub-active portion 714 on the substrate may be sequentially connected in the second direction Y. The second active layer may be formed of an oxide semiconductor, such as indium gallium zinc oxide.

[0119] It should be noted that considering process factors, there may be an error range for the boundaries in the figures of this exemplary embodiment.

[0120] As shown Figure 20 , 25 , 31, and 34, the third conductive layer may include: a second sub-reset signal line 2Re1 and a second sub-gate driving signal line 2G1. The second sub-reset signal line 2Re1 is used to provide Figure 1 the first reset signal terminal in Figure 1 , and the second sub-gate driving signal line 2G1 is used to provide

[0121] As shown Figure 20 , 26 , 32, the fourth conductive layer may include: a first power supply line VDD1, a first initial signal line Vinit1, a second initial signal line Vinit2, a conductive part 41, a third conductive part 43, a conductive part 42, and a conductive part 44. Among them, the first power supply line VDD1 is used to provide Figure 1 the first power supply terminal in Figure 1 , the first initial signal line Vinit1 is used to provide Figure 1The second initial signal terminal in. The conductive portion 41 can be connected to the first active layer on one side of the active portion 64 through the via hole H4 to connect the first pole of the fourth transistor. The third conductive portion 43 can be connected to the conductive portion 11 through the via hole H5 and connected to the first sub-active portion 711 through the via hole H1 to connect the gate of the driving transistor and the first pole of the first transistor, and the gate of the driving transistor and the first pole of the second transistor. The conductive portion 42 can be connected to the first active layer on one side of the active portion 66 through the via hole H6 and connected to the fourth sub-active portion 714 through the via hole H3 to connect the first pole of the sixth transistor and the second pole of the second transistor. The conductive portion 44 can be connected to the first active layer on one side of the active portion 66 through the via hole H9 to connect the second pole of the sixth transistor. The first power supply line VDD1 can be connected to the first active layer on one side of the active portion 65 through the via hole H7 to connect the first pole of the fifth transistor and the first power supply terminal. The first power supply line VDD1 can also be connected to the conductive portion 21 through the via hole H8 to connect the capacitor C and the first power supply terminal. The first initial signal line Vinit1 can include a fourth conductive portion Vinit14. The fourth conductive portion Vinit14 can be connected to the second sub-active portion 712 through the via hole H2 to connect the second pole of the first transistor and the second initial signal terminal. The second initial signal line Vinit2 can be connected to the first active layer on one side of the active portion 67 through the via hole H10 to connect the second initial signal terminal and the second pole of the seventh transistor.

[0122] It should be noted that the orthographic projection of the first via hole H1 on the substrate can be slightly smaller than the orthographic projection of the first sub-active portion 711 on the substrate, and the orthographic projection of the second via hole H2 on the substrate can be slightly smaller than the orthographic projection of the second sub-active portion 712 on the substrate. As Figure 24As shown, the first sub-active part 711 may include edges 7111 and 7112 opposite to each other in the second direction Y. The second sub-active part 712 may include an edge 7121 on a side close to the first sub-active part 711. The fourth sub-active part 714 may include an edge 7141 on a side facing the first sub-active part 711. Among them, the orthographic projection of the edge 7111 on the substrate may at least partially coincide with the orthographic projection of the first conductive part 1Re11 on the substrate; the orthographic projection of the edge 7112 on the substrate may at least partially coincide with the orthographic projection of the fifth conductive part 1G15 on the substrate; the orthographic projection of the edge 7121 on the substrate may at least partially coincide with the orthographic projection of the first conductive part 1Re11 on the substrate; the orthographic projection of the edge 7141 on the substrate may at least partially coincide with the orthographic projection of the fifth conductive part 1G15 on the substrate. The orthographic projection of the first conductive part 1Re11 on the substrate may also at least partially coincide with the orthographic projection of the first via hole H1 on the substrate, and the orthographic projection of the first conductive part 1Re11 on the substrate may also at least partially coincide with the orthographic projection of the second via hole H2 on the substrate. In other exemplary embodiments, the orthographic projection of the fifth conductive part 1G15 on the substrate may also at least partially coincide with the orthographic projection of the first via hole H1 on the substrate, and the orthographic projection of the fifth conductive part 1G15 on the substrate may also at least partially coincide with the orthographic projection of the second via hole H3 on the substrate.

[0123] As Figure 20 , 27 shown, the fifth conductive layer may include: a second power supply line VDD2, a data line Da, and a connection part 51. Among them, the second power supply line VDD2 is used to provide Figure 1 the first power supply terminal in Figure 1 , and the data line Da is used to provide Figure 1 the data signal terminal in Figure 20 . The second power supply line VDD2 may be connected to the first power supply line VDD1 through a via hole H11. The data line Da may be connected to the connection part 41 through a via hole H12 to connect the first pole of the fourth transistor and the data signal terminal. The connection part 51 may be connected to the conductive part 44 through a via hole. The connection part 51 may be used to connect Figure 1 the anode of the light-emitting unit in Figure 20 . As

[0124] shown, the orthographic projection of the first power supply line VDD1 on the substrate may be located between the orthographic projection of the data line Da on the substrate and the orthographic projection of the conductive part 11 on the substrate. The first power supply line VDD1 may shield the interference of the data line Da to the conductive part 11.

[0124] As Figure 35 shown, for Figure 32Partial cross-sectional view along the dashed line B. Among them, the display panel may further include a first buffer layer 82, a first gate insulating layer 83, a second gate insulating layer 84, a first dielectric layer 85, a second buffer layer 86, a third gate insulating layer 87, and a second dielectric layer 88. Among them, the substrate 81, the first buffer layer 82, the first active layer, the first gate insulating layer 83, the first conductive layer, the second gate insulating layer 84, the second conductive layer, the first dielectric layer 85, the second buffer layer 86, the second active layer, the third gate insulating layer 87, the third conductive layer, the second dielectric layer 88, and the fourth conductive layer are stacked in sequence. The first buffer layer and the second buffer layer may include at least one of a silicon oxide layer and a silicon nitride layer. The first gate insulating layer, the second gate insulating layer, and the third gate insulating layer may be silicon oxide layers. The first dielectric layer and the second dielectric layer may be silicon nitride layers. The materials of the fourth conductive layer and the fifth conductive layer may include metal materials, such as one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminate, etc., or may be a titanium / aluminum / titanium laminate. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminate, etc. The substrate 81 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.

[0125] In this exemplary embodiment, as Figure 35 shown, the positive projection of the first conductive portion 1Re11 on the substrate may cover the positive projection of the third sub-active portion 713 on the substrate. The positive projection of the third gate insulating layer 87 on the substrate may cover the positive projection of the first active portion 71 on the substrate. The positive projection of the second conductive portion 2Re12 on the substrate may cover the positive projection of the first transistor channel region (the third sub-active portion 7133) on the substrate. The positive projection of the second conductive portion on the substrate is located between the positive projection of the first sub-active portion on the substrate and the positive projection of the second sub-active portion on the substrate, that is, the positive projection of the second conductive portion 2Re12 on the substrate may not intersect with the positive projection of the first sub-active portion 7131 on the substrate, and the positive projection of the second conductive portion 2Re12 on the substrate may not intersect with the positive projection of the second sub-active portion 7132 on the substrate.

[0126] When the conductorization process is performed on the second active layer in this exemplary embodiment, since the third gate insulating layer 87 is covered on the second active layer, and the third gate insulating layer 87 has a blocking effect on the diffusion of conductorization ions, the diffusion amount of the conductorization ions in the lateral direction is extremely small or even zero. Furthermore, the size of the channel region formed by using the second conductive portion 2Re12 as a mask in its length direction (i.e., the second direction Y) is the same as or extremely close to the size of the second conductive portion 2Re12 in the same direction. Thus, the display panel can form the first transistor T1 with a larger channel size under the action of the second conductive portion 2Re12 with a limited size. At the same time, since the third gate insulating layer 87 has a blocking effect on the diffusion of conductorization ions, the ion doping concentration of the first sub-active portion 7131 and the second sub-active portion 7132 not covered by the second conductive portion 2Re12 is relatively low, so the on-current of the first transistor T1 is small. In addition, in this exemplary embodiment, the orthographic projection of the first conductive portion 1Re11 on the substrate covers the orthographic projection of the third sub-active portion 713 on the substrate. Under the action of the conduction voltage of the first conductive portion 1Re11, the sheet resistance of the first sub-active portion 7131 and the second sub-active portion 7132 not covered by the second conductive portion 2Re12 decreases, so that a larger on-current of the first transistor T1 can be ensured. In addition, since the first sub-active portion 7131 and the second sub-active portion 7132 not covered by the second conductive portion 2Re12 have a relatively large sheet resistance, the first transistor has a small off-current.

[0127] In this exemplary embodiment, the sheet resistance of the first sub-active portion 7131 may be equal to the sheet resistance of the second sub-active portion 7132. The sheet resistance of the first sub-active portion 7131 may be less than the sheet resistance of the first sub-active portion 711. The sheet resistance of the first sub-active portion 7131 may be less than the sheet resistance of the second sub-active portion 712. The sheet resistance of the first sub-active portion may be 2000 - 20000 Ω / sq. For example, 2000 Ω / sq, 5000 Ω / sq, 10000 Ω / sq, 20000 Ω / sq. The sheet resistance of the first sub-active portion may be 500 - 2000 Ω / sq. For example, 500 Ω / sq, 1000 Ω / sq, 2000 Ω / sq. The sheet resistance of the second sub-active portion may be 500 - 2000 Ω / sq. For example, 500 Ω / sq, 1000 Ω / sq, 2000 Ω / sq. It should be understood that due to process errors, the sheet resistance of the first sub-active portion 7131 may be slightly greater than or slightly less than the sheet resistance of the second sub-active portion 7132, and the difference between the sheet resistance of the first sub-active portion and the sheet resistance of the second sub-active portion is less than a preset value. The preset value may be 0 - 100 Ω / sq. For example, the preset value may be 0, 50, 100.

[0128] In this exemplary embodiment, asFigure 35 As shown, the first sub-active part 711 can be shared as the first pole of the second transistor T2. The positive projection of the fifth conductive part 1G15 on the substrate can cover the positive projection of the fifth sub-active part 715 on the substrate. The positive projection of the sixth conductive part 2G16 on the substrate can cover the positive projection of the channel region (the sixth sub-active part 7156) of the second transistor T2 on the substrate. The positive projection of the sixth conductive part on the substrate is located between the positive projection of the fifth sub-active part on the substrate and the positive projection of the fourth sub-active part on the substrate, that is, the positive projection of the sixth conductive part 2G16 on the substrate does not intersect with the positive projection of the fifth sub-active part 7155 on the substrate, and the positive projection of the sixth conductive part 2G16 on the substrate does not intersect with the positive projection of the fourth sub-active part 7154 on the substrate.

[0129] When the conductorization process is performed on the second active layer in this exemplary embodiment, since the third gate insulating layer 87 is covered on the second active layer, and the third gate insulating layer 87 has a blocking effect on the diffusion of conductorization ions, the diffusion amount of the conductorization ions in the lateral direction is extremely small or even zero. Furthermore, the size of the channel region formed with the sixth conductive part 2G16 as a mask in its length direction (i.e., the second direction Y) is the same as or extremely close to the size of the sixth conductive part 2G16 in the same direction. Thus, the display panel can form the second transistor T2 with a larger channel size under the action of the sixth conductive part 2G16 with a limited size. At the same time, since the third gate insulating layer 87 has a blocking effect on the diffusion of conductorization ions, the ion doping concentration of the fourth sub-active part 7154 and the fifth sub-active part 7155 not covered by the sixth conductive part 2G16 is relatively low, so the on-current of the second transistor T2 is small. In addition, in this exemplary embodiment, the positive projection of the fifth conductive part 1G15 on the substrate covers the positive projection of the fifth sub-active part 715 on the substrate. Under the action of the conduction voltage of the fifth conductive part 1G15, the sheet resistance of the fourth sub-active part 7154 and the fifth sub-active part 7155 not covered by the sixth conductive part 2G16 decreases, so that a larger on-current of the second transistor T2 can be ensured. In addition, since the fourth sub-active part 7154 and the fifth sub-active part 7155 not covered by the sixth conductive part 2G16 have a larger sheet resistance, the second transistor T2 has a smaller off-current.

[0130] In this exemplary embodiment, the sheet resistance of the fourth sub-active part 7154 may be equal to that of the fifth sub-active part 7155, the sheet resistance of the fourth sub-active part 7154 may be less than that of the fourth sub-active part 714, and the sheet resistance of the fourth sub-active part 7154 may be less than that of the first sub-active part 711. The sheet resistance of the fourth sub-active part 7154 is 2000 to 20000 Ω / sq. For example, 2000 Ω / sq, 5000 Ω / sq, 10000 Ω / sq, 20000 Ω / sq. The sheet resistance of the fourth sub-active part 714 may be 500 to 2000 Ω / sq. For example, 500 Ω / sq, 1000 Ω / sq, 2000 Ω / sq. It should be understood that due to process errors, the sheet resistance of the fourth sub-active part 7154 may be slightly greater than or slightly less than that of the fifth sub-active part 7155, and the difference between the sheet resistance of the fourth sub-active part 7154 and that of the fifth sub-active part 7155 is less than a preset value, which may be 0 - 100 Ω / sq. For example, the preset value may be 0, 50, 100.

[0131] As Figure 36 shown, it is a schematic structural diagram of a first transistor in another exemplary embodiment of the display panel of the present disclosure. And Figure 35Different from the first transistor structure, the first active part may further include a sixth sub-active part 716. The sixth sub-active part 716 may be located between the first sub-active part 711 and the third sub-active part 713. The orthographic projection of the sixth sub-active part 716 on the substrate may be located between the orthographic projection of the first sub-active part 711 on the substrate and the orthographic projection of the first conductive part 1Re11 on the substrate, that is, the orthographic projection of the sixth sub-active part 716 on the substrate does not intersect with the orthographic projection of the first conductive part 1Re11 on the substrate. Wherein, the sheet resistance of the sixth sub-active part may be 2000 to 20000 Ω / sq. In addition, the first active part may further include a seventh sub-active part 717. The seventh sub-active part 717 may be located between the second sub-active part 712 and the third sub-active part 713. The orthographic projection of the seventh sub-active part 717 on the substrate may be located between the orthographic projection of the second sub-active part 712 on the substrate and the orthographic projection of the first conductive part 1Re11 on the substrate, that is, the orthographic projection of the seventh sub-active part 717 on the substrate does not intersect with the orthographic projection of the first conductive part 1Re11 on the substrate. Wherein, the sheet resistance of the seventh sub-active part 717 may be 2000 to 20000 Ω / sq. In addition, in order to ensure that the first transistor has a large on-current, the sizes of the sixth sub-active part 716 and the seventh sub-active part 717 in the length direction of the first transistor channel region cannot be too large. In this exemplary embodiment, the total length of the sixth sub-active part 716 and the seventh sub-active part 717 in the length direction of the first transistor channel region may be S1, and the total length of the sixth sub-active part 716, the seventh sub-active part 717, the first sub-active part, and the second sub-active part in the length direction of the first transistor channel region may be S2. S2 / (S1 + S2) may be greater than or equal to 80%, where the length direction of the first transistor channel region is the conductive direction of the first transistor channel region. The second transistor in the display panel may have the same structure as the first transistor.

[0132] According to one aspect of the present disclosure, a display device is provided. The display device includes the above-mentioned display panel. The display device may be a display device of a mobile phone, a tablet computer, or a television.

[0133] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily think of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0134] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only defined by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a first transistor, and the display panel includes: substrate substrate; A second conductive layer, located on one side of the base substrate, the second conductive layer includes a first conductive portion, and the first conductive portion is used to form a first gate of the first transistor; A second active layer, located on a side of the second conductive layer away from the base substrate, the second active layer comprising a first active portion, the first active portion comprising a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion; The first sub-active portion is used to form a first electrode of the first transistor, the second sub-active portion is used to form a second electrode of the first transistor, a part of the structure of the third sub-active portion is used to form a channel region of the first transistor, and the first conductive portion covers the third sub-active portion in an orthographic projection on the substrate; A third gate insulating layer is located on a side of the second active layer away from the base substrate, and the orthographic projection of the third gate insulating layer on the base substrate covers the orthographic projection of the first active portion on the base substrate; A third conductive layer is located on a side of the third gate insulating layer away from the substrate, the third conductive layer includes a second conductive portion, the second conductive portion is used to form a second gate of the first transistor, and the orthographic projection of the second conductive portion on the substrate covers the orthographic projection of the channel region of the first transistor on the substrate.

2. The display panel according to claim 1, wherein, The third sub-active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion, wherein the first sub-active portion is connected between the first sub-active portion and the third sub-active portion, the second sub-active portion is connected between the third sub-active portion and the second sub-active portion, and the third sub-active portion is used to form a channel region of the first transistor; The orthographic projection of the second conductive portion on the base substrate covers the orthographic projection of the third sub-active portion on the base substrate, and the orthographic projection of the second conductive portion on the base substrate is located between the orthographic projection of the first sub-active portion on the base substrate and the orthographic projection of the second sub-active portion on the base substrate.

3. The display panel according to claim 2, wherein, The difference between the block resistance of the first sub-active portion and the block resistance of the second sub-active portion is less than a preset value, and the preset value is 0-100Ω / sq. The block resistance of the first sub-active portion is less than the block resistance of the first sub-active portion, and the block resistance of the first sub-active portion is less than the block resistance of the second sub-active portion.

4. The display panel according to claim 2, wherein, The difference between the sheet resistance of the first sub-active portion and the sheet resistance of the second sub-active portion is less than a preset value, the preset value is 0-100Ω / sq, and the sheet resistance of the first sub-active portion is 2000-20000Ω / sq.

5. The display panel according to claim 2, wherein, The sheet resistance of the first sub-active portion is 500 to 2000 Ω / sq, and the sheet resistance of the second sub-active portion is 500 to 2000 Ω / sq.

6. The display panel according to claim 1, wherein, The display panel further includes: a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer comprising a third conductive portion and a fourth conductive portion; The third conductive part is connected to the first sub-active part through a first via hole, and the fourth conductive part is connected to the second sub-active part through a second via hole.

7. The display panel according to claim 6, wherein, The orthographic projection of the first via hole on the substrate is located on the orthographic projection of the first sub-active part on the substrate, and the orthographic projection of the second via hole on the substrate is located on the orthographic projection of the second sub-active part on the substrate; The area of the orthographic projection of the first via hole on the substrate is less than or equal to the area of the orthographic projection of the first sub-active part on the substrate; The area of the orthographic projection of the second via hole on the substrate is less than or equal to the area of the orthographic projection of the second sub-active part on the substrate.

8. The display panel according to claim 1, wherein, At least part of the edge of the orthographic projection of the first sub-active part on the substrate coincides with at least part of the orthographic projection of the first conductive part on the substrate; At least part of the edge of the orthographic projection of the second sub-active part on the substrate coincides with at least part of the orthographic projection of the first conductive part on the substrate.

9. The display panel according to claim 1, wherein, The first active part further includes: A sixth sub-active part, which is located between the first sub-active part and the third sub-active part, and the orthographic projection of the sixth sub-active part on the substrate is located between the orthographic projection of the first sub-active part on the substrate and the orthographic projection of the first conductive part on the substrate; The sheet resistance of the sixth sub-active part is 2000 - 20000 Ω / sq.

10. The display panel according to claim 1, wherein, The first transistor is an oxide transistor.

11. The display panel according to claim 10, wherein, The display panel further includes a pixel driving circuit, and the pixel driving circuit includes the first transistor; The pixel driving circuit further includes a driving transistor, a first pole of the first transistor is connected to the gate of the driving transistor, and a second pole is connected to a first initial signal terminal; The pixel driving circuit further includes a second transistor, a first pole of the second transistor is connected to the gate of the driving transistor, and a second pole is connected to the second pole of the driving transistor, and the second transistor is an oxide transistor.

12. The display panel according to claim 11, wherein, The first active part further includes: A fourth sub-active part for forming the second pole of the second transistor; A fifth sub-active part is connected between the fourth sub-active part and the first sub-active part, and a part of the structure of the fifth sub-active part is used to form the channel region of the second transistor; The first sub-active part is shared as the first pole of the second transistor; The second conductive layer further includes a fifth conductive part for forming the first gate of the second transistor, and the orthographic projection of the fifth conductive part on the substrate covers the orthographic projection of the fifth sub-active part on the substrate; The third conductive layer further includes a sixth conductive part for forming the second gate of the second transistor, and the orthographic projection of the sixth conductive part on the substrate covers the orthographic projection of the channel region of the second transistor on the substrate.

13. The display panel according to claim 12, wherein, The fifth sub-active portion includes a fourth sub-active portion, a fifth sub-active portion, and a sixth sub-active portion, wherein the fourth sub-active portion is connected between the first sub-active portion and the sixth sub-active portion, the fifth sub-active portion is connected between the sixth sub-active portion and the fourth sub-active portion, and the sixth sub-active portion is used to form a channel region of the second transistor; The orthographic projection of the sixth conductive portion on the substrate covers the orthographic projection of the sixth sub-active portion on the substrate, and the orthographic projection of the sixth conductive portion on the substrate is located between the orthographic projection of the fifth sub-active portion on the substrate and the orthographic projection of the fourth sub-active portion on the substrate.

14. The display panel according to claim 13, wherein, The difference between the block resistance of the fourth sub-active portion and the block resistance of the fifth sub-active portion is less than a preset value, and the preset value is 0-100Ω / sq. The block resistance of the fourth sub-active portion is less than the block resistance of the fourth sub-active portion, and the block resistance of the fourth sub-active portion is less than the block resistance of the first sub-active portion.

15. The display panel according to claim 13, wherein, The difference between the sheet resistance of the fourth sub-active portion and the sheet resistance of the fifth sub-active portion is less than a preset value, the preset value is 0-100Ω / sq, and the sheet resistance of the fourth sub-active portion is 2000-20000Ω / sq.

16. A method for manufacturing a display panel, wherein, The display panel includes a first transistor, and the display panel manufacturing method includes: Providing a substrate; Forming a second conductive layer on one side of the base substrate, the second conductive layer comprising a first conductive portion, the first conductive portion being used to form a first gate of the first transistor; forming a second active material layer on a side of the second conductive layer away from the base substrate, wherein the second active material layer comprises a first active material portion, wherein the first active material portion comprises a first sub-active material portion, a second sub-active material portion, and a third sub-active material portion connected between the first sub-active material portion and the second sub-active material portion; A partial structure of the third sub-active material portion is used to form a channel region of the first transistor, and an orthographic projection of the first conductive portion on the substrate covers an orthographic projection of the third sub-active material portion on the substrate; forming a third gate insulating layer on a side of the second active material layer away from the base substrate, wherein the orthographic projection of the third gate insulating layer on the base substrate covers the orthographic projection of the first active material portion on the base substrate; forming a third conductive layer on a side of the third gate insulating layer away from the base substrate, the third conductive layer comprising a second conductive portion, the second conductive portion being used to form a second gate of the first transistor, and an orthographic projection of the second conductive portion on the base substrate overlaps with an orthographic projection of the third sub-active material portion on the base substrate; The second active material layer is subjected to conductor processing by using the third conductive layer as a mask.

17. The method for manufacturing a display panel according to claim 16, wherein, The first transistor is an oxidation transistor, and the second active material layer is an oxide semiconductor.

18. The method for manufacturing a display panel according to claim 16, wherein, Conducting the second active material layer with the third conductive layer as a mask includes: Using a gaseous chemical deposition process, forming a second dielectric layer on a side of the third conductive layer away from the substrate; Among them, conductive ions are generated during the formation of the second dielectric layer, and the conductive ions can conductivize the second active material layer.

19. The method for manufacturing a display panel according to claim 18, wherein, The material of the second dielectric layer is silicon nitride, and the conductive ions are hydrogen ions.

20. The method for manufacturing a display panel according to claim 18, wherein, The method for manufacturing the display panel further includes: forming a first via hole and a second via hole penetrating through the third gate insulating layer and the second dielectric layer through a dry etching gas, wherein the positive projection of the first via hole on the substrate is located on the positive projection of the first sub-active material portion on the substrate, and the positive projection of the second via hole on the substrate is located on the positive projection of the second sub-active material portion on the substrate. Among them, the dry etching gas can generate conductive ions during the dry etching process, and the conductive ions can conductivize the second active material layer; forming a fourth conductive layer on a side of the second dielectric layer facing away from the substrate, the fourth conductive layer including a third conductive portion and a fourth conductive portion; the third conductive portion is connected to the first sub-active material portion through the first via hole, and the fourth conductive portion is connected to the second sub-active material portion through the second via hole.

21. The method for manufacturing a display panel according to claim 20, wherein, The area of the positive projection of the first via hole on the substrate is less than or equal to the area of the positive projection of the first sub-active material portion on the substrate; The area of the positive projection of the second via hole on the substrate is less than or equal to the area of the positive projection of the second sub-active material portion on the substrate.

22. The method for manufacturing a display panel according to claim 16, wherein, At least a part of the edge of the positive projection of the first sub-active material portion on the substrate coincides with at least a part of the positive projection of the first conductive portion on the substrate; At least a part of the edge of the positive projection of the second sub-active material portion on the substrate coincides with at least a part of the positive projection of the first conductive portion on the substrate.

23. The method for manufacturing a display panel according to claim 16, wherein, Conductivizing the second active material layer with the third conductive layer as a mask, including: injecting conductive ions into the second active material layer through an ion implantation process.

24. The method for manufacturing a display panel according to claim 16, wherein, The third sub-active material portion includes a first sub-active material portion, a second sub-active material portion, and a third sub-active material portion. The first sub-active material portion is connected between the first sub-active material portion and the third sub-active material portion, and the second sub-active material portion is connected between the third sub-active material portion and the second sub-active material portion; The positive projection of the second conductive portion on the substrate covers the positive projection of the third sub-active material portion on the substrate.

25. A display device, wherein, including the display panel according to any one of claims 1-15.

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