Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a first display area and a second display area, wherein the first display area is located around the second display area. The first display area includes a first light-emitting element, a first pixel circuit, a second pixel circuit, and a third pixel circuit, wherein the first pixel circuit is connected to the first light-emitting element. The second display area includes a second light-emitting element, the second pixel circuit is connected to the second light-emitting element, and the third pixel circuit is a dummy pixel circuit. The display substrate also includes a first data line and a second data line, wherein the first data line is configured to be connected to the first pixel circuit, and the second data line is configured to be connected to at least the second pixel circuit. At least a portion of the third pixel circuit that overlaps with the second data line is insulated from the second data line in a direction perpendicular to the base substrate. By reducing the number of pixel circuits connected to the second data line to reduce the load, the phenomenon of dark vertical stripes in the second display area can be alleviated.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] As people continue to pursue higher visual quality in display products, narrow bezels and even full-screen displays are becoming a new trend in the development of organic light-emitting diode (OLED) displays. The front camera is crucial to the design of full-screen displays. To achieve a higher screen-to-body ratio, display products with notches and punch-hole displays have emerged. These full-screen form factors increase the screen-to-body ratio at the expense of the phone's appearance. Therefore, the design of an under-screen camera can maintain the phone's appearance while increasing the screen-to-body ratio. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate and a display device.

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising a base substrate and a plurality of data lines located on the base substrate. The display substrate comprises a first display area and a second display area, wherein the first display area is located around the second display area, the first display area comprises a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits, wherein the plurality of first pixel circuits are connected to the plurality of first light-emitting elements in a one-to-one correspondence, the second display area comprises a plurality of second light-emitting elements, the plurality of second pixel circuits are connected to the plurality of second light-emitting elements in a one-to-one correspondence, and the third pixel circuits are dummy pixel circuits; a plurality of data lines do not pass through the second display area, wherein the plurality of data lines comprise a plurality of first data lines and a plurality of second data lines, each first data line is configured to be connected to the first pixel circuit, and each second data line is configured to be connected to at least the second pixel circuit. In a direction perpendicular to the base substrate, portions of the plurality of third pixel circuits overlap with the plurality of second data lines, and at least portions of the third pixel circuits that overlap with the second data lines are insulated from the second data lines.

[0005] For example, according to an embodiment of the present disclosure, each of the third pixel circuits overlapping the second data line is insulated from the second data line.

[0006] For example, according to an embodiment of the present disclosure, each of the first data lines extends along a first direction, and the first data lines among the multiple first data lines whose extended lines do not pass through the second display area are configured to transmit data signals to M first pixel circuits, and each of the second data lines is configured to transmit signals to N pixel circuits, and M≥N, and the N pixel circuits include at least the second pixel circuit.

[0007] For example, according to an embodiment of the present disclosure, the second data line includes a first sub-data line and a second sub-data line extending along the first direction, and a switching line connecting the first sub-data line and the second sub-data line; the first sub-data line, the second sub-data line and the first data line are arranged on the same layer, the first sub-data line is configured to be connected to the first pixel circuit, and the second sub-data line is configured to be connected to the second pixel circuit.

[0008] For example, according to an embodiment of the present disclosure, the display substrate further includes: a plurality of traces extending along the first direction and not passing through the second display area; the plurality of traces are disposed on the same layer as the plurality of first data lines, with at least one data line disposed between two adjacent traces; and each of the traces overlaps only with the third pixel circuit in a direction perpendicular to the base substrate.

[0009] For example, according to an embodiment of the present disclosure, the plurality of routing lines include a plurality of first routing lines, the number of the first routing lines being the same as the number of the second sub-data lines, at least a portion of a first routing line and a second sub-data line being approximately located on the same straight line, and a gap being provided between the two; and a transfer area including the plurality of transfer lines. The transfer area includes a first transfer area located on one side of the second display area in the first direction, the transfer lines in the first transfer area extending along a second direction intersecting the first direction and being located on a different layer from the first data lines, the gap being located on a side of the first transfer area away from the second display area, and the first routing line overlapping at least a portion of the third pixel circuit.

[0010] For example, according to an embodiment of the present disclosure, the first routing line and the second sub-data line are configured to transmit different electrical signals.

[0011] For example, according to an embodiment of the present disclosure, the first trace is configured to transmit a power supply voltage signal.

[0012] For example, according to an embodiment of the present disclosure, the transition area further includes a second transition area located on the other side of the second display area in the first direction, and the second transition area is located in a non-display area outside the first display area and the second display area.

[0013] For example, according to an embodiment of the present disclosure, each of the transfer lines in the second transfer area includes a first transfer line and a second transfer line that are connected to each other and arranged in different layers, and one of the first transfer line and the second transfer line is connected to the second sub-data line and is located at a different layer from the second sub-data line.

[0014] For example, according to an embodiment of the present disclosure, in each of the second data lines, two first sub-data lines are connected to the same second sub-data line, the two first sub-data lines are respectively located on both sides of the second display area in the first direction, and at least part of the two first sub-data lines are approximately located on the same straight line.

[0015] For example, according to an embodiment of the present disclosure, a second sub-data line extends along the first direction and overlaps with an orthographic projection of the routing line on a straight line extending along the first direction.

[0016] For example, according to an embodiment of the present disclosure, the adapter line is located in a non-display area outside the first display area and the second display area.

[0017] For example, according to an embodiment of the present disclosure, each of the transfer lines includes a first transfer line and a second transfer line that are connected to each other and arranged in different layers, and one of the first transfer line and the second transfer line is connected to the second sub-data line and is located in a different layer from the second sub-data line.

[0018] For example, according to an embodiment of the present disclosure, the length of the second sub-data line is not less than the length of the first data lines whose extended lines do not pass through the second display area.

[0019] For example, according to an embodiment of the present disclosure, the first sub-data line and a first data line are respectively located on both sides of the second display area in the first direction, and are approximately located on the same straight line, and each first sub-data line and the first data line approximately located on the same straight line are configured to transmit the same data signal.

[0020] For example, according to an embodiment of the present disclosure, the other of the first switching line and the second switching line extends along a second direction intersecting with the first direction, and is located in the same layer as the second sub-data line.

[0021] For example, according to an embodiment of the present disclosure, the second data line extends along the first direction, and the second data line is configured to be connected only to the second pixel circuit.

[0022] For example, according to an embodiment of the present disclosure, the plurality of pixel circuits included in the first display area are arrayed along the first direction and the second direction, and the plurality of second pixel circuits are located on both sides of the second display area in the second direction.

[0023] For example, according to an embodiment of the present disclosure, the pixel circuit column where the second pixel circuits arranged along the first direction are located includes the third pixel circuit, and the third pixel circuit in the pixel circuit column overlaps with the second data line.

[0024] For example, according to an embodiment of the present disclosure, the multiple third pixel circuits include multiple third pixel circuit columns extending along the first direction and arranged along the second direction, and at least part of the multiple third pixel circuit columns are located on at least one side of the second display area in the first direction.

[0025] For example, according to an embodiment of the present disclosure, the plurality of third pixel circuit columns further include portions located on both sides of the second display area in the second direction.

[0026] For example, according to an embodiment of the present disclosure, the pixel circuit includes a data writing transistor, which includes a first electrode, a second electrode and a gate. An insulating layer is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located. The first electrode of the data writing transistor in the first pixel circuit and the second pixel circuit is connected to the data line through a via located in the insulating layer. The first electrode of the data writing transistor in at least a portion of the third pixel circuit overlapping with the second data line is insulated from the second data line by the insulating layer.

[0027] At least one embodiment of the present disclosure provides a display substrate, comprising a base substrate, a plurality of pixel circuits located on the base substrate, and a plurality of data lines. The plurality of pixel circuits include a plurality of first-type pixel circuits and a plurality of second-type pixel circuits, wherein the first-type pixel circuits are electrically connected to the data lines, and the second-type pixel circuits are insulated from the data lines.

[0028] For example, according to an embodiment of the present disclosure, the first-type pixel circuit is electrically connected to the data line overlapping with the first-type pixel circuit, and the second-type pixel circuit is insulated from the data line overlapping with the second-type pixel circuit.

[0029] For example, according to an embodiment of the present disclosure, at least a portion of the first-type pixel circuit is configured to drive a light-emitting element connected thereto to emit light, and the second-type pixel circuit is a first dummy pixel circuit.

[0030] For example, according to an embodiment of the present disclosure, the first type of pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit and the light-emitting element connected thereto overlap in a direction perpendicular to the substrate, and the second pixel circuit and the light-emitting element connected thereto do not overlap in a direction perpendicular to the substrate; the first type of pixel circuit also includes a second dummy pixel circuit.

[0031] For example, according to an embodiment of the present disclosure, the second-type pixel circuits and some of the first-type pixel circuits are located in the same column.

[0032] For example, according to an embodiment of the present disclosure, the second-type pixel circuit and the second pixel circuit are located in the same column.

[0033] For example, according to an embodiment of the present disclosure, the pixel circuit includes a data writing transistor, which includes a first electrode, a second electrode and a gate. An insulating layer is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located. The first electrode of the data writing transistor of the first type pixel circuit is connected to the corresponding data line through a via located in the insulating layer; the first electrode of the data writing transistor of the second type pixel circuit is insulated from the data line by the insulating layer.

[0034] At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0036] Figure 1 A schematic diagram of a partial planar structure of a display substrate in a display device with an under-screen camera;

[0037] Figure 2 A schematic diagram of a partial planar structure of a display substrate provided according to an example of an embodiment of the present disclosure;

[0038] Figure 3 for Figure 2 A partial enlarged structural schematic diagram of a display substrate is shown;

[0039] Figure 4 A schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure;

[0040] Figure 5 for Figure 4 A partial enlarged structural schematic diagram of a display substrate is shown;

[0041] Figure 6 A schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure;

[0042] Figure 7 for Figures 2 to 6 The equivalent diagram of each pixel circuit in the display substrate is shown;

[0043] Figure 8 A schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, and a source-drain metal layer of a second pixel circuit provided according to an embodiment of the present disclosure;

[0044] Figure 9 A schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, a source / drain metal layer, and a second conductive layer of a second pixel circuit provided according to an embodiment of the present disclosure;

[0045] Figure 10 for Figure 8 A schematic diagram of a partial cross-sectional structure of the pixel circuit taken along line AA';

[0046] Figure 11 A schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, and a source-drain metal layer of a third pixel circuit provided according to an embodiment of the present disclosure;

[0047] Figure 12 for Figure 11 A schematic diagram of a partial cross-sectional structure of the pixel circuit taken along line BB';

[0048] Figure 13 for Figure 2 A schematic diagram of a display area of ​​a display substrate and a second data line is shown;

[0049] Figure 14 for Figure 13 An enlarged view of region E1 is shown;

[0050] Figure 15 for Figure 13 An enlarged view of region E2 is shown;

[0051] Figure 16 for Figure 13 An enlarged view of region E3 is shown;

[0052] Figure 17 for Figure 13 An enlarged view of region E4 is shown;

[0053] Figure 18 To include Figure 16 Part of the structure of the partial enlarged view shown; and

[0054] Figure 19 To include Figure 17 Part of the structure shown in the enlarged view. DETAILED DESCRIPTION

[0055] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0057] A full display camera (FDC) is a device with a front-facing camera located below the screen without affecting the display. When the front-facing camera is not in use, the screen above the camera can still display images normally. Externally, the under-screen camera has no camera hole, achieving a true full-screen display.

[0058] Figure 1 Schematic diagram of a partial planar structure of a display substrate in a display device with an under-screen camera. Figure 1 As shown, the display substrate includes a base substrate 10, which includes a first display area 11 for normal display and a second display area 12 for setting a camera. The first display area 11 can be located on at least one side of the second display area 12. For example, the first display area 11 surrounds the second display area 12, the second display area 12 is a light-transmitting display area, and the first display area 11 is an opaque display area used only for display.

[0059] Figure 1The first display area 11 in the display substrate shown includes a first light-emitting element and a first pixel circuit that drives the first light-emitting element to emit light, and the second display area 12 includes a second light-emitting element. The second pixel circuit that drives the second light-emitting element in the second display area 12 to emit light is located in the first display area to improve the light transmittance of the second display area 12, that is, the light transmittance of the second display area 12 is improved by separating the light-emitting element and the pixel circuit. For example, a plurality of second pixel circuits can be spaced apart and distributed between a plurality of first pixel circuits. For example, the second light-emitting element can be connected to the second pixel circuit through a transparent trace. For example, the second display area 12 can be a hole area in the entire display area where no pixel circuit is set. For example, the density of the light-emitting elements set in the first display area 11 and the second display area 12 can be the same or different.

[0060] like Figure 1 As shown, the display substrate includes a plurality of data lines 20 located on a base substrate 10. In a display device with an under-screen camera, the plurality of data lines are arranged in two ways: winding inside the second display area and winding outside the second display area. Due to the limitation of the space size of the second display area, Figure 1 The display substrate shown is designed according to a fully compressed pixel circuit scheme, employing a data line routing method outside the second display area 12. In this display substrate, the first display area includes a plurality of first pixel circuit columns and a plurality of second pixel circuit columns. The second pixel circuit columns, where the second pixel circuits are located, include, in addition to the second pixel circuits, dummy pixel circuits not connected to any light-emitting elements. The first display area also includes a plurality of dummy pixel circuit columns, with at least one first pixel circuit column disposed between two adjacent dummy pixel circuit columns. The fully compressed pixel circuit scheme refers to compressing the plurality of pixel circuit columns in the overall display area (including the first display area and the second display area) in the X direction (e.g., reducing the size of each pixel circuit in the X direction) to increase the number of pixel circuits arranged in the X direction without reducing the pixel density of the overall display area (including the first display area and the second display area). The newly added pixel circuit columns include a second pixel circuit column for connecting to the second light-emitting element in the second display area, and a dummy pixel circuit column not connected to any light-emitting element.

[0061] like Figure 1As shown, the plurality of data lines 20 include a data line 21 connected only to the first pixel circuit and a data line 22 connected to at least the second pixel circuit. The data line 21 is a data line extending along the Y direction. For example, each data line 20 can be driven by a single path, and some data lines 20 are disconnected at the edge of the second display area 12, that is, some data lines 20 include two data lines 22-1 located on the upper and lower sides of the second display area 12. These two data lines 22-1 are both connected to the first pixel circuit. These two data lines 22-1 can be electrically connected via a patch cord 22-3 and a data line 22-2 connected to the second pixel circuit, so that the two data lines 22-1 transmit the same data signal. Thus, the data line 22, for example, includes five parts, which are, in order, the data line 22-1, the patch cord 22-3, the data line 22-2, the patch cord 22-3, and the data line 22-1. The numbers of first pixel circuits connected to the two data lines 22-1 are a1 and a3, respectively. The numbers of second pixel circuits and dummy pixel circuits connected to data line 22-2 are a2 and (a4 + a5), respectively. That is, the number of pixel circuits connected to data line 22 is b, where b = a1 + a2 + a3 + a4 + a5. a1 to a5 represent the number of pixel circuits connected to the data lines at corresponding positions in the figure.

[0062] During research, the inventors of this application discovered that the extension of data line 21 does not pass through the second display area 12, and the number of pixel circuits connected to data line 21 is a (a=a1+a2+a3). In order to reduce the data loading of data line 22-2 connected to the second pixel circuit, the metal wire on which data line 22-2 is located is split into two parts at the side of adapter line 22-3 away from the second display area 12. The metal wire includes data line 22-2 and routing 30. A gap 23 is provided between data line 22-2 and routing 30 to achieve insulation between the two. Routing 30 is connected to a dummy pixel circuit. To avoid floating of routing 30, routing 30 can be connected to a power supply voltage signal (VDD). However, the number b of pixel circuits connected to the above-mentioned data line 22 is greater than the number a of pixel circuits connected to data line 21, which will cause the load on data line 22 to be too large. For example, when all data lines are input with the same signal at the same time (ET is turned on), dark vertical stripes are likely to appear at the position of the second display area, affecting the display quality of the display device.

[0063] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate and a plurality of data lines located on the base substrate. The display substrate includes a first display area and a second display area, the first display area being located around the second display area. The first display area includes a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits, wherein the plurality of first pixel circuits are connected one-to-one with the plurality of first light-emitting elements. The second display area includes a plurality of second light-emitting elements, a plurality of second pixel circuits are connected one-to-one with the plurality of second light-emitting elements, and the third pixel circuits are dummy pixel circuits. The plurality of data lines do not pass through the second display area. The plurality of data lines include a plurality of first data lines and a plurality of second data lines. Each first data line is configured to be connected only to the first pixel circuit, and each second data line is configured to be connected to at least the second pixel circuit. In a direction perpendicular to the base substrate, portions of the plurality of third pixel circuits overlap with the plurality of second data lines, and at least portions of the third pixel circuits that overlap with the second data lines are insulated from the second data lines. In the display substrate provided by the embodiment of the present disclosure, by setting at least a portion of the third pixel circuit overlapping with the second data line to be disconnected from the second data line, the number of pixel circuits connected to the second data line can be reduced to reduce the load, thereby alleviating the phenomenon of dark vertical stripes appearing in the second display area and improving the display quality of the display substrate.

[0064] The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0065] Figure 2 FIG1 is a schematic diagram of a partial planar structure of a display substrate provided according to an example of an embodiment of the present disclosure. Figure 3 for Figure 2 The partially enlarged structural diagram of the display substrate is shown in FIG. Figure 2 and Figure 3 As shown, the display substrate includes a base substrate 100 and a plurality of data lines 200 located on the base substrate 100. The display substrate includes a first display area 111 and a second display area 112, and the first display area 111 is located around the second display area 112. For example, the first display area 111 surrounds the second display area 112, that is, the second display area 112 can be surrounded by the first display area 111. Of course, the embodiments of the present disclosure are not limited thereto, and the second display area 112 can also be set at other positions. The setting position of the second display area 112 can be determined as needed. For example, the second display area 112 can be located at the top center of the entire display area (including the display area of ​​the first display area and the second display area), or at the upper left corner or the upper right corner of the entire display area. Figure 2It is schematically shown that the shape of the first display area 111 is rectangular and the shape of the second display area 112 is circular, but not limited to this. The shape of the second display area 112 can also be a regular shape such as a rectangle, an ellipse, or an irregular shape, and the shape of the first display area 111 can also be a regular shape such as a circle, a hexagon, or an irregular shape.

[0066] like Figure 2 and Figure 3 As shown, the first display area 110 includes a plurality of first light-emitting elements 111, a plurality of first pixel circuits 112, a plurality of second pixel circuits 113, and a plurality of third pixel circuits 114. The plurality of first pixel circuits 112 are connected to the plurality of first light-emitting elements 111 in a one-to-one correspondence to drive the plurality of first light-emitting elements 111 to emit light. The second display area 120 includes a plurality of second light-emitting elements 121, a plurality of second pixel circuits 113 are connected to the plurality of second light-emitting elements 121 in a one-to-one correspondence to drive the plurality of second light-emitting elements 121 to emit light, and the third pixel circuit 114 is a dummy pixel circuit. The above-mentioned dummy pixel circuit refers to a pixel circuit that is not connected to any light-emitting element. The second display area is only provided with transparent second light-emitting elements, and no non-transparent pixel circuits are provided. The second display area can be used as an under-screen camera area, which can have a high light transmittance to realize the camera function, and can also realize light emission by connecting to the pixel circuits in other areas without affecting the display function of the screen.

[0067] For example, along a direction perpendicular to the substrate 100, at least a portion of the first pixel circuit 112 overlaps with the first light-emitting element 111 connected thereto; and the second pixel circuit 113 does not overlap with the second light-emitting element 121 connected thereto. Alternatively, for example, along a direction perpendicular to the substrate 100, the average distance between the first pixel circuit 112 and the first light-emitting element 111 connected thereto is less than the average distance between the second pixel circuit 113 and the second light-emitting element 121 connected thereto. The average distance is, for example, the average distance between the driving transistors of a column of pixel circuits and the centers of the light-emitting elements connected thereto. For example, the second pixel circuit 113 can be connected to the corresponding second light-emitting element 121 via a transparent trace 400; neither the second pixel circuit 113 nor the third pixel circuit 114 overlaps with the light-emitting elements. For example, the second pixel circuit 113 can be located only on two sides of the second display area 120 along the X direction, while the first pixel circuit 112 includes both portions located on both sides of the second display area 120 along the X direction and portions located on both sides of the second display area 120 along the Y direction.

[0068] For example, the pixel circuit column where the second pixel circuit 113 is arranged along the first direction includes the third pixel circuit 114, and the third pixel circuit 114 in the pixel circuit column overlaps or is electrically connected to the second data line 220. For example, the pixel circuit column where the second pixel circuit 113 is located (for example, a plurality of pixel circuits arranged along the Y direction constitutes a pixel circuit column) includes, in addition to the second pixel circuit 113, the third pixel circuit 114. For example, to ensure uniformity of the pixel circuits, the number of pixel circuits included in the pixel circuit column where the second pixel circuit 113 is located can be substantially the same as the number of pixel circuits included in the pixel circuit column where the first pixel circuit 112 is located (excluding the pixel circuit columns where the data lines connected to the pixel circuit columns pass through the second display area 120). However, the pixel circuit column where the first pixel circuit 112 is located only includes the first pixel circuit 112, while the pixel circuit column where the second pixel circuit 113 is located includes the second pixel circuit 113 and the third pixel circuit 114. For example, at least one first pixel circuit column can be provided between two adjacent pixel circuit columns where second pixel circuits are located.

[0069] For example, the first display area 110 includes a plurality of pixel circuits arranged in an array along the first direction and the second direction, and the plurality of second pixel circuits 113 are located on both sides of the second display area 120 in the second direction.

[0070] For example, the display substrate further includes a plurality of third pixel circuit columns ( Figure 2 and Figure 3 (Not shown, each third pixel circuit column includes only third pixel circuits, and at least one first pixel circuit column is disposed between adjacent third pixel circuit columns.) For example, the third pixel circuit columns include portions distributed on both sides of the second display area 120 along the X direction, and the third pixel circuit columns may also be distributed on another portion on both sides of the second display area 120 along the Y direction.

[0071] like Figure 2 and Figure 3 As shown, the multiple data lines 200 do not pass through the second display area 120 to prevent affecting the transmittance of the second display area 120. In a display device with an under-screen camera, the multiple data lines are arranged in two ways: winding within the second display area and winding outside the second display area. Due to the limited space size of the second display area, the display substrate provided in the embodiment of the present disclosure is designed according to a fully compressed pixel circuit solution, and the data lines are arranged by winding the data lines outside the second display area 120. The multiple data lines 200 include multiple first data lines 210 and multiple second data lines 220. Each first data line 210 is configured to be connected only to the first pixel circuit 112, and each second data line 220 is configured to be connected to at least the second pixel circuit 113.

[0072] For example, Figure 2 and Figure 3 As shown, among the plurality of second data lines 220 located on both sides of the second display area 120 in the X direction, a plurality of first data lines 210 may be arranged between adjacent second data lines 220. For example, 2 to 10 ( Figure 3 Two first data lines are schematically shown. This is not limited in the present disclosure and can be configured based on actual product requirements. For example, the plurality of second data lines 220 located on both sides of the second display area 120 in the X direction can be evenly distributed, but the present invention is not limited thereto. For example, depending on wiring requirements, the second data lines can be unevenly distributed, and the number of first data lines provided between adjacent second data lines can be different.

[0073] like Figure 2 and Figure 3 As shown, along a direction perpendicular to the base substrate 100, portions of the plurality of third pixel circuits 114 overlap with the plurality of second data lines 220 (for example, the third pixel circuits overlapping and connected to the second data lines can be electrically connected through vias perpendicular to the substrate), and at least a portion of the third pixel circuits 114 overlapping with the second data lines 220 are insulated from the second data lines 220 (for example, compared to normal pixel circuits, at least a portion of the vias used to electrically connect the pixel circuits to the data lines do not have vias, but are isolated by an insulating layer, so that the pixel circuits cannot be electrically connected to the data lines to achieve the function of the pixel circuits). Figure 3 A black dot is provided between the data line 200 and the pixel circuit overlapping therewith, indicating that the two are connected; no black dot is provided between the data line 200 and the pixel circuit overlapping therewith, indicating that the two are insulated, ie, not connected.

[0074] In the display substrate provided by the embodiments of the present disclosure, by isolating at least a portion of the third pixel circuit that overlaps the second data line from the second data line, the number of pixel circuits connected to the second data line can be reduced, thereby lowering the load. Consequently, when all data lines simultaneously input the same signal (ET lighting), the phenomenon of dark vertical stripes appearing in the second display area can be alleviated, thereby improving the display quality of the display substrate. Furthermore, by reducing the number of pixel circuits connected to the second data line to lower the load, the burden on the driver IC can be reduced when each data line inputs a corresponding data signal (module lighting).

[0075] For example, Figure 2 and Figure 3 As shown, each third pixel circuit 114 overlapping with the second data line 220 is insulated from the second data line 220, that is, all third pixel circuits 114 overlapping with the second data line 220 are not connected to the second data line 220, and the pixel circuits connected to the second data line 220 are all pixel circuits configured to drive the light-emitting element to emit light, thereby greatly reducing the number of pixel circuits connected to the second data line, and further reducing the load of the second data line.

[0076] For example, Figure 2 and Figure 3 As shown, each first data line 210 extends along a first direction. For example, the first direction is schematically shown in the figure as the Y direction, but it is not limited thereto and may also be the X direction shown in the figure. Among the multiple first data lines, the first data line 210 whose extension line does not pass through the second display area 120 is configured to transmit data signals to M first pixel circuits 112. For example, the first data line 210 may run through the first display area 110. Each second data line 220 is configured to transmit signals to N pixel circuits, and M≥N, and the N pixel circuits include at least a second pixel circuit. The N pixel circuits here refer to pixel circuits connected to the second data line 220, including the second pixel circuit connected to the second sub-data line described later and the first pixel circuit connected to the first sub-data line, or only include the second pixel circuit.

[0077] For example, in Figure 2 and Figure 3 In the example shown, the first data lines 210 only include data lines located on both sides of the second display area 120 in the X direction. Therefore, when the second data lines 220 are not connected to dummy pixel circuits, the number N of pixel circuits connected to the second data lines 220 is not greater than the number M of pixel circuits connected to the first data lines 210. For example, the number N of pixel circuits connected to the second data lines 220 is equal to the number M of first pixel circuits 111 connected to the first data lines 210.

[0078] For example, Figure 2 and Figure 3 As shown, each second data line 220 includes a first sub-data line 221 and a second sub-data line 222 extending along a first direction, and a switching line 223 connecting the first sub-data line 221 and the second sub-data line 222 .

[0079] For example, Figure 2 and Figure 3 As shown, the first sub-data line 221 , the second sub-data line 222 and the first data line 210 are arranged in the same layer, the first sub-data line 221 is configured to be connected to the first pixel circuit 112 , and the second sub-data line 222 is configured to be connected to the second pixel circuit 113 .

[0080] For example, the first sub-data line 221 included in the second data line 220 is a data line extending to the edge of the second display area 120 . Figure 2 and Figure 3In the example shown, the data line 200 connected to the first pixel circuits 112 located on both sides of the second display area 120 in the X direction is a first data line 210, the data line 200 connected to the first pixel circuits 112 located on both sides of the second display area 120 in the Y direction is a first sub-data line 221 in the second data line 220, and the data line 200 connected to the second pixel circuit 113 is a second sub-data line 222 in the second data line 220.

[0081] For example, Figure 2 and Figure 3 It is schematically shown that the first sub-data line 221 in each second data line 220 includes two parts distributed on both sides of the second display area 120 in the Y direction, but is not limited to this. The first sub-data line included in each second data line can also be located only on one side of the second display area. For example, the first pixel circuit and the first sub-data line are not arranged above the second display area (with the direction indicated by the arrow in the Y direction as upward).

[0082] For example, Figure 2 and Figure 3 As shown, the display substrate includes a transfer area 2230, a plurality of transfer lines 223 are arranged in the transfer area 2230, the transfer area 2230 includes a first transfer area 2231 located on one side of the second display area 120 in the first direction, and the transfer area 2230 also includes a second transfer area 2232 located on the other side of the second display area 120 in the first direction.

[0083] For example, Figure 2 and Figure 3 As shown, the adapter line 223 in the first adapter area 2231 extends along a second direction intersecting the first direction. The second direction is schematically shown as the X direction in the figure, but is not limited thereto, and the first direction and the second direction can be interchangeable. Figure 2 and Figure 3 It is schematically shown that the first direction and the second direction are perpendicular to each other, but the present invention is not limited thereto. The first direction and the second direction may not be perpendicular to each other.

[0084] For example, Figure 2 and Figure 3 As shown, the transfer line 223 in the first transfer area 2231 and the first sub-data line 221 are located in different layers. For example, the transfer line 223 may be located on a side of the first sub-data line 221 away from the base substrate 100 .

[0085] For example, Figure 2 and Figure 3As shown, the transfer line 223 in the second transfer area 2232 may include a first transfer line 223-1 and a second transfer line 223-2 that are connected to each other and arranged at different layers. One of the first transfer line 223-1 and the second transfer line 223-2 is connected to the second sub-data line 222 and is located at a different layer from the second sub-data line 222.

[0086] For example, Figure 3 As shown, each adapter line 223 includes two second adapter lines 223-2 and a first adapter line 223-1 connecting the two second adapter lines 223-2. One of the two second adapter lines 223-2 is connected to the second sub-data line 222, and the other of the two second adapter lines 223-2 is connected to the first sub-data line 221. For example, the first adapter line 223-1 extends along the second direction, and the second adapter line 223-2 extends along the first direction. For example, the first adapter line 223-1 can be substantially parallel to the adapter line 223 located in the first adapter area 2231.

[0087] For example, the second transfer line 223-2 and the second sub-data line 222 are located in different layers. For example, the first transfer line 223-1 and the second sub-data line 222 can be located in the same layer. Of course, the embodiments of the present disclosure are not limited thereto. The first transfer line and the second sub-data line can be located in different layers, and the second transfer line and the second sub-data line can be located in the same layer.

[0088] For example, Figure 2 and Figure 3 As shown, the second data line 220 includes five sequentially connected parts, such as a first sub-data line 221, a transition line 223, a second sub-data line 222, a transition line 223, and the first sub-data line 221. For example, the two first sub-data lines 221 are each connected to the same continuous second sub-data line 222 via two portions of the transition line 223. These two first sub-data lines 221 are located on opposite sides of the second display area 120 in the first direction, and the two first sub-data lines 221 are located on the same straight line. In the disclosed embodiments, "two data lines are located on the same straight line" means that the two data lines are substantially located on the same straight line, for example, more than 50% of the two data lines are located on the same straight line, or the maximum offset distance between the two data lines in the second direction is less than 5 microns, or 3 microns, etc.

[0089] For example, the data signal is loaded onto the first data line 210 located on the left and right sides of the second display area 120 through a circuit board (not shown) located on the lower side of the first display area 110, so as to be provided to the M first pixel circuits 112 connected to the first data line 210; the data signal is loaded onto the first sub-data line 221 located on the lower side of the second display area 120 through the circuit board located on the lower side of the first display area 110, so as to be provided to the first pixel circuit 112 connected to the first sub-data line 221; the data signal loaded onto the first sub-data line 221 located on the lower side of the second display area 120 is transmitted to the second sub-data line 222 through the first adapter line 223 to be provided to the second pixel circuit 113, and then the data signal is transmitted to the first sub-data line 221 located on the upper side of the second display area 120 through the second adapter line 223 to be provided to the first pixel circuit 112. Then, the first sub-data lines located on both sides of the second display area and the second sub-data lines connected to the two first sub-data lines all transmit the same data signal, and this data signal transmission method can be called single-channel driving.

[0090] like Figure 2 As shown, the numbers of first pixel circuits 112 connected to the two first sub-data lines 221 are a1 and a3 respectively, and the number of second pixel circuits 113 connected to the second sub-data line 222 is a2. Then, the number N of pixel circuits connected to the second data line 220 is equal to a1+a2+a3, and the number M of first pixel circuits 111 connected to the first data line 210 is also equal to a1+a2+a3, so M=N. Figure 2 The data lines in the display substrate shown are driven by a single path. By reducing the number of third pixel circuits connected to the second data line, the number of pixel circuits connected in series on the second data line can be reduced, achieving M = N. This reduces the load on the second data line to a certain extent, thereby alleviating the phenomenon of dark vertical stripes appearing in the second display area when all data lines are simultaneously fed the same signal (ET lighting). Furthermore, reducing the number of pixel circuits connected to the second data line to reduce the load also reduces the burden on the driver IC when each data line is fed a corresponding data signal (module lighting).

[0091] Since the second display area is provided with a first pixel circuit on both sides of the first direction, the second display area is provided with a first sub-data line connected to the first pixel circuit on both sides of the first direction. In single-channel driving, the two parts of the first sub-data lines need to be electrically connected through the second sub-data line and the two parts of the transfer line. Therefore, the transfer area includes a first transfer area and a second transfer area respectively located on both sides of the second display area.

[0092] For example, the second transfer area 2232 is located in the non-display area outside the first display area 110 and the second display area 112 to prevent the transfer wires in the second transfer area from affecting the display effect of the display substrate.

[0093] For example, the distance between two adjacent first transfer lines 223 - 1 in the second transfer area 2232 may be smaller than the distance between two adjacent transfer lines 223 in the first transfer area 2231 , so as to minimize the size of the frame and achieve a narrow frame.

[0094] For example, Figure 2 and Figure 3 As shown, the third pixel circuit 114 includes two parts located on both sides of each second pixel circuit column extending along the first direction, that is, in the pixel circuit column where the second pixel circuit 113 is located, the third pixel circuit 114 includes two parts distributed on both sides of the second pixel circuit 113.

[0095] Of course, the embodiments of the present disclosure are not limited thereto. When the second display area is located at the top of the entire display area, the third pixel circuit may be located only on the lower side of each second pixel circuit column, that is, no third pixel circuit is provided on the upper side of the second pixel circuit. The upper side and the lower side are, for example, the two sides along the long side of the entire display area, and the top position is, for example, the end away from the driver IC. In this case, when the shape of the first display area is rectangular and the shape of the second display area is circular, some first pixel circuits will be provided on the upper edge of the second display area, and the transfer area will also include the following: Figure 2 The first transfer area and the second transfer area shown; when the shape of the first display area is rectangular and the shape of the second display area is also rectangular, the upper edge of the first display area can be flush with the upper edge of the second display area. At this time, the first pixel circuit is no longer provided on the upper side of the second display area, and the transfer area only includes Figure 2 The first transition area shown omits the second transition area, which can further achieve a narrow frame.

[0096] For example, Figure 2 and Figure 3 As shown, the display substrate further includes a plurality of traces 300 extending along a first direction. The traces 300 do not pass through the second display area 120. The plurality of traces 300 are arranged in the same layer as the plurality of data lines 200, and at least one data line 200 is arranged between two adjacent traces 300. In a direction perpendicular to the base substrate 100, each trace 300 overlaps only with the third pixel circuit 114. For example, each trace 300 is connected to the third pixel circuit 114 with which it overlaps. The traces in the disclosed embodiment overlap only with the dummy pixel circuit.

[0097] For example, the routing lines 300 include first routing lines 310. The number of first routing lines 310 is the same as the number of second sub-data lines 222. Each first routing line 310 and a second sub-data line 222 are substantially aligned on the same line, with a gap 230 disposed between them. The aligned line is, for example, a straight line extending substantially along the second direction, and may also have some bends at certain locations, but the majority, for example, more than 50%, of the aligned line is aligned. For example, each first routing line 310 and at least a portion of a second sub-data line 222 are aligned on the same line, with a gap 230 disposed between them. For example, a second sub-data line 222 and the first routing lines 310 aligned on the same line may be two disconnected sections of a single metal line. In this case, the length of the second sub-data line 222 is less than that of the first data line 210, thereby reducing the load on the second sub-data line 222.

[0098] For example, Figure 2 and Figure 3 As shown, the gap 230 between the second sub-data line 222 and the first wiring 310 is located on the side of the first transfer area 2231 away from the second display area 120 , so the first wiring 310 does not affect the data signal transmitted on the second sub-data line 222 .

[0099] For example, Figure 2 and Figure 3 As shown, each first trace 310 is connected to the third sub-pixel 114 that overlaps with it and is configured to transmit an electrical signal. In the embodiment of the present disclosure, by connecting the first trace to the third pixel circuit that overlaps with the first trace and transmitting the electrical signal on the first trace, floating of the first trace can be avoided.

[0100] For example, the second sub-data line 222 is configured to transmit a data signal data, and the electrical signal transmitted on the first trace 310 is different from the signal transmitted on the second sub-data line 222 .

[0101] For example, the first trace 310 is configured to transmit a power supply voltage signal, which may be, for example, a constant positive voltage VDD, but is not limited thereto, and may also be other electrical signals, such as a reset voltage signal.

[0102] For example, Figure 2As shown, the routing 300 also includes a second routing 320 extending along the first direction. The second routing 320 includes portions located on both sides of the second display area 120 in the X direction and a portion located on at least one side of the second display area 120 in the Y direction. For example, in the second routing 320 located on both sides of the second display area 120 in the X direction, multiple first data lines 210 are disposed between two adjacent second routings 320, or multiple second sub-data lines 222 are disposed between two adjacent second routings 320. In the second routing 320 located on at least one side of the second display area 120 in the Y direction, multiple first sub-data lines 221 are disposed between two adjacent second routings 320. For example, in the second routing 320 located on both sides of the second display area 120 in the Y direction, multiple first sub-data lines 221 are disposed between two adjacent second routings 320 on either side. Figure 2 The second wirings located on both sides of the second display area 120 in the Y direction are not shown.

[0103] For example, each second trace 320 can transmit a power supply voltage signal. For example, multiple second traces 320 can be connected to a connecting line extending along the X direction. However, the present invention is not limited thereto. The second traces located on one side of the second display area can also not transmit electrical signals, that is, be floating.

[0104] Figure 4 FIG1 is a schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure. Figure 5 for Figure 4 The partially enlarged structural diagram of the display substrate is shown in FIG. Figure 4 and Figure 5 As shown, Figure 4 and Figure 5 The example shown is the same as Figure 2 and Figure 3 The difference of the illustrated example is that the first pixel circuit 112 located on at least one side of the second display area 120 in the first direction is connected to the first data line 210 , and the first data line 210 is not connected to the second sub-data line 222 .

[0105] For example, Figure 4 and Figure 5 As shown, each second sub-data line 222 extends along the first direction and overlaps with the orthographic projection of each routing line 300 on a straight line extending along the first direction. In this example, each second sub-data line 222 is essentially a data line 200 that passes through the first display area 110. Each second sub-data line 222 is not located on the same straight line as any routing line 300. In other words, the routing line 300 only includes a portion that passes through the first display area 110 and another portion that extends to the edge of the second display area 120.

[0106] For example, Figure 4 and Figure 5 As shown, the first data line 210 is connected to the first pixel circuit 112 located on one side of the second display area 120 in the Y direction and the first pixel circuits 112 located on both sides of the second display area 120 in the X direction.

[0107] For example, Figure 4 and Figure 5 As shown, each first sub-data line 221 and a first data line 210 are respectively located on both sides of the second display area 120 in the first direction and are located on the same straight line. Each first sub-data line 211 and the first data line 210 located on the same straight line are configured to transmit the same data signal.

[0108] For example, Figure 4 and Figure 5 As shown, the number of first pixel circuits 112 connected to the first data lines 210 on both sides of the second display area 120 in the X direction is M, and the number of first pixel circuits 112 connected to the first data line 210 on one side of the second display area 120 in the Y direction is a1.

[0109] For example, Figure 4 and Figure 5 As shown, each second data line 220 includes a first sub-data line 221, a second sub-data line 222, and a connecting line 223 connecting the first sub-data line 221 and the second sub-data line 222. For example, the connecting line 223 is located in a non-display area outside the first display area 110 and the second display area 120. The second data line 220 includes three parts connected in sequence, such as the second sub-data line 222, the connecting line 223, and the first sub-data line 221.

[0110] For example, Figure 4 and Figure 5 As shown, the number of the second pixel circuits 113 connected to the second sub-data line 222 is a2, and the number of the first pixel circuits 112 connected to the first sub-data line 221 is a3.

[0111] For example, the data signal is loaded onto the first data line 210 located on the left and right sides of the second display area 120 through the circuit board (not shown) located at the lower side of the first display area 110, so as to be provided to the M first pixel circuits 112 connected to the first data line 210; the data signal is loaded onto the first sub-data line 221 located on the lower side of the second display area 120 through the circuit board located at the lower side of the first display area 110, so as to be provided to the a1 first pixel circuits 112 connected to the first sub-data line 221; the data signal is loaded onto the first sub-data line 221 located on the lower side of the second display area 120 through the circuit board located at the lower side of the first display area 110, so as to be provided to the a1 first pixel circuits 112 connected to the first sub-data line 221. 0, so as to be provided to the a2 second pixel circuits 113 connected to the second sub-data line 222, and then the data signal is transmitted to the first sub-data line 221 located on the upper side of the second display area 120 through the adapter line 223 to be provided to the a3 first pixel circuits 112 connected to the first sub-data line 221, and the first data line 210 located on the lower side of the second display area 120 and the first sub-data line 221 located in the same straight line as the first data line 210 are configured to transmit the same data signal. This data signal transmission method can be called dual-channel driving.

[0112] In this dual-path driving mode, the number M of first pixel circuits connected to the first data lines whose extended lines do not pass through the second display area among the multiple first data lines is (a1+a2+a3), the number a1 of first pixel circuits connected to the first data lines whose extended lines pass through the second display area is less than M, and the number N of pixel circuits connected to the second data lines is (a2+a3), where N is less than M. Figure 4 The data lines in the display substrate shown are dual-channel driven. By reducing the number of third pixel circuits connected to the second data lines, the number of pixel circuits connected in series on the second data lines can be reduced, so that M is greater than or equal to N. This reduces the load on the second data lines to a certain extent, and further alleviates the phenomenon of dark vertical stripes appearing in the second display area when all data lines are simultaneously fed the same signal (ET lighting). In addition, reducing the number of pixel circuits connected to the second data lines to reduce the load can also reduce the burden on the driver IC when each data line is fed a corresponding data signal (module lighting).

[0113] For example, Figure 4 and 5 As shown, the length of each second sub-data line 222 is not less than the length of the first data line 210 whose extension line does not pass through the second display area 120. For example, the second sub-data line 222, part of the first data line 120 and part of the trace 300 all pass through the first display area 110.

[0114] Since the second sub-data line has the same length as the first data line whose extension line does not pass through the second display area, and the second sub-data line with this length is only connected to the second pixel circuit and is not connected to any dummy pixel circuit, and at the same time, the second sub-data line is not connected to the first sub-data line through the adapter line, the capacitance generated by the second sub-data line can be reduced.

[0115] For example, Figure 4 and Figure 5 As shown, each transfer line 223 includes a first transfer line 223-1 and a second transfer line 223-2 connected to each other and arranged at different layers. One of the first transfer line 223-1 and the second transfer line 223-2 is connected to the second sub-data line 222 and is located at a different layer from the second sub-data line 222.

[0116] For example, Figure 4 and Figure 5 As shown, the other of the first transfer line 223 - 1 and the second transfer line 223 - 2 extends along a second direction intersecting the first direction and is located at the same layer as the second sub-data line 212 .

[0117] Figure 6 FIG. 1 is a schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure. Figure 6 As shown, Figure 6 The example shown is the same as Figure 5 The example shown is different in that each second data line 220 extends along the first direction, and each second data line 220 is configured to be connected only to the second pixel circuit 113. Figure 6 As shown, the second display area 120 and the first display area 110 have the same shape, and one side edge (e.g., the upper edge) of the second display area 120 is flush with one side edge (e.g., the upper edge) of the first display area 110, so that the first pixel circuit 112 is only distributed on three sides of the second display area 120.

[0118] For example, Figure 6 As shown, the second display area 120 is provided with a first pixel circuit 112 on one side of the Y direction, and no first pixel circuit 112 is provided on the other side of the Y direction. The second data line 220 is only configured to provide a data signal to the second pixel circuit 113, and there is no need to provide a data signal to the first pixel circuit.

[0119] For example, Figure 6 As shown, all third pixel circuits 114 overlapping with the second data line 220 can be insulated from the second data line 220, but are not limited to this. Among the third pixel circuits overlapping with the second data line, some third pixel circuits can be connected to the second data line, and another part of the third pixel circuits can be insulated from the second data line.

[0120] For example, Figure 7 for Figures 2 to 6 The equivalent diagram of each pixel circuit in the display substrate is shown in FIG. Figure 7 Taking the second pixel circuit 113 as an example, the second pixel circuit 113 is configured to drive the second light-emitting element 121 to emit light. The structures of other pixel circuits, such as the first pixel circuit and the third pixel circuit, are the same as those of the second pixel circuit, but the third pixel circuit is not connected to the light-emitting element. For example, the display substrate further includes a reset power signal line, a scan signal line, a power signal line, a reset control signal line, and a light-emitting control signal line located on the base substrate.

[0121] For example, Figure 7 As shown, the second pixel circuit 113 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first electrode of the threshold compensation transistor T2 is connected to the first electrode of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3; the first electrode of the first reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit, and the second electrode of the first reset control transistor T7 is connected to the second light emitting element 121; the first electrode of the data writing transistor T4 is connected to the second electrode of the driving transistor T3. For example, Figure 7As shown, the second pixel circuit 113 further includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. The gate of the data writing transistor T4 is electrically connected to the scanning signal line to receive the scanning signal Gate; the first electrode of the storage capacitor C is electrically connected to the power signal line, and the second electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal line to receive the compensation control signal; the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1); the first electrode of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, and the second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the first electrode of the second light-emitting control transistor T5 is electrically connected to the power signal line to receive the power voltage signal VDD; the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3; the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; and the first electrode of the second light-emitting element 121 is connected to the voltage terminal to receive the signal VSS. The power signal line refers to a signal line that outputs the power voltage signal VDD and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0122] For example, the scanning signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can also be electrically connected to different signal lines, that is, the gate of the data writing transistor T3 is electrically connected to a first scanning signal line, and the gate of the threshold compensation transistor T2 is electrically connected to a second scanning signal line. The signals transmitted by the first scanning signal line and the second scanning signal line can be the same or different, thereby allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, thereby increasing the flexibility of controlling the pixel circuit.

[0123] For example, the light control signals input to the first light control transistor T6 and the second light control transistor T5 can be the same, that is, the gates of the first light control transistor T6 and the second light control transistor T5 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gates of the first light control transistor T6 and the second light control transistor T5 can also be electrically connected to different light control signal lines, respectively, and the signals transmitted by the different light control signal lines can be the same or different.

[0124] For example, the reset control signal input to the first reset transistor T7 and the second reset transistor T1 can be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 can also be electrically connected to different reset control signal lines, respectively. In this case, the signals on the different reset control signal lines can be the same or different.

[0125] For example, Figure 7 As shown, when the display substrate is working, in the first stage of picture display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage of picture display, the data is stored in the N1 node through the data writing transistor T4, the driving transistor T3 and the threshold compensation transistor T2; in the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 are all turned on, and the light-emitting element is forward-conducted to emit light.

[0126] It should be noted that, in the embodiment of the present disclosure, the pixel circuit can be Figure 7 In addition to the 7T1C structure (i.e., seven transistors and one capacitor) shown, it can also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, an 8T1C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0127] Figure 8 FIG1 is a schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, and a source / drain metal layer of a second pixel circuit provided according to an embodiment of the present disclosure. Figure 8As shown, the active semiconductor layer 3100 can be formed by patterning a semiconductor material. The active semiconductor layer 3100 can be used to form the active layer of the second reset transistor T1, threshold compensation transistor T2, drive transistor T3, data write transistor T4, second emission control transistor T5, first emission control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes active layer patterns (channel regions) and doping region patterns (source and drain doping regions) for each transistor.

[0128] For example, the active layer may include an integrally formed low-temperature polysilicon layer, and the source and drain regions may be made conductive by doping, etc., to achieve electrical connection between the various structures. For example, the active semiconductor layer of each transistor may be an integral pattern formed of p-silicon, and each transistor in the same pixel circuit may include a doped region pattern (i.e., a source and drain region) and an active layer pattern, with the active layers of different transistors separated by a doped structure.

[0129] For example, the active semiconductor layer 3100 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0130] Figure 10 for Figure 8 The schematic diagram of the partial cross-sectional structure of the pixel circuit is shown along AA'. Figure 8 and Figure 10 As shown, a gate insulating layer 71 is provided on the side of the active semiconductor layer 3100 away from the base substrate 100, and a first conductive layer 3200 (i.e., a gate metal layer) is provided on the side of the gate insulating layer 71 away from the active semiconductor layer 3100. The first conductive layer 3200 may include a second electrode CC2 of the capacitor C, a scanning signal line 52 extending along the X direction, a reset control signal line 51, a light-emission control signal line 53, and gates of a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light-emission control transistor T5, a first light-emission control transistor T6, and a first reset control transistor T7.

[0131] For example, Figure 8 and Figure 10As shown, the gate of the data writing transistor T3 can be the portion where the scanning signal line 52 overlaps with the active semiconductor layer 3100; the gate of the first light-emitting control transistor T6 can be the first portion where the light-emitting control signal line 53 overlaps with the active semiconductor layer 3100, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line 53 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 is the first portion where the reset control signal line 51 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is the second portion where the reset control signal line 51 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 can be a thin film transistor with a dual-gate structure. Figure 8 As shown, the gate of the driving transistor T1 may be the second electrode CC2 of the capacitor C.

[0132] It should be noted that Figure 8 The dotted rectangular boxes in the figure show the overlapping parts of the active semiconductor layer 3100 and the first conductive layer 3200, that is, the channel region. As the channel region of each transistor, the active semiconductor layer on both sides of each channel region is conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0133] For example, Figure 8 As shown, the scanning signal line 52, the reset control signal line 51, and the light-emission control signal line 53 are arranged along the Y direction. The scanning signal line 52 is located between the reset control signal line 51 and the light-emission control signal line 53. For example, the second electrode CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scanning signal line 52 and the light-emission control signal line 53.

[0134] For example, Figure 8 As shown, a source-drain metal layer 3300 is provided on a side of the first conductive layer 3200 away from the base substrate. The source-drain metal layer 3300 includes a data line 200 and a power signal line 54 extending along the Y direction. The source-drain metal layer 3300 also includes a first connecting portion 55, a second connecting portion 56, a third connecting portion 57, and a fourth connecting portion 58.

[0135] Figure 9 Schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, a source / drain metal layer, and a second conductive layer of a second pixel circuit provided according to an embodiment of the present disclosure. Figure 9 and Figure 10As shown, a first insulating layer 72 is provided on the side of the first conductive layer 3200 away from the base substrate 100, a second conductive layer 3400 is provided on the side of the second insulating layer 72 away from the base substrate 100, a second insulating layer 73 is provided on the side of the second conductive layer 3400 away from the base substrate 100, and a source-drain metal layer 3300 is provided on the side of the second insulating layer 73 away from the base substrate 100.

[0136] For example, Figure 9 As shown, the second conductive layer 3400 includes a first electrode CC1 of the capacitor C and a first reset power signal line 81 and a second reset power signal line 82. The first electrode CC1 of the capacitor C at least partially overlaps with the second electrode CC2 of the capacitor C to form a capacitor C.

[0137] For example, the second conductive layer 3400 further includes a plurality of covering portions S, and each threshold compensation transistor T2 includes two gates and an active semiconductor layer located between orthographic projections of the two gates on the active semiconductor layer 3100. Along a direction perpendicular to the substrate, the covering portion S overlaps the active semiconductor layer 3100 between the two gates.

[0138] For example, Figures 8 to 10 As shown, the second sub-data line 222 is electrically connected to the second electrode of the data writing transistor T2 in the second pixel circuit through the via H1 that penetrates the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73, so that the second sub-data line 222 inputs the data signal for the second pixel circuit.

[0139] For example, Figure 8 and Figure 9 As shown, the power signal line 54 is electrically connected to the first electrode of the second light-emitting control transistor T5 via a via hole that penetrates the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line 54 and the data line 200 are arranged alternately along the X direction. The power signal line 54 is electrically connected to the first electrode CC1 of the capacitor C via a via hole that penetrates the second insulating layer. For example, the second insulating layer is an interlayer insulating layer.

[0140] For example, a dual-gate threshold compensation transistor can reduce leakage current. For example, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is easily affected by the surrounding line voltage and jumps, thereby affecting the leakage current of the threshold compensation transistor T2, and further affecting the luminous brightness. In order to maintain the voltage stability of the active semiconductor layer between the two channels of the threshold compensation transistor T2, a capacitor is formed between the cover portion S and the active semiconductor layer between the two channels of the threshold compensation transistor T2. The cover portion S can be connected to the power signal line 54 to obtain a constant voltage, so that the voltage of the active semiconductor layer in the floating state can be kept stable. The cover portion S overlaps with the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2, and can also prevent the active semiconductor layer between the two gates from being illuminated by light and changing its characteristics, for example, preventing the voltage of this part of the active semiconductor layer from changing, so as to prevent crosstalk.

[0141] For example, Figure 8 and Figure 9 As shown, the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 via a first connecting portion 55. The first end of the first connecting portion 55 is connected to the second electrode of the threshold compensation transistor T2 via a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The second end of the first connecting portion 55 is connected to the gate of the driving transistor T3 via a via penetrating the first insulating layer and the second insulating layer. For example, the first connecting portion 55 overlaps with the first electrode CC1 of the capacitor C. The first electrode of the second reset transistor T1 is electrically connected to the first reset power signal line 81 via a second connecting portion 56. One end of the second connecting portion 56 is connected to the first electrode of the second reset transistor T1 via a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the second connecting portion 56 is connected to the first reset power signal line 81 via a via penetrating the second insulating layer. The first electrode of the first reset transistor T7 is electrically connected to the second reset power signal line 82 via the third connection portion 57. One end of the third connection portion 57 is connected to the first electrode of the first reset transistor T7 via a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the third connection portion 57 is connected to the second reset power signal line 82 via a via penetrating the second insulating layer. Because the second display area has a large ITO capacitance (i.e., the capacitance generated by the transparent trace connecting the second light-emitting element and the second pixel circuit and the overlapping conductive layers, source and drain metal layers, and other film layers), the anode voltage of the second light-emitting element rises very slowly. For low grayscales, the turn-on time of the second light-emitting element is significantly delayed. In the disclosed embodiment, the first reset power signal line and the second reset power signal line are connected to the first reset transistor and the second reset transistor, respectively. Appropriately increasing the first reset power signal voltage can improve the uneven grayscale brightness of the second display area.

[0142] For example, Figure 8 and Figure 9 As shown, the fourth connection portion 58 is connected to the second electrode of the first light emission control transistor T6 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.

[0143] It should be noted that the first pixel circuit and the second pixel circuit have the same structure, and the positional relationship and connection relationship between the first pixel circuit and the data line, scan line, reset control signal line, light control signal line, and power signal line are the same as the relationship between the second pixel circuit and the corresponding signal lines, and are not further described here. Similarly, the third pixel circuit and the second pixel circuit have the same structure, and the positional relationship and connection relationship between the third pixel circuit and the routing line, scan line, reset control signal line, light control signal line, and power signal line are the same as the relationship between the second pixel circuit and the corresponding signal lines, and are not further described here.

[0144] For example, Figure 11 FIG. 1 is a schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, and a source / drain metal layer of a third pixel circuit provided according to an embodiment of the present disclosure. Figure 11 As shown, the third pixel circuit overlaps with the second sub-data line 222, and the third pixel circuit overlaps with the second sub-data line 222. Figure 8 The second pixel circuit overlapping the second sub-data line 222 is different in that the third pixel circuit overlapping the second sub-data line 222 is insulated from the second sub-data line 222 .

[0145] Figure 12 for Figure 11 The schematic diagram of the partial cross-sectional structure of the pixel circuit is shown along BB'. Figure 11 and Figure 12 As shown, the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73 set between the second sub-data line 222 and the second electrode of the data writing transistor T2 in the third pixel circuit are not provided with vias, so that the second sub-data line 222 and the second electrode of the data writing transistor T2 located directly thereunder are insulated.

[0146] Therefore, an insulating layer (including a gate insulating layer, a first insulating layer and a second insulating layer) is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located, the first electrode of the data writing transistor in the first pixel circuit and the second pixel circuit is connected to the data line through a via located in the insulating layer, and the first electrode of the data writing transistor in at least a part of the third pixel circuit overlapping with the second data line is insulated from the second data line by the insulating layer.

[0147] For example, at least one insulating layer between the third pixel circuit and the film layer where the second data line is located may not have any vias in the area corresponding to the third pixel circuit. For example, all insulating layers between the third pixel circuit and the second data line may not have any vias in the area corresponding to the third pixel circuit.

[0148] For example, Figure 13 for Figure 2 A schematic diagram of a display area of ​​a display substrate and a second data line is shown, Figure 14 for Figure 13 An enlarged view of region E1 is shown, Figure 15 for Figure 13 An enlarged view of region E2 is shown, Figure 16 for Figure 13 An enlarged view of region E3 is shown, Figure 17 for Figure 13 An enlarged view of area E4 is shown. Figures 14 to 16 A schematic plan view of a stacked structure of a source / drain metal layer and a third conductive layer is shown schematically. Figures 13 to 16 As shown, the display substrate further includes a third conductive layer located on the side of the source / drain metal layer away from the base substrate, the third conductive layer includes a transfer line 223 located in the display area, a shielding electrode SE, a fifth connecting portion 59 and a second transfer line 223-2 located outside the display area.

[0149] For example, the shielding electrode SE is connected to the power signal line 54, so that the voltage on the shielding electrode SE is stable, which can serve as a shield to prevent the transparent wiring connecting the second light-emitting element and the second pixel circuit from affecting the gate of the driving transistor and the potential of the first connecting portion. The orthographic projection of the first connecting portion on the base substrate falls within the orthographic projection of the shielding electrode SE on the base substrate.

[0150] For example, Figures 13 to 17 As shown, a third insulating layer can be provided between the third conductive layer and the source / drain metal layer, and the fifth connecting portion 59 can be connected to the fourth connecting portion 58 through a via hole in the third insulating layer to achieve connection with the second electrode of the first light emitting control transistor T6.

[0151] For example, each light-emitting element includes a stacked first electrode, a light-emitting layer, and a second electrode (not shown). The first electrode is located on the side of the light-emitting layer facing the substrate, and the first electrode is connected to the second electrode of the first light-emitting control transistor T6 through the fifth connecting portion and the fourth connecting portion.

[0152] For example, Figure 14 and Figure 15 As shown, the transfer line 223 connected to one of the first sub-data lines 221 may overlap with the second connection portion 56 and the third connection portion 57. For example, in a direction perpendicular to the substrate, the transfer line 223 may overlap with the reset control signal line.

[0153] For example, Figure 16 and Figure 17 As shown, the first transfer line 223-1 can be formed by patterning the source and drain metal layer to save film layers, and the second transfer line 223-2 can be formed by patterning the third conductive layer. The second transfer line 223-1 is connected to the first sub-data line 221 and the first transfer line 223-1 respectively through two vias H2 in the third insulating layer. The disclosed embodiments are not limited to this. The second transfer line can be provided on the same layer as the first sub-data line (or the second sub-data line) and can be the same signal line, while the first transfer line and the first sub-data line are provided on different layers.

[0154] For example, Figure 16 and Figure 17 As shown, the third insulating layer further includes a plurality of via holes H3 so that the third insulating layer can be etched more uniformly.

[0155] For example, Figure 18 To include Figure 16 Part of the structure of the partial enlarged view shown, Figure 19 To include Figure 17 The partial structure of the enlarged view shown. Figures 16 to 19 As shown, seven first data lines 210 can be arranged between two adjacent second sub-data lines 222, and seven first sub-data lines 221 can be arranged between two adjacent traces 300. For example, the first sub-data lines 221 located on the upper side of the second display area are connected to the second sub-data lines 222 located on the left and right sides of the second display area through the first adapter line 223-1 and the second adapter line 223-2.

[0156] At least one embodiment of the present disclosure provides a display substrate, such as Figures 2 to 19 As shown, the display substrate includes a base substrate 100, a plurality of pixel circuits 1000 located on the base substrate 100, and a plurality of data lines 200. The plurality of pixel circuits 1000 include a plurality of first-type pixel circuits 1001 and a plurality of second-type pixel circuits 1002. The first-type pixel circuits 1001 are electrically connected to the data lines 200, and the second-type pixel circuits 1002 are insulated from the data lines 200. In the display substrate provided by the embodiments of the present disclosure, by isolating the second-type pixel circuits from the data lines, the number of pixel circuits connected to the data lines can be reduced to reduce the load, thereby alleviating the phenomenon of dark vertical stripes in the display area and improving the display quality of the display substrate.

[0157] For example, Figures 2 to 19 As shown, the first-type pixel circuit 1001 is electrically connected to the data line 200 overlapping therewith, and the second-type pixel circuit 1002 is insulated from the data line 200 overlapping therewith.

[0158] For example, Figures 2 to 19 As shown, at least a portion of the first-type pixel circuit 1001 is configured to drive the light-emitting element connected thereto (e.g., the first light-emitting element 111 or the second light-emitting element 121) to emit light, and the second-type pixel circuit 1002 is a first dummy pixel circuit. The first dummy pixel circuit is a pixel circuit that is not connected to any light-emitting element.

[0159] For example, Figures 2 to 19 As shown, the first-type pixel circuit 1001 includes a first pixel circuit 112 and a second pixel circuit 113. The first pixel circuit 112 and the light-emitting element (first light-emitting element 111) connected thereto overlap in a direction perpendicular to the base substrate 100, while the second pixel circuit 113 and the light-emitting element (second light-emitting element 121) connected thereto do not overlap in a direction perpendicular to the base substrate 100. The first-type pixel circuit 1001 also includes a second dummy pixel circuit 1003. The second dummy pixel circuit 1003 is a pixel circuit that is not connected to any light-emitting element.

[0160] For example, Figures 2 to 19 As shown, the second-type pixel circuits 1002 and part of the first-type pixel circuits 1002 are located in the same column.

[0161] For example, Figures 2 to 19 As shown, the second-type pixel circuit 1002 and the second pixel circuit 113 are located in the same column.

[0162] For example, Figures 2 to 19 As shown, the pixel circuit 1000 includes a data writing transistor T4, and the data writing transistor T4 includes a first electrode, a second electrode and a gate. An insulating layer is provided between the film layer where the first electrode of the data writing transistor T4 is located and the film layer where the data line 200 is located. The first electrode of the data writing transistor T4 of the first type pixel circuit 1001 is connected to the corresponding data line 200 through a via H1 located in the insulating layer (for example, the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73); the first electrode of the data writing transistor T4 of the second type pixel circuit 1002 is insulated from the data line 200 by the insulating layer (for example, the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73).

[0163] The first type pixel circuit in this embodiment includes the first pixel circuit, the second pixel circuit, and a portion of the third pixel circuit (the third pixel circuit connected to the wiring) in the above embodiment, and the second type pixel circuit includes another portion of the third pixel circuit (the pixel circuit not connected to the wiring or the data line). The substrate, data line, pixel circuit, and light-emitting element structures in the disclosed embodiment have the same features as the substrate, data line, pixel circuit, and light-emitting element structures in the above embodiment, and will not be repeated here.

[0164] Another embodiment of the present disclosure provides a display device, which includes any of the above-mentioned display substrates.

[0165] For example, the display device provided in the embodiments of the present disclosure may be an organic light emitting diode display device.

[0166] For example, in the display device provided by the embodiment of the present disclosure, by setting at least a portion of the third pixel circuit overlapping with the second data line to be disconnected from the second data line, the number of pixel circuits connected to the second data line can be reduced to reduce the load, thereby alleviating the phenomenon of dark vertical stripes appearing in the second display area and improving the display quality of the display device.

[0167] For example, the display device may further include a cover plate located on the display side of the display substrate. For example, the display device may further include a functional component located on a side of the base substrate away from the light emitting element, the functional component facing the second display area.

[0168] For example, the functional components include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.

[0169] For example, the front-facing camera module is typically activated when a user takes a selfie or makes a video call, and the pixel display area of ​​the display device displays the image captured by the selfie for the user to view. The front-facing camera module includes, for example, a lens, an image sensor, and an image processing chip. The optical image of the scene generated by the lens is projected onto the surface of the image sensor (image sensors include CCD and CMOS), where it is converted into an electrical signal. The image processing chip then converts the signal into a digital image signal after analog-to-digital conversion. The signal is then sent to the processor for processing and output on the display screen.

[0170] For example, a 3D structured light sensor and a time of flight (ToF) sensor can be used for face recognition to unlock a display device, etc.

[0171] For example, the functional component 20 may only include a camera module to realize the function of selfie or video call; for example, the functional component 20 may further include a 3D structured light module or a time-of-flight 3D imaging module to realize face recognition unlocking, etc. This embodiment includes but is not limited to this.

[0172] For example, the display device may be any product or component with a display function, such as a mobile phone, tablet computer, laptop computer, navigator, etc., with an under-screen camera, but this embodiment is not limited thereto.

[0173] There are a few points to note:

[0174] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0175] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0176] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a first display area and a second display area, wherein the first display area is located around the second display area, the first display area comprises a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits, the plurality of first pixel circuits being connected to the plurality of first light-emitting elements in a one-to-one correspondence, the second display area comprises a plurality of second light-emitting elements, the plurality of second pixel circuits being connected to the plurality of second light-emitting elements in a one-to-one correspondence, and the third pixel circuits being dummy pixel circuits; the plurality of pixel circuits included in the first display area are arranged in an array along a first direction and a second direction; a plurality of data lines located on the base substrate and not passing through the second display area, wherein the plurality of data lines include a plurality of first data lines and a plurality of second data lines, each of the first data lines is configured to be connected to the first pixel circuit, and each of the second data lines is configured to be connected to at least the second pixel circuit; The second data lines include a first sub-data line and a second sub-data line extending along the first direction, and a switching line connecting the first sub-data line and the second sub-data line; the first sub-data line, the second sub-data line, and the first data line are arranged in the same layer; the data line connected to the first pixel circuit located on one side of the second display area in the first direction is the first sub-data line among the second data lines, and the data line connected to the second pixel circuit is the second sub-data line among the second data lines; Parts of the plurality of third pixel circuits overlap with the plurality of second data lines along a direction perpendicular to the base substrate, and at least a portion of the third pixel circuits overlapping with the second data lines is insulated from the second data lines; The number of pixel circuits included in the pixel circuit column where the second pixel circuit is located is the same as the number of pixel circuits included in the pixel circuit column where the first pixel circuit is located. The pixel circuit column where the first pixel circuit is located is a pixel circuit column excluding the pixel circuit column where the data line connected to the pixel circuit column passes through the pixel circuit column in the second display area; the pixel circuit column where the first pixel circuit is located only includes the first pixel circuit, and the pixel circuit column where the second pixel circuit is located includes the second pixel circuit and the third pixel circuit.

2. The display substrate according to claim 1, wherein Each of the third pixel circuits overlapping the second data line is insulated from the second data line.

3. The display substrate according to claim 1, wherein The first pixel circuits are arranged on a side of at least part of the third pixel circuits away from the second display area, and at least one first pixel circuit column is arranged between two adjacent pixel circuit columns where the second pixel circuits are located.

4. The display substrate according to any one of claims 1 to 3, wherein: Each of the first data lines extends along the first direction, and the first data lines whose extended lines do not pass through the second display area are configured to transmit data signals to M first pixel circuits, and each of the second data lines is configured to transmit signals to N pixel circuits, and M≥N, so as to reduce the number of pixel circuits connected to the second data line and reduce the load of the second data line; the N pixel circuits include at least the second pixel circuit.

5. The display substrate according to claim 4, wherein: The first sub-data line is configured to be connected to the first pixel circuit, and the second sub-data line is configured to be connected to the second pixel circuit.

6. The display substrate according to claim 5, further comprising: A plurality of lines extending along the first direction and not passing through the second display area, The plurality of routing lines and the plurality of first data lines are arranged in the same layer, and at least one data line is arranged between two adjacent routing lines; Along a direction perpendicular to the substrate, the wiring only overlaps with the third pixel circuit.

7. The display substrate according to claim 6, wherein: The plurality of routing lines include a plurality of first routing lines, the number of the first routing lines is the same as the number of the second sub-data lines, and at least a portion of one of the first routing lines and one of the second sub-data lines are substantially located on the same straight line with a gap provided therebetween; The transfer area includes a plurality of transfer lines. In which, the transfer area includes a first transfer area located on one side of the second display area in the first direction, the transfer line in the first transfer area extends along the second direction intersecting with the first direction and is located on a different layer from the first data line, the gap is located on the side of the first transfer area away from the second display area, and the first routing line overlaps with at least part of the third pixel circuit.

8. The display substrate according to claim 7, wherein: The first data line and the second sub-data line are configured to transmit different electrical signals.

9. The display substrate according to claim 8, wherein: The first trace is configured to transmit a power supply voltage signal.

10. The display substrate according to claim 7, wherein: The transition area further includes a second transition area located on the other side of the second display area in the first direction, and the second transition area is located in a non-display area outside the first display area and the second display area.

11. The display substrate according to claim 10, wherein: Each of the transfer lines in the second transfer area includes a first transfer line and a second transfer line that are connected to each other and arranged in different layers. One of the first transfer line and the second transfer line is connected to the second sub-data line and is located in a different layer from the second sub-data line.

12. The display substrate according to claim 5, wherein: Among the second data lines, two first sub-data lines are connected to the same second sub-data line. The two first sub-data lines are respectively located on both sides of the second display area in the first direction, and at least parts of the two first sub-data lines are approximately located on the same straight line.

13. The display substrate according to claim 6, wherein: A second sub-data line extends along the first direction and overlaps with an orthographic projection of the routing line on a straight line extending along the first direction.

14. The display substrate according to claim 13, wherein: The adapter line is located in a non-display area outside the first display area and the second display area.

15. The display substrate according to claim 14, wherein: Each of the transfer lines includes a first transfer line and a second transfer line that are connected to each other and arranged in different layers. One of the first transfer line and the second transfer line is connected to the second sub-data line and is located in a different layer from the second sub-data line.

16. The display substrate according to claim 14, wherein: The length of the second sub-data line is not less than the length of the first data lines whose extended lines do not pass through the second display area.

17. The display substrate according to claim 13, wherein: The first sub-data lines and a first data line are respectively located on both sides of the second display area in the first direction and are approximately located on the same straight line. Each first sub-data line and the first data line approximately located on the same straight line are configured to transmit the same data signal.

18. The display substrate according to claim 11, wherein The other of the first switching line and the second switching line extends along the second direction intersecting with the first direction, and is located in the same layer as the second sub-data line.

19. The display substrate according to claim 4, wherein: The second data line extends along the first direction, and the second data line is configured to be connected only to the second pixel circuit.

20. The display substrate according to claim 4, wherein The plurality of second pixel circuits are located on both sides of the second display area in the second direction.

21. The display substrate according to claim 20, wherein: The pixel circuit column where the second pixel circuit is located and arranged along the first direction includes the third pixel circuit, and the third pixel circuit in the pixel circuit column overlaps with the second data line.

22. The display substrate according to claim 6, wherein: The plurality of third pixel circuits include a plurality of third pixel circuit columns extending along the first direction and arranged along the second direction. At least a portion of the plurality of third pixel circuit columns is located on at least one side of the second display area in the first direction.

23. The display substrate according to claim 22, wherein: The plurality of third pixel circuit columns further include portions located on both sides of the second display area in the second direction.

24. The display substrate according to any one of claims 1 to 3, wherein: The pixel circuit includes a data writing transistor, which includes a first electrode, a second electrode and a gate. An insulating layer is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located. The first electrode of the data writing transistor in the first pixel circuit and the second pixel circuit is connected to the data line through a via located in the insulating layer. The first electrode of the data writing transistor in at least a portion of the third pixel circuit overlapping with the second data line is insulated from the second data line by the insulating layer.

25. A display substrate comprising: A base substrate, comprising a first display area and a second display area, wherein the first display area is located around the second display area; A plurality of pixel circuits are located on the base substrate, wherein the plurality of pixel circuits included in the first display area are arranged in an array along a first direction and a second direction; A plurality of data lines are located on the substrate. Wherein, the plurality of pixel circuits include a plurality of first-type pixel circuits and a plurality of second-type pixel circuits; The first type pixel circuit includes a first pixel circuit and a second pixel circuit, the plurality of data lines include a plurality of first data lines and a plurality of second data lines, each of the first data lines is configured to be connected to the first pixel circuit, and each of the second data lines is configured to be connected to at least the second pixel circuit; The second data line includes a first sub-data line and a second sub-data line extending along the first direction, the first sub-data line is configured to be connected to the first pixel circuits located on both sides of the second display area in the first direction, and the second sub-data line is configured to be connected to the second pixel circuit; The display substrate further includes a plurality of routing lines extending along the first direction, wherein the plurality of routing lines are arranged in the same layer as the plurality of first data lines, and at least one data line is arranged between two adjacent routing lines; The plurality of routing lines include a plurality of first routing lines, the number of the first routing lines is the same as the number of the second sub-data lines, at least a portion of a first routing line and a second sub-data line are substantially located on the same straight line with a gap provided therebetween; a second sub-data line and the first routing line located on the same straight line are two disconnected portions of a metal line, and a length of the second sub-data line is less than a length of the first data line; The first-type pixel circuit is electrically connected to the data line overlapping with the first-type pixel circuit, and the second-type pixel circuit is insulated from the data line overlapping with the second-type pixel circuit.

26. The display substrate according to claim 25, wherein: At least a portion of the first-type pixel circuit is configured to drive a light-emitting element connected thereto to emit light, and the second-type pixel circuit is a first dummy pixel circuit.

27. The display substrate according to claim 26, wherein: The first pixel circuit and the light-emitting element connected thereto overlap in a direction perpendicular to the substrate, and the second pixel circuit and the light-emitting element connected thereto do not overlap in a direction perpendicular to the substrate; The first-type pixel circuit further includes a second dummy pixel circuit.

28. The display substrate according to claim 27, wherein: The second-type pixel circuits and some of the first-type pixel circuits are located in the same column.

29. The display substrate according to claim 28, wherein: The second-type pixel circuit and the second pixel circuit are located in the same column.

30. The display substrate according to any one of claims 25 to 29, wherein: The pixel circuit includes a data writing transistor, the data writing transistor includes a first electrode, a second electrode and a gate, an insulating layer is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located, The first electrode of the data writing transistor of the first type pixel circuit is connected to the corresponding data line through a via located in the insulating layer; the first electrode of the data writing transistor of the second type pixel circuit is insulated from the data line by the insulating layer.

31. A display device comprising the display substrate according to any one of claims 1 to 30.

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